XML

Targets

• msrtool (partially done)
• superiotool (partially done)
• inteltool

Possible ways

• Codegeneration (already implemented - see https://bitbucket.org/droiddev/pygen/wiki/Home )
• Use xml format always - read/write it in runtime
• Embedding data from xml files into target elf file at build stage.

Now, we think, preffered way - embedding data from xml into elf file

Output

Improve possibility of export/output in XML format for easy automated parse output of utils

Sample

Example for Super I/O definitions:

<?xml version="1.0" encoding="UTF-8"?>
<sioarray name="ite" description="ite superios">
<sio model="IT8228E" id="0x8228" >
</sio>
<sio model="IT8500B/E" id="0x8500" >
<noldn>
<reg address="0x20" default_value="0x85" />
<reg address="0x21" default_value="0x0" />
<reg address="0x22" default_value="0x1" />
<reg address="0x23" default_value="0x1" />
<reg address="0x25" default_value="0x0" />
<reg address="0x2d" default_value="0x0" />
<reg address="0x2e" default_value="NANA" />
<reg address="0x2f" default_value="NANA" />
<reg address="0x30" default_value="0x0" />
</noldn>
<ldn number="0x4" name="System Wake-Up Control (SWUC)" description="">
<reg address="0x30" default_value="0x0" />
<reg address="0x60" default_value="0x0" />
<reg address="0x61" default_value="0x0" />
<reg address="0x62" default_value="0x0" />
<reg address="0x63" default_value="0x0" />
<reg address="0x70" default_value="0x0" />
<reg address="0x71" default_value="0x1" />
</ldn>
</sio>
<sio model="IT8513E/F/G" id="0x8513" >
</sio>
</sioarray>

Example for MSR definitions

<?xml version="1.0" encoding="UTF-8"?>
<msrarray name="k8" description="bla-bla">
<cpu family="0x6" model="0x17" stepping="5" />
<msr address="0xc0000080" type="rw" name="EFER Register" description="Extended Feature Enable Register">
<bitfield start="63" size="32" name="RSVD" description="Reserved" type="hex">
</bitfield>
<bitfield start="31" size="18" name="RSVD" description="Reserved" type="hex">
</bitfield>
<bitfield start="14" size="1" name="FFXSR:" description="Fast FXSAVE/FRSTOR Enable" type="dec">
<value number="0" description="FXSAVE/FRSTOR disabled" />
<value number="1" description="FXSAVE/FRSTOR enabled" />
</bitfield>
<bitfield start="13" size="1" name="LMSLE:" description="Long Mode Segment Limit Enable" type="dec">
<value number="0" description="Long mode segment limit check disabled" />
<value number="1" description="Long mode segment limit check enabled" />
</bitfield>
</msr>
</msrarray>

First goal

We need unify XML format data:

<?xml version="1.0" encoding="UTF-8"?>
<domain name="MSR" description="CPU Model Specific Registers definitions">
<regarray name="k8" vendor="AMD" description="AMD K8 CPU definitions" type="msrarray">
<reg type="msr" address="0xc0000080" type="rw" name="EFER Register" description="Extended Feature Enable Register">
<bitarray start="13" size="1" name="LMSLE:" description="Long Mode Segment Limit Enable" type="dec">
<!-- Possible Values -->
<value number="0" description="Long mode segment limit check disabled" />
<value number="1" description="Long mode segment limit check enabled" />
</bitarray>
</reg>
</regarray>
</domain>
<domain name="SIO" description="Super I/O defitions">
<regarray name="it8500" vendor="ITE" description="ITE IT8500 definitions" type="sioarray">
<reg type="sio" address="0x80" type="rw" name="Some Register" description="Extended Feature Enable Register">
<value number="0" description="Long mode segment limit check disabled" />
<value number="1" description="Long mode segment limit check enabled" />
</reg>
</domain>

Possible features, other ideas

Use gzip or lzma-packed xml base