https://www.coreboot.org/api.php?action=feedcontributions&user=DavidHubbard&feedformat=atomcoreboot - User contributions [en]2024-03-19T03:40:10ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=Board:hp/pavilion_m6_1035dx&diff=13636Board:hp/pavilion m6 1035dx2014-04-21T04:59:34Z<p>DavidHubbard: /* What doesn't work */</p>
<hr />
<div>Hello. I'll have some more info soon enough. For now, remember this:<br />
<br />
$ flashrom -pinternal:amd_imc_force=yes -w coreboot.rom<br />
<br />
Now chances are that will brick your system if you're not already booting coreboot. Expect to do an external flash initially.<br />
<br />
== Status ==<br />
<br />
Note that this information is for my personal records keeping, and is based on the latest local patches, some of which may not have been published yet.<br />
<br />
=== What works ===<br />
<br />
* Succesfully booting to OS<br />
* Keyboard and touchpad. (This touchpad is DIVINE!!!)<br />
* Built-in Audio<br />
* USB ports (USB 3.0 not tested, though the ports work with USB 2.0 devices)<br />
* Wired and wireless networking. (Wired is a little wonky with some cables, works with others)<br />
* Batterry status and notifications<br />
* Batterry charging<br />
* AC status LED next to power jack (white = charged, amber = charging)<br />
* Power LED on power button (Not sure if it works as expected during suspend)<br />
* Keyboard backlight and on/off control<br />
* Hotkeys: Volume (Up/Down/Mute), Media (Prev/Play/Next), Keyboard backlight, WLAN toggle<br />
* Caps Lock LED<br />
* WLAN enabled/disabled LED<br />
* Suspend/resume on lid closed/open<br />
<br />
=== What doesn't work ===<br />
<br />
* DVD drive. (has anyone tried HP's [http://h10025.www1.hp.com/ewfrf/wc/softwareCategory?os=4063&lc=en&cc=us&dlc=en&sw_lang=&product=5273902#N1363|firmware update for the DVD drive]?)<br />
* Suspend/Resume (Kinda works, no video on resume)<br />
* Power LED on the side (right above disk activity LED)<br />
* Hotkeys: Brightess (Up/Down), Display Toggle. (We get SCIs from the EC)<br />
* Mute LED (Note: doesn't work, even using OEM BIOS)<br />
* Shutdown on critical battery level (We get a _Q25 SCI at 15% level, but that's also shared with insert/remove events)<br />
* Setting Fn key mode to default on or default off. Right now it's default on.<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls WLAN (rfkill pin on minipcie slot)<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GEVENT3 -> GPE3 - EC SCI<br />
* GEVENT8 -> PCIE WAKE -> GPE24<br />
* GEVENT23 -> EC SMI -> Configured as GEVENT23 SMI, not GPE23 SMI/SCI<br />
* GEVENT22 -> GPE22 - EC LID<br />
<br />
== EC headaches ==<br />
<br />
=== To ACPI or not to ACPI ===<br />
<br />
The EC likes to start up in APM mode. In APM mode, it will generate an SMI whenever an external event occurs. To make it generate SCIs instead, and play nicely with ACPI, we need to tell it to go to ACPI mode.<br />
<br />
=== The MMIO dilemma ===<br />
<br />
The EC RAM, which contains the batterry/AC etc information is normally accessed by read commands on the EC index I/O ports (0x62 and 0x66). The EC will also respond to LPC memory read/write cycles in the address range 0xff000000 + 0x1000. In order for this to work, the chipset must pass MMIO accesses in this range to the LPC bridge, which in turn, must decode them to the LPC bus.<br />
<br />
This can't work if there is something else using that address range, so any system with 16MiB is out of the question. Luckily, the 1035dx uses a 4 MiB chip, so that's a non-issue. As a bonus, the LPC bridge can map a 4 KiB MMIO window on the LPC bus (or two, I can't remember).<br />
<br />
The following script enables the needed MMIO window:<br />
# '''iotools pci_write32 0 0x14 3 0x4c 0xff000000'''<br />
# '''iotools pci_write32 0 0x14 3 0x48 0x00b0ff07'''<br />
<br />
<br />
The EC RAM is at an offset of 0x800 from the MMIO base address. The current compal/ene932 ACPI implementation does not handle MMIO. This should be easily fixable with some preprocessor love.<br />
<br />
=== Switching between APM/ACPI modes ===<br />
<br />
Coreboot does it in the SMI handler on request form the OS. Doing that can also be accomplished in userspace by uberawesome blackmagic:<br />
<br />
# '''iotools io_write8 0x66 0x59 && iotools io_write8 0x62 0xe9''' # Put EC in APM mode<br />
# '''iotools io_write8 0x66 0x59 && iotools io_write8 0x62 0xe8''' # Put EC in ACPI mode<br />
<br />
== TODO ==<br />
<br />
* Check PCIe lane assignment<br />
* <s>Check grub2 payload</s> (Run VGA option ROM and Keep VESA framebuffer -- works)<br />
* Check AHCI port mask<br />
* Make Suspend/resume (ACPI)<br />
* WLAN hotkey does not follow OS security model<br />
** With vendor firmware, WLAN hotkey only works after logging in -- _Qxx handler uses device notifications rather than controlling the GPIOs directly<br />
** Figure out how to make coreboot's ACPI behave the same way<br />
<br />
== Detective work ==<br />
<br />
=== Undocumented EC bits ===<br />
<br />
Offsets relative to EC RAM.<br />
<br />
* 0xb8.1 : Lid state (1 = closed, 0 = open)<br />
<br />
== Native graphics init ==<br />
<br />
Judging from schematics of similar hardware, the display output is DisplayPort, which is passed through a DP to LVDS converter. Seems this guy might be responsible for enabling the panel back-light. The VGA ROM knows how to tell the little guy to enable the backlight. linux does not.<br />
<br />
Not happening yet. There has been some initial work in this regard:<br />
<br />
* http://www.coreboot.org/pipermail/coreboot/2013-June/076035.html</div>DavidHubbardhttps://www.coreboot.org/index.php?title=Board:hp/pavilion_m6_1035dx&diff=13634Board:hp/pavilion m6 1035dx2014-04-21T04:52:23Z<p>DavidHubbard: /* What doesn't work */ Mute LED status</p>
<hr />
<div>Hello. I'll have some more info soon enough. For now, remember this:<br />
<br />
$ flashrom -pinternal:amd_imc_force=yes -w coreboot.rom<br />
<br />
Now chances are that will brick your system if you're not already booting coreboot. Expect to do an external flash initially.<br />
<br />
== Status ==<br />
<br />
Note that this information is for my personal records keeping, and is based on the latest local patches, some of which may not have been published yet.<br />
<br />
=== What works ===<br />
<br />
* Succesfully booting to OS<br />
* Keyboard and touchpad. (This touchpad is DIVINE!!!)<br />
* Built-in Audio<br />
* USB ports (USB 3.0 not tested, though the ports work with USB 2.0 devices)<br />
* Wired and wireless networking. (Wired is a little wonky with some cables, works with others)<br />
* Batterry status and notifications<br />
* Batterry charging<br />
* AC status LED next to power jack (white = charged, amber = charging)<br />
* Power LED on power button (Not sure if it works as expected during suspend)<br />
* Keyboard backlight and on/off control<br />
* Hotkeys: Volume (Up/Down/Mute), Media (Prev/Play/Next), Keyboard backlight, WLAN toggle<br />
* Caps Lock LED<br />
* WLAN enabled/disabled LED<br />
* Suspend/resume on lid closed/open<br />
<br />
=== What doesn't work ===<br />
<br />
* DVD drive.<br />
* Suspend/Resume (Kinda works, no video on resume)<br />
* Power LED on the side (right above disk activity LED)<br />
* Hotkeys: Brightess (Up/Down), Display Toggle. (We get SCIs from the EC)<br />
* Mute LED (Note: doesn't work, even using OEM BIOS)<br />
* Shutdown on critical battery level (We get a _Q25 SCI at 15% level, but that's also shared with insert/remove events)<br />
* Setting Fn key mode to default on or default off. Right now it's default on.<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls WLAN (rfkill pin on minipcie slot)<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GEVENT3 -> GPE3 - EC SCI<br />
* GEVENT8 -> PCIE WAKE -> GPE24<br />
* GEVENT23 -> EC SMI -> Configured as GEVENT23 SMI, not GPE23 SMI/SCI<br />
* GEVENT22 -> GPE22 - EC LID<br />
<br />
== EC headaches ==<br />
<br />
=== To ACPI or not to ACPI ===<br />
<br />
The EC likes to start up in APM mode. In APM mode, it will generate an SMI whenever an external event occurs. To make it generate SCIs instead, and play nicely with ACPI, we need to tell it to go to ACPI mode.<br />
<br />
=== The MMIO dilemma ===<br />
<br />
The EC RAM, which contains the batterry/AC etc information is normally accessed by read commands on the EC index I/O ports (0x62 and 0x66). The EC will also respond to LPC memory read/write cycles in the address range 0xff000000 + 0x1000. In order for this to work, the chipset must pass MMIO accesses in this range to the LPC bridge, which in turn, must decode them to the LPC bus.<br />
<br />
This can't work if there is something else using that address range, so any system with 16MiB is out of the question. Luckily, the 1035dx uses a 4 MiB chip, so that's a non-issue. As a bonus, the LPC bridge can map a 4 KiB MMIO window on the LPC bus (or two, I can't remember).<br />
<br />
The following script enables the needed MMIO window:<br />
# '''iotools pci_write32 0 0x14 3 0x4c 0xff000000'''<br />
# '''iotools pci_write32 0 0x14 3 0x48 0x00b0ff07'''<br />
<br />
<br />
The EC RAM is at an offset of 0x800 from the MMIO base address. The current compal/ene932 ACPI implementation does not handle MMIO. This should be easily fixable with some preprocessor love.<br />
<br />
=== Switching between APM/ACPI modes ===<br />
<br />
Coreboot does it in the SMI handler on request form the OS. Doing that can also be accomplished in userspace by uberawesome blackmagic:<br />
<br />
# '''iotools io_write8 0x66 0x59 && iotools io_write8 0x62 0xe9''' # Put EC in APM mode<br />
# '''iotools io_write8 0x66 0x59 && iotools io_write8 0x62 0xe8''' # Put EC in ACPI mode<br />
<br />
== TODO ==<br />
<br />
* Check PCIe lane assignment<br />
* <s>Check grub2 payload</s> (Run VGA option ROM and Keep VESA framebuffer -- works)<br />
* Check AHCI port mask<br />
* Make Suspend/resume (ACPI)<br />
* WLAN hotkey does not follow OS security model<br />
** With vendor firmware, WLAN hotkey only works after logging in -- _Qxx handler uses device notifications rather than controlling the GPIOs directly<br />
** Figure out how to make coreboot's ACPI behave the same way<br />
<br />
== Detective work ==<br />
<br />
=== Undocumented EC bits ===<br />
<br />
Offsets relative to EC RAM.<br />
<br />
* 0xb8.1 : Lid state (1 = closed, 0 = open)<br />
<br />
== Native graphics init ==<br />
<br />
Not happening yet. There has been some initial work in this regard:<br />
<br />
* http://www.coreboot.org/pipermail/coreboot/2013-June/076035.html</div>DavidHubbardhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12116Board:asus/f2a85-m2013-07-23T01:58:39Z<p>DavidHubbard: Explain seabios payload better</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is same as F2A85-M.<br />
* get VGA from original bios using this:<br />
Source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html<br />
<br />
for internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
extracting from your system: dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768<br />
<br />
* Add VGA bios in the menuconfig<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI<br />
* update VERB tables<br />
* test suspend<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = <br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multicore_comments = <br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
|RAM_ecc_comments =<br />
<br />
|IDE_status = N/A<br />
|IDE_comments = <br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|PP_comments = <br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|CPUfreq_comments = <br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend untested.<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'.<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>DavidHubbardhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12115Board:asus/f2a85-m2013-07-23T01:56:23Z<p>DavidHubbard: Remove seabios patch, update status</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is same as F2A85-M.<br />
* get VGA from original bios using this:<br />
Source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html<br />
<br />
for internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
extracting from your system: dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768<br />
<br />
* Add VGA bios in the menuconfig<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI<br />
* update VERB tables<br />
* test suspend<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = <br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multicore_comments = <br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
|RAM_ecc_comments =<br />
<br />
|IDE_status = N/A<br />
|IDE_comments = <br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|PP_comments = <br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|CPUfreq_comments = <br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend untested.<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'.<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>DavidHubbardhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=12107Build HOWTO2013-07-12T00:50:53Z<p>DavidHubbard: Add git submodule update --init --checkout</p>
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<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Known issues ==<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>DavidHubbardhttps://www.coreboot.org/index.php?title=User:DavidHubbard&diff=12061User:DavidHubbard2013-06-19T18:42:38Z<p>DavidHubbard: Created page with "David Hubbard previously worked on lm-sensors with Rudolf Marek, Jean Delvare, ... He has an Asus F2A85-M/CSM and helps out with small tasks there."</p>
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<div>David Hubbard previously worked on lm-sensors with Rudolf Marek, Jean Delvare, ...<br />
<br />
He has an Asus F2A85-M/CSM and helps out with small tasks there.</div>DavidHubbardhttps://www.coreboot.org/index.php?title=Talk:Board:asus/f2a85-m&diff=11364Talk:Board:asus/f2a85-m2012-12-28T03:47:42Z<p>DavidHubbard: Linux complains about prefetchable memory regions</p>
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<div></div>DavidHubbardhttps://www.coreboot.org/index.php?title=Talk:Board:asus/f2a85-m&diff=11363Talk:Board:asus/f2a85-m2012-12-28T03:46:42Z<p>DavidHubbard: Linux complains about prefetchable memory regions</p>
<hr />
<div></div>DavidHubbardhttps://www.coreboot.org/index.php?title=Talk:Board:asus/f2a85-m&diff=11362Talk:Board:asus/f2a85-m2012-12-28T03:02:42Z<p>DavidHubbard: Linux complains about prefetchable memory regions</p>
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<div></div>DavidHubbard