https://www.coreboot.org/api.php?action=feedcontributions&user=Idwer&feedformat=atomcoreboot - User contributions [en]2024-03-28T17:49:09ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=EHCI_Debug_Port&diff=28139EHCI Debug Port2017-08-20T20:18:49Z<p>Idwer: </p>
<hr />
<div>[[Image:PLX_NET20DC.jpg|thumb|right|Ajays (now bankcrupt) NET20DC 2.0 EHCI controller debug device.]]<br />
<br />
Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.<br />
<br />
The '''EHCI Debug Port''' is an optional capability of EHCI controllers which can be used for that purpose.<br />
<br />
All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.<br />
<br />
While the '''Debug Class''' functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.<br />
<br />
== Supported chipsets ==<br />
<br />
The following southbridges have USB debug support in coreboot:<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background:lime" | OK<br />
| Tested by [[User:Uwe|Uwe Hermann]].<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700<br />
| style="background:orange" | WIP<br />
| Probably won't work, a patch is being prepared.<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB900<br />
| style="background:lime" | OK<br />
| Tested on HP Pavilion m6 1035dx<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| A85X (Hudson D4)<br />
| style="background:lime" | OKhttps://www.coreboot.org/BeagleBone_Black_-_screwdriver<br />
| Tested by [[User:Ranma|Tobias Diedrich]] on ASUS F2A85M-LE.<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel<br />
| 82801GX (ICH7)<br />
| style="background:lime" | OK<br />
| Tested by [[User:SvenS|Sven Schnelle]] on Lenovo Thinkpad X60/T60. <br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<br />
| Tested by [[User:Uwe|Uwe Hermann]]. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966<br />
| style="background:yellow" | Untested<br />
| '''Note:''' It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).<br />
<br />
|}<br />
<br />
== Finding the USB debug port ==<br />
<br />
Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port without software is rather difficult because you need to look at lots of information.<br />
<br />
* <code>sudo lshw</code> can be used to find EHCI cabpable USB ports. It may yield something like:<br />
<pre><br />
*-usb:1<br />
description: USB controller<br />
product: MCP55 USB Controller<br />
vendor: NVIDIA Corporation<br />
physical id: 2.1<br />
bus info: pci@0000:00:02.1<br />
version: a2<br />
width: 32 bits<br />
clock: 66MHz<br />
capabilities: debug pm ehci bus_master cap_list<br />
configuration: driver=ehci_hcd latency=0 maxlatency=1 mingnt=3<br />
resources: irq:22 memory:ee204000-ee2040ff<br />
</pre><br />
* As <code>dmesg</code> are part of the core system it can be used from Live distributions that often protect the filesystem from file execution which means that scripts cannot be used. The easiest way to locate the physical USB port that has EHCI debug support can be verified by doing the following:<br />
** <code>sudo dmesg -c</code><br />
** Plug a USB flash memory<br />
** <code>dmesg | tail -22 | grep ehci</code><br />
* Carl-Daniel Hailfinger [http://www.coreboot.org/pipermail/coreboot/2008-September/038618.html has written] [http://www.coreboot.org/pipermail/coreboot/attachments/20080909/ae11c291/attachment.sh a script] which can help finding that port. An [http://www.coreboot.org/pipermail/coreboot/attachments/20140530/245547f8/attachment.sh updated script] was posted [http://www.coreboot.org/pipermail/coreboot/2014-May/078022.html here] on May 30 2014.<br />
<br />
== Using the EHCI debug port ==<br />
<br />
=== usb_debug kernel module and minicom ===<br />
<br />
To get a USB debug console, enable both '''CONFIG_USBDEBUG''' and '''CONFIG_CONSOLE_USB''' (menu option '''USB 2.0 EHCI debug dongle support''') in coreboot's kconfig.<br />
<br />
In case your system has more than one debug-capable EHCI, you can select the index as CONFIG_USBDEBUG_HCD_INDEX, with a southbridge-specific value (on AMD Hudson, 0 and 1 both indicate the first port, 2 is the second port).<br />
<br />
On your "host PC" you need a Linux system which is recent enough to provide the '''usb_debug''' kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a '''/dev/ttyUSB0''' device to which you can connect as usual using any serial terminal program, e.g. '''minicom''' (115200, 8n1).<br />
<br />
TODO: Is the Baud rate actually configurable somewhere?<br />
<br />
You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.<br />
<br />
Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.<br />
<br />
=== usb_debug_io.c ===<br />
<br />
As an alternative, you can also use [http://tracker.coreboot.org/trac/coreboot/ticket/57 this small libusb-based user-space program] on the host PC to retrieve the coreboot logs.<br />
<br />
== Hardware capability ==<br />
<br />
The Debug Port is optional, please check if EHCI controllers near you support it: <code>lspci -v | grep ehci</code>. If you get any result try <code>lspci -v</code> and locate the entry.<br />
<br />
<br />
This might not work for your system but you can also try:<br />
$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do<br />
$ ''' lspci -vs $i'''<br />
$ '''done'''<br />
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])<br />
Subsystem: IBM Unknown device 0566<br />
Flags: bus master, medium devsel, latency 0, IRQ 5<br />
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]<br />
Capabilities: [50] Power Management version 2<br />
Capabilities: [58] '''Debug port'''<br />
<br />
Look for a line like the last one above. Please include the PCI device ID too:<br />
<br />
$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do<br />
$ ''' lspci -ns $i'''<br />
$ '''done'''<br />
00:1d.7 0c03: 8086:265c (rev 03)<br />
<br />
If your controller isn't already listed below then please add it or send an email to the [[Mailinglist|mailing list]] if you don't have a wiki account yet and want one, or want us to add your controller to the page.<br />
<br />
=== Controllers verified to have the debug port capability ===<br />
<br />
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)<br />
* 8086:24cd Intel ICH4/ICH4-M<br />
* 8086:24dd Intel ICH5<br />
* 8086:265c Intel ICH6<br />
* 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)<br />
* 8086:27cc Intel ICH7<br />
* 8086:2836 Intel ICH8<br />
* 8086:283a Intel ICH8<br />
* 8086:293a Intel ICH9 (rev 2)<br />
* 8086:3a3a Intel ICH10<br />
* 8086:3a3c Intel ICH10<br />
* 10de:0088 NVIDIA MCP2A (rev a2)<br />
* 10de:005b NVIDIA CK804 (rev a3)<br />
* 10de:026e NVIDIA MCP51 (rev a3)<br />
* 10de:036d NVIDIA MCP55 (rev a2)<br />
* 10de:03f2 NVIDIA MCP61 (rev a3)<br />
* 1002:4386 ATI/AMD SB600<br />
* 1002:4396 ATI/AMD SB700<br />
* 1022:7808 AMD A85X<br />
* 1106:3104 VIA VX800 (rev 90)<br />
<br />
=== Controllers verified to lack the debug port capability ===<br />
<br />
* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)<br />
* 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)<br />
* 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)<br />
* 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHCI (rev 02)<br />
* 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)<br />
* 1039:7002 SiS EHCI (rev 00)<br />
<br />
==Debug devices==<br />
<br />
=== Debug software ===<br />
A prebuilt Linux distribution called 'screwdriver' exists: "A tool for coreboot/libreboot/flashrom developers and users. The firmware itself is based on vanilla OpenWrt Chaos Calmer(15.04) with some modifications. This firmware is mainly intended for BeagleBone Black (BBB)."<br />
See [[BeagleBone_Black_-_screwdriver]].<br />
<br />
=== DIY / BeagleBone Black ===<br />
<br />
==== EHCI Debug gadget driver ====<br />
If you have a device running GNU/Linux that has an usb device port, you could then try to use the [[EHCI Gadget Debug]].<br />
Note that it's not guaranteed to work on old kernels, and may be dependant on the usb device/otg controller driver.<br />
<br />
You can make your own usb debug dongle, see [[DIY EHCI debug dongle]].<br />
<br />
A BeagleBone Black with a 5v power supply can achieve this. [https://johnlewis.ie/coreboot-ehci-debug-gadget-demonstration/] (John Lewis)<br />
<br />
=== Commercial Devices/Dongles ===<br />
<br />
To be able to use the debug port it needs to be connected to a compatible device.<br />
There are two commercial devices available which can use the EHCI Debug Port, the '''AMIDebug Rx''' and '''Ajays NET20DC'''.<br />
<br />
==== AMIDebug Rx ====<br />
[[Image:AMI_Debug_Rx_2009-06-10_012.jpg|thumb|right|AMI Debug Rx USB 2.0 EHCI controller device.]]<br />
<br />
This device is expensive compared to the other devices on this page. The main advantage of this product is that it comes with LCD.<br />
<br />
* http://www.ami.com/products/bios-uefi-tools-and-utilities/amidebug-rx/<br />
<br />
"Interested parties may contact AMI for pricing and purchasing information" - AMI. point of contact: www.ami.com, phone number 1-800-828-9264.<br />
<br />
==== Ajays NET20DC ====<br />
Disclaimer:Ajays is bankcrupt so their product line is end of life (EOL). Symmetry Electronics and other companies have disengaged as a supplier of the Ajays Technology product line. This limits the number of available units on the market.<br />
<br />
* [http://web.archive.org/web/20080219120613/http://www.plxtech.com/products/NET2000/NET20DC/default.asp http://www.plxtech.com/products/NET2000/NET20DC/default.asp] (archive.org)<br />
<br />
The device can be used in both directions, but only one side provides power for the circuit.<br />
Make sure to connect the front port (see picture at the top) to your host device and the rear port to the DUT.<br />
On the host side it doesn't matter which USB port to use, on the DUT side use the DEBUG port.<br />
Under GNU/Linux the device shows up as a regular serial USB device (ttyUSBx).<br />
<br />
== More information ==<br />
<br />
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) &mdash; The Debug Port is described in Appendix C.<br />
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) &mdash; This is what has to be connected to the EHCI controller.<br />
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) &mdash; ''dead URL'' ([https://web.archive.org/web/20050826153054/http://www.intel.com/technology/magazine/computing/it09021.pdf copy at archive.org])<br />
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]<br />
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]<br />
* http://coreboot.org/pipermail/coreboot/2006-December/thread.html#17480<br />
* http://lkml.org/lkml/2006/12/1/214<br />
* http://www.usb.org/developers/presentations/pres0602/john_keys.pdf<br />
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5c05917e7fe313a187ad6ebb94c1c6cf42862a0b Linux early USB Debug Port support finally commited]<br />
* [http://www.kernel.org/doc/Documentation/x86/earlyprintk.txt early printk support in Linux]<br />
* http://www.spinics.net/lists/linux-usb/msg32912.html (Linux USB EHCI Debug Port device gadget)<br />
* http://cs.usfca.edu/~cruse/cs698s10/ - various EHCI debug port and Ajays resources</div>Idwerhttps://www.coreboot.org/index.php?title=EHCI_Gadget_Debug&diff=14707EHCI Gadget Debug2014-10-23T18:21:26Z<p>Idwer: </p>
<hr />
<div>== Introduction ==<br />
This page is about using embedded GNU/Linux devices in order to get the USB debug logs.<br />
<br />
== Howto ==<br />
=== Patching ===<br />
Download the [[:File:Ehci-debug-gadget-patches.tar.gz|patches]] that maintain TTY connected while debug target power-cycles or when host controller is reset.<br />
<br />
Apply the patches from one of the v3.8- or v3.10-debug-gadget directories on your kernel build tree.<br />
<br />
=== Compiling ===<br />
* You need to be familiar with (cross) compiling your kernel.<br />
Be sure to set CONFIG_LOCALVERSION.<br />
For example, on Fedora the output of 'uname -r' is 3.16.6-200.fc20.armv7hl, so to be able to load g_dbgp later on CONFIG_LOCALVERSION must be set to -200.fc20.armv7hl. You can extract this from a running system by using this shell command:<br />
uname -r | cut -d- -f 2-<br />
<br />
* (Cross) compile it as usual but during the configuration do the following:<br />
<br />
Go into Device Drivers:<br />
Device Drivers ---><br />
Then go into USB support:<br />
[*] USB support ---><br />
Then go into USB Gadget Support:<br />
<M> USB Gadget Support ---><br />
Then enable the following option (CONFIG_USB_G_DBGP=m):<br />
<M> EHCI Debug Device Gadget<br />
<br />
Then select the serial option:<br />
EHCI Debug Device mode (serial) ---><br />
<br />
Then run<br />
make M=drivers/usb/gadget<br />
which will take about 2,5 minutes when running a native compile on the beagleboneblack. As long as you use the distribution's kernel source code package there is no need to compile all the other modules and initramfs/uImage/uInitrd/vmlinuz.<br />
<br />
=== Loading ===<br />
Remove all usb gadget drivers such as g_ether or g_mass_storage with rmmod or modprobe -r.<br />
Then move the distribution's dir<br />
/lib/modules/$(uname -r)/kernel/drivers/usb/gadget/<br />
to<br />
/lib/modules/$(uname -r)/kernel/drivers/usb/gadget.distribution<br />
and recreate<br />
/lib/modules/$(uname -r)/kernel/drivers/usb/gadget/<br />
<br />
Copy over the modules:<br />
for f in $(find drivers/usb/gadget/ -name *.ko); do sudo cp $f /lib/modules/$(uname -r)/kernel/drivers/usb/gadget/ ; done<br />
<br />
Finally, load g_dbgp:<br />
modprobe g_dbgp<br />
<br />
=== Running ===<br />
I recommend to open the TTY before starting debug target. Doing it the other way<br />
around slows down the debug target boot and seems to confuse serial gadget framework.<br />
<br />
You may want to disable some CR/LF translations on the device:<br />
stty -icrnl -inlcr -F /dev/ttyGS0<br />
<br />
You can directly open the device node, possibly redirecting to file:<br />
cat /dev/ttyGS0<br />
.. or use a terminal client:<br />
picocom -ir /dev/ttyGS0<br />
<br />
=== Finding the USB debug port ===<br />
See [[EHCI Debug Port#Finding the USB debug port]]<br />
<br />
== Tested hardware ==<br />
{| class="wikitable" border="1"<br />
! Brand and Device<br />
! kernel used<br />
! Target devices<br />
! works?<br />
|-<br />
! [http://projects.goldelico.com/p/gta04-main/ Goldelico GTA04 A3]<br />
| [https://github.com/goldelico/gta04-kernel/commits/neil-plus neil-plus kernel and branch (3.7)]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
! [http://wiki.buglabs.net/index.php/Welcome_to_BUG_Wiki Buglabs's bug 2.0]<br />
| [https://github.com/buglabs/bug20-2.6.35-linaro/commits/master bug20-2.6.35-linaro's master (2.6.35) ]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
|}</div>Idwerhttps://www.coreboot.org/index.php?title=EHCI_Debug_Port&diff=14705EHCI Debug Port2014-10-21T23:15:36Z<p>Idwer: /* Finding the USB debug port */</p>
<hr />
<div>[[Image:PLX_NET20DC.jpg|thumb|right|Ajays NET20DC USB Debug Device.]]<br />
<br />
Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.<br />
<br />
The '''EHCI Debug Port''' is an optional capability of EHCI controllers which can be used for that purpose.<br />
<br />
All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.<br />
<br />
While the '''Debug Class''' functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.<br />
<br />
== Supported chipsets ==<br />
<br />
The following southbridges have USB debug support in coreboot:<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background:lime" | OK<br />
| Tested by [[User:Uwe|Uwe Hermann]].<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700<br />
| style="background:orange" | WIP<br />
| Probably won't work, a patch is being prepared.<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB900<br />
| style="background:lime" | OK<br />
| Tested on HP Pavilion m6 1035dx<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel<br />
| 82801GX (ICH7)<br />
| style="background:lime" | OK<br />
| Tested by [[User:SvenS|Sven Schnelle]] on Lenovo Thinkpad X60/T60. <br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<br />
| Tested by [[User:Uwe|Uwe Hermann]]. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966<br />
| style="background:yellow" | Untested<br />
| '''Note:''' It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).<br />
<br />
|}<br />
<br />
== Finding the USB debug port ==<br />
<br />
Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port is rather difficult because you need to look at lots of information.<br />
<br />
Carl-Daniel Hailfinger [http://www.coreboot.org/pipermail/coreboot/2008-September/038618.html has written] [http://www.coreboot.org/pipermail/coreboot/attachments/20080909/ae11c291/attachment.sh a script] which can help finding that port.<br />
<br />
An [http://www.coreboot.org/pipermail/coreboot/attachments/20140530/245547f8/attachment.sh updated script] was posted [http://www.coreboot.org/pipermail/coreboot/2014-May/078022.html here] on May 30 2014.<br />
<br />
== Using the EHCI debug port ==<br />
<br />
=== usb_debug kernel module and minicom ===<br />
<br />
To get a USB debug console, enable '''CONFIG_USBDEBUG''' (menu option '''USB 2.0 EHCI debug dongle support''') in coreboot's kconfig.<br />
<br />
On your "host PC" you need a Linux system which is recent enough to provide the '''usb_debug''' kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a '''/dev/ttyUSB0''' device to which you can connect as usual using any serial terminal program, e.g. '''minicom''' (115200, 8n1).<br />
<br />
TODO: Is the Baud rate actually configurable somewhere?<br />
<br />
You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.<br />
<br />
Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.<br />
<br />
=== usb_debug_io.c ===<br />
<br />
As an alternative, you can also use [http://tracker.coreboot.org/trac/coreboot/ticket/57 this small libusb-based user-space program] on the host PC to retrieve the coreboot logs.<br />
<br />
== Hardware capability ==<br />
<br />
The Debug Port is optional, please check if EHCI controllers near you support it:<br />
<br />
$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do<br />
$ ''' lspci -vs $i'''<br />
$ '''done'''<br />
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])<br />
Subsystem: IBM Unknown device 0566<br />
Flags: bus master, medium devsel, latency 0, IRQ 5<br />
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]<br />
Capabilities: [50] Power Management version 2<br />
Capabilities: [58] '''Debug port'''<br />
<br />
Look for a line like the last one above. Please include the PCI device ID too:<br />
<br />
$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do<br />
$ ''' lspci -ns $i'''<br />
$ '''done'''<br />
00:1d.7 0c03: 8086:265c (rev 03)<br />
<br />
If your controller isn't already listed below then please add it or send an email to the [[Mailinglist|mailing list]] if you don't have a wiki account yet and want one, or want us to add your controller to the page.<br />
<br />
=== Controllers verified to have the debug port capability ===<br />
<br />
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)<br />
* 8086:24cd Intel ICH4/ICH4-M<br />
* 8086:24dd Intel ICH5<br />
* 8086:265c Intel ICH6<br />
* 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)<br />
* 8086:27cc Intel ICH7<br />
* 8086:2836 Intel ICH8<br />
* 8086:283a Intel ICH8<br />
* 8086:293a Intel ICH9 (rev 2)<br />
* 8086:3a3a Intel ICH10<br />
* 8086:3a3c Intel ICH10<br />
* 10de:0088 NVIDIA MCP2A (rev a2)<br />
* 10de:005b NVIDIA CK804 (rev a3)<br />
* 10de:026e NVIDIA MCP51 (rev a3)<br />
* 10de:036d NVIDIA MCP55 (rev a2)<br />
* 10de:03f2 NVIDIA MCP61 (rev a3)<br />
* 1002:4386 ATI/AMD SB600<br />
* 1002:4396 ATI/AMD SB700<br />
* 1106:3104 VIA VX800 (rev 90)<br />
<br />
=== Controllers verified to lack the debug port capability ===<br />
<br />
* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)<br />
* 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)<br />
* 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)<br />
* 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)<br />
* 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)<br />
* 1039:7002 SiS EHCI (rev 00)<br />
<br />
== Devices/Dongles ==<br />
<br />
To be able to use the debug port it needs to be connected to a compatible device.<br />
Currently there seems to be only two commercial devices available which can use the EHCI Debug Port, the '''NET20DC''' and the '''AMIDebug RX'''.<br />
<br />
=== DIY ===<br />
But you can also make your own usb debug dongle, see [[DIY_EHCI_debug_dongle]].<br />
<br />
=== NET20DC ===<br />
<br />
* [http://web.archive.org/web/20080219120613/http://www.plxtech.com/products/NET2000/NET20DC/default.asp http://www.plxtech.com/products/NET2000/NET20DC/default.asp] (archive.org)<br />
* http://www.semiconductorstore.com/cart/pc/viewPrd.asp?idproduct=12083<br />
* http://www.semiconductorstore.com/pages/asp/supplier.asp?pl=0121<br />
* http://www.ajaystech.com/net20dc.htm<br />
* http://www.ajaystech.com/resources.htm<br />
<br />
=== AMIDebug RX ===<br />
<br />
* http://www.ami.com/amidebugrx/<br />
<br />
=== EHCI Debug gadget driver ===<br />
If you have a device running GNU/Linux that has an usb device port, you could then try to use the [[EHCI Gadget Debug]].<br />
Note that it's not guaranteed to work on old kernels, and may be dependant on the usb device/otg controller driver.<br />
<br />
== More information ==<br />
<br />
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) &mdash; The Debug Port is described in Appendix C.<br />
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) &mdash; This is what has to be connected to the EHCI controller.<br />
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) &mdash; ''dead URL''<br />
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]<br />
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]<br />
* http://coreboot.org/pipermail/coreboot/2006-December/thread.html#17480<br />
* http://lkml.org/lkml/2006/12/1/214<br />
* http://www.usb.org/developers/presentations/pres0602/john_keys.pdf<br />
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5c05917e7fe313a187ad6ebb94c1c6cf42862a0b Linux early USB Debug Port support finally commited]<br />
* [http://www.kernel.org/doc/Documentation/x86/earlyprintk.txt early printk support in Linux]<br />
* http://www.spinics.net/lists/linux-usb/msg32912.html (Linux USB EHCI Debug Port device gadget)</div>Idwerhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=14704Board:lenovo/x60/Installation2014-10-20T16:05:57Z<p>Idwer: /* Step 3: Build Macronix-patched Flashrom */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
{{Note|If you plan to use Libreboot with the T60 (FSF-Certified, cannot use proprietary blobs), it requires a ''ThinkPad T60 with Intel GPU and a 15" Flexview 1400x1050 SXGA+ display'' (1600x1200, 2048x1536, and 14.1" 1400x1050 panels are also known to work).<br />
<br />
The libreboot project lists compatible screens at the time of writing, using changeset 5345 from review.coreboot.org: [http://libreboot.org/docs/index.html#supported_t60_list list of known-working lcd panels]<br />
<br />
Thus, Libreboot users will have to make a custom FrankenPad; either by replacing the motherboard with an Intel board; or the screen and the inverter with an SXGA+ display, at great expense.}}<br />
<br />
{{Warning|The vast majority of ThinkPad T60/T60p laptops require [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p proprietary VGABIOS blobs] for the display to work (see the links for more information). '''Do not forget to build Coreboot with these blobs, or your machine will be BRICKED!'''<br />
<br />
* '''ThinkPad T60/T60p laptops with a 4:3 1024x768 XGA, or 16:10 Widescreen LCD''' [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p must extract the proprietary VGABIOS from the Lenovo BIOS, and build Coreboot with it.]<br />
** ''(Libreboot Users)'' [http://libreboot.org/docs/index.html#supported_t60_list These LCDs do not work with Libreboot.] You will have to replace them with a rare and expensive Flexview 1400x1050 SXGA+ display; which is only compatible with 15" ThinkPad T60/T60p models. <br />
* '''ThinkPad T60/T60p laptops with an ATI GPU''' [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p must extract the proprietary VGABIOS from the Lenovo BIOS, and build Coreboot with it.]<br />
** All ThinkPad T60p and all Flexview SXGA+ T60 laptops come with an ATI GPU.<br />
** ''(Libreboot Users)'' Needless to say, [http://libreboot.org/docs/index.html#t60_ati_intel ATI T60/T60p laptops are NOT compatible with Libreboot.] You must replace the motherboard with an Intel one.}}<br />
<br />
= Libreboot Flashing Procedure (Easy Method) =<br />
<br />
{{Note|Libreboot is not officially part of the coreboot project. Do not contact coreboot for support; instead, contact the libreboot community.}}<br />
<br />
The [http://libreboot.org/ Libreboot distribution] distributes pre-compiled ROM images along with scripts and instructions for easy flashing. Choose between these two guides:<br />
<br />
* [http://libreboot.org/docs/index.html Official Libreboot Documentation] - Official documentation created by the Libreboot developers themselves.<br />
** '''Note:''' If you choose to follow the Official Libreboot Documentation, make sure to follow the Lenovo BIOS Backup procedure details below.<br />
* [https://github.com/bibanon/Coreboot-ThinkPads/wiki BASLQC Libreboot ThinkPad Guides] - Vastly streamlined unofficial Libreboot installation guide. Organized in a more straightforward fashion, and has a few tips and tricks for specific devices.<br />
** [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X60 ThinkPad X60 and X60 Tablet]<br />
** [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60 ThinkPad T60 (Intel GPU)]<br />
** [https://github.com/bibanon/Coreboot-ThinkPads/wiki/Macbook-2-1 Macbook 2 1]<br />
** [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p ThinkPad T60/T60p (ATI GPU)] - Requires proprietary VGABIOS.<br />
<br />
=== Back up Official Lenovo BIOS (Libreboot) ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/docs/release.html Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory, enter the {{ic|flashrom/}} directory. <br />
#: {{ic|cd flashrom}}<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# If a {{ic|factory.bin}} file was created in the {{ic|flashrom/}} directory, the Lenovo BIOS has been backed up successfully. If not, try the commands again. Copy this dump to a safe place.<br />
# Return to the {{ic|libreboot_bin/}} directory. <br />
#: {{ic|cd ..}}<br />
<br />
* Source: [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X60#back-up-official-lenovo-bios BASLQC Libreboot ThinkPads - Backing up the Lenovo BIOS on the ThinkPad X60]<br />
<br />
= Coreboot Flashing Procedure (Advanced) =<br />
<br />
Below is a procedure that describes all the steps needed to flash Coreboot, in fine detail.<br />
<br />
The Libreboot scripts have fully automated this complicated process, so these instructions have been expanded for educational purposes.<br />
<br />
== Briefing ==<br />
<br />
* '''Some SPI Flash chips require ''special flashrom patches''.'''<br />
** Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte.<br />
** Unfortunately, the vendor BIOS forbids higher quality identification commands, so flashrom must be patched to use the lower quality opcodes. <br />
** This type of patch will never be merged upstream, so it must be applied manually.<br />
<br />
* '''The ''BUCTS register bit'' must be flipped before flashing Coreboot.'''<br />
** [http://git.stuge.se/?p=bucts.git The bucts utility] can be used to flip the bit.<br />
** This register bit doubles as a unique safety net that allows the vendor BIOS and Coreboot to coexist.<br />
** Just unplug the CMOS battery to return to the vendor BIOS, in case Coreboot doesn't boot.<br />
<br />
* '''The Coreboot ROM has to be specially patched to prevent it from overwriting the vendor BIOS.'''<br />
** If the vendor BIOS gets overwritten, it would defeat the purpose of the BUCTS safety net.<br />
** Just use this convenient little Bash one-liner to leave some free space at the beginning of the ROM.<br />
*: {{ic|1=dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k; dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump; dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc}}<br />
<br />
* '''It is important to figure out ''what type of flashchip'' is on the motherboard.'''.<br />
** Early Coreboot developers had to disassemble the entire laptop just to take a peek at the flashchip. A magnifying glass is needed to read the tiny text burned on top of the chip.<br />
** The Libreboot installation scripts have '''an ingenious new brute-force method''' of identifying the flashchip.<br />
** First, build two patched flashrom binaries, one for SST and one for Macronix. Then try both of the binaries until you find one that works. <br />
** Seems way too simple, but it's way better than ripping out the motherboard just to look at a chip.<br />
<br />
== Flashrom Patch Definitions ==<br />
<br />
: ''Source: [https://github.com/bibanon/Coreboot-ThinkPads/wiki/BIOS-Flashchip-Identification-Method#use-flashrom-to-identify-bios-chip-experimental BASQLC Libreboot ThinkPads - BIOS Flashchip Identification Method]''<br />
<br />
Flashrom must be patched to use RES SPI identification and {{ic|spi_chip_write_1}} for your flash chip, and to set the flash chip {{ic|model_id}} to the RES opcode. <br />
<br />
Below are the definitions that must be patched into {{ic|flashrom/flashchips.c}} :<br />
<br />
* '''SST25VF016B'''<br />
** .probe - {{ic|probe_spi_res2}}<br />
** .model_id - {{ic|0x41}}<br />
** .write - {{ic|spi_chip_write_1}}<br />
* '''MX25l1605D'''<br />
** .probe - {{ic|probe_spi_res1}}<br />
** .model_id - {{ic|0x14}}<br />
** .write - {{ic|spi_chip_write_1}}<br />
* '''Atmel ???''' (T60 Only?)<br />
** Use -p internal:laptop=force_I_want_a_brick instead of -p internal, when running flashrom<br />
** No patches necessary. You still need to do 2 flashing rounds, with the bucts/dd trick outlined in this guide.<br />
<br />
These definitions were painstakingly discovered from excessively long and hardly informative flashchip documentation, mailing lists, and the output of flashrom. These definitions been confirmed to work after rigorous testing, [https://github.com/bibanon/Coreboot-ThinkPads/wiki/BIOS-Flashchip-Identification-Method#use-flashrom-to-identify-bios-chip-experimental See this wiki page for more information.]<br />
<br />
* [http://paste.flashrom.org/view.php?id=1454 Flashrom Pastebin - Thinkpad R60 Flashrom Output] - Probing for SST SST25VF016B.RES2, 2048 kB: probe_spi_res2: id1 0xbf, id2 0x41<br />
* [http://www.coreboot.org/pipermail/coreboot/2013-June/075962.html Coreboot Mailing List - Invalid OPCODE] - Allows us to infer that the model_id for {{ic|SST25VF016B}} is 0xbf<br />
* [http://coreboot.org/pipermail/coreboot/2013-June/076027.html Coreboot Mailing List - Bricked Lenovo T60]<br />
* [http://macbook.donderklumpen.de/coreboot/ Donderclumpen - Coreboot on Macbook 2,1]] - Found {{ic|id1 0xbf, id2 0x2541}} there, which corroborates with the inference from Peter Stuge.<br />
* [http://ww1.microchip.com/downloads/en/DeviceDoc/S71271_04.pdf SST - SST25VF016B Official Datasheet]<br />
<br />
== What You Need ==<br />
<br />
* The [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom)<br />
* Flashrom patches for SST and Macronix flashchip support (provided in the next section).<br />
* [http://git.stuge.se/?p=bucts.git The bucts utility].<br />
* '''Dependencies''' (Debian/Ubuntu/Trisquel):<br />
** '''Version Control''' - {{ic|sudo apt-get install subversion git}}<br />
** '''Build Essentials''' - {{ic|sudo apt-get -y install build-essential}}<br />
** '''flashrom''' - {{ic|sudo apt-get install libpci-dev pciutils zlib1g-dev libftdi-dev}}<br />
** '''Coreboot''' - {{ic|sudo apt-get install libncurses-dev iasl libc6-dev bison flex git}}<br />
** '''GRUB2''' (optional) - {{ic|sudo apt-get install bison libopts25 libselinux1-dev autogen m4 autoconf help2man libopts25-dev flex libfont-freetype-perl automake autotools-dev libfreetype6-dev texinfo ttf-unifont}}<br />
<br />
== Patch Flashrom ==<br />
<br />
: ''Source: [https://github.com/bibanon/Coreboot-ThinkPads/wiki/BIOS-Flashchip-Identification-Method BASQLC Libreboot ThinkPads - Flashrom Patches]''<br />
<br />
This method uses the ''brute force flashchip identification method'' used in the Libreboot flashing scripts. The idea is, if the patched flashrom can't identify the chip, it won't do anything; so why not try both patches?<br />
<br />
''The most reliable method to identify the flashchip is to visually identify it; but flipping the motherboard requires complete disassembly.''<br />
<br />
First, build both the SST and Macronix patches of Flashrom.<br />
<br />
=== Step 1: Build Normal Flashrom ===<br />
<br />
# Obtain the latest {{ic|flashrom}} source code with Subversion:<br />
#: {{ic|svn co svn://flashrom.org/flashrom/trunk flashrom}}<br />
# Build {{ic|flashrom</code> using the <code>make}} command.<br />
#: {{ic|make}}<br />
# Rename the {{ic|flashrom</code> binary to <code>flashrom_orig}} .<br />
#: {{ic|mv flashrom flashrom_orig}}<br />
<br />
=== Step 2: Build SST-patched Flashrom ===<br />
<br />
# Open the <code>flashchips.c</code> file in the <code>flashrom</code> source code directory.<br />
# Use '''Ctrl-F''' to find the {{ic|SST25VF016B}} entry.<br />
# Modify the <code>.probe</code> , <code>.model_id</code> , and <code>.write</code> definitions with the following values.<br />
#* .probe - {{ic|probe_spi_res2}}<br />
#* .model_id - {{ic|0x41}}<br />
#* .write - {{ic|spi_chip_write_1}}<br />
# The result should look something like this:<br />
<br />
{{bc|1={<br />
.vendor = "SST",<br />
.name = "SST25VF016B",<br />
.bustype = BUS_SPI,<br />
.manufacture_id = SST_ID,<br />
.model_id = 0x41,<br />
.total_size = 2048,<br />
.page_size = 256,<br />
.feature_bits = FEATURE_WRSR_EITHER,<br />
.tested = TEST_OK_PREW,<br />
.probe = probe_spi_res2,<br />
/*<br />
unimportant code statements<br />
in between, leave them alone<br />
*/<br />
.write = spi_chip_write_1,<br />
.read = spi_chip_read,<br />
.voltage = {2700, 3600},<br />
},}}<br />
<br />
# Build <code>flashrom</code> using the <code>make</code> command.<br />
#: {{ic|make}}<br />
# Rename the <code>flashrom</code> binary to <code>flashrom_lenovobios_sst</code> .<br />
#: {{ic|mv flashrom flashrom_lenovobios_sst}}<br />
<br />
=== Step 3: Build Macronix-patched Flashrom ===<br />
<br />
# Revert the changes previously made to flashchips.c<br />
# Use '''Ctrl-F''' to find the {{ic|MX25L1605D}} entry.<br />
# Modify the <code>.probe</code> , <code>.model_id</code> , and <code>.write</code> definitions with the following values.<br />
#* .probe - {{ic|probe_spi_res1}}<br />
#* .model_id - {{ic|0x14}}<br />
#* .write - {{ic|spi_chip_write_1}}<br />
# The result should look something like this:<br />
<br />
{{bc|1={<br />
.vendor = "Macronix",<br />
.name = "MX25L1605D/MX25L1608D/MX25L1673E",<br />
.bustype = BUS_SPI,<br />
.manufacture_id = MACRONIX_ID,<br />
.model_id = 0x14,<br />
.total_size = 2048,<br />
.page_size = 256,<br />
.feature_bits = FEATURE_WRSR_WREN,<br />
.tested = TEST_OK_PREW,<br />
.probe = probe_spi_res1,<br />
/*<br />
unimportant code statements<br />
in between, leave them alone<br />
*/<br />
.write = spi_chip_write_1,<br />
.read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */<br />
.voltage = {2700, 3600},<br />
},}}<br />
<br />
# Build <code>flashrom</code> using the <code>make</code> command.<br />
#: {{ic|make}}<br />
# Rename the <code>flashrom</code> binary to <code>flashrom_lenovobios_macronix</code> .<br />
#: {{ic|mv flashrom flashrom_lenovobios_macronix}}<br />
# Revert the changes previously made to flashchips.c<br />
<br />
=== Step 4: Rename the Vanilla Flashrom Binary ===<br />
<br />
We renamed the untouched flashrom binary to {{ic|flashrom_orig}}, so that it wouldn't be overwritten. Now we need to restore the original name.<br />
<br />
# Rename the <code>flashrom_orig</code> binary to <code>flashrom</code> .<br />
#: {{ic|mv flashrom_orig flashrom}}<br />
<br />
== Back up Official Lenovo BIOS ==<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Enter the {{ic|flashrom/}} directory. <br />
#: {{ic|cd flashrom}}<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -r factory.bin -c "MX25L1605"}}<br />
# If a <code>factory.bin</code> file was created in the <code>flashrom/</code> directory, the Lenovo BIOS has been backed up successfully. If not, try the commands again. Copy this dump to a safe place.<br />
# Return to the {{ic|libreboot_bin/}} directory. <br />
#: {{ic|cd ..}}<br />
<br />
* Source: [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X60#back-up-official-lenovo-bios BASLQC Libreboot ThinkPads - Backing up the Lenovo BIOS on the ThinkPad X60]<br />
<br />
== Build the Coreboot ROM ==<br />
<br />
{{Warning|The vast majority of ThinkPad T60/T60p laptops require [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p proprietary VGABIOS blobs] for the display to work. If you forget to install them, your machine will be BRICKED!}}<br />
<br />
* See [http://www.coreboot.org/Build_HOWTO Build HOWTO] for how to build ROM images in coreboot.<br />
** ''(optional)'' If you need to obtain and embed the VGABIOS in Coreboot (e.g. T60 with ATI GPU, text in SeaBIOS), [https://github.com/bibanon/Coreboot-ThinkPads/wiki/T60p-Extract-VGABIOS follow this procedure.]<br />
** [https://github.com/bibanon/Coreboot-ThinkPads/wiki/T60p-Build-Coreboot Here is a clearer guide] which shows exactly how to build Coreboot, set up the {{ic|.config}} file, and embed the VGABIOS.<br />
<br />
== Patch Coreboot ROM for bucts ==<br />
<br />
The BUCTS switch provides a safety net in case Coreboot does not run the first time; just unplug the CMOS battery to return to the vendor BIOS.<br />
<br />
This patch prevents the Coreboot ROM from overwriting the vendor BIOS (which would destroy the safety net). ''Choose one method:''<br />
<br />
=== Method 1: One-line Patcher===<br />
<br />
# Place the {{ic|coreboot.rom}} file in the current directory.<br />
# Run this one-liner to patch the ROM in one command:<br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k; dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump; dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
=== Method 2: Verbose Method ===<br />
<br />
# Copy the built {{ic|coreboot.rom</code> to the <code>flashrom}} source code directory.<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
# Copy the {{ic|coreboot.rom</code> to the <code>flashrom/}} directory.<br />
# Run {{ic|su}} to become root.<br />
# Run {{ic|bucts 1}} <br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since half the flashchip is write protected). <br />
# Check to make sure that the errors match the following:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are an exact match, the flash was successful.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''. Flash again.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot). Your laptop will reboot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, but GNU/Linux should work fine after booting.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
=== Recover from Failed Flash with Bucts ===<br />
<br />
{{Note|If you forgot to set {{ic|bucts 1}} , forgot to install the proprietary VGABIOS blob on T60 systems with ATI GPUs or 1024x768 screens, or forgot to patch the Coreboot ROM; your laptop has been bricked, and requires hardware flashing for recovery.}}<br />
<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a CMOS battery on the mainboard.<br />
<br />
# Unscrew the keyboard (check Lenovo Hardware Maintenence Manual for more info).<br />
# Remove the keyboard. <br />
# Unplug the CMOS battery (it's a yellow circle). <br />
# Wait a few seconds, and plug it back in.<br />
# Reassemble the ThinkPad.<br />
# Turn the ThinkPad back on.<br />
#* On the ThinkPad x60 series, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
<br />
Afterwards, the register should be reset and the system should boot into the vendor BIOS.<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS.<br />
<br />
# Run {{ic|su}} to become root.<br />
# Enter the {{ic|flashrom}} directory.<br />
# Run {{ic|./flashrom -p internal -w coreboot.rom}} <br />
#: This will successfully overwrite the entire flash chip with no errors, including the last 64k that were write protected with the factory BIOS.<br />
#: If it complains about 3 different flashchips (in the case of macronix chip), do this instead:<br />
#: Run {{ic|./flashrom -p internal -w coreboot.rom -c "MX25L1605D/MX25L1608D/MX25L1673E"}} <br />
# Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
{{Note|The BASLQC provides a more comprehensive guide to hardware-based firmware flashing below, with research on a Raspberry Pi-based hardware flasher: (Not a Coreboot project)<br />
* [https://github.com/bibanon/Coreboot-ThinkPads/wiki/X60-T60-Hardware-Flashing BASLQC Libreboot ThinkPads - Hardware-based Firmware Flashing]}}<br />
<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Disassembling the ThinkPad ===<br />
<br />
Follow the [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] to disassemble the laptop, until you can access the flash chip.<br />
<br />
(photos needed)<br />
<br />
* On the X60, the flash chip is on the bottom of the motherboard, under a layer of protective black tape.<br />
* On the T60, the flash chip is just under the palmrest, but blocked by a magnesium frame (which you will have to remove).<br />
<br />
=== Bus Pirate + SOIC Clip Configuration ===<br />
<br />
Below is a diagram of how to plug the Bus Pirate into the SOIC Clip, with colors based on [http://dangerousprototypes.com/docs/Common_Bus_Pirate_cable_pinouts the Seeed Studio pinout.] Your cable colors may differ (such as the Sparkfun layout).<br />
<br />
<pre>8765<br />
----<br />
| |<br />
----<br />
1234</pre> <br />
<br />
# CS (white)<br />
# MISO (black)<br />
# ''not used''<br />
# GND (brown)<br />
# MOSI (gray)<br />
# CLK (purple)<br />
# ''not used''<br />
# 3.3V (red) - Depends on chip<br />
<br />
{{Note|Make sure the pinouts are correct; otherwise, Bus Pirate will fail to detect a chip, or it will "detect" an {{ic|0x0}} chip.}}<br />
<br />
Finally, make sure that the Pomona clip makes contact with the metal wires of the chip. It can be a challenge, but keep trying.<br />
<br />
=== How to supply power to the flashchip ===<br />
<br />
There are two ways to supply power to the chip: plugging in an AC adapter (without turning it on), and using the 8th 3.3v pin.<br />
<br />
I have found that the SST chips work best with the 8th pin, while the Macronix chips require an AC Adapter to power up.<br />
<br />
Your results may vary.<br />
<br />
== Reading the Flashchip with Bus Pirate ==<br />
<br />
# Visually inspect (with a magnifying glass) the type of flashchip on the motherboard.<br />
# Clip the Pomona SOIC-8 Clip onto the flashchip. Make sure that the Bus Pirate is connected to it as shown above.<br />
# download and extract the Libreboot binaries, and enter the {{ic|libreboot_bin/flashrom}} directory.<br />
<br />
{{bc|cd libreboot_bin/flashrom}} <br />
If it is an SST, run this command:<br />
<br />
{{bc|1=sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -r test.rom}} <br />
If it is a Macronix, run this command:<br />
<br />
{{bc|1=sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -r test.rom -c "MX25L1605D/MX25L1608D/MX25L1673E"}} <br />
Next, check the sha512sum of the dump:<br />
<br />
{{bc|sha512sum test.rom}} <br />
Run the {{ic|flashrom}} command again to make a second dump. Then, check the sha512sum of the second dump:<br />
<br />
{{bc|sha512sum test.rom}} <br />
If the sha512sums match after three tries, {{ic|flashrom}} has managed to read the flashchip precisely (but not always accurately). You may try and flash Libreboot now.<br />
<br />
== Flashing Libreboot with Bus Pirate ==<br />
<br />
{{Note|replace <code>/path/to/libreboot.rom</code> with the location of your chosen ROM, such as <code>../bin/x60/libreboot_usqwerty.rom</code>):}}<br />
<br />
If your chip is SST, run this command:<br />
<br />
{{bc|1=sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w /path/to/libreboot.rom}} <br />
<br />
If your chip is Macronix, run this command:<br />
<br />
{{bc|1=sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w /path/to/libreboot.rom -c "MX25L1605D/MX25L1608D/MX25L1673E" }}<br />
<br />
Once that command outputs the following, the flash has completed successfully. If not, just flash again.<br />
<br />
{{bc|Reading old flash chip contents... done.Erasing and writing flash chip... Erase/write done.Verifying flash... VERIFIED.}}<br />
<br />
=== Howto (old) ===<br />
<br />
{{Note|The libreboot project also has picture guides showing disassembly and external flashing instructions ('''these 3 links are to the libreboot project. Contact libreboot, *not* coreboot, for support'''):<br />
* [http://libreboot.org/docs/howtos/x60_unbrick.html X60/X60s unbricking guide]<br />
* [http://libreboot.org/docs/howtos/x60tablet_unbrick.html X60 Tablet unbricking guide]<br />
* [http://libreboot.org/docs/howtos/t60_unbrick.html T60 unbricking guide]<br />
<br />
The libreboot guides linked above are based on the information below from the coreboot project.}}<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Idwerhttps://www.coreboot.org/index.php?title=EHCI_Gadget_Debug&diff=13730EHCI Gadget Debug2014-05-25T23:47:32Z<p>Idwer: /* Loading */</p>
<hr />
<div>== Introduction ==<br />
This page is about using embedded GNU/Linux devices in order to get the USB debug logs.<br />
<br />
== Howto ==<br />
=== Patching ===<br />
Download the [[:File:Ehci-debug-gadget-patches.tar.gz|patches]] that maintain TTY connected while debug target power-cycles or when host controller is reset.<br />
<br />
Apply the patches from one of the v3.8- or v3.10-debug-gadget directories on your kernel build tree.<br />
<br />
=== Compiling ===<br />
* You need to be familiar with (cross) compiling your kernel.<br />
* (Cross) compile it as usual but during the configuration do the following:<br />
Go into Device Drivers:<br />
Device Drivers ---><br />
Then go into USB support:<br />
[*] USB support ---><br />
Then go into USB Gadget Support:<br />
<M> USB Gadget Support ---><br />
Then enable the following option:<br />
<M> EHCI Debug Device Gadget<br />
Then select the serial option:<br />
EHCI Debug Device mode (serial) ---><br />
<br />
=== Loading ===<br />
Remove all usb gadget drivers such as g_ether or g_mass_storage with rmmod then do:<br />
modprobe g_dbgp<br />
<br />
=== Running ===<br />
I recommend to open the TTY before starting debug target. Doing it the other way<br />
around slows down the debug target boot and seems to confuse serial gadget framework.<br />
<br />
You may want to disable some CR/LF translations on the device:<br />
stty -icrnl -inlcr -F /dev/ttyGS0<br />
<br />
You can directly open the device node, possibly redirecting to file:<br />
cat /dev/ttyGS0<br />
.. or use a terminal client:<br />
picocom -ir /dev/ttyGS0<br />
<br />
=== Finding the USB debug port ===<br />
See [[EHCI Debug Port#Finding the USB debug port]]<br />
<br />
== Tested hardware ==<br />
{| class="wikitable" border="1"<br />
! Brand and Device<br />
! kernel used<br />
! Target devices<br />
! works?<br />
|-<br />
! [http://projects.goldelico.com/p/gta04-main/ Goldelico GTA04 A3]<br />
| [https://github.com/goldelico/gta04-kernel/commits/neil-plus neil-plus kernel and branch (3.7)]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
! [http://wiki.buglabs.net/index.php/Welcome_to_BUG_Wiki Buglabs's bug 2.0]<br />
| [https://github.com/buglabs/bug20-2.6.35-linaro/commits/master bug20-2.6.35-linaro's master (2.6.35) ]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
|}</div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13481Board:asus/f2a85-m2014-03-18T00:12:32Z<p>Idwer: /* Supported CPUs */</p>
<hr />
<div>== Status ==<br />
<br />
=== Supported Board Variants ===<br />
<br />
Only the Asus F2A85-M and Asus F2A85-M CSM are supported. However there is a chance that "PRO" or other variants could be easily supported (contact via mailing list for details).<br />
<br />
=== Supported CPUs ===<br />
<br />
Note: Only the trinity CPU are supported (see list below) but with a hack also Richland CPUs might work (contact via mailing list for details).<br />
<br />
* AMD Athlon X2 340<br />
* AMD Athlon X4 740<br />
* AMD Athlon X4 750k<br />
* AMD FirePro A300<br />
* AMD FirePro A320<br />
* AMD A4-5300<br />
* AMD A4-5300B<br />
* AMD A6-5400K<br />
* AMD A6-5400B<br />
* AMD A8-5500<br />
* AMD A8-5500B<br />
* AMD A8-5600K<br />
* AMD A10-5700<br />
* AMD A10-5800B<br />
* AMD A10-5800K<br />
<br />
This list might be maintained more actively: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29<br />
<br />
=== Notes ===<br />
<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* blink in suspend mode<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = the board will start with an AMD A8-5500<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== UEFI builds that allow flash chip access ==<br />
<br />
* v5016 is untested, but expected to work as well<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402 <br />
* v6404 (requires downgrading to v6402 to flash coreboot)<br />
* v6501 (requires downgrading to v6402 to flash coreboot)<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
If you use single dimm plug it to DIMM_A2 or DIMM_B2.<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Git&diff=13423Git2014-03-05T15:49:58Z<p>Idwer: /* Commit messages */</p>
<hr />
<div>= Gerrit =<br />
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.<br />
<br />
== Register with gerrit ==<br />
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br />
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.<br />
<br />
=== OpenID ===<br />
Gerrit uses OpenID for authentication. Besides many large web services that provide OpenID identity services (eg. Google, Yahoo), you can run your own, if you want.<br />
<br />
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive (but will improve in the future)<br />
<br />
== Gerrit workflow ==<br />
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br />
<br />
Reviews grant points on a scale from -2 to 2. The meaning is:<br />
* -2: Do not merge (blocks gerrit from merging)<br />
* -1: I'd prefer you don't merge it<br />
* 0: neutral<br />
* +1: Looks good, but I won't make the last call on it<br />
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)<br />
<br />
-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br />
<br />
=== Gerrit and CLI ===<br />
Reviews normally happens through the website.<br />
<br />
Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled. You can find the official Gerrit documentation about its CLI tools [http://gerrit.googlecode.com/svn/documentation/2.0.34/cmd-index.html here].<br />
<br />
=== Gerrit and Email ===<br />
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br />
<br />
This gateway will provide:<br />
* no patch submission mechanism ("git push" is CLI friendly)<br />
* patch review (maybe openpgp signed "Acked-by" mails)<br />
* patch submission (automatically with Acked-by?)<br />
* maybe patch rejection? (openpgp signed "Nacked-by" mails)<br />
<br />
= Accessing the repository =<br />
The repository can be accessed using ssh (with public key authentication) or http (anonymous read-only or read-write using user/password authentication). The latter is particularily interesting for people behind firewalls, but requires git to be version 1.6.6 or newer (for "Smart HTTP" transfer). The http password can be generated (and regenerated if necessary) at http://review.coreboot.org/#settings,http-password.<br />
<br />
git clone ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
git clone <nowiki>http://[<username>:<password>@]review.coreboot.org/p/coreboot.git</nowiki><br />
<br />
Inside the checkout you should install a commit-msg hook that adds a Change-Id into commit messages, which uniquely identifies the logical change in Gerrit even across multiple iterations of the commit. The hook only needs to be installed once per clone, and installation can be done with<br />
<br />
wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \<br />
chmod +x .git/hooks/commit-msg<br />
<br />
Or you can also just run<br />
<br />
make gitconfig<br />
<br />
= Working with Git =<br />
<br />
Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065422.html a Git introduction] after the switch to Git had been announced on the mailing list.<br />
<br />
== Commit messages ==<br />
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br />
<br />
# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary<br />
# The second line is empty (no whitespace at all)<br />
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br />
::'''Shell syntax is not relevant background information!'''<br />
# The next line is empty (no whitespace at all)<br />
# A Change-Id: line to let gerrit track this logical change<br />
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br />
<br />
Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Accessing_the_repository|above]], and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.<br />
<br />
Here is an example of a well-formatted commit message:<br />
examplecomponent: Refactor duplicated setup into a function<br />
<br />
Setting up the demo device correctly requires the exact same register<br />
values to be written into each of the PCI device functions. Moving the<br />
writes into a function allows also otherexamplecomponent to use them.<br />
<br />
Signed-off-by: Joe Hacker <joe@hacker.email><br />
<br />
The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br />
<br />
=== Guidelines on commit message content ===<br />
<br />
* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.<br />
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:<br />
git show<br />
<br />
== Pushing changes ==<br />
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[Git#Authenticated read/write access|Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br />
<br />
git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br />
<br />
git config remote.origin.push HEAD:refs/for/master<br />
<br />
After this, the command to push your changes is:<br />
<br />
git push origin<br />
<br />
If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br />
<br />
git config branch.<particularbranchname>.remote origin<br />
<br />
...after which you then push changes with any of the configured branches checked out with a simple:<br />
<br />
git push<br />
<br />
Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br />
<br />
'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br />
<br />
git log origin/master..<br />
<br />
before '''git push''' to verify which commits you are about to send for review.<br />
<br />
For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].<br />
<br />
== Pushing Drafts ==<br />
git push origin HEAD:refs/drafts/master<br />
== Pushing to Topics ==<br />
git push origin HEAD:refs/for/master/i915-kernel-x60<br />
will push to the i915-kernel-x60 topic.<br />
<br />
== Evolving patches ==<br />
<br />
Often it might happen that the patch you sent for approval is not good enough from the first attempt. Gerrit and git make it easy to track patch evolution during the review process until patches meet our quality standards and are ready for approval.<br />
<br />
You can easily modify a patch sent to gerrit by you or even by someone else. Just apply it locally using one of the possible ways to do it, make a new local commit that fixes the issues reported by the reviewers, then rebase the change by preserving the same Change-ID. We recommend you to use the git rebase command in interactive mode, <br />
<br />
git rebase -i master<br />
<br />
then commit and push the updated patch.<br />
<br />
Alternatively, you may amend your local commit and push the updated patch to gerrit:<br />
<br />
git add <path/to/updated/files><br />
git commit --amend<br />
<br />
then push the updated patch.<br />
<br />
== Further Git reading ==<br />
There are tons of git tutorials out there. Take a look at some of these documents:<br />
* http://git-scm.com/<br />
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html<br />
* http://git.or.cz/course/svn.html<br />
* and in particular the [http://progit.org/ Pro Git book]<br />
<br />
Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].<br />
<br />
= Browsing =<br />
<br />
See http://review.coreboot.org/gitweb?p=coreboot.git</div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13388Board:asus/f2a85-m2014-03-04T17:08:17Z<p>Idwer: /* UEFI builds that allow flash chip access */</p>
<hr />
<div>== Status ==<br />
<br />
=== Supported CPUs ===<br />
<br />
* AMD Athlon X2 340<br />
* AMD Athlon X2 740<br />
* AMD Athlon X2 750k<br />
* AMD FirePro A300<br />
* AMD FirePro A320<br />
* AMD A4-5300<br />
* AMD A4-5300B<br />
* AMD A6-5400K<br />
* AMD A6-5400B<br />
* AMD A8-5500<br />
* AMD A8-5500B<br />
* AMD A8-5600K<br />
* AMD A10-5700<br />
* AMD A10-5800B<br />
* AMD A10-5800K<br />
<br />
This list might be maintained more actively: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = the board will start with an AMD A8-5500<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== UEFI builds that allow flash chip access ==<br />
<br />
* v5016 is untested, but expected to work as well<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402 <br />
* v6404 (requires downgrading to v6402 to flash coreboot)<br />
* v6501 (requires downgrading to v6402 to flash coreboot)<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=GRUB2&diff=13363GRUB22014-02-21T03:03:24Z<p>Idwer: /* Compiling */</p>
<hr />
<div>'''[https://www.gnu.org/software/grub/grub.html GRUB 2]''' is a modular, multiboot-capable bootloader for many operating systems that can be used as a payload for coreboot. <br />
<br />
== Status ==<br />
GRUB 2 can be launched:<br />
* Directly by coreboot as a payload<br />
* Directly by SeaBIOS as a payload<br />
* By SeaBIOS, on disk, as it would with a normal BIOS.<br />
<br />
Recent git versions have improved memory management that removes the memory limitations when ran as a payload.<br />
<br />
== features ==<br />
=== Interesting features sumarry ===<br />
* It can open and boot from encrypted LUKS partitions.<br />
* It can verify the signatures of files ( interesting for initramfs and kernels )<br />
* has a "cbmemc" command that can see cbmem<br />
* it's compatible with the coreboot framebuffer.<br />
* it has some cmos commands that permits to interact with the nvram, like:<br />
** cmostest<br />
** cmosclear<br />
** cmosset<br />
** cmosdump<br />
* it can loads and run coreboot payloads from cbfs(both compressed and uncompressed), its memdisk, or any other filesystem it can read...<br />
<br />
=== Security ===<br />
==== signed kernels ====<br />
GRUB is capable of running only trusted(signed) kernels.<br />
* it supports both RSA and DSA gpg keys<br />
<br />
Here's a little howto.<br />
<br />
First generate a key:<br />
$ gpg --gen-key<br />
gpg (GnuPG) 2.0.19; Copyright (C) 2012 Free Software Foundation, Inc.<br />
This is free software: you are free to change and redistribute it.<br />
There is NO WARRANTY, to the extent permitted by law.<br />
<br />
Please select what kind of key you want:<br />
(1) RSA and RSA (default)<br />
(2) DSA and Elgamal<br />
(3) DSA (sign only)<br />
(4) RSA (sign only)<br />
Your selection? 3<br />
DSA keys may be between 1024 and 3072 bits long.<br />
What keysize do you want? (2048) 3072<br />
Requested keysize is 3072 bits<br />
Please specify how long the key should be valid.<br />
0 = key does not expire<br />
<n> = key expires in n days<br />
<n>w = key expires in n weeks<br />
<n>m = key expires in n months<br />
<n>y = key expires in n years<br />
Key is valid for? (0) <br />
Key does not expire at all<br />
Is this correct? (y/N) y<br />
<br />
GnuPG needs to construct a user ID to identify your key.<br />
<br />
Real name: Denis 'GNUtoo' Carikli<br />
Email address: GNUtoo@no-log.org<br />
Comment: Kernel signing key<br />
You selected this USER-ID:<br />
"Denis 'GNUtoo' Carikli (Kernel signing key) <GNUtoo@no-log.org>"<br />
<br />
Change (N)ame, (C)omment, (E)mail or (O)kay/(Q)uit? o<br />
You need a Passphrase to protect your secret key.<br />
<br />
We need to generate a lot of random bytes. It is a good idea to perform<br />
some other action (type on the keyboard, move the mouse, utilize the<br />
disks) during the prime generation; this gives the random number<br />
generator a better chance to gain enough entropy.<br />
gpg: WARNING: some OpenPGP programs can't handle a DSA key with this digest <br />
size<br />
gpg: key C86D4C64 marked as ultimately trusted<br />
public and secret key created and signed.<br />
<br />
gpg: checking the trustdb<br />
gpg: 3 marginal(s) needed, 1 complete(s) needed, PGP trust model<br />
gpg: depth: 0 valid: 2 signed: 0 trust: 0-, 0q, 0n, 0m, 0f, 2u<br />
pub 3072D/C86D4C64 2013-03-13<br />
Key fingerprint = 7244 AC33 F9A7 9AE8 30DE 8996 9097 B48D C86D 4C64<br />
uid Denis 'GNUtoo' Carikli (Kernel signing key) <br />
<GNUtoo@no-log.org><br />
<br />
Note that this key cannot be used for encryption. You may want to use<br />
the command "--edit-key" to generate a subkey for this purpose.<br />
Then sign the kernels and initramfs:<br />
cd /boot<br />
sudo -E gpg --detach-sign vmlinuz-linux-libre-pae<br />
sudo -E gpg --detach-sign initramfs-linux-libre-pae.img<br />
<br />
gpg --export > boot.key<br />
Then you can put the key on the memdisk (advised) or the boot partition for test purposes only.<br />
Then in GRUB do (for testing purposes):<br />
trust boot.key<br />
set check_signatures=enforce<br />
to only boot correctly signed kernels and initramfs...<br />
<br />
Then load kernel and initramfs as usual...<br />
<br />
==== Trisquel, Ubuntu, Debian ====<br />
We want automatics hooks to sign our kernel so we don't have to do it manually each time...<br />
The following howto was tested on trisquel 6<br />
Generate the key as root(sudo su) like we just explained, but without a password<br />
In debian based distributions you can hook the kernel build to sign the result:<br />
Add the following to /etc/kernel/postinst.d/yy-update-signatures<br />
#! /bin/sh<br />
set -e<br />
<br />
version="$1"<br />
<br />
rm -f /boot/vmlinuz-${version}.sig<br />
gpg --detach-sign /boot/vmlinuz-${version}<br />
rm -f /boot/initrd.img-${version}.sig<br />
gpg --detach-sign /boot/initrd.img-${version}<br />
Then do:<br />
chmod +x /etc/kernel/postinst.d/yy-update-signatures<br />
Then do:<br />
gpg --export > /boot/boot.key<br />
<br />
Then modify /etc/grub.d/10_linux to use bash instead of sh like that:<br />
#! /bin/bash<br />
And also modify to that:<br />
<pre><br />
case x`uname -m` in<br />
xi?86 | xx86_64)<br />
list=`for i in /boot/vmlinuz-* /vmlinuz-* /boot/kernel-* ; do<br />
if grub_file_is_not_garbage "$i" ; then echo -n "$i " ; fi<br />
done` ;;<br />
*) <br />
list=`for i in /boot/vmlinuz-* /boot/vmlinux-* /vmlinuz-* /vmlinux-* /boot/kernel-* ; do<br />
if grub_file_is_not_garbage "$i" ; then echo -n "$i " ; fi<br />
done` ;;<br />
esac<br />
</pre><br />
To look like that:<br />
<pre><br />
case x`uname -m` in<br />
xi?86 | xx86_64)<br />
list=`for i in /boot/vmlinuz-* /vmlinuz-* /boot/kernel-* ; do<br />
if [[ "$i" != /boot/*.sig ]] ; then <br />
if grub_file_is_not_garbage "$i" ; then echo -n "$i " ; fi<br />
fi<br />
done` ;;<br />
*) <br />
list=`for i in /boot/vmlinuz-* /boot/vmlinux-* /vmlinuz-* /vmlinux-* /boot/kernel-* ; do<br />
if grub_file_is_not_garbage "$i" ; then echo -n "$i " ; fi<br />
done` ;;<br />
esac<br />
</pre><br />
<br />
==== LUKS disks openning ====<br />
GRUB is capable of opening LUKS disks like that:<br />
grub> ls <br />
(ata2) (ata2,msdos3) (ata2,msdos2) (ata2,msdos1) (usb0) (usb0,msdos1) (ata6) (memdisk)<br />
grub> cryptomount (ata2,msdos3)<br />
Attempting to decrypt master key...<br />
Enter passphrase for ata2,msdos3 (431439b0870f40a3bfe8f3ca3aa7072a):<br />
Slot 0 opened<br />
grub> ls<br />
(crypto0) (ata2) (ata2,msdos3) (ata2,msdos2) (ata2,msdos1) (usb0) (usb0,msdos1) (ata6) (memdisk) <br />
grub> set root=crypto0<br />
grub> ls /<br />
lost+found/ boot/ var/ dev/ run/ etc/ tmp/ sys/ proc/ usr/ lib/ sbin/ bin/ home/ mnt/ opt/ root/ srv/ media/<br />
<br />
Note that you have to type the password and so it's better to have some kind of output (VGA, Serial etc...)<br />
<br />
=== Other features ===<br />
==== Payloads launching ====<br />
GRUB is capable of launching coreboot payloads. See the "Payloads" section of this page<br />
<br />
== grub.cfg ==<br />
=== Serial ===<br />
==== On a real serial port ====<br />
To enable serial, add the following on top of your grub.cfg:<br />
serial --speed=115200 --word=8 --parity=no --stop=1<br />
terminal_input --append serial<br />
terminal_output --append serial<br />
<br />
==== On an usb serial or usb debug adapter ====<br />
To enable serial, first find out the name of your usb serial port trough:<br />
insmod nativedisk # needed not to get the disk disapearing when insmoding the *hci<br />
insmod ehci<br />
insmod ohci<br />
insmod uhci<br />
insmod usb<br />
insmod usbserial_pl2303<br />
insmod usbserial_ftdi<br />
insmod usbserial_usbdebug<br />
terminal_output<br />
The terminal_output command should print it:<br />
grub> terminal_output <br />
Active output terminals:<br />
serial_usb1 gfxterm <br />
Available output terminals:<br />
console vga_text serial <br />
Here we can see "serial_usb1" so we now know that its name is usb1<br />
<br />
Then add the following on top of your grub.cfg:<br />
insmod nativedisk<br />
insmod ehci<br />
insmod ohci<br />
insmod uhci<br />
insmod usb<br />
insmod usbserial_pl2303<br />
insmod usbserial_ftdi<br />
insmod usbserial_usbdebug<br />
serial --speed=115200 --word=8 --parity=no --stop=1 usb1<br />
terminal_output --append serial_usb1<br />
terminal_input --append serial_usb1<br />
<br />
The following chips/protocols are supported:<br />
* usbdebug<br />
* ftdi<br />
* pl2303<br />
<br />
=== Other things ===<br />
Append that in your configuration:<br />
terminal_input --append at_keyboard #add keyboard support.<br />
#set timeout=1 #you may want to set a timeout<br />
#set pager=1 # you may want to use the pager or not<br />
play 480 440 1 #play a beep at startup<br />
set prefix=(memdisk)/boot/grub<br />
In case of native graphics you may want the following:<br />
gfxpayload=keep<br />
terminal_output --append gfxterm<br />
<br />
=== Payloads ===<br />
Here is how to load the SeaBIOS payload from the memdisk.<br />
menuentry 'SeaBios' {<br />
set root='memdisk'<br />
echo 'Loading SeaBios ...'<br />
chainloader /bios.bin.elf<br />
}<br />
see in "creating the GRUB payload" how to include the file in the memdisk...<br />
<br />
=== Distributions ===<br />
Here's an example on how to load the parabola distribution on the Lenovo X60 from the fifth partition.<br />
menuentry 'Parabola GNU/Linux-libre GNU/Linux, with Linux librepae kernel [Serial]' {<br />
insmod ahci<br />
insmod part_msdos<br />
set root='ahci0,msdos5'<br />
echo 'Loading Linux librepae kernel ...'<br />
linux /vmlinuz-linux-libre-pae root=/dev/mapper/root ro cryptdevice=/dev/sda6:root idle=halt pcie_aspm=force console=ttyS0,115200<br />
echo 'Loading initial ramdisk ...'<br />
initrd /initramfs-linux-libre-pae.img<br />
}<br />
<br />
=== Scanning for grub.cfg on local Hard Drives. ===<br />
<br />
menuentry 'Scan for OS on internal HDD' {<br />
insmod regexp<br />
insmod ahci<br />
insmod part_msdos<br />
for x in (ahci0,*) ; do<br />
if [ -f "$x/grub/grub.cfg" ] ; then<br />
menuentry "Load Config from $x" $x { <br />
root=$2<br />
configfile /grub/grub.cfg<br />
}<br />
fi<br />
if [ -f "$x/boot/grub/grub.cfg" ] ; then<br />
menuentry "Load Config from $x" $x {<br />
root=$2<br />
configfile /boot/grub/grub.cfg<br />
}<br />
fi<br />
done<br />
}<br />
<br />
== Compiling ==<br />
git clone git://git.savannah.gnu.org/grub.git grub<br />
cd grub<br />
./autogen.sh<br />
./configure --with-platform=coreboot<br />
make<br />
sudo make install #install the utilities<br />
<br />
== creating the GRUB payload==<br />
Create a target directory:<br />
mkdir memdisk<br />
Then copy your grub.cfg in:<br />
memdisk/boot/grub/grub.cfg<br />
<br />
Then adapt and run that script:<br />
#!/bin/sh<br />
rm -f grub2-x60.elf<br />
#copy the payloads you want<br />
cp ../../seabios-x60/out/bios.bin.elf ./memdisk/<br />
cp ../../coreboot-qemu/payloads/nvramcui/nvramcui.elf ./memdisk/<br />
cp ../../coreboot-x60/payloads/coreinfo/build/coreinfo.elf ./memdisk/<br />
cp ../../memtest86+-4.20/memtest ./memdisk/memtest.elf<br />
#and some files<br />
cp ../../coreboot-x60/bootsplash.jpg ./memdisk/<br />
cd memdisk<br />
grub-mkstandalone -O i386-coreboot -o ../grub2-x60.elf $(find -type f)<br />
echo "--RESULT--"<br />
ls -l -h ../grub2-x60.elf<br />
<br />
== combining with coreboot ==<br />
=== As a SeaBIOS payload ===<br />
build/cbfstool build/coreboot.rom add-payload -n img/grub2 -f grub2.elf -t raw<br />
build/cbfstool build/coreboot.rom print<br />
That way it will be possible to run GRUB as a payload after SeaBIOS: <br />
The advantage is that it's less risky. At runtime press F12 and you'll <br />
have the GRUB option.<br />
<br />
=== As a Coreboot payload ===<br />
Advantages: faster, can be used for security<br />
<br />
Disadvantages: more risky if you have no way to recover<br />
<br />
==== Howto ====<br />
<br />
In make menuconfig of coreboot, select the path of grub2.elf.<br />
<br />
Also make sure you have some kinds of output such as VGA or serial (it <br />
needs to be activated in both coreboot and GRUB)<br />
<br />
== Before flashing ==<br />
You should try the grub2.elf on qemu before flashing it to a real mainboard/laptop.</div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13337Board:asus/f2a85-m2014-02-16T20:33:39Z<p>Idwer: /* UEFI builds */</p>
<hr />
<div>== Status ==<br />
<br />
=== Supported CPUs ===<br />
<br />
* AMD Athlon X2 340<br />
* AMD Athlon X2 740<br />
* AMD Athlon X2 750k<br />
* AMD FirePro A300<br />
* AMD FirePro A320<br />
* AMD A4-5300<br />
* AMD A4-5300B<br />
* AMD A6-5400K<br />
* AMD A6-5400B<br />
* AMD A8-5500<br />
* AMD A8-5500B<br />
* AMD A8-5600K<br />
* AMD A10-5700<br />
* AMD A10-5800B<br />
* AMD A10-5800K<br />
<br />
This list might be maintained more actively: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = the board will start with an AMD A8-5500<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== UEFI builds that allow flash chip access ==<br />
<br />
* v5016 (untested, but expected to work as well)<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402 <br />
* v6404 (requires downgrade to flash coreboot to v6402)<br />
* v6501 (requires downgrade to flash coreboot to v6402)<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13327Board:asus/f2a85-m2014-02-12T13:13:47Z<p>Idwer: markup correction for CPU support</p>
<hr />
<div>== Status ==<br />
<br />
=== Supported CPUs ===<br />
<br />
* AMD Athlon X2 340<br />
* AMD Athlon X2 740<br />
* AMD Athlon X2 750k<br />
* AMD FirePro A300<br />
* AMD FirePro A320<br />
* AMD A4-5300<br />
* AMD A4-5300B<br />
* AMD A6-5400K<br />
* AMD A6-5400B<br />
* AMD A8-5500<br />
* AMD A8-5500B<br />
* AMD A8-5600K<br />
* AMD A10-5700<br />
* AMD A10-5800B<br />
* AMD A10-5800K<br />
<br />
This list might be maintained more actively: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = the board will start with an AMD A8-5500<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== UEFI builds ==<br />
<br />
* v5016 (untested, but expected to work as well)<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402 <br />
* v6404 (requires downgrade to flash coreboot to v6402)<br />
* v6501 (requires downgrade to flash coreboot to v6402)<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13326Board:asus/f2a85-m2014-02-12T13:12:56Z<p>Idwer: moved the uefi paragraph</p>
<hr />
<div>== Status ==<br />
<br />
=== Supported CPUs ===<br />
<br />
AMD Athlon X2 340<br />
AMD Athlon X2 740<br />
AMD Athlon X2 750k<br />
AMD FirePro A300<br />
AMD FirePro A320<br />
AMD A4-5300<br />
AMD A4-5300B<br />
AMD A6-5400K<br />
AMD A6-5400B<br />
AMD A8-5500<br />
AMD A8-5500B<br />
AMD A8-5600K<br />
AMD A10-5700<br />
AMD A10-5800B<br />
AMD A10-5800K<br />
<br />
This list might be maintained more actively: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = the board will start with an AMD A8-5500<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== UEFI builds ==<br />
<br />
* v5016 (untested, but expected to work as well)<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402 <br />
* v6404 (requires downgrade to flash coreboot to v6402)<br />
* v6501 (requires downgrade to flash coreboot to v6402)<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13325Board:asus/f2a85-m2014-02-12T13:11:49Z<p>Idwer: Listed the supported CPUs.</p>
<hr />
<div>== UEFI builds ==<br />
<br />
* v5016 (untested, but expected to work as well)<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402 <br />
* v6404 (requires downgrade to flash coreboot to v6402)<br />
* v6501 (requires downgrade to flash coreboot to v6402)<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Status ==<br />
<br />
=== Supported CPUs ===<br />
<br />
AMD Athlon X2 340<br />
AMD Athlon X2 740<br />
AMD Athlon X2 750k<br />
AMD FirePro A300<br />
AMD FirePro A320<br />
AMD A4-5300<br />
AMD A4-5300B<br />
AMD A6-5400K<br />
AMD A6-5400B<br />
AMD A8-5500<br />
AMD A8-5500B<br />
AMD A8-5600K<br />
AMD A10-5700<br />
AMD A10-5800B<br />
AMD A10-5800K<br />
<br />
This list might be maintained more actively: http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = the board will start with an AMD A8-5500<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Talk:FOSDEM_2014&diff=13263Talk:FOSDEM 20142014-01-31T01:09:18Z<p>Idwer: final change</p>
<hr />
<div>Relevant or possibly interesting talk(s):<br />
* https://fosdem.org/2014/schedule/event/uefienemy/<br />
<br />
=Who is coming?=<br />
<br />
* Idwer Vollering<br />
* Peter Stuge<br />
* Carl-Daniel Hailfinger<br />
* Vladimir Serbinenko<br />
* Denis 'GNUtoo' Carikli<br />
<br />
=Who brings what?=<br />
<br />
== Vladimir ==<br />
<br />
* X201<br />
* X230<br />
* 2x Lenovo power supplies (don't forget EU power cords)<br />
* EHCI debug dongle (+cables)<br />
* Buspirate (+cables)<br />
* Pomona SOIC-8 clip<br />
* 5 x SST 49LF008A<br />
* 5 x SST 49LF160C<br />
* 2 x 2.5" disk SATA<br />
* 8-port switch.<br />
* Keyboard (USB, +PS/2 adapter)<br />
* PLCC extractor<br />
<br />
==Idwer==<br />
<br />
* Samsung Lumpy+charger<br />
* Buspirate (+cables)<br />
* breadboard<br />
* Pomona SOIC-8 clip<br />
* 2x W25Q64 soic8, 2x soic8 that are converted to fit dip8<br />
* USB removable media<br />
* PS/2 keyboard with PS/2-to-USB adapter<br />
note to self: bring screwdrivers<br />
<br />
==Peter==<br />
<br />
==Carl-Daniel==<br />
* lots of power sockets and extension cords<br />
* Bus Pirate<br />
* Asrock E350M1 mainboard<br />
* Thinkpad T60p laptop<br />
* Raspberry Pi (for faster flashing)<br />
* Various flash chips<br />
* Artec FlexyICE (if I can find it)<br />
* 19" flat screen monitor with DVI+VGA incl. cables<br />
* 14" flat screen monitor with DVI+VGA incl. cables<br />
* flashrom flyers<br />
* coreboot flyers<br />
* posters<br />
* thousands of cables<br />
* ATX power supply (for the Asrock E350M1)<br />
* serial cables<br />
<br />
== [[User:GNUtoo|Denis 'GNUtoo' Carikli]] ==<br />
=== I'll try to bring: ===<br />
* My x60 (without batteries)<br />
* My t60 (with my battery)<br />
* A null modem cable<br />
* An usb to serial adapter(standard voltage).<br />
* A jack-jack audio cable for spkmodem<br />
* My gpg fingerprint<br />
* One power strip<br />
* some flash chips for testing the programmers setups<br />
<br />
=== I wonder if I should bring: ===<br />
* My E350M1<br />
* A programmer<br />
* My pomona clip<br />
* The fragile LPC dongle for the ALIX.1C<br />
<br />
=== I'd like not to have to bring: ===<br />
* The GTA04 which has:<br />
** A standard voltage serial port and db9 connector.<br />
** USB debug capabilities trough g_dbgp.<br />
<br />
=== I'd like other people to bring: ===<br />
* An x60 dock(I'll cary only a backpack)<br />
* Their gpg fingerprint<br />
* A soldering iron that works(full setup) would be nice, but not strictly needed.<br />
* network cables.<br />
<br />
==Stuff we need (please check if you can bring it)==<br />
* Few USB sticks to boot boards.<br />
* supported small system (alix?)<br />
* supported ARM board<br />
* gpg fingerprints?</div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13218Board:asus/f2a85-m2014-01-26T13:02:36Z<p>Idwer: adding detailed instructions</p>
<hr />
<div>== UEFI builds ==<br />
<br />
UEFI builds that allow access to the flash chip from userspace are:<br />
* v5016 (untested, but expected to work as well)<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
Downgrading is done by downloading build v6402 from http://www.asus.com/support/Download/1/43/F2A85M/8/ and copying it to (the root directory of) a FAT32 formatted USB flash drive.<br />
<br />
Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".<br />
<br />
== Status ==<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=13185Board:asus/f2a85-m2014-01-26T02:42:25Z<p>Idwer: adding a section about efi builds that allow ISP (in-system) flash chip access</p>
<hr />
<div>== UEFI builds ==<br />
<br />
UEFI builds that allow access to the flash chip, without using an external programmer, are:<br />
* v5018<br />
* v5103<br />
* v5104<br />
* v5107<br />
* v5202<br />
* v6002<br />
* v6004<br />
* v6102<br />
* v6402<br />
<br />
Build v6404 and v6501 do not allow access to the flash chip.<br />
<br />
Fortunately it is possible to downgrade build v6501 and v6404 to v6402, with EZFlash.<br />
<br />
== Status ==<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
=== DDR voltage controller ===<br />
<br />
The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website).<br />
<br />
=== The ASUS digi VRM ===<br />
<br />
The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded)<br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Talk:FOSDEM_2014&diff=13164Talk:FOSDEM 20142014-01-25T19:29:02Z<p>Idwer: </p>
<hr />
<div>Relevant or possibly interesting talk(s):<br />
* https://fosdem.org/2014/schedule/event/uefienemy/<br />
<br />
=Who is coming?=<br />
<br />
* Idwer Vollering<br />
* Peter Stuge<br />
* Carl-Daniel Hailfinger<br />
* Vladimir Serbinenko<br />
* Denis 'GNUtoo' Carikli<br />
<br />
=Who brings what?=<br />
<br />
== Vladimir ==<br />
<br />
* X201<br />
* X230<br />
* 2x Lenovo power supplies (don't forget EU power cords)<br />
* EHCI debug dongle (+cables)<br />
* Buspirate (+cables)<br />
* Pomona SOIC-8 clip<br />
* 5 x SST 49LF008A<br />
* 5 x SST 49LF160C<br />
<br />
==Idwer==<br />
<br />
* Samsung Lumpy+charger<br />
* Buspirate (+cables)<br />
* breadboard<br />
* Pomona SOIC-8 clip<br />
* 2x W25Q64 soic8 (and perhaps 2x soic8 that are converted to fit dip8)<br />
* USB removable media<br />
* PS/2 keyboard with PS/2-to-USB adapter<br />
* (when someone brings his/her asus f2a85-m board: an SSD with win7 installed)<br />
** LET ME KNOW IF YOU BRING ONE :)<br />
<br />
==Peter==<br />
<br />
==Carl-Daniel==<br />
* Lots of power sockets and extension cords<br />
* Bus Pirate<br />
* HP 635 laptop<br />
* Various flash chips<br />
* Artec FlexyICE<br />
* 19" flat screen monitor with DVI+VGA incl. cables<br />
* flashrom flyers<br />
* posters<br />
* thousands of cables<br />
<br />
== [[User:GNUtoo|Denis 'GNUtoo' Carikli]] ==<br />
=== I'll try to bring: ===<br />
* My x60 (without batteries)<br />
* My t60 (with my battery)<br />
* A null modem cable<br />
* An usb to serial adapter(standard voltage).<br />
* A jack-jack audio cable for spkmodem<br />
* My gpg fingerprint<br />
* I am also able to create an ipxe bootable system rapidely, assuming that:<br />
** I've access to the Internet<br />
** The "client" computer has a way of storing ipxe, like:<br />
*** A NIC with a flash chip(shows off flashrom and seabios ability of loading option roms)<br />
*** Any PCI card used as a carrier(shows off the "carrier" "feature", flashrom, and option rom loading).<br />
*** Or we could simply put ipxe into coreboot's flash.<br />
*** Putting it on a common storage device is not a good idea for attracting visitors.<br />
** I don't have scripts to boot an nfsroot over wifi, instead I can either:<br />
*** Boot it trough an ethernet NIC.<br />
*** Boot small self-contained kenrel and initramfs over wifi (no nfsroot).<br />
<br />
=== I wonder if I should bring: ===<br />
* My E350M1<br />
* A programmer<br />
* My pomona clip<br />
* some flash chips for testing the programmers setups<br />
* The fragile LPC dongle for the ALIX.1C<br />
<br />
=== I can't bring ===<br />
* The ALIX.1C: in use<br />
* The M4A785T-M: too big<br />
=== I'd like not to have to bring: ===<br />
* The GTA04 which has:<br />
** A standard voltage serial port and db9 connector.<br />
** USB debug capabilities trough g_dbgp.<br />
<br />
=== I'd like other people to bring: ===<br />
* An x60 dock(I'll cary only a backpack)<br />
* Their gpg fingerprint<br />
* A soldering iron that works(full setup) would be nice, but not strictly needed.<br />
* network cables.<br />
<br />
==Stuff we need (please check if you can bring it)==<br />
* Power supply units<br />
* Monitors<br />
* Flyers for coreboot and flashrom. Who has the PDFs for our latest flyers (probably Carl-Daniel)?<br />
* CF/USB sticks/... to boot boards.<br />
* Keyboards<br />
* supported recent AMD board<br />
* supported small system (alix?)<br />
* supported ARM board<br />
* gpg fingerprints?</div>Idwerhttps://www.coreboot.org/index.php?title=Talk:FOSDEM_2014&diff=13135Talk:FOSDEM 20142014-01-24T17:52:48Z<p>Idwer: </p>
<hr />
<div>Relevant or possibly interesting talk(s):<br />
* https://fosdem.org/2014/schedule/event/uefienemy/<br />
<br />
=Who is coming?=<br />
<br />
* Idwer Vollering<br />
* Peter Stuge<br />
* Carl-Daniel Hailfinger<br />
* Vladimir Serbinenko<br />
* Denis 'GNUtoo' Carikli<br />
<br />
=Who brings what?=<br />
<br />
== Vladimir ==<br />
<br />
* X201<br />
* X230<br />
* 2x Lenovo power supplies (don't forget EU power cords)<br />
* EHCI debug dongle (+cables)<br />
* Buspirate (+cables)<br />
* Pomona SOIC-8 clip<br />
* 5 x SST 49LF008A<br />
* 5 x SST 49LF160C<br />
<br />
==Idwer==<br />
<br />
* Samsung Lumpy+charger<br />
* USB serial port+nullmodem<br />
* Buspirate (+cables), breadboard<br />
* Pomona SOIC-8 clip<br />
* 2x W25Q64 soic8 (and perhaps 2x soic8 converted to dip8)<br />
* USB removable media<br />
* 'USB' keyboard<br />
* (when someone brings his/her asus f2a85-m board: an SSD with win7 installed)<br />
** LET ME KNOW IF YOU BRING ONE :)<br />
<br />
==Peter==<br />
<br />
==Carl-Daniel==<br />
* Lots of power sockets and extension cords<br />
* Bus Pirate<br />
* HP 635 laptop<br />
* Various flash chips<br />
* Artec FlexyICE<br />
* 19" flat screen monitor with DVI+VGA incl. cables<br />
* flashrom flyers<br />
* posters<br />
* thousands of cables<br />
<br />
==Stuff we need (please check if you can bring it)==<br />
* Power supply units<br />
* Monitors<br />
* Flyers for coreboot and flashrom. Who has the PDFs for our latest flyers (probably Carl-Daniel)?<br />
* CF/USB sticks/... to boot boards.<br />
* Keyboards<br />
* supported recent AMD board<br />
* supported small system (alix?)<br />
* supported ARM board</div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12165Board:asus/f2a85-m2013-10-14T17:29:53Z<p>Idwer: updated 'suspend' status take 2</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|Suspend_status = WIP<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12164Board:asus/f2a85-m2013-10-14T17:24:05Z<p>Idwer: updated 'suspend' status</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend: this is work in progress<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend is WIP (work in progress).<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12161Board:asus/f2a85-m2013-10-02T23:29:06Z<p>Idwer: tested audio with headphones</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend<br />
** resuming from suspend isn't working, possibly because I let coreboot handle the VGA optionrom... also, I have set CONFIG_S3_VGA_ROM_RUN=y<br />
<pre>coreboot-4.0-4711-gdd6c4ec wo sep 25 13:00:52 CEST 2013 starting...<br />
POST: 0x34<br />
BSP Family_Model: 00610f01<br />
cpu_init_detectedx = 00000000<br />
POST: 0x37<br />
agesawrapper_amdinitreset Fch OEM config in INIT RESET Done<br />
Got past agesawrapper_amdinitearly<br />
S3 detected<br />
POST: 0x60<br />
agesawrapper_amdinitresume passed.<br />
agesawrapper_amds3laterestore passed.<br />
POST: 0x61<br />
Find resume memory location<br />
CBMEM region bf11f000-bfffffff (cbmem_reinit)<br />
POST: 0x62<br />
Move CAR stack.<br />
POST: 0x30<br />
<br />
<br />
coreboot-4.0-4711-gdd6c4ec wo sep 25 13:00:52 CEST 2013 starting...<br />
POST: 0x34<br />
BSP Family_Model: 00610f01<br />
cpu_init_detectedx = 00000000<br />
POST: 0x37<br />
agesawrapper_amdinitreset Fch OEM config in INIT RESET Done</pre><br />
<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = tested with headphones in line-out (lime colored)<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend untested.<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12159Board:asus/f2a85-m2013-09-25T11:24:13Z<p>Idwer: </p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend<br />
** resuming from suspend isn't working, possibly because I let coreboot handle the VGA optionrom... also, I have set CONFIG_S3_VGA_ROM_RUN=y<br />
<pre>coreboot-4.0-4711-gdd6c4ec wo sep 25 13:00:52 CEST 2013 starting...<br />
POST: 0x34<br />
BSP Family_Model: 00610f01<br />
cpu_init_detectedx = 00000000<br />
POST: 0x37<br />
agesawrapper_amdinitreset Fch OEM config in INIT RESET Done<br />
Got past agesawrapper_amdinitearly<br />
S3 detected<br />
POST: 0x60<br />
agesawrapper_amdinitresume passed.<br />
agesawrapper_amds3laterestore passed.<br />
POST: 0x61<br />
Find resume memory location<br />
CBMEM region bf11f000-bfffffff (cbmem_reinit)<br />
POST: 0x62<br />
Move CAR stack.<br />
POST: 0x30<br />
<br />
<br />
coreboot-4.0-4711-gdd6c4ec wo sep 25 13:00:52 CEST 2013 starting...<br />
POST: 0x34<br />
BSP Family_Model: 00610f01<br />
cpu_init_detectedx = 00000000<br />
POST: 0x37<br />
agesawrapper_amdinitreset Fch OEM config in INIT RESET Done</pre><br />
<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend untested.<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=12158Board:asus/f2a85-m2013-09-25T11:22:31Z<p>Idwer: minor cleanup, posting my findings</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is identical to the F2A85-M.<br />
* Retrieve the VGA optionrom from the vendor EFI binary by running 'dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768' (source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html )<br />
<br />
For internal VGA:<br />
Boot the legacy BIOS, and use [[VGA_support]] chapter <br />
<br />
* Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID.<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios<br />
* It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read [[SeaBIOS]] for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload.<br />
** its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings:<br />
** CONFIG_VGA_ROM_RUN=y<br />
** CONFIG_PCI_ROM_RUN=y<br />
** CONFIG_ON_DEVICE_ROM_RUN=y<br />
* Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested.<br />
* update VERB tables<br />
* test suspend<br />
** resuming from suspend isn't working, possibly because I let coreboot handle the VGA optionrom...<br />
<pre>coreboot-4.0-4711-gdd6c4ec wo sep 25 13:00:52 CEST 2013 starting...<br />
POST: 0x34<br />
BSP Family_Model: 00610f01<br />
cpu_init_detectedx = 00000000<br />
POST: 0x37<br />
agesawrapper_amdinitreset Fch OEM config in INIT RESET Done<br />
Got past agesawrapper_amdinitearly<br />
S3 detected<br />
POST: 0x60<br />
agesawrapper_amdinitresume passed.<br />
agesawrapper_amds3laterestore passed.<br />
POST: 0x61<br />
Find resume memory location<br />
CBMEM region bf11f000-bfffffff (cbmem_reinit)<br />
POST: 0x62<br />
Move CAR stack.<br />
POST: 0x30<br />
<br />
<br />
coreboot-4.0-4711-gdd6c4ec wo sep 25 13:00:52 CEST 2013 starting...<br />
POST: 0x34<br />
BSP Family_Model: 00610f01<br />
cpu_init_detectedx = 00000000<br />
POST: 0x37<br />
agesawrapper_amdinitreset Fch OEM config in INIT RESET Done</pre><br />
<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested all ports of sixpack.<br />
|USB_status = OK<br />
|USB_comments = Issues with XHCI exist with Asus' BIOS as well<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Use dd to [[VGA_support|extract the legacy BIOS]], HDMI untested<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend untested.<br />
|Reboot_status = OK<br />
|Reboot_comments = warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot<br />
|Poweroff_status = OK<br />
|LEDs_status = OK<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Hardware info ==<br />
<br />
This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:<br />
<br />
{|<br />
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]] <br />
|}<br />
<br />
The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]<br />
<br />
For out of band flashing, I use a<br />
<br />
3M test clip model 923739-08-ND<br />
<br />
It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever:<br />
<br />
<pre><br />
# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom<br />
flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64)<br />
flashrom is free software, get the source code at http://www.flashrom.org<br />
<br />
Calibrating delay loop... OK.<br />
Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi.<br />
Reading old flash chip contents... done.<br />
Erasing and writing flash chip... Erase/write done.<br />
Verifying flash... VERIFIED.<br />
<br />
real 35m35.409s<br />
user 0m55.976s<br />
sys 0m12.920s<br />
</pre><br />
<br />
== Memory ==<br />
<br />
I use:<br />
<br />
2x 2GB DDR3 modules in blue slots:<br />
<br />
<pre><br />
#modprobe i2c-piix4<br />
#modprobe eeprom<br />
#decode-dimms<br />
<br />
---=== Memory Characteristics ===--- <br />
Fine time base 2.500 ps <br />
Medium time base 0.125 ns <br />
Maximum module speed 1333MHz (PC3-10666) <br />
Size 2048 MB <br />
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 <br />
Ranks 2 <br />
SDRAM Device Width 8 bits <br />
tCL-tRCD-tRP-tRAS 8-8-8-24 <br />
Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T <br />
</pre></div>Idwerhttps://www.coreboot.org/index.php?title=Board:asus/f2a85-m&diff=11813Board:asus/f2a85-m2013-04-20T12:22:18Z<p>Idwer: /* Notes */</p>
<hr />
<div>== Status ==<br />
<br />
<br />
=== Notes ===<br />
<br />
* The ASUS F2A85-M CSM is same as F2A85-M.<br />
* get VGA from original bios using this:<br />
Source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html<br />
<br />
for internal VGA:<br />
Boot the legacy BIOS, and use http://www.coreboot.org/VGA_support chapter <br />
<br />
extracting from your system: dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768<br />
<br />
You will need following patch to seabios:<br />
<code><br />
--- a/src/optionroms.c<br />
+++ b/src/optionroms.c<br />
@@ -215,7 +215,10 @@ is_pci_vga(struct pci_device *pci)<br />
{<br />
if (pci->class != PCI_CLASS_DISPLAY_VGA)<br />
return 0;<br />
- u16 cmd = pci_config_readw(pci->bdf, PCI_COMMAND);<br />
+ u16 cmd = pci_config_readw(pci->bdf, PCI_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;<br />
+<br />
+ pci_config_writew(pci->bdf, PCI_COMMAND, cmd);<br />
+<br />
if (!(cmd & PCI_COMMAND_IO && cmd & PCI_COMMAND_MEMORY))<br />
return 0;<br />
while (pci->parent) {<br />
</code><br />
<br />
Reason is unknown, I see coreboot is writing 7 to cmd, but there is actually <br />
6... Maybe there is some magic about IO decode bit...<br />
<br />
* Add VGA bios in the menuconfig<br />
* If you use PS/2 de-select legacy free<br />
* De-select running option ROMs, leave this to Seabios<br />
* Use seabios as payload<br />
* Hotswapping has some issues (most likely USB3, disable it in orig bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.<br />
<br />
=== TODOs ===<br />
* test virtualization<br />
* test HDMI<br />
* update VERB tables<br />
* test suspend<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = <br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multicore_comments = <br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK <br />
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
|RAM_ecc_comments =<br />
<br />
|IDE_status = N/A<br />
|IDE_comments = <br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|SATA_comments = Tested only first top port on left in sixpack (from outside view).<br />
|USB_status = Untested<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = HDMI untested<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|PP_comments = <br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = ?<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|CPUfreq_comments = <br />
|Powersave_status = ?<br />
|ACPI_status = OK<br />
|ACPI_comments = ACPI power button event works, suspend untested.<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|LEDs_status = Unknown<br />
|HPET_status = OK<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}</div>Idwerhttps://www.coreboot.org/index.php?title=Project_Ideas&diff=11810Project Ideas2013-04-17T00:13:37Z<p>Idwer: /* coreboot cheap testing rig */</p>
<hr />
<div></div>Idwerhttps://www.coreboot.org/index.php?title=Bios_extract&diff=11747Bios extract2013-04-09T21:38:11Z<p>Idwer: Sucking in content from http://www.coreboot.org/Development_Guidelines</p>
<hr />
<div>'''bios_extract''' is a GPL tool for extracting individual modules from proprietary BIOS/UEFI images.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
It is very useful for extracting PCI Expansion ROMs from onboard devices, like IGP graphics, raid controllers, nic boot roms, etc, for inclusion in a coreboot image.<br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ git clone http://review.coreboot.org/p/bios_extract<br />
$ cd bios_extract<br />
$ make<br />
$ sudo make install<br />
<br />
You can view sources via gitweb - http://review.coreboot.org/gitweb?p=bios_extract.git<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=Documentation/CodingStyle;hb=HEAD Linux kernel coding style] for bios_extract.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
== The 80 character limit ==<br />
<br />
Lines larger than 80 columns should be broken down into readable pieces. This includes not only source files, but also Makefiles, Kconfig files, and any file meant to be edited by a human. We recommend setting your editor to show the 80th character limit.<br />
This limit is not a relic from long forgotten times, but a very practical and efficient way to organize code and increase productivity. Several files can be edited on the same monitor, without the need to side-scroll. Side-scrolling source files is inefficient, time-consuming, and uncomfortable. On average, 95% of source lines are shorter than 80 characters, so limiting the line length is this manner is not only _not_ an impediment, it also gets you to think on how to best organize the code.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''why'' and ''what'', not ''how'' (No comments like ''/* add one to i */'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* We use gerrit for change management, using the instance on http://review.coreboot.org/<br />
* While not necessary with gerrit, '''make sure that your change is against current master'''. Patches that fail on merge (after some developer looked at it and approved it) might linger around until '''you''' update it.<br />
* Rebase, if necessary, '''then test''' again. You might be the only contributor with that specific mainboard.<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* Make sure all added files are actually within the commit.<br />
* Make one commit per logical change.<br />
* For more details on using gerrit, see our [[Git]] documentation. Things are somewhat different (eg. it's normal to rebase changes that were already pushed).<br />
* Double-check that your changes are correct, and that the commit only contains what you think it contains.<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for bios_extract<br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be pushed to gerrit!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to [[Git|gerrit]] for review.<br />
** Provide useful commit messages. Explain what the change does and why. Our short intro to [[Git|git]] explains the format in more detail.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch (<code>git commit -s</code> helps, but make sure you understand and comply with the DCO).<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
* The developers will review and/or test your change and send comments or suggestions. Please push updated patches as described in "[[Git#Evolving_patches|evolving patches]]".<br />
* If the change looks ok to one or more developers, they will approve and submit it to the master branch.<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
Note: some python is under '3-clause BSD license'.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the bios_extract project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the bios_extract project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>Idwerhttps://www.coreboot.org/index.php?title=AMD_Geode_Porting_Guide&diff=11168AMD Geode Porting Guide2012-08-16T08:08:00Z<p>Idwer: /* Manual build */</p>
<hr />
<div>Welcome! This is a collection on information to help you on your way to porting coreboot to an AMD Geode platform. Most of the information is about the Geode LX and CS5536 but may also be relevant to older versions of Geode. (Note that this does not cover the Geode NX).<br />
<br />
If you find something incorrect or other deficiencies in this information please fix them!<br />
<br />
== Documentation ==<br />
* [[Development Guidelines]]<br />
* [[Developer Manual]]<br />
* Many Geode LX systems are based on the [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800 reference design], so that is a good place to start.<br />
* [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234H_LX_databook.pdf Geode LX CPU databook]<br />
* [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33238G_cs5536_db.pdf Geode CS5536 Southbridge databook]<br />
* [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E11363,00.html Geode Linux webpage] - The VSA and GeodeROM Porting guides are interesting.<br />
* [http://linuxbios.org/images/8/88/Crouse-Reprint.pdf Breaking the Chains -- Using LinuxBIOS to Liberate Embedded x86 Processors] - was heavily influenced by the experience of the initial Geode LX port.<br />
<br />
== Build coreboot for Geode ==<br />
Use [[Buildrom|buildrom]]. It can handle the payload and VSA for you.<br />
<br />
$ svn co svn://coreboot.org/buildrom<br />
<br />
Checkout coreboot:<br />
<br />
$ svn co svn://coreboot.org/coreboot/trunk coreboot<br />
<br />
Build a db800 for starters and set buildrom to build your local svn directory in menuconfig.<br />
<br />
$ make menuconfig<br />
$ make<br />
<br />
From this point you can customize the db800 and then make the target, mainboard, and buildrom customization patches later. <br />
<br />
==== Manual build ====<br />
If you really want to get your hands dirty. Roll up your sleeves...<br />
<br />
Get the current VSA binary, '''gpl_vsa_lx_102.bin''', from the blobs git repository:<br />
''git clone http://review.coreboot.org/p/blobs.git''. The VSA code/binary can be found in blobs/cpu/amd/geode_lx/<br />
<br />
Older versions like '''amd_vsa_lx_1.01.bin.gz''' are still available [http://support.amd.com/us/Embedded_TechDownloads/amd_vsa_lx_1.01.bin.gz here] and extract it. It will need to be compressed and padded to make the correct ROM size. For a typical Geode platform the binary should be 36KB. Calculate the padding as follows: 36864 - size of lx_vsa.nrv2b = padding. The current image requires padding of 3264.<br />
<br />
Then, find a [[Payloads|payload]] and build it.<br />
<br />
$ cd coreboot/targets<br />
$ ./buildtarget amd/db800<br />
$ cd amd/db800/db800<br />
$ cp /from/someplace/payloadx ./payload.elf<br />
$ make<br />
$ cp /from/someplace/gpl_vsa_lx_102.bin .<br />
$ fallback/nrv2b e gpl_vsa_lx_102.bin lx_vsa.nrv2b<br />
$ dd if=/dev/zero of=padding bs=1 count=3264 <br />
$ cat lx_vsa.nrv2b padding > lx_vsa.36k.bin<br />
$ cat lx_vsa.36k.bin db800.rom > amd-db800.rom<br />
<br />
You should now have a 512KB ROM image. You should be able to use [[flashrom]] or a ROM programmer to get the image onto your system. (Be prepared to brick it...)<br />
<br />
The current GPL VSA source is hosted by coreboot.org, <code>http://review.coreboot.org/gitweb?p=blobs.git;a=tree</code>.<br />
The original source is still available on [http://dev.laptop.org/git?p=geode-vsa;a=tree;h=10f157122acaae414431c88a2403ed692453c960;hb=10f157122acaae414431c88a2403ed692453c960 laptop.org].<br />
<br />
Although not currently functional: [[OpenVSA]] aims to provide VSA buildable with open tools.<br />
<br />
== Porting ==<br />
Now that you are building Geode coreboot images you are ready to make customizations to your platform. Most customizations can be handled in the mainboard directory.<br />
<br />
$ cd coreboot-v2/src/mainboard/amd/db800<br />
<br />
Make yourself familiar with this directory. There are not too many files.<br />
<br />
=== IRQ routing ===<br />
Almost every platform will require customization of the PIR table in '''irq_table.c'''.<br />
<br />
Make yourself familiar with the [http://www.microsoft.com/whdc/archive/pciirq.mspx PIR table specification].<br />
<br />
If you have the motherboard schematics adjusting the table is fairly simple. <br />
<br />
First check how many on board devices (including PCI slots) and update '''IRQ_SLOT_COUNT''' in Options.lb. Remember any time you change Options.lb or Config.lb you need to redo ./buildtarget.<br />
<br />
Next check the INT lines (GPIOs) into the CS5536.<br />
<br />
{| border="1"<br />
|+ CS5536<br />
! line !! CS5536 signal/pin <br />
|-<br />
! PCI$INTA_X<br />
| GPIO0 / INTA_L<br />
|-<br />
! PCI$INTB_X<br />
| GPIO7 / INTB_X <br />
|-<br />
! PCI$INTC_X <br />
| GPIO12 / INTR <br />
|-<br />
! PCI$INTD_X<br />
| GPIO13 / 8MI_L<br />
|}<br />
<br />
Based on this information you can setup the<br />
register "enable_gpio_int_route" = "0x0D0C0700"<br />
line in Config.lb.<br />
<br />
For each motherboard device check the INT pins. For example a PCI slot would look something like this:<br />
{| border="1"<br />
|+ PCI slot<br />
! pin !! device !! line <br />
|-<br />
! pin A6<br />
| INTA_X || PCI$INTB_X <br />
|-<br />
! pin A7<br />
| INTC_X || PCI$INTD_X <br />
|-<br />
! pin B7<br />
| INTB_X || PCI$INTC_X <br />
|-<br />
! pin B8<br />
| INTD_X || PCI$INTA_X <br />
|}<br />
<br />
Take a closer look at irq_tables.c.<br />
L_PIRQA is the chipset incoming IRQ line and M_PIRQA is the bitmap of IRQ numbers it can generate. These should not change. You can adjust the IRQs generated by changing PIRQA etc. Yes, it is fine if they all share 10 or 11 but it might be easier to debug if they all have a different IRQ.<br />
<br />
The table entries are the slot/device IRQ lines. I will break one entry down.<br />
<br />
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br />
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */<br />
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */<br />
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */<br />
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */<br />
<br />
I will break the last entry down.<br />
<br />
* '''0x00, (0x0E << 3) | 0x0''' &mdash; slot(device) address (IDSEL)<br />
* '''{L_PIRQC, M_PIRQC}''' &mdash; slot INT line A to chipset INT line C (L_PIRQC), it can generate IRQs (M_PIRQC)<br />
* '''{L_PIRQD, M_PIRQD}''' &mdash; slot INT line B to chipset INT line C (L_PIRQD), it can generate IRQs (M_PIRQD)<br />
* '''{L_PIRQA, M_PIRQA}''' &mdash; slot INT line C to chipset INT line A...<br />
* '''{L_PIRQB, M_PIRQB}''' &mdash; slot INT lineD to chipset INT line B...<br />
* '''0x1''' &mdash; arbitrary slot number<br />
* '''0x0''' &mdash; rfu, always 0<br />
<br />
If you don't have the schematics you will have to figure out the routing on your own. With '''lspci''' output and some trial and error you can figure it out. [[IRC]] or the [[Mailinglist|mailing list]] is a good place to get help if you are stuck.<br />
<br />
There's also a wiki entry on [[Creating Valid IRQ Tables|figuring out the routing table]].<br />
<br />
==== LPC Serial IRQs ====<br />
IRQs from [http://en.wikipedia.org/wiki/Low_Pin_Count LPC] need to be passed to the SC5536 [http://en.wikipedia.org/wiki/Intel_8259 PIC]. It is important to only enable the expected sources and to configure the polarity. Enables are a bit mask. It depends on the [http://en.wikipedia.org/wiki/Super_I/O SIO] but typically, the polarity is the inverse of the enables as you can see in the example below. (Note that the Geode MFGPT driver uses IRQ7 by default. That will conflict with LPC SIRQ for the LPT port if you require it.)<br />
<br />
Config.lb - <br />
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK<br />
register "lpc_serirq_enable" = "0x0000105a"<br />
register "lpc_serirq_polarity" = "0x0000EFA5"<br />
register "lpc_serirq_mode" = "1"<br />
<br />
=== Memory ===<br />
On some systems the memory is soldered down and there is no SPD (Serial Presence Detect) which is required to properly setup DDR memory. In this case you will need to provide an SPD values in coreboot. This should be done by customizing '''spd_read_byte()''' in '''cache_as_ram_auto.c''' to do a table lookup. A good example can be found in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c src/mainboard/pcengines/alix1c/cache_as_ram_auto.c].<br />
<br />
=== Power button ===<br />
By default the CS5536 code sets the power button up for the '''4 second soft off setting'''. If your system is booting and shuts off after four seconds check for a power button enable jumper. If your system doesn't have a power button and comes on when plugged in you will need to adjust the power button MSR. This is best done in cache_as_ram_main() in cache_as_ram_auto.c after the call to cs5536_early_setup(). The MSR name is PM Fail-Safe Delay and Enable (PM_FSD). (Yes, this could be made a Config.lb option)<br />
<br />
Add the following line:<br />
outl(0x00, PMS_IO_BASE + 0x40); // disable the power button<br />
<br />
=== Graphics ===<br />
For Geode graphics, use the upstreamed [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=drivers/video/geode;h=e680c13755a7bfd9fb40d7f41cb7b30b033fdd67;hb=HEAD Geode framebuffer driver] and the [http://gitweb.freedesktop.org/?p=xorg/driver/xf86-video-amd.git;a=summary Geode X driver]. There is no VGA ROM for Geode at this time.<br />
<br />
=== Debug ===<br />
<br />
==== Serial Output ====<br />
The Geode CS5536 has two serial ports but on many mainboards the SIO serial ports are used instead. Setup Config.lb and the serial initialization depending on the configuration of the mainboard.<br />
<br />
Config.lb -<br />
register "com1_enable" = "1"<br />
register "com1_address" = "0x3F8"<br />
register "com1_irq" = "4"<br />
register "com2_enable" = "1"<br />
register "com2_address" = "0x2F8"<br />
register "com2_irq" = "3"<br />
<br />
In this [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb case] ''' "1" ''' enables the CS5536 serial port and the address and irq are setup to these values. The other important part of serial output is to setup the ports very early. This is done in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c cache_as_ram_main()].<br />
<br />
For an example of using the SIO serial ports instead of the CS5536, see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb DB800 mainboard].<br />
<br />
==== Dump System Configuration ====<br />
'''print_conf()''' in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c#L125 src/northbridge/amd/lx/northbridge.c] can help provide a good picture of the system configuration and should be one of the first tools you use to debug memory or other configuration issues.<br />
<br />
=== Other ===<br />
What are we missing?<br />
<br />
{{GPL}}</div>Idwerhttps://www.coreboot.org/index.php?title=Board:samsung/lumpy&diff=11153Board:samsung/lumpy2012-08-08T20:28:32Z<p>Idwer: </p>
<hr />
<div>= aka Samsung Lumpy aka chromebook =<br />
<br />
Features a "Multi Card Slot 4- in-1 (SD/SDHC/SDXC/MMC)"<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core i5-2467M, FCBGA1023<br />
|CPU_L1_status = ?<br />
|CPU_L2_status = ?<br />
|CPU_L3_status = ?<br />
|CPU_virt_status = ?<br />
|CPU_virt_status_comments = Untested<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = OK<br />
|RAM_SODIMM_comments = One SODIMM slot.<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = ?<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = mSATA. This chromebook comes with a SanDisk SDSA4DH-016G.<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = Untested<br />
|Onboard_VGA_comments = Instead of an analog VGA connector there is a displayport (dp++) connector. Untested.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Realtek 8111/8168<br />
|Onboard_wireless = OK<br />
|Onboard_wireless_comments = Atheros AR9300 (ar5bhb116), 802.11 a/b/g/n<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_modem_comments = Qualcomm WWAN modem, t77z204t12/pkrnvwe396/3229b-e396. You most likely need a SIM card to use this modem.<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = Untested<br />
|Smartcard_comments = A SIM card slot is available.<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|Mini_PCI_cards_comments = One mini-PCIe slot.<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|COM2_comments = coreboot has a driver for Oxford OXPCIe952 serial port PCIe cards<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = WIP<br />
|Speaker_comments = http://review.coreboot.org/#/c/1410/<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = ?<br />
|Watchdog_status = ?<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = N/A<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = External programmer required.<br />
}}</div>Idwerhttps://www.coreboot.org/index.php?title=Board:samsung/lumpy&diff=11152Board:samsung/lumpy2012-08-08T20:24:52Z<p>Idwer: </p>
<hr />
<div>= aka Samsung Lumpy aka chromebook =<br />
<br />
Features a "Multi Card Slot 4- in-1 (SD/SDHC/SDXC/MMC)"<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core i5-2467M, FCBGA1023<br />
|CPU_L1_status = ?<br />
|CPU_L2_status = ?<br />
|CPU_L3_status = ?<br />
|CPU_virt_status = ?<br />
|CPU_virt_status_comments = Untested<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = OK<br />
|RAM_SODIMM_comments = One SODIMM slot.<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = ?<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = mSATA. This chromebook comes with a SanDisk SDSA4DH-016G.<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_VGA_comments = Instead of an analog VGA connector there is a displayport (dp++) connector. Untested.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Realtek 8111/8168<br />
|Onboard_wireless = OK<br />
|Onboard_wireless_comments = Atheros AR9300 (ar5bhb116), 802.11 a/b/g/n<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_modem_comments = Qualcomm WWAN modem, t77z204t12/pkrnvwe396/3229b-e396. You most likely need a SIM card to use this modem.<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = Untested<br />
|Smartcard_comments = A SIM card slot is available.<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|Mini_PCI_cards_comments = One mini-PCIe slot.<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|COM2_comments = coreboot has a driver for Oxford OXPCIe952 serial port PCIe cards<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = WIP<br />
|Speaker_comments = http://review.coreboot.org/#/c/1410/<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = ?<br />
|Watchdog_status = ?<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = N/A<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = External programmer required.<br />
}}</div>Idwerhttps://www.coreboot.org/index.php?title=Board:samsung/lumpy&diff=11151Board:samsung/lumpy2012-08-08T20:24:15Z<p>Idwer: VGA</p>
<hr />
<div>= Samsung XE550C22-H02US (aka Samsung Lumpy aka chromebook) =<br />
<br />
Features a "Multi Card Slot 4- in-1 (SD/SDHC/SDXC/MMC)"<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core i5-2467M, FCBGA1023<br />
|CPU_L1_status = ?<br />
|CPU_L2_status = ?<br />
|CPU_L3_status = ?<br />
|CPU_virt_status = ?<br />
|CPU_virt_status_comments = Untested<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = OK<br />
|RAM_SODIMM_comments = One SODIMM slot.<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = ?<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = mSATA. This chromebook comes with a SanDisk SDSA4DH-016G.<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_VGA_comments = Instead of an analog VGA connector there is a displayport (dp++) connector. Untested.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Realtek 8111/8168<br />
|Onboard_wireless = OK<br />
|Onboard_wireless_comments = Atheros AR9300 (ar5bhb116), 802.11 a/b/g/n<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_modem_comments = Qualcomm WWAN modem, t77z204t12/pkrnvwe396/3229b-e396. You most likely need a SIM card to use this modem.<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = Untested<br />
|Smartcard_comments = A SIM card slot is available.<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|Mini_PCI_cards_comments = One mini-PCIe slot.<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|COM2_comments = coreboot has a driver for Oxford OXPCIe952 serial port PCIe cards<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = WIP<br />
|Speaker_comments = http://review.coreboot.org/#/c/1410/<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = ?<br />
|Watchdog_status = ?<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = N/A<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = External programmer required.<br />
}}</div>Idwerhttps://www.coreboot.org/index.php?title=Developer_Manual/Tools&diff=11150Developer Manual/Tools2012-08-08T19:49:35Z<p>Idwer: /* External EPROM/Flash programmer that can program the flash chip on your motherboard */</p>
<hr />
<div></div>Idwerhttps://www.coreboot.org/index.php?title=Board:samsung/lumpy&diff=11149Board:samsung/lumpy2012-08-08T16:26:56Z<p>Idwer: </p>
<hr />
<div>= Samsung XE550C22-H02US (aka Samsung Lumpy aka chromebook) =<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core i5-2467M, FCBGA1023<br />
|CPU_L1_status = ?<br />
|CPU_L2_status = ?<br />
|CPU_L3_status = ?<br />
|CPU_virt_status = ?<br />
|CPU_virt_status_comments = untested<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = OK<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = ?<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = mSATA.<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = WIP<br />
|Onboard_VGA_comments = displayport (dp++), untested.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Realtek 8111/8168<br />
|Onboard_wireless = OK<br />
|Onboard_wireless_comments = Atheros AR9300 802.11 a/b/g/n<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|Mini_PCI_cards_comments = there is a mini-pcie slot.<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Onboard_multicard_slot = WIP<br />
|Onboard_multicard_slot_comments = SD/SDHC/SDXC/MMC, untested.<br />
|Onboard_webcam_status = OK<br />
|Onboard_webcam_status_comments = I look pretty.<br />
|Onboard_SIM_slot = ?<br />
|Onboard_SIM_slot_comments = untested.<br />
|Mini_PCIe_cards_status = OK<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|COM2_comments = coreboot has a driver for Oxford OXPCIe952 serial port PCIe cards<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = WIP<br />
|Speaker_comments = http://review.coreboot.org/#/c/1410/<br />
|DiskOnChip_status = N/A<br />
<br />
<br />
|Sensors_status = ?<br />
|Watchdog_status = ?<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = WIP<br />
|LEDs_comments = ?<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = External programmer required.<br />
}}</div>Idwerhttps://www.coreboot.org/index.php?title=Board:samsung/lumpy&diff=11148Board:samsung/lumpy2012-08-08T15:56:15Z<p>Idwer: Created page with "= Lenovo ThinkPad X60s = == Status == {{Status| |CPU_status = OK |CPU_comments = Core i5-2467M, FCBGA1023 |CPU_L1_status = OK |CPU_L2_status = OK |CPU_L3_status = N/A |CPU_vi..."</p>
<hr />
<div>= Lenovo ThinkPad X60s =<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core i5-2467M, FCBGA1023<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = ?<br />
|CPU_virt_status_comment = untested<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_SODIMM_status = OK<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = ?<br />
|RAM_ecc_status = ?<br />
<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_displayport_status = WIP<br />
|Onboard_displayport_status_comment = untested.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Realtek 8111/8168<br />
|Onboard_wireless = OK<br />
|Onboard_wireless_comment = Atheros AR9300 802.11 a/b/g/n<br />
|Onboard_audio_status = OK<br />
|Onboard_multicard_slot = WIP<br />
|Onboard_multicard_slot_comment = SD/SDHC/SDXC/MMC, untested.<br />
|Onboard_webcam_status = OK<br />
|Onboard_webcam_status_comment = I look pretty.<br />
|Onboard_SIM_slot = ?<br />
|Onboard_SIM_slot_comment = untested.<br />
|Mini_PCIe_cards_status = OK<br />
<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|COM2_comments = coreboot has a driver for Oxford OXPCIe952 serial port PCIe cards<br />
|Speaker_status = WIP<br />
|Speaker_comment = http://review.coreboot.org/#/c/1410/<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = WIP<br />
|LEDs_comments = ?<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = External programmer required.<br />
}}</div>Idwer