http://www.coreboot.org/api.php?action=feedcontributions&user=MBertens&feedformat=atom 2013-06-19T05:56:27Z User contributions MediaWiki 1.21.1 http://www.coreboot.org/Talk:FOSDEM_2011 2011-01-29T11:53:00Z

<p>MBertens: /* Who brings what */</p> <hr /> <div>== Useful info ==<br /> <br /> Question:<br /> Is there a limit for the power we can draw at our booth? The coreboot/flashrom projects have a joint booth and we have lots of hardware for demos, and some of that hardware is a bit hungry... the number of outlets is not a problem for us, we have our own multi-socket extender.<br /> <br /> Answer:<br /> In that case, please bring a sufficiently long extension cord so we can hook you up directly to the power distribution cabinets in the hallway. I'm not sure how much they can cope with, it's all ULB infrastructure, but I suppose it should be enough :)<br /> <br /> <br /> == Who brings what ==<br /> <br /> * carldani<br /> ** 1x Schuko multi-outlet power strip with 10 sockets and CEE 7/7 hybrid Schuko/French plug<br /> * ruik<br /> ** 1x LCD monitor<br /> ** 1x usb2serial + serial cable<br /> ** 1x PSU 400W<br /> ** 1x Asus M2V-MX SE + CPU + RAM<br /> ** 1x Asrock 939A785GMH/128M + CPU + RAM<br /> ** 1x IDE system HDD + CABLE<br /> ** 1x SATA hdd (no system so far)<br /> ** 1x POST card<br /> ** 1x CDROM IDE<br /> ** couple of SPI flash chips (1M winbonds some 512KB AMICs)<br /> ** 1x PS2 keyboard and mouse + usb2ps2<br /> * Svens<br /> ** Thinkpad X60s running coreboot <br /> * mbertens<br /> ** Nokia IP530 coreboot development machine <br /> ** Nokia IP330 <br /> ** Some Compact PCI cards<br /> <br /> == Hotel ==<br /> <br /> We mostly stay in http://www.booking.com/hotel/be/hibrusselscc.html?aid=304142;label=postbooking_confemail<br /> <br /> So far we know that following Coreboot fellows stays there:<br /> <br /> * Ruik (plus 2 colleagues Pavel and Milan)<br /> * CareBear<br /> * Carldani<br /> * Svens<br /> * MBertens</div>

MBertens http://www.coreboot.org/Talk:FOSDEM_2011 2011-01-29T11:44:23Z

<p>MBertens: /* Who brings what */</p> <hr /> <div>== Useful info ==<br /> <br /> Question:<br /> Is there a limit for the power we can draw at our booth? The coreboot/flashrom projects have a joint booth and we have lots of hardware for demos, and some of that hardware is a bit hungry... the number of outlets is not a problem for us, we have our own multi-socket extender.<br /> <br /> Answer:<br /> In that case, please bring a sufficiently long extension cord so we can hook you up directly to the power distribution cabinets in the hallway. I'm not sure how much they can cope with, it's all ULB infrastructure, but I suppose it should be enough :)<br /> <br /> <br /> == Who brings what ==<br /> <br /> * 1x Schuko multi-outlet power strip with 10 sockets and CEE 7/7 hybrid Schuko/French plug (carldani)<br /> * 1x LCD monitor (ruik)<br /> * 1x usb2serial + serial cable (ruik)<br /> * 1x PSU 400W<br /> * 1x Asus M2V-MX SE + CPU + RAM (ruik)<br /> * 1x Asrock 939A785GMH/128M + CPU + RAM (ruik)<br /> * 1x IDE system HDD + CABLE (ruik)<br /> * 1x SATA hdd (no system so far) (ruik)<br /> * 1x POST card (ruik)<br /> * 1x CDROM IDE<br /> * couple of SPI flash chips (1M winbonds some 512KB AMICs)<br /> * 1x PS2 keyboard and mouse + usb2ps2<br /> * Thinkpad X60s running coreboot (svens)<br /> * Nokia IP530 coreboot development machine (mbertens)<br /> * Nokia IP330 (mbertens)<br /> * Some Compact PCI cards (mbertens)<br /> <br /> == Hotel ==<br /> <br /> We mostly stay in http://www.booking.com/hotel/be/hibrusselscc.html?aid=304142;label=postbooking_confemail<br /> <br /> So far we know that following Coreboot fellows stays there:<br /> <br /> * Ruik (plus 2 colleagues Pavel and Milan)<br /> * CareBear<br /> * Carldani<br /> * Svens<br /> * MBertens</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-29T07:46:18Z

<p>MBertens: /* EEPROM behide the SuperIO */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> <br /> ----<br /> === Device connectors ===<br /> <br /> * '''J1''' Backplane CPU fan<br /> * '''J2''' Backplane system fan<br /> * '''J3''' Backplane system fan<br /> * '''J4''' Backplane system fan<br /> * '''J5''' CPU fan (not used)<br /> * '''J9''' IDE connector<br /> * '''J10''' The Floppy connector<br /> * '''J15''' Serial port connector (ML10), COM2<br /> * '''J16''' Phone connector (behind front)<br /> * '''J17''' Ethernet RJ45 connector eth s3<br /> * '''J18''' Ethernet RJ45 connector eth s4<br /> * '''J19''' Ethernet RJ45 connector eth s5<br /> <br /> <br /> -----<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> <br /> ----<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP330\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker between NB and SB<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:33:27Z

<p>MBertens: /* Front LED */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> <br /> ----<br /> === Device connectors ===<br /> <br /> * '''J1''' Backplane CPU fan<br /> * '''J2''' Backplane system fan<br /> * '''J3''' Backplane system fan<br /> * '''J4''' Backplane system fan<br /> * '''J5''' CPU fan (not used)<br /> * '''J9''' IDE connector<br /> * '''J10''' The Floppy connector<br /> * '''J15''' Serial port connector (ML10), COM2<br /> * '''J16''' Phone connector (behind front)<br /> * '''J17''' Ethernet RJ45 connector eth s3<br /> * '''J18''' Ethernet RJ45 connector eth s4<br /> * '''J19''' Ethernet RJ45 connector eth s5<br /> <br /> <br /> -----<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> <br /> ----<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:33:16Z

<p>MBertens: /* jumpers */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> <br /> ----<br /> === Device connectors ===<br /> <br /> * '''J1''' Backplane CPU fan<br /> * '''J2''' Backplane system fan<br /> * '''J3''' Backplane system fan<br /> * '''J4''' Backplane system fan<br /> * '''J5''' CPU fan (not used)<br /> * '''J9''' IDE connector<br /> * '''J10''' The Floppy connector<br /> * '''J15''' Serial port connector (ML10), COM2<br /> * '''J16''' Phone connector (behind front)<br /> * '''J17''' Ethernet RJ45 connector eth s3<br /> * '''J18''' Ethernet RJ45 connector eth s4<br /> * '''J19''' Ethernet RJ45 connector eth s5<br /> <br /> <br /> -----<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> <br /> ----<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:32:59Z

<p>MBertens: /* System Setup */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> <br /> ----<br /> === Device connectors ===<br /> <br /> * '''J1''' Backplane CPU fan<br /> * '''J2''' Backplane system fan<br /> * '''J3''' Backplane system fan<br /> * '''J4''' Backplane system fan<br /> * '''J5''' CPU fan (not used)<br /> * '''J9''' IDE connector<br /> * '''J10''' The Floppy connector<br /> * '''J15''' Serial port connector (ML10), COM2<br /> * '''J16''' Phone connector (behind front)<br /> * '''J17''' Ethernet RJ45 connector eth s3<br /> * '''J18''' Ethernet RJ45 connector eth s4<br /> * '''J19''' Ethernet RJ45 connector eth s5<br /> <br /> <br /> -----<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:32:44Z

<p>MBertens: /* Device connectors */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> * '''J1''' Backplane CPU fan<br /> * '''J2''' Backplane system fan<br /> * '''J3''' Backplane system fan<br /> * '''J4''' Backplane system fan<br /> * '''J5''' CPU fan (not used)<br /> * '''J9''' IDE connector<br /> * '''J10''' The Floppy connector<br /> * '''J15''' Serial port connector (ML10), COM2<br /> * '''J16''' Phone connector (behind front)<br /> * '''J17''' Ethernet RJ45 connector eth s3<br /> * '''J18''' Ethernet RJ45 connector eth s4<br /> * '''J19''' Ethernet RJ45 connector eth s5<br /> <br /> <br /> -----<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:32:33Z

<p>MBertens: /* Device connectors */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> * '''J1''' Backplane CPU fan<br /> * '''J2''' Backplane system fan<br /> * '''J3''' Backplane system fan<br /> * '''J4''' Backplane system fan<br /> * '''J5''' CPU fan (not used)<br /> * '''J9''' IDE connector<br /> * '''J10''' The Floppy connector<br /> * '''J15''' Serial port connector (ML10), COM2<br /> * '''J16''' Phone connector (behind front)<br /> * '''J17''' Ethernet RJ45 connector eth s3<br /> * '''J18''' Ethernet RJ45 connector eth s4<br /> * '''J19''' Ethernet RJ45 connector eth s5<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:31:54Z

<p>MBertens: /* Device connectors */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> <br /> * '''J1''' Backplane CPU fan<br /> <br /> * J2 Backplane system fan<br /> <br /> * J3 Backplane system fan<br /> <br /> * J4 Backplane system fan<br /> <br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J10 The Floppy connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> <br /> * J16 Phone connector (behind front)<br /> <br /> * J17 Ethernet RJ45 connector eth s3<br /> <br /> * J18 Ethernet RJ45 connector eth s4<br /> <br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:31:43Z

<p>MBertens: /* Device connectors */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> <br /> * 'J1' Backplane CPU fan<br /> <br /> * J2 Backplane system fan<br /> <br /> * J3 Backplane system fan<br /> <br /> * J4 Backplane system fan<br /> <br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J10 The Floppy connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> <br /> * J16 Phone connector (behind front)<br /> <br /> * J17 Ethernet RJ45 connector eth s3<br /> <br /> * J18 Ethernet RJ45 connector eth s4<br /> <br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:31:34Z

<p>MBertens: /* Device connectors */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> <br /> * ''J1'' Backplane CPU fan<br /> <br /> * J2 Backplane system fan<br /> <br /> * J3 Backplane system fan<br /> <br /> * J4 Backplane system fan<br /> <br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J10 The Floppy connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> <br /> * J16 Phone connector (behind front)<br /> <br /> * J17 Ethernet RJ45 connector eth s3<br /> <br /> * J18 Ethernet RJ45 connector eth s4<br /> <br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:31:10Z

<p>MBertens: /* Device connectors */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> <br /> * J1 Backplane CPU fan<br /> <br /> * J2 Backplane system fan<br /> <br /> * J3 Backplane system fan<br /> <br /> * J4 Backplane system fan<br /> <br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J10 The Floppy connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> <br /> * J16 Phone connector (behind front)<br /> <br /> * J17 Ethernet RJ45 connector eth s3<br /> <br /> * J18 Ethernet RJ45 connector eth s4<br /> <br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:29:05Z

<p>MBertens: /* Connectors &amp; jumpers */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> <br /> ==== J1 ====<br /> <br /> Backplane CPU fan<br /> <br /> ==== J2 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J3 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J4 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J5 ====<br /> <br /> CPU fan (not used)<br /> <br /> ==== J9 ====<br /> <br /> IDE connector<br /> <br /> ==== J10 ====<br /> <br /> The J10 Floppy connector<br /> <br /> ==== J15 ====<br /> <br /> Serial port connector (ML10), COM2<br /> <br /> ==== J16 ====<br /> <br /> Phone connector (behind front)<br /> <br /> ==== J17 ====<br /> <br /> Ethernet RJ45 connector eth s3<br /> <br /> ==== J18 ====<br /> <br /> Ethernet RJ45 connector eth s4<br /> <br /> ==== J19 ====<br /> <br /> Ethernet RJ45 connector eth s5<br /> <br /> === jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> === Power connectors ===<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:28:22Z

<p>MBertens: /* J1 */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> === Device connectors ===<br /> <br /> <br /> ==== J1 ====<br /> <br /> Backplane CPU fan<br /> <br /> ==== J2 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J3 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J4 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J5 ====<br /> <br /> CPU fan (not used)<br /> <br /> ==== J9 ====<br /> <br /> IDE connector<br /> <br /> ==== J10 ====<br /> <br /> The J10 Floppy connector<br /> <br /> ==== J15 ====<br /> <br /> Serial port connector (ML10), COM2<br /> <br /> ==== J16 ====<br /> <br /> Phone connector (behind front)<br /> <br /> ==== J17 ====<br /> <br /> Ethernet RJ45 connector eth s3<br /> <br /> ==== J18 ====<br /> <br /> Ethernet RJ45 connector eth s4<br /> <br /> ==== J19 ====<br /> <br /> Ethernet RJ45 connector eth s5<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:27:40Z

<p>MBertens: /* EEPROM behide the SuperIO */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J1 ====<br /> <br /> Backplane CPU fan<br /> <br /> ==== J2 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J3 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J4 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J5 ====<br /> <br /> CPU fan (not used)<br /> <br /> ==== J9 ====<br /> <br /> IDE connector<br /> <br /> ==== J10 ====<br /> <br /> The J10 Floppy connector<br /> <br /> ==== J15 ====<br /> <br /> Serial port connector (ML10), COM2<br /> <br /> ==== J16 ====<br /> <br /> Phone connector (behind front)<br /> <br /> ==== J17 ====<br /> <br /> Ethernet RJ45 connector eth s3<br /> <br /> ==== J18 ====<br /> <br /> Ethernet RJ45 connector eth s4<br /> <br /> ==== J19 ====<br /> <br /> Ethernet RJ45 connector eth s5<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, <br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> The eeprom can be read through the LDN RTC of the superio.<br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:26:04Z

<p>MBertens: /* J10 */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J1 ====<br /> <br /> Backplane CPU fan<br /> <br /> ==== J2 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J3 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J4 ====<br /> <br /> Backplane system fan<br /> <br /> ==== J5 ====<br /> <br /> CPU fan (not used)<br /> <br /> ==== J9 ====<br /> <br /> IDE connector<br /> <br /> ==== J10 ====<br /> <br /> The J10 Floppy connector<br /> <br /> ==== J15 ====<br /> <br /> Serial port connector (ML10), COM2<br /> <br /> ==== J16 ====<br /> <br /> Phone connector (behind front)<br /> <br /> ==== J17 ====<br /> <br /> Ethernet RJ45 connector eth s3<br /> <br /> ==== J18 ====<br /> <br /> Ethernet RJ45 connector eth s4<br /> <br /> ==== J19 ====<br /> <br /> Ethernet RJ45 connector eth s5<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:24:36Z

<p>MBertens: /* Connectors &amp; jumpers */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 Floppy connector<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:24:08Z

<p>MBertens: /* J10 */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 Floppy connector<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * J1 Backplane CPU fan<br /> * J2 Backplane system fan<br /> * J3 Backplane system fan<br /> * J4 Backplane system fan<br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> * J16 Phone connector (behind front)<br /> * J17 Ethernet RJ45 connector eth s3<br /> * J18 Ethernet RJ45 connector eth s4<br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T21:21:13Z

<p>MBertens: /* Connectors &amp; jumpers */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J10 connector (JDEBUG)<br /> ! Pin# !! Name !! Description || Pin# || Name || Description<br /> |------------------------------<br /> | 1|| unknown||?||2||VCC +5 Volt||n/a<br /> |------------------------------<br /> | 3|| A16 ||Address line A16 || 4||A18||Address line A18 <br /> |------------------------------<br /> | 5|| A15 ||Address line A15 || 6||A17||Address line A17 <br /> |------------------------------<br /> | 7|| A12 ||Address line A12 || 8||A14||Address line A14 <br /> |------------------------------<br /> | 9|| A7 ||Address line A7 || 10||A13||Address line A13<br /> |------------------------------<br /> |11|| A6 ||Address line A6 || 12|| A8||Address line A8 <br /> |------------------------------<br /> |13|| A5 ||Address line A5 || 14|| A9||Address line A9 <br /> |------------------------------<br /> |15|| A4 ||Address line A4 || 16|| A11 ||Address line A11 <br /> |------------------------------<br /> |17|| A3 ||Address line A3 || 18|| OE# ||Chip Enable Line OE# <br /> |------------------------------<br /> |19|| A2 ||Address line A2 || 20|| A10 ||Address line A10 <br /> |------------------------------<br /> |21|| A1 ||Address line A1 || 22|| JP800.1 || BIOSCS#<br /> |------------------------------<br /> |23|| A0 ||Address line A0 || 24|| D7 ||Data line D7 <br /> |------------------------------<br /> |25|| D0 ||Data line A0 || 26|| D6 ||Data line D6<br /> |------------------------------<br /> |27|| D1 ||Data line D1 || 28|| D5 ||Data line D5<br /> |------------------------------<br /> |29|| D2 ||Data line D2 || 30|| D4 ||Data line D4<br /> |------------------------------<br /> |31|| IOW#||Control line IOW#|| 32|| D3 ||Data line D3<br /> |------------------------------<br /> |33|| GND ||Ground || 34|| IOR#||Control line IOR#<br /> |}<br /> <br /> For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. <br /> <br /> [[media:Rom-option-board-schema.pdf|Schematic ROM option board]]<br /> <br /> As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.<br /> <br /> [[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]<br /> <br /> The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time. <br /> <br /> The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in. <br /> <br /> [[media:Rom-option-board-overview.pdf|Components overview PCB]]<br /> <br /> When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. <br /> <br /> ----<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> ** 1-2 <br /> ** 3-4 <br /> ** 5-6 <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * J1 Backplane CPU fan<br /> * J2 Backplane system fan<br /> * J3 Backplane system fan<br /> * J4 Backplane system fan<br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> * J16 Phone connector (behind front)<br /> * J17 Ethernet RJ45 connector eth s3<br /> * J18 Ethernet RJ45 connector eth s4<br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T19:55:40Z

<p>MBertens: /* J10 */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J10 connector (JDEBUG)<br /> ! Pin# !! Name !! Description || Pin# || Name || Description<br /> |------------------------------<br /> | 1|| unknown||?||2||VCC +5 Volt||n/a<br /> |------------------------------<br /> | 3|| A16 ||Address line A16 || 4||A18||Address line A18 <br /> |------------------------------<br /> | 5|| A15 ||Address line A15 || 6||A17||Address line A17 <br /> |------------------------------<br /> | 7|| A12 ||Address line A12 || 8||A14||Address line A14 <br /> |------------------------------<br /> | 9|| A7 ||Address line A7 || 10||A13||Address line A13<br /> |------------------------------<br /> |11|| A6 ||Address line A6 || 12|| A8||Address line A8 <br /> |------------------------------<br /> |13|| A5 ||Address line A5 || 14|| A9||Address line A9 <br /> |------------------------------<br /> |15|| A4 ||Address line A4 || 16|| A11 ||Address line A11 <br /> |------------------------------<br /> |17|| A3 ||Address line A3 || 18|| OE# ||Chip Enable Line OE# <br /> |------------------------------<br /> |19|| A2 ||Address line A2 || 20|| A10 ||Address line A10 <br /> |------------------------------<br /> |21|| A1 ||Address line A1 || 22|| JP800.1 || BIOSCS#<br /> |------------------------------<br /> |23|| A0 ||Address line A0 || 24|| D7 ||Data line D7 <br /> |------------------------------<br /> |25|| D0 ||Data line A0 || 26|| D6 ||Data line D6<br /> |------------------------------<br /> |27|| D1 ||Data line D1 || 28|| D5 ||Data line D5<br /> |------------------------------<br /> |29|| D2 ||Data line D2 || 30|| D4 ||Data line D4<br /> |------------------------------<br /> |31|| IOW#||Control line IOW#|| 32|| D3 ||Data line D3<br /> |------------------------------<br /> |33|| GND ||Ground || 34|| IOR#||Control line IOR#<br /> |}<br /> <br /> For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. <br /> <br /> [[media:Rom-option-board-schema.pdf|Schematic ROM option board]]<br /> <br /> As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.<br /> <br /> [[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]<br /> <br /> The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time. <br /> <br /> The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in. <br /> <br /> [[media:Rom-option-board-overview.pdf|Components overview PCB]]<br /> <br /> When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. <br /> <br /> ----<br /> <br /> === Connectors &amp; jumpers ===<br /> * JP1<br /> ** 1-2 = short reset CMOS ? <br /> <br /> * JP2 (besides CPU, not soldered in) <br /> <br /> * JP3<br /> ** 1-2 = P or E mode<br /> ** 2-3 = All BLK locked (default)<br /> <br /> * JP4<br /> ** 1-2 = B.B. Unlocked<br /> ** 2-3 = B.B locked (default)<br /> <br /> * JP5<br /> ** <br /> **<br /> <br /> * JP6<br /> ** 1-6 B.B. Locked (default) <br /> ** 2-5 B.B. Unlocked<br /> ** 3-4 B.B. DPD Locked<br /> <br /> * JP11-JP13 Serial port COM2<br /> * JP12-JP14 Internal modem<br /> <br /> * J1 Backplane CPU fan<br /> * J2 Backplane system fan<br /> * J3 Backplane system fan<br /> * J4 Backplane system fan<br /> * J5 CPU fan (not used)<br /> <br /> * J9 IDE connector<br /> <br /> * J15 Serial port connector (ML10), COM2<br /> * J16 Phone connector (behind front)<br /> * J17 Ethernet RJ45 connector eth s3<br /> * J18 Ethernet RJ45 connector eth s4<br /> * J19 Ethernet RJ45 connector eth s5<br /> <br /> * P1 option power connector<br /> * P2 IDE power connector<br /> * P3 Serial port connector (DB9), COM1<br /> <br /> * P6 Power connector<br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T13:52:11Z

<p>MBertens: /* System Setup */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * CPU: Socket 7, AMD K6 II at 266 MHz normally, <br /> ** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those. <br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> ** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM. <br /> ** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J10 connector (JDEBUG)<br /> ! Pin# !! Name !! Description || Pin# || Name || Description<br /> |------------------------------<br /> | 1|| unknown||?||2||VCC +5 Volt||n/a<br /> |------------------------------<br /> | 3|| A16 ||Address line A16 || 4||A18||Address line A18 <br /> |------------------------------<br /> | 5|| A15 ||Address line A15 || 6||A17||Address line A17 <br /> |------------------------------<br /> | 7|| A12 ||Address line A12 || 8||A14||Address line A14 <br /> |------------------------------<br /> | 9|| A7 ||Address line A7 || 10||A13||Address line A13<br /> |------------------------------<br /> |11|| A6 ||Address line A6 || 12|| A8||Address line A8 <br /> |------------------------------<br /> |13|| A5 ||Address line A5 || 14|| A9||Address line A9 <br /> |------------------------------<br /> |15|| A4 ||Address line A4 || 16|| A11 ||Address line A11 <br /> |------------------------------<br /> |17|| A3 ||Address line A3 || 18|| OE# ||Chip Enable Line OE# <br /> |------------------------------<br /> |19|| A2 ||Address line A2 || 20|| A10 ||Address line A10 <br /> |------------------------------<br /> |21|| A1 ||Address line A1 || 22|| JP800.1 || BIOSCS#<br /> |------------------------------<br /> |23|| A0 ||Address line A0 || 24|| D7 ||Data line D7 <br /> |------------------------------<br /> |25|| D0 ||Data line A0 || 26|| D6 ||Data line D6<br /> |------------------------------<br /> |27|| D1 ||Data line D1 || 28|| D5 ||Data line D5<br /> |------------------------------<br /> |29|| D2 ||Data line D2 || 30|| D4 ||Data line D4<br /> |------------------------------<br /> |31|| IOW#||Control line IOW#|| 32|| D3 ||Data line D3<br /> |------------------------------<br /> |33|| GND ||Ground || 34|| IOR#||Control line IOR#<br /> |}<br /> <br /> For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. <br /> <br /> [[media:Rom-option-board-schema.pdf|Schematic ROM option board]]<br /> <br /> As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.<br /> <br /> [[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]<br /> <br /> The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time. <br /> <br /> The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in. <br /> <br /> [[media:Rom-option-board-overview.pdf|Components overview PCB]]<br /> <br /> When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. <br /> <br /> ----<br /> <br /> JP1<br /> * 1-2 = short reset CMOS ? <br /> <br /> JP2 (besides CPU, not soldered in) <br /> <br /> JP3<br /> * 1-2 = P or E mode<br /> * 2-3 = All BLK locked (default)<br /> <br /> JP4<br /> * 1-2 = B.B. Unlocked<br /> * 2-3 = B.B locked (default)<br /> <br /> JP5<br /> * <br /> * <br /> JP6<br /> * 1-6 B.B. Locked (default) <br /> * 2-5 B.B. Unlocked<br /> * 3-4 B.B. DPD Locked<br /> <br /> JP11-JP13 Serial port COM2<br /> JP12-JP14 Internal modem<br /> <br /> <br /> J1 Backplane CPU fan<br /> J2 Backplane system fan<br /> J3 Backplane system fan<br /> J4 Backplane system fan<br /> J5 CPU fan (not used)<br /> <br /> J9 IDE connector<br /> <br /> J15 Serial port connector (ML10), COM2<br /> J16 Phone connector (behind front)<br /> J17 Ethernet RJ45 connector eth s3<br /> J18 Ethernet RJ45 connector eth s4<br /> J19 Ethernet RJ45 connector eth s5<br /> <br /> P1 option power connector<br /> P2 IDE power connector<br /> P3 Serial port connector (DB9), COM1<br /> <br /> P6 Power connector<br /> <br /> <br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T13:23:33Z

<p>MBertens: /* System Setup */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * AMD K6<br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J10 connector (JDEBUG)<br /> ! Pin# !! Name !! Description || Pin# || Name || Description<br /> |------------------------------<br /> | 1|| unknown||?||2||VCC +5 Volt||n/a<br /> |------------------------------<br /> | 3|| A16 ||Address line A16 || 4||A18||Address line A18 <br /> |------------------------------<br /> | 5|| A15 ||Address line A15 || 6||A17||Address line A17 <br /> |------------------------------<br /> | 7|| A12 ||Address line A12 || 8||A14||Address line A14 <br /> |------------------------------<br /> | 9|| A7 ||Address line A7 || 10||A13||Address line A13<br /> |------------------------------<br /> |11|| A6 ||Address line A6 || 12|| A8||Address line A8 <br /> |------------------------------<br /> |13|| A5 ||Address line A5 || 14|| A9||Address line A9 <br /> |------------------------------<br /> |15|| A4 ||Address line A4 || 16|| A11 ||Address line A11 <br /> |------------------------------<br /> |17|| A3 ||Address line A3 || 18|| OE# ||Chip Enable Line OE# <br /> |------------------------------<br /> |19|| A2 ||Address line A2 || 20|| A10 ||Address line A10 <br /> |------------------------------<br /> |21|| A1 ||Address line A1 || 22|| JP800.1 || BIOSCS#<br /> |------------------------------<br /> |23|| A0 ||Address line A0 || 24|| D7 ||Data line D7 <br /> |------------------------------<br /> |25|| D0 ||Data line A0 || 26|| D6 ||Data line D6<br /> |------------------------------<br /> |27|| D1 ||Data line D1 || 28|| D5 ||Data line D5<br /> |------------------------------<br /> |29|| D2 ||Data line D2 || 30|| D4 ||Data line D4<br /> |------------------------------<br /> |31|| IOW#||Control line IOW#|| 32|| D3 ||Data line D3<br /> |------------------------------<br /> |33|| GND ||Ground || 34|| IOR#||Control line IOR#<br /> |}<br /> <br /> For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. <br /> <br /> [[media:Rom-option-board-schema.pdf|Schematic ROM option board]]<br /> <br /> As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.<br /> <br /> [[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]<br /> <br /> The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time. <br /> <br /> The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in. <br /> <br /> [[media:Rom-option-board-overview.pdf|Components overview PCB]]<br /> <br /> When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. <br /> <br /> ----<br /> <br /> JP1<br /> * 1-2 = short reset CMOS ? <br /> <br /> JP2 (besides CPU, not soldered in) <br /> <br /> JP3<br /> * 1-2 = P or E mode<br /> * 2-3 = All BLK locked (default)<br /> <br /> JP4<br /> * 1-2 = B.B. Unlocked<br /> * 2-3 = B.B locked (default)<br /> <br /> JP5<br /> * <br /> * <br /> JP6<br /> * 1-6 B.B. Locked (default) <br /> * 2-5 B.B. Unlocked<br /> * 3-4 B.B. DPD Locked<br /> <br /> JP11-JP13 Serial port COM2<br /> JP12-JP14 Internal modem<br /> <br /> <br /> J1 Backplane CPU fan<br /> J2 Backplane system fan<br /> J3 Backplane system fan<br /> J4 Backplane system fan<br /> J5 CPU fan (not used)<br /> <br /> J9 IDE connector<br /> <br /> J15 Serial port connector (ML10), COM2<br /> J16 Phone connector (behind front)<br /> J17 Ethernet RJ45 connector eth s3<br /> J18 Ethernet RJ45 connector eth s4<br /> J19 Ethernet RJ45 connector eth s5<br /> <br /> P1 option power connector<br /> P2 IDE power connector<br /> P3 Serial port connector (DB9), COM1<br /> <br /> P6 Power connector<br /> <br /> <br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T13:22:56Z

<p>MBertens: /* System Setup */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * AMD K6<br /> * I430TX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F200, 256 Kbyte flashrom.<br /> * SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.<br /> * LM72 temp controller.<br /> * 3 intel 82558B ethernet controllers.<br /> * 2 SD-RAM sockets.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * HOWTO read the status of the jumpers.<br /> * HOWTO enable/disable the LEDs.<br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J10 connector (JDEBUG)<br /> ! Pin# !! Name !! Description || Pin# || Name || Description<br /> |------------------------------<br /> | 1|| unknown||?||2||VCC +5 Volt||n/a<br /> |------------------------------<br /> | 3|| A16 ||Address line A16 || 4||A18||Address line A18 <br /> |------------------------------<br /> | 5|| A15 ||Address line A15 || 6||A17||Address line A17 <br /> |------------------------------<br /> | 7|| A12 ||Address line A12 || 8||A14||Address line A14 <br /> |------------------------------<br /> | 9|| A7 ||Address line A7 || 10||A13||Address line A13<br /> |------------------------------<br /> |11|| A6 ||Address line A6 || 12|| A8||Address line A8 <br /> |------------------------------<br /> |13|| A5 ||Address line A5 || 14|| A9||Address line A9 <br /> |------------------------------<br /> |15|| A4 ||Address line A4 || 16|| A11 ||Address line A11 <br /> |------------------------------<br /> |17|| A3 ||Address line A3 || 18|| OE# ||Chip Enable Line OE# <br /> |------------------------------<br /> |19|| A2 ||Address line A2 || 20|| A10 ||Address line A10 <br /> |------------------------------<br /> |21|| A1 ||Address line A1 || 22|| JP800.1 || BIOSCS#<br /> |------------------------------<br /> |23|| A0 ||Address line A0 || 24|| D7 ||Data line D7 <br /> |------------------------------<br /> |25|| D0 ||Data line A0 || 26|| D6 ||Data line D6<br /> |------------------------------<br /> |27|| D1 ||Data line D1 || 28|| D5 ||Data line D5<br /> |------------------------------<br /> |29|| D2 ||Data line D2 || 30|| D4 ||Data line D4<br /> |------------------------------<br /> |31|| IOW#||Control line IOW#|| 32|| D3 ||Data line D3<br /> |------------------------------<br /> |33|| GND ||Ground || 34|| IOR#||Control line IOR#<br /> |}<br /> <br /> For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. <br /> <br /> [[media:Rom-option-board-schema.pdf|Schematic ROM option board]]<br /> <br /> As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.<br /> <br /> [[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]<br /> <br /> The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time. <br /> <br /> The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in. <br /> <br /> [[media:Rom-option-board-overview.pdf|Components overview PCB]]<br /> <br /> When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. <br /> <br /> ----<br /> <br /> JP1<br /> * 1-2 = short reset CMOS ? <br /> <br /> JP2 (besides CPU, not soldered in) <br /> <br /> JP3<br /> * 1-2 = P or E mode<br /> * 2-3 = All BLK locked (default)<br /> <br /> JP4<br /> * 1-2 = B.B. Unlocked<br /> * 2-3 = B.B locked (default)<br /> <br /> JP5<br /> * <br /> * <br /> JP6<br /> * 1-6 B.B. Locked (default) <br /> * 2-5 B.B. Unlocked<br /> * 3-4 B.B. DPD Locked<br /> <br /> JP11-JP13 Serial port COM2<br /> JP12-JP14 Internal modem<br /> <br /> <br /> J1 Backplane CPU fan<br /> J2 Backplane system fan<br /> J3 Backplane system fan<br /> J4 Backplane system fan<br /> J5 CPU fan (not used)<br /> <br /> J9 IDE connector<br /> <br /> J15 Serial port connector (ML10), COM2<br /> J16 Phone connector (behind front)<br /> J17 Ethernet RJ45 connector eth s3<br /> J18 Ethernet RJ45 connector eth s4<br /> J19 Ethernet RJ45 connector eth s5<br /> <br /> P1 option power connector<br /> P2 IDE power connector<br /> P3 Serial port connector (DB9), COM1<br /> <br /> P6 Power connector<br /> <br /> <br /> <br /> ==== Front LED ====<br /> <br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:58:34Z

<p>MBertens: /* Hardware status */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}<br /> <br /> <br /> == System Setup ==<br /> <br /> On board of the IP530 can be found the following:<br /> * Pentium III.<br /> * I440BX northbridge.<br /> * 82371 southbridge.<br /> * intel 21150 PCI to PCI bridge.<br /> * 28F400, 512 Kbyte flashrom.<br /> * SMSC FDC37B787 superio with 1024 bits SPI eeprom attached.<br /> * LM78 power controller.<br /> * 4 intel 21143PD ethernet controllers with KS8716 PHY interface, with each a 1024 bits SPI eeprom attached.<br /> * Texas instruments PCI1225 PCMCIA/Cardbus controller with TPS22061 slot controller.<br /> * 4 SD-RAM sockets.<br /> <br /> Below the description is given for the following;<br /> * For the connectors on the mainboard of the Nokia IP530, due missing documentation of the manufacturer. <br /> * To create a flash option board on the J-DEBUG connector. <br /> * To create a USB port.<br /> * HOWTO read the status of the jumpers.<br /> * HOWTO enable/disable the LEDs.<br /> * The layout of the SPI eeprom behind the SuperIO.<br /> <br /> ----<br /> ==== J10 ====<br /> <br /> The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.<br /> <br /> {|border=&quot;1&quot;<br /> |+ JDEBUG connector<br /> ! Pin# !! Name !! Description || Pin# || Name || Description<br /> |------------------------------<br /> | 1|| unknown||?||2||VCC +5 Volt||n/a<br /> |------------------------------<br /> | 3|| A16 ||Address line A16 || 4||A18||Address line A18 <br /> |------------------------------<br /> | 5|| A15 ||Address line A15 || 6||A17||Address line A17 <br /> |------------------------------<br /> | 7|| A12 ||Address line A12 || 8||A14||Address line A14 <br /> |------------------------------<br /> | 9|| A7 ||Address line A7 || 10||A13||Address line A13<br /> |------------------------------<br /> |11|| A6 ||Address line A6 || 12|| A8||Address line A8 <br /> |------------------------------<br /> |13|| A5 ||Address line A5 || 14|| A9||Address line A9 <br /> |------------------------------<br /> |15|| A4 ||Address line A4 || 16|| A11 ||Address line A11 <br /> |------------------------------<br /> |17|| A3 ||Address line A3 || 18|| OE# ||Chip Enable Line OE# <br /> |------------------------------<br /> |19|| A2 ||Address line A2 || 20|| A10 ||Address line A10 <br /> |------------------------------<br /> |21|| A1 ||Address line A1 || 22|| JP800.1 || BIOSCS#<br /> |------------------------------<br /> |23|| A0 ||Address line A0 || 24|| D7 ||Data line D7 <br /> |------------------------------<br /> |25|| D0 ||Data line A0 || 26|| D6 ||Data line D6<br /> |------------------------------<br /> |27|| D1 ||Data line D1 || 28|| D5 ||Data line D5<br /> |------------------------------<br /> |29|| D2 ||Data line D2 || 30|| D4 ||Data line D4<br /> |------------------------------<br /> |31|| IOW#||Control line IOW#|| 32|| D3 ||Data line D3<br /> |------------------------------<br /> |33|| GND ||Ground || 34|| IOR#||Control line IOR#<br /> |}<br /> <br /> For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. <br /> <br /> [[media:Rom-option-board-schema.pdf|Schematic ROM option board]]<br /> <br /> As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.<br /> <br /> [[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]<br /> <br /> The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time. <br /> <br /> The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in. <br /> <br /> [[media:Rom-option-board-overview.pdf|Components overview PCB]]<br /> <br /> When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. <br /> <br /> ----<br /> <br /> ==== Jumper JP800 - BIOSCS select ====<br /> <br /> This jumper selected the on-board flash or the J-DEBUG connector where the BIOSCS# line is routed.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J800 Jumper<br /> ! Pin# !! Name !! Description<br /> |-<br /> |1||JDEBUG.P22||This is connected to PIN 22 of the JDEBUG connection on the board<br /> |-<br /> |2||BIOSCS#||Connected to the ROMCS# line of the Northbridge<br /> |-<br /> |3||CS#||This is connected to CS# of the on-board flash chip.<br /> |}<br /> <br /> The WP# line of the on-board flashchip is controlled by Pin39 of the SMSC FDC37B787 Super I/O chip.<br /> <br /> On the production boards the J800 is not present and the R814 (0 Ohm) is placed, remove this resistor and solder in the 3 pin-jumper for JP800. And place the jumper on position 2-3 to select the on-board flash chip.<br /> <br /> ----<br /> <br /> ==== Jumper JP900 ====<br /> <br /> This is a input signal on the Super I/O chip.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J900 Jumper<br /> ! Pin# !! Name !! Description<br /> |-<br /> |1||GND||Ground of the system<br /> |-<br /> |2||GPIO16||Pin 4 of the SMSC FDC37B787 Super I/O chip.<br /> |}<br /> <br /> Pin 2 is pulled-up by resistor up VCC.<br /> <br /> #define REG_GP1x 0xF6<br /> #define JP900 0x20<br /> <br /> sio_enter_config( 0x3F0 );<br /> val = (sio_read( 0x3F0, REG_GP6x ) &amp; JP901); <br /> sio_leave_config( 0x3F0 );<br /> <br /> <br /> ----<br /> <br /> ==== Jumper JP901 ====<br /> <br /> This is a input signal on the Super I/O chip.<br /> <br /> {|border=&quot;1&quot;<br /> |+ J901 Jumper<br /> ! Pin# !! Name !! Description<br /> |-<br /> |1||GND||Ground of the system<br /> |-<br /> |2||GPIO67||Pin 90 of the SMSC FDC37B787 Super I/O chip.<br /> |}<br /> <br /> Pin 2 is pulled-up by resistor up VCC.<br /> <br /> #define REG_GP6x 0xYY<br /> #define JP901 0x80<br /> <br /> sio_enter_config( 0x3F0 );<br /> val = (sio_read( 0x3F0, REG_GP6x ) &amp; JP901); <br /> sio_leave_config( 0x3F0 );<br /> <br /> <br /> ----<br /> <br /> ==== Front LED ====<br /> {|border=&quot;1&quot;<br /> |+ LEDs in front<br /> ! LED !! Control line !! Description<br /> |-<br /> |Fault||FDC37B787-GP13||active low<br /> |}<br /> <br /> #define REG_GP1x 0xF6<br /> #define LED_FAULT 0x08<br /> <br /> sio_enter_config( 0x3F0 );<br /> val = sio_read( 0x3F0, REG_GP1x );<br /> <br /> // To enable the ALERT led<br /> val &amp;= ~LED_ALERT;<br /> <br /> // To disable the ALERT led<br /> val |= LED_ALERT;<br /> <br /> // To enable the FAULT led<br /> val &amp;= ~LED_FAULT;<br /> <br /> // To disable the FAULT led<br /> val |= LED_FAULT;<br /> <br /> sio_write( 0x3F0, REG_GP1x, val );<br /> sio_leave_config( 0x3F0 );<br /> <br /> By using the sio_xxx() functions from flashrom, makes easy work dis-/en-abling the LEDs in the front.<br /> <br /> ----<br /> ==== EEPROM behide the SuperIO ====<br /> {|border=&quot;1&quot;<br /> |+ EEPROM information<br /> ! address range !! length !! Content !! Description<br /> |-<br /> |0x00-0x05||6 bytes||IP530\x00||Product name<br /> |-<br /> |0x06-0x13||14 bytes||0x55||Filler<br /> |-<br /> |0x14-0x17||4 bytes||0x05,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x18-0x1B||4 bytes||0x04,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x1C-0x1F||4 bytes||0x03,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown<br /> |-<br /> |0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu<br /> |-<br /> |0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces<br /> |-<br /> |0x38-0x3D||6 bytes||0x55||Filler<br /> |-<br /> |0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42<br /> |-<br /> |0x40-0x51||18 bytes||0x55||Filler<br /> |-<br /> |0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)<br /> |-<br /> |0x5E-0x7D||32 bytes||0x55||Filler<br /> |-<br /> |0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF<br /> |}<br /> <br /> On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.<br /> <br /> &lt;font color=&quot;red&quot;&gt;&lt;br&gt;<br /> Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.<br /> &lt;br&gt;&lt;/font&gt;<br /> <br /> ----</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:56:41Z

<p>MBertens: /* Hardware status */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = WIP<br /> |CPU_comments = K6<br /> |CPU_L1_status = WIP<br /> |CPU_L1_comments = <br /> |CPU_L2_status = WIP<br /> |CPU_L2_comments = <br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = WIP<br /> |RAM_SDRAM_comments =<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = <br /> <br /> |IDE_status = OK<br /> |IDE_comments = One IDE connector on-board<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = N/A<br /> |USB_comments = <br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = WIP<br /> |Onboard_ethernet_comments = Three intel SB82558B controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = N/A<br /> |Onboard_PCMCIA_status = N/A<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = WIP<br /> |PCI_cards_comments = <br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = N/A<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = WIP<br /> |LEDs_comments = Special-purpose LED available on the board, '''Fault''' is controlled by the superio?<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = WIP<br /> |Flashrom_comments = Supported flashrom revision will be higher than 1257.<br /> }}</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:51:48Z

<p>MBertens: /* Development status */</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet<br /> <br /> <br /> <br /> == Hardware status ==<br /> <br /> {{Status|<br /> <br /> |CPU_status = OK<br /> |CPU_comments = PIII SL5DV (1000 / 256 / 133 / 1.75V)<br /> |CPU_L1_status = OK<br /> |CPU_L1_comments = CPU: L1 I cache: 16K, L1 D cache: 16K<br /> |CPU_L2_status = OK<br /> |CPU_L2_comments = L2 cache is standard for the P3-68X models<br /> |CPU_L3_status = N/A<br /> |CPU_multiple_status = N/A<br /> |CPU_multicore_status = N/A<br /> |CPU_virt_status = N/A<br /> <br /> |RAM_EDO_status = N/A<br /> |RAM_SDRAM_status = OK<br /> |RAM_SDRAM_comments = upto 4 single sided 128Mb or 4 dual sided 256Mb<br /> |RAM_SODIMM_status = N/A<br /> |RAM_DDR_status = N/A<br /> |RAM_DDR2_status = N/A<br /> |RAM_DDR3_status = N/A<br /> |RAM_dualchannel_status = N/A<br /> |RAM_ecc_status = WIP<br /> |RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.<br /> <br /> |IDE_status = OK<br /> |IDE_comments = Primary and secondary controllers, the primary controller has a Compact Flash slot attached on board, as primary drive.<br /> |IDE_25_status = N/A<br /> |SATA_status = N/A<br /> |USB_status = OK<br /> |USB_comments = The USB is not routed to any connector, u can be picked up from the board it self, there is an instruction below on this wiki-page how to do this<br /> |Onboard_VGA_status = N/A<br /> |Onboard_ethernet_status = OK<br /> |Onboard_ethernet_comments = Four intel 21143PD controllers.<br /> |Onboard_audio_status = N/A<br /> |Onboard_modem_status = N/A<br /> |Onboard_firewire_status = N/A<br /> |Smartcard_status = N/A<br /> |Onboard_CF_status = OK<br /> |Onboard_CF_comments = Is wrired are primary drive on primary IDE controller.<br /> |Onboard_PCMCIA_status = OK<br /> |Onboard_PCMCIA_comments = Texas Instruments PCI1225 PCMCIA/Cardbus controller<br /> |Onboard_SCSI_status = N/A<br /> <br /> |ISA_cards_status = N/A<br /> |AMR_cards_status = N/A<br /> |Mini_PCI_cards_status = N/A<br /> |PCIX_cards_status = N/A<br /> |PCI_cards_status = OK<br /> |PCI_cards_comments = Tested: With 4 Ethernet adapter card of Nokia (Compact-PCI slots)<br /> |AGP_cards_status = N/A<br /> |PCIE_cards_status = N/A<br /> |PCIE_x1_status = N/A<br /> |PCIE_x2_status = N/A<br /> |PCIE_x4_status = N/A<br /> |PCIE_x8_status = N/A<br /> |PCIE_x16_status = N/A<br /> |PCIE_x32_status = N/A<br /> |HTX_status = N/A<br /> <br /> |Floppy_status = N/A<br /> |COM1_status = OK<br /> |COM2_status = OK<br /> |PP_status = N/A<br /> |PS2_keyboard_status = OK<br /> |PS2_keyboard_comments = Internal 4 pin connector J-KBD<br /> |PS2_mouse_status = N/A<br /> |Game_port_status = N/A<br /> |IR_status = N/A<br /> |Speaker_status = N/A<br /> |DiskOnChip_status = N/A<br /> <br /> |Sensors_status = WIP<br /> |Watchdog_status = N/A<br /> |CAN_bus_status = N/A<br /> |CPUfreq_status = N/A<br /> |Powersave_status = N/A<br /> |ACPI_status = No<br /> |ACPI_comments = There's no ACPI implementation for this board, but it's on our TODO list.<br /> |SMBus_status = WIP<br /> |Reboot_status = N/A<br /> |Poweroff_status = N/A<br /> |LEDs_status = OK<br /> |LEDs_comments = Special-purpose LEDs available on the board, '''Alert''' and '''Fault''' are controlled by the superio<br /> |HPET_status = N/A<br /> |RNG_status = N/A<br /> |WakeOnModem_status = N/A<br /> |WakeOnLAN_status = N/A<br /> |WakeOnKeyboard_status = N/A <br /> |WakeOnMouse_status = N/A<br /> |Flashrom_status = OK<br /> |Flashrom_comments = Supported flashrom revision 1010 or higher.<br /> }}</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:51:19Z

<p>MBertens: </p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling<br /> <br /> <br /> == Development status ==<br /> <br /> The current development status is; No coreboot running yet</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:50:10Z

<p>MBertens: </p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by [[User:MBertens|Marc Bertens]].<br /> <br /> <br /> The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling</div>

MBertens http://www.coreboot.org/User:MBertens 2011-01-28T12:48:58Z

<p>MBertens: </p> <hr /> <div>Hi, my name is Marc Bertens. I'm interested in developing software and hardware. <br /> <br /> My interests and project(s), At the moment is coreboot, trying to contribute for the Nokia IP530 and later on the IP330.<br /> <br /> My contrubutions up to Jan 8, 2011<br /> <br /> * Superiotool support for the SMSC FDC37B787 <br /> <br /> * [[Nokia_IP530]], hardware rom optionboard for recovery and USB option board. <br /> * [[Nokia_IP330]], hardware rom optionboard for recovery.<br /> <br /> * File support for the getpir tool, to validate the PIRQ table compiled in the coreboot image.<br /> <br /> * [[Mini HOWTO: using a CF card for testing and developing coreboot]]<br /> <br /> Legal disclaimer: My opinions do not represent the opinions of the coreboot project.</div>

MBertens http://www.coreboot.org/Upgrading_the_Nokia-IP530_to_coreboot 2011-01-28T12:47:37Z

<p>MBertens: Blanked the page</p> <hr /> <div></div>

MBertens http://www.coreboot.org/Upgrading_the_Nokia-IP530_to_coreboot 2011-01-28T12:47:25Z

<p>MBertens: </p> <hr /> <div>#REDIRECT [[Nokia IP330]]<br /> #REDIRECT [[Nokia IP530]]</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:46:43Z

<p>MBertens: moved Upgrading the Nokia-IP530 to coreboot to Nokia IP330</p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by Marc Bertens.<br /> front view<br /> <br /> <br /> The Nokia IP530 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. The original is only capable of starting a FreeBSD FS. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling</div>

MBertens http://www.coreboot.org/Upgrading_the_Nokia-IP530_to_coreboot 2011-01-28T12:46:43Z

<p>MBertens: moved Upgrading the Nokia-IP530 to coreboot to Nokia IP330</p> <hr /> <div>#REDIRECT [[Nokia IP330]]</div>

MBertens http://www.coreboot.org/Nokia_IP330 2011-01-28T12:46:21Z

<p>MBertens: </p> <hr /> <div>This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by Marc Bertens.<br /> front view<br /> <br /> <br /> The Nokia IP530 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. The original is only capable of starting a FreeBSD FS. There is as far as I known no CD support in the orginal BIOS.<br /> <br /> The System has no VGA, all console activity must be done through a serial console.<br /> At the front the following can be found;<br /> <br /> * Power LED<br /> * Fault LED<br /> * 2 Serial interfaces COM1 and COM2<br /> * 3 Ethernet RJ45 sockets<br /> * Reset button<br /> * 1 Compact PCI slot<br /> <br /> At the back the following can be found;<br /> <br /> * EURO Power connector<br /> * Power switch<br /> * Three FANs for system unit cooling <br /> * One FAN for CPU cooling</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-26T16:41:12Z

<p>MBertens: /* CMOS layout */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the end of line are treated as comment.<br /> <br /> * Page 0: 0 - 1024 128 Bytes <br /> ** position bit 0 - bit 112 : RTC clock data<br /> ** position bit 113 - bit 1024 : other data<br /> * Page 1: 1025 - 2048 128 Bytes<br /> ** user free space, not always available.<br /> <br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ? hide ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> # &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> # &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-26T16:34:28Z

<p>MBertens: /* CMOS layout */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the end of line are treated as comment.<br /> <br /> * Page 0: 0 - 1024 128 Bytes <br /> ** position bit 0 - bit 112 : RTC clock data<br /> * Page 1: 1025 - 2048 128 Bytes<br /> ** user free space, not always available.<br /> <br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ? hide ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> # &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> # &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:31:12Z

<p>MBertens: /* CMOS layout */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the end of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ? hide ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> # &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> # &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:26:35Z

<p>MBertens: /* entries section */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ? hide ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> # &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> # &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:26:04Z

<p>MBertens: /* Example cmos.layout file */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> # &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> # &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:23:42Z

<p>MBertens: /* Example cmos.layout file */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> #start-bit length config config-ID name<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> # &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:23:05Z

<p>MBertens: /* Example cmos.layout file */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> #start-bit length config config-ID name<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #&lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> <br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:19:46Z

<p>MBertens: /* Example cmos.layout file */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> #start-bit length config config-ID name<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #ID value text<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> <br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:19:21Z

<p>MBertens: /* Example cmos.layout file */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==<br /> <br /> '''entries'''<br /> <br /> #start-bit length config config-ID name<br /> 0 384 r 0 reserved_memory<br /> 384 1 e 4 boot_option<br /> 385 1 e 4 last_boot<br /> 386 1 e 1 ECC_memory<br /> 388 4 r 0 reboot_bits<br /> 392 3 e 5 baud_rate<br /> 395 1 e 1 hw_scrubber<br /> 396 1 e 1 interleave_chip_selects<br /> 397 2 e 8 max_mem_clock<br /> 399 1 e 2 multi_core<br /> 400 1 e 1 power_on_after_fail<br /> 412 4 e 6 debug_level<br /> 416 4 e 7 boot_first<br /> 420 4 e 7 boot_second<br /> 424 4 e 7 boot_third<br /> 428 4 h 0 boot_index<br /> 432 8 h 0 boot_countdown<br /> 440 4 e 9 slow_cpu<br /> 444 1 e 1 nmi<br /> 445 1 e 1 iommu<br /> 728 256 h 0 user_data<br /> 984 16 h 0 check_sum<br /> # Reserve the extended AMD configuration registers<br /> 1000 24 r 0 amd_reserved<br /> <br /> '''enumerations'''<br /> <br /> #ID value text<br /> # for ECC_memory, hw_scrubber, interleave_chip_selects, power_on_after_fail, nmi, iommu<br /> 1 0 Disable<br /> 1 1 Enable<br /> # multi_core<br /> 2 0 Enable<br /> 2 1 Disable<br /> # boot_option, last_boot <br /> 4 0 Fallback<br /> 4 1 Normal<br /> # baud_rate<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> # debug_level<br /> 6 6 Notice<br /> 6 7 Info<br /> 6 8 Debug<br /> 6 9 Spew<br /> # boot_first, boot_second, boot_third<br /> 7 0 Network<br /> 7 1 HDD<br /> 7 2 Floppy<br /> 7 8 Fallback_Network<br /> 7 9 Fallback_HDD<br /> 7 10 Fallback_Floppy<br /> 7 3 ROM<br /> # max_mem_clock<br /> 8 0 DDR400<br /> 8 1 DDR333<br /> 8 2 DDR266<br /> 8 3 DDR200<br /> # slow_cpu<br /> 9 0 off<br /> 9 1 87.5%<br /> 9 2 75.0%<br /> 9 3 62.5%<br /> 9 4 50.0%<br /> 9 5 37.5%<br /> 9 6 25.0%<br /> 9 7 12.5%<br /> <br /> '''checksums'''<br /> <br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:11:09Z

<p>MBertens: /* entries section */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section. The &lt;config-id&gt; does not have to be unique, a &lt;config-id&gt; in the enumeration section can be used for different entries. <br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T17:08:48Z

<p>MBertens: /* entries section */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> This section defined all the variables used within coreboot. Each line consists out of the following parameters;<br /> <br /> &lt;start-bit&gt; &lt;bit-length&gt; &lt;config&gt; &lt;config-id&gt; &lt;parameter-name&gt;<br /> <br /> The parameter &lt;start-bit&gt; is the start position is bit position where the parameter get stored.<br /> <br /> The parameter &lt;bit-length&gt; is the length in bits of the parameter.<br /> <br /> The parameter &lt;config&gt; indicates the type of parameter, currently there are three known types;<br /> <br /> ** r = register<br /> ** e = enumeration<br /> ** h = ?<br /> <br /> The parameter &lt;config-id&gt; is used when the &lt;config&gt; is set to 'e', than there must be at least one item in the enumeration section.<br /> <br /> The parameter &lt;parameter-name&gt; is the name the coreboot retrieval and storage functions will refer to.<br /> <br /> Example:<br /> 0 384 r 0 reserved_memory<br /> 384 3 e 5 baud_rate<br /> 487 1 e 1 power_on_after_fail<br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T16:58:31Z

<p>MBertens: /* enumerations section */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The parameter &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The parameter &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The parameter &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T16:58:06Z

<p>MBertens: /* enumerations section */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> <br /> === enumerations section ===<br /> <br /> Each line in the the enumerations section is contructed as follows;<br /> <br /> &lt;config-id&gt; &lt;value&gt; &lt;label&gt;<br /> <br /> The paramater &lt;config-id&gt; is the same value as the &lt;config-id&gt; from the entries section. <br /> <br /> The paramater &lt;value&gt; is the value that get stored at the bit location defined in the entries section, where that config-id is being used.<br /> <br /> The paramater &lt;label&gt; is the label for displaying in the the presentation layer.<br /> <br /> Example;<br /> <br /> 1 0 Disable<br /> 1 1 Enable<br /> 5 0 115200<br /> 5 1 57600<br /> 5 2 38400<br /> 5 3 19200<br /> 5 4 9600<br /> 5 5 4800<br /> 5 6 2400<br /> 5 7 1200<br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T16:51:08Z

<p>MBertens: /* CMOS layout */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> <br /> === enumerations section ===<br /> <br /> <br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984<br /> <br /> == Example cmos.layout file ==</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T16:50:34Z

<p>MBertens: /* CMOS.layout */</p> <hr /> <div>== CMOS layout ==<br /> <br /> This page explain the workings of the CMOS layout file. The CMOS layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> <br /> === enumerations section ===<br /> <br /> <br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T16:50:01Z

<p>MBertens: /* CMOS.layout */</p> <hr /> <div>== CMOS.layout ==<br /> <br /> This page explain the workings of the CMOS.layout file. The CMOS.layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> The hash (#) character is the comment prefix, all characters until the eof of line are treated as comment.<br /> <br /> === entries section ===<br /> <br /> <br /> === enumerations section ===<br /> <br /> <br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984</div>

MBertens http://www.coreboot.org/CMOS.layout_guide 2011-01-25T16:48:26Z

<p>MBertens: /* checksums section */</p> <hr /> <div>== CMOS.layout ==<br /> <br /> This page explain the workings of the CMOS.layout file. The CMOS.layout file can be linked into a board specific environment. By creating the cmos.layout file in the board directory. and set the HAVE_OPTION_TABLE in the Kconfig file of the board. <br /> <br /> The CMOS layout file must contain the following sections;<br /> * entries<br /> * enumerations<br /> * checksums<br /> <br /> === entries section ===<br /> <br /> <br /> === enumerations section ===<br /> <br /> <br /> <br /> === checksums section ===<br /> The checksums section has one variable with three parameters;<br /> checksum &lt;startbit&gt; &lt;endbit&gt; &lt;start-of-checksumbit&gt;<br /> <br /> The &lt;startbit&gt; parameter is the bit position where the calculation of the checksum starts from.<br /> <br /> The &lt;endbit&gt; parameter is the bit position there the calculation of the checksum starts on.<br /> <br /> The &lt;start-of-checksumbit&gt; parameter is the bit position there the checksum will be stored, there must be space for 16 bits of checksum data.<br /> <br /> Example;<br /> checksum 392 983 984</div>

MBertens