http://www.coreboot.org/api.php?action=feedcontributions&user=Stuge&feedformat=atom 2013-05-20T14:24:07Z User contributions MediaWiki 1.20.5 http://www.coreboot.org/Lenovo_x60x 2012-10-04T18:54:50Z

<p>Stuge: </p> <hr /> <div>== Flashing on the laptop instructions. ==<br /> '''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br /> <br /> For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection).<br /> <br /> You will need: the flashrom source, a small patch for it, and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. <br /> #: Alternatively, you can copy the existing definition first as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. Choose either method: apply the patch in the link, or do the patch yourself, as per instruction below.<br /> #* Find the definition of your flash chip in flashrom's flashchips.c<br /> #* Change the .probe field to probe_spi_res1<br /> #* Change the .model_id field to the RES1 ID given in the datasheet of the flash chip<br /> #* Change the .write field to spi_chip_write_1<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k&lt;/code&gt;<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br /> #: &lt;code&gt;0000000 ffff ffff ffff ffff ffff ffff ffff ffff&lt;/code&gt;<br /> #: &lt;code&gt;*&lt;/code&gt;<br /> #: &lt;code&gt;0010000&lt;/code&gt;<br /> #: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say &quot;FAILED!&quot; at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009121.html Peter's mail] before you panic.<br /> # Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt;<br /> <br /> <br /> <br /> See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br /> <br /> == Recovery ==<br /> If you had a bad flash you will need a recovery method.<br /> you will need:<br /> * [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] (for disassembling the laptop)<br /> * An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br /> * An external flashrom programmer<br /> &lt;to be continued&gt;<br /> <br /> == Status ==<br /> * [[Thinkpad_X60s|Thinkpad X60s Status]]</div>

Stuge http://www.coreboot.org/Lenovo_x60x 2012-10-04T18:54:14Z

<p>Stuge: </p> <hr /> <div>== Flashing on the laptop instructions. ==<br /> '''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br /> <br /> For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection).<br /> <br /> You will need: the flashrom source, a small patch for it, and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. <br /> #: Alternatively, you can copy the existing definition first as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. Choose either method: apply the patch in the link, or do the patch yourself, as per instruction below.<br /> #* Find the definition of your flash chip in flashrom's flashchips.c<br /> #* Change the .probe field to probe_spi_res1<br /> #* Change the .model_id field to the RES1 ID given in the datasheet of the flash chip<br /> #* Change the .write field to spi_chip_write_1<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k&lt;/code&gt;<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br /> #: &lt;code&gt;0000000 ffff ffff ffff ffff ffff ffff ffff ffff&lt;/code&gt;<br /> #: &lt;code&gt;*&lt;/code&gt;<br /> #: &lt;code&gt;0010000&lt;/code&gt;<br /> #: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say &quot;FAILED!&quot; at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009121.html Peter's mail] before you panic.<br /> # Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br /> # Undo the flashrom patch, so that you have a stock flashrom<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt;<br /> <br /> <br /> <br /> See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br /> <br /> == Recovery ==<br /> If you had a bad flash you will need a recovery method.<br /> you will need:<br /> * [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] (for disassembling the laptop)<br /> * An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br /> * An external flashrom programmer<br /> &lt;to be continued&gt;<br /> <br /> == Status ==<br /> * [[Thinkpad_X60s|Thinkpad X60s Status]]</div>

Stuge http://www.coreboot.org/Lenovo_x60x 2012-09-24T19:14:13Z

<p>Stuge: </p> <hr /> <div>== Flashing on the laptop instructions. ==<br /> '''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br /> <br /> For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection).<br /> <br /> You will need: the flashrom source, a small patch for it, and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. <br /> #: Alternatively, you can copy the existing definition first as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. Choose either method: apply the patch in the link, or do the patch yourself, as per instruction below.<br /> #* Find the definition of your flash chip in flashrom's flashchips.c<br /> #* Change the .probe field to probe_spi_res1<br /> #* Change the .model_id field to the RES1 ID given in the datasheet of the flash chip<br /> #* Change the .write field to spi_chip_write1<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k&lt;/code&gt;<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br /> #: &lt;code&gt;0000000 ffff ffff ffff ffff ffff ffff ffff ffff&lt;/code&gt;<br /> #: &lt;code&gt;*&lt;/code&gt;<br /> #: &lt;code&gt;0010000&lt;/code&gt;<br /> #: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say &quot;FAILED!&quot; at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009121.html Peter's mail] before you panic.<br /> # Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br /> # Undo the flashrom patch, so that you have a stock flashrom<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt; (do '''NOT''' power off before running flashrom in the next step, or you '''will''' brick the machine!)<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> <br /> <br /> <br /> See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br /> <br /> == Recovery ==<br /> If you had a bad flash you will need a recovery method.<br /> you will need:<br /> * [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] (for disassembling the laptop)<br /> * An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br /> * An external flashrom programmer<br /> &lt;to be continued&gt;<br /> <br /> == Status ==<br /> &lt;insert the status here&gt;</div>

Stuge http://www.coreboot.org/Lenovo_x60x 2012-09-24T19:12:10Z

<p>Stuge: </p> <hr /> <div>== Flashing on the laptop instructions. ==<br /> '''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br /> <br /> For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection).<br /> <br /> You will need: the flashrom source, a small patch for it, and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. <br /> #: Alternatively, you can copy the existing definition first as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. Choose either method: apply the patch in the link, or do the patch yourself, as per instruction below.<br /> #* Find the definition of your flash chip in flashrom's flashchips.c<br /> #* Change the .probe field to probe_spi_res1<br /> #* Modify .model_id field to the RES1 ID given in the datasheet of the flash chip<br /> #* Change the .write field to spi_chip_write1<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k&lt;/code&gt;<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br /> #: &lt;code&gt;0000000 ffff ffff ffff ffff ffff ffff ffff ffff&lt;/code&gt;<br /> #: &lt;code&gt;*&lt;/code&gt;<br /> #: &lt;code&gt;0010000&lt;/code&gt;<br /> #: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say &quot;FAILED!&quot; at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009121.html Peter's mail] before you panic.<br /> # Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br /> # Undo the flashrom patch, so that you have a stock flashrom<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt; (do '''NOT''' power off before running flashrom in the next step, or you '''will''' brick the machine!)<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> <br /> <br /> <br /> See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br /> <br /> == Recovery ==<br /> If you had a bad flash you will need a recovery method.<br /> you will need:<br /> * [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf the x60 manual] (for disassembling the laptop)<br /> * some clip, like [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ a pomona] for instance.<br /> * an external flashrom programmer<br /> &lt;to be continued&gt;<br /> <br /> == Status ==<br /> &lt;insert the status here&gt;</div>

Stuge http://www.coreboot.org/Git 2012-09-14T15:34:09Z

<p>Stuge: /* Accessing the repository */</p> <hr /> <div>= Gerrit =<br /> As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive (but will improve in the future)<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Accessing the repository =<br /> The repository can be accessed using ssh (with public key authentication) or http (anonymous read-only or read-write using user/password authentication). The latter is particularily interesting for people behind firewalls, but requires git to be version 1.6.6 or newer (for &quot;Smart HTTP&quot; transfer). The http password can be generated (and regenerated if necessary) at http://review.coreboot.org/#settings,http-password.<br /> <br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> git clone &lt;nowiki&gt;http://[&lt;username&gt;:&lt;password&gt;@]review.coreboot.org/p/coreboot.git&lt;/nowiki&gt;<br /> <br /> Inside the checkout you should install a commit-msg hook that adds a Change-Id into commit messages, which uniquely identifies the logical change in Gerrit even across multiple iterations of the commit. The hook only needs to be installed once per clone, and installation can be done with<br /> <br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> Or you can also just run<br /> <br /> make gitconfig<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Accessing_the_repository|above]], and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br /> <br /> === Guidelines on commit message content ===<br /> <br /> * If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.<br /> * Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:<br /> git show<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[Git#Authenticated read/write access|Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> <br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> <br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> <br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> <br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> <br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> <br /> git log origin/master..<br /> <br /> before '''git push''' to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].<br /> <br /> == Evolving patches ==<br /> <br /> Often it might happen that the patch you sent for approval is not good enough from the first attempt. Gerrit and git make it easy to track patch evolution during the review process until patches meet our quality standards and are ready for approval.<br /> <br /> You can easily modify a patch sent to gerrit by you or even by someone else. Just apply it locally using one of the possible ways to do it, make a new local commit that fixes the issues reported by the reviewers, then rebase the change by preserving the same Change-ID. We recommend you to use the git rebase command in interactive mode, <br /> <br /> git rebase -i master<br /> <br /> then commit and push the updated patch.<br /> <br /> Alternatively, you may amend your local commit and push the updated patch to gerrit:<br /> <br /> git add &lt;path/to/updated/files&gt;<br /> git commit --amend<br /> <br /> then push the updated patch.<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at some of these documents:<br /> * http://git-scm.com/<br /> * http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html<br /> * http://git.or.cz/course/svn.html<br /> * and in particular the [http://progit.org/ Pro Git book]<br /> <br /> Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].<br /> <br /> = Browsing =<br /> <br /> See http://review.coreboot.org/gitweb?p=coreboot.git</div>

Stuge http://www.coreboot.org/Lenovo_x60x 2012-08-08T04:40:59Z

<p>Stuge: Add reference hexdump output</p> <hr /> <div>'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed. Detailed instructions follow.<br /> <br /> You will need: the flashrom source, a small patch ''[WHAT PATCH? --rah]'', and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. ''[WHAT DOES THIS MEAN? HOW DO YOU DO THIS? --rah]''<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k&lt;/code&gt;<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:&lt;pre&gt;<br /> #: 0000000 ffff ffff ffff ffff ffff ffff ffff ffff<br /> #: *<br /> #: 0010000&lt;/pre&gt;<br /> #: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, and shall generate an erase error at e.g. 0x1f0000 when working with a 2 Mbyte flash chip.<br /> # Power cycle the machine, now starting with coreboot<br /> # Undo the flashrom patch, so that you have a stock flashrom<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> <br /> <br /> <br /> These instructions were gleaned from the following mailing list threads: http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575</div>

Stuge http://www.coreboot.org/Lenovo_x60x 2012-08-08T04:36:26Z

<p>Stuge: Replace sizeof() with actual $(stat -c %s) shell command</p> <hr /> <div>'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed. Detailed instructions follow.<br /> <br /> You will need: the flashrom source, a small patch ''[WHAT PATCH? --rah]'', and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. ''[WHAT DOES THIS MEAN? HOW DO YOU DO THIS? --rah]''<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k&lt;/code&gt;<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding further. If this is not the case, the coreboot image needs to be recreated with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, and shall generate an erase error at e.g. 0x1f0000 when working with a 2 Mbyte flash chip.<br /> # Power cycle the machine, now starting with coreboot<br /> # Undo the flashrom patch, so that you have a stock flashrom<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> <br /> <br /> <br /> These instructions were gleaned from the following mailing list threads: http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575</div>

Stuge http://www.coreboot.org/Lenovo_x60x 2012-08-07T21:59:29Z

<p>Stuge: </p> <hr /> <div>'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br /> <br /> These Lenovo laptops have a register that must be flipped before coreboot can be flashed. Detailed instructions follow.<br /> <br /> You will need: the flashrom source, a small patch ''[WHAT PATCH? --rah]'', and [http://git.stuge.se/?p=bucts.git the bucts utility].<br /> <br /> # Patch flashrom to use RES1 SPI identification and spi_chip_write1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. ''[WHAT DOES THIS MEAN? HOW DO YOU DO THIS? --rah]''<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin&lt;/code&gt;<br /> #: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or &quot;planar&quot; in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br /> # Run &lt;code&gt;dd if=coreboot.rom of=top64k.bin bs=1 skip=$[sizeof(coreboot.rom) - 0x10000] count=64k&lt;/code&gt; ''[sizeof() ISN'T A SHELL FUNCTION. WHAT ARE THE PROPER SHELL COMMAND(S) TO DO THIS STEP? --rah]''<br /> # Run &lt;code&gt;dd if=coreboot.rom bs=1 skip=$[sizeof(coreboot.rom) - 0x20000] count=64k | hexdump&lt;/code&gt;<br /> #: Verify that the complete range is filled with ff bytes before proceeding further. If this is not the case, the coreboot image needs to be recreated with the second-to-last 64kbyte block unused.<br /> # Run &lt;code&gt;dd if=top64k.bin of=coreboot.rom bs=1 seek=$[sizeof(coreboot.rom) - 0x20000] count=64k conv=notrunc&lt;/code&gt;<br /> # Run &lt;code&gt;bucts 1&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;<br /> #: This will be slow, and shall generate an erase error at e.g. 0x1f0000 when working with a 2 Mbyte flash chip.<br /> # Power cycle the machine, now starting with coreboot<br /> # Undo the flashrom patch, so that you have a stock flashrom<br /> # Run &lt;code&gt;bucts 0&lt;/code&gt;<br /> # Run &lt;code&gt;flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom&lt;/code&gt;.<br /> #: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br /> <br /> <br /> <br /> These instructions were gleaned from the following mailing list threads: http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575</div>

Stuge http://www.coreboot.org/Datasheets 2011-10-15T02:42:58Z

<p>Stuge: Update all AMD SB7x0 links to developer.amd.com/assets/ URLs</p> <hr /> <div>This page lists '''publically available datasheets''' and programming guides from various vendors. It includes CPU, chipset, Super I/O, and many other datasheets.<br /> <br /> = x86 architecture =<br /> <br /> == AMD ==<br /> <br /> AMD provides their [http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.1&amp;product=5.7&amp;contentType=Tech+Doc+Processor&amp;ostype=&amp;keywords=&amp;items=20 AMD64 Architecture and Software manuals], which are a very useful reference for AMD systems, of course (but also explain lots of non-AMD-specific x86 stuff too):<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/24592.pdf Volume 1: Application Programming]<br /> * [http://support.amd.com/us/Processor_TechDocs/24593.pdf Volume 2: System Programming 24593]<br /> * [http://support.amd.com/us/Processor_TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]<br /> * [http://support.amd.com/us/Processor_TechDocs/26568.pdf Volume 4: 128-Bit Media Instructions]<br /> * [http://support.amd.com/us/Processor_TechDocs/26569.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions]<br /> * [http://support.amd.com/us/Processor_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions]<br /> <br /> Other AMD documents:<br /> * [http://support.amd.com/us/Processor_TechDocs/43724.pdf Lightweight Profiling Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf AMD I/O Virtualization Technology (IOMMU) Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/32200.pdf Open Platform Management Architecture Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/25481.pdf CPUID Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/41918.pdf Advanced Platform Management Link (APML) Specification]<br /> <br /> == Intel ==<br /> <br /> Intel provides their [http://developer.intel.com/products/processor/manuals/index.htm Intel&amp;reg; 64 and IA-32 Architectures Software Developer's Manuals] which are a very useful reference to the x86 architecture in general:<br /> <br /> * [http://developer.intel.com/Assets/PDF/manual/253665.pdf Volume 1: Basic Architecture]<br /> * [http://developer.intel.com/Assets/PDF/manual/253666.pdf Volume 2A: Instruction Set Reference, A-M]<br /> * [http://developer.intel.com/Assets/PDF/manual/253667.pdf Volume 2B: Instruction Set Reference, N-Z]<br /> * [http://developer.intel.com/Assets/PDF/manual/253668.pdf Volume 3A: System Programming Guide]<br /> * [http://developer.intel.com/Assets/PDF/manual/253669.pdf Volume 3B: System Programming Guide]<br /> * [http://www.intel.com/Assets/PDF/manual/252046.pdf Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes]<br /> <br /> Other Intel documents:<br /> <br /> * [http://www.intel.com/Assets/PDF/manual/318148.pdf Intel® 64 Architecture x2APIC Specification]<br /> * [http://www.intel.com/Assets/PDF/manual/248966.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual]<br /> * [http://www.intel.com/Assets/PDF/manual/323640.pdf Intel® Carry-Less Multiplication Instruction and its Usage for Computing the GCM Mode White Paper]<br /> * [http://www.intel.com/Assets/PDF/manual/323641.pdf Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Set White Paper]<br /> * [http://www.intel.com/Assets/PDF/manual/323850.pdf Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) Application Note]<br /> <br /> = CPU =<br /> <br /> == AMD ==<br /> <br /> === AMD Fam14 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/43170.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Processors]<br /> ** [http://support.amd.com/us/Embedded_TechDocs/47534.pdf Revision Guide for AMD Family 14h Processors]<br /> <br /> === AMD Fam11h ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/41256.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors]<br /> ** [http://support.amd.com/us/Processor_TechDocs/41788.pdf Revision Guide for AMD Family 11h Processors]<br /> ** [http://support.amd.com/us/Processor_TechDocs/43373.pdf AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks]<br /> <br /> Turion64:<br /> * [http://support.amd.com/us/Processor_TechDocs/32816.pdf AMD Turion™ 64 Mobile Technology Product Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/41407.pdf AMD Turion™ 64 X2 Mobile Technology Dual-Core Processor Product Data Sheet]<br /> <br /> Athlon64:<br /> * [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]<br /> <br /> === AMD Fam10h ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/31116.pdf BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h]<br /> ** [http://support.amd.com/us/Processor_TechDocs/41322.pdf Revision Guide for AMD Family 10h Processors]<br /> * [http://support.amd.com/us/Processor_TechDocs/40546-PUB-Optguide_3-11_5-21-09.pdf Software Optimization Guide for AMD Family 10h Processors]<br /> * [http://support.amd.com/us/Processor_TechDocs/43374.pdf AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/43375.pdf AMD Family 10h Desktop Processor Power and Thermal Data Sheet]<br /> <br /> Opteron:<br /> * [http://support.amd.com/us/Processor_TechDocs/40036.pdf Family 10h AMD Opteron Processor Product Data Sheet]<br /> <br /> Phenom:<br /> * [http://support.amd.com/us/Processor_TechDocs/44109.pdf Family 10h AMD Phenom&amp;trade; Processor Product Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/46878.pdf Family 10h AMD Phenom&amp;trade; II Processor Product Data Sheet]<br /> <br /> === AMD K8 ===<br /> <br /> Athlon64/Opteron:<br /> * [http://support.amd.com/us/Processor_TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon&amp;trade; and AMD Opteron&amp;trade; Processors]<br /> ** [http://support.amd.com/us/Processor_TechDocs/25759.pdf Revision Guide for AMD Athlon&amp;trade; and AMD Opteron&amp;trade; Processors]<br /> ** [http://support.amd.com/us/Processor_TechDocs/26633_5649.pdf AMD Athlon&amp;trade; and AMD Opteron&amp;trade; Processors Thermal Design Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/40555.pdf Performance Guidelines for AMD Athlon&amp;trade; and AMD Opteron&amp;trade; ccNUMA Multiprocessor Systems]<br /> * [http://support.amd.com/us/Processor_TechDocs/24707_PUB.PDF Clock Generator Specification for AMD Athlon&amp;trade; and AMD Opteron&amp;trade; Processors]<br /> <br /> Opteron:<br /> * [http://support.amd.com/us/Processor_TechDocs/23932.pdf AMD Opteron&amp;trade; Processor Product Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/30417.pdf AMD Opteron&amp;trade; Processor Power and Thermal Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/40820_PUB_AMD_Opteron_Processor_Production_Notice_rev_3_08.pdf AMD Opteron&amp;trade; x52 and x54 Production Notice]<br /> * [http://support.amd.com/us/Processor_TechDocs/30925.pdf Builders Guide for AMD Opteron&amp;trade; Processor-Based Servers and Workstations]<br /> * [http://support.amd.com/us/Processor_TechDocs/33340.pdf AMD Opteron&amp;trade; Multiprocessor Systems Running Linux Technical Bulletin for AMD OEMs and Partners]<br /> <br /> Family 0Fh:<br /> * [http://support.amd.com/us/Processor_TechDocs/32559.pdf BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors]<br /> ** [http://support.amd.com/us/Processor_TechDocs/33610.pdf Revision Guide for AMD NPT Family 0Fh Processors]<br /> ** [http://support.amd.com/us/Processor_TechDocs/31119.pdf AMD NPT Family 0Fh Processor Electrical Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/33954.pdf AMD NPT Family 0Fh Desktop Processor Power and Thermal Data Sheet]<br /> <br /> === Athlon64 ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/24659.pdf AMD Athlon™ Processor Product Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/31783.pdf AMD Athlon™ Processor Competitive Performance Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/43042.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/33425.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet] (ver 3.10, 1/21/2007)<br /> ** [http://support.amd.com/us/Processor_TechDocs/42989.pdf AMD Athlon™ X2 Dual-Core Processor for Notebooks Product Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/30431.pdf AMD Athlon™ FX Processor Product Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/31366.pdf AMD Athlon™ FX-60 Processor Competitive Performance Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/31225.pdf Mobile AMD Athlon™ Processor 3400+ Competitive Performance Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/31684.pdf Builder's Guide for AMD Athlon™ Processor-Based Desktops and Workstations]<br /> <br /> === Athlon (32bit) ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/21016.pdf AMD Athlon™ Processor Module Data Sheet] (rev. M-0, 5/31/2000)<br /> ** [http://support.amd.com/us/Processor_TechDocs/22054.pdf AMD Athlon™ Processor Technical Brief]<br /> * [http://support.amd.com/us/Processor_TechDocs/26237.PDF AMD Athlon™ XP Processor Model 10 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/27375.pdf AMD Athlon XP Processor Model 10 with 256K L2 Cache]<br /> ** [http://support.amd.com/us/Processor_TechDocs/27532.pdf AMD Athlon™ Processor Model 10 Revision Guide]<br /> ** [http://support.amd.com/us/Processor_TechDocs/26426.PDF AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms]<br /> * [http://support.amd.com/us/Processor_TechDocs/25175.pdf AMD Athlon™ XP Processor Model 8 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/25703.pdf AMD Athlon™ Processor Model 8 Revision Guide]<br /> ** [http://support.amd.com/us/Processor_TechDocs/25722.pdf AMD Athlon™ MP Processor Model 8 Data Sheet for Multiprocessor Platforms]<br /> * [http://support.amd.com/us/Processor_TechDocs/24685.pdf AMD Athlon™ MP Processor Model 6 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/24309.pdf AMD Athlon™ XP Processor Model 6 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/24332.pdf AMD Athlon™ Processor Model 6 Revision Guide]<br /> ** [http://support.amd.com/us/Processor_TechDocs/25480.pdf AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms]<br /> * [http://support.amd.com/us/Processor_TechDocs/23792.pdf AMD Athlon™ Processor Model 4 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/23614.pdf AMD Athlon™ Processor Model 4 Revision Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/22651.pdf AMD Athlon™ Processor Voltage Regulation Application Note]<br /> * [http://support.amd.com/us/Processor_TechDocs/23811.pdf AMD Athlon™ Processor Module Signal and Power-Up Requirements Application Note]<br /> * [http://support.amd.com/us/Processor_TechDocs/25823.pdf Builder’s Guide for 2P Capable Servers and Workstations]<br /> * [http://support.amd.com/us/Processor_TechDocs/25325.pdf System Considerations for Dual AMD Athlon™ MP Processors in Tower and 1U Form Factors]<br /> * [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]<br /> * [http://support.amd.com/us/Processor_TechDocs/24228.pdf Methodologies for Measuring Temperature on AMD Athlon™ and AMD Duron™ Processors]<br /> * [http://support.amd.com/us/Processor_TechDocs/22007.pdf AMD Athlon™ Processor x86 Code Optimization Guide]<br /> <br /> === Sempron ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/31805.pdf AMD Sempron™ Processor Product Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/31994.pdf AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/31993.pdf AMD Sempron™ Processor Model 10 Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/31693.pdf AMD Sempron™ Processor Model 8 Data Sheet]<br /> <br /> === Duron ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/TN13.pdf AMD Duron™ Processor Rev. A0: CPUID Reporting of L2 Cache Size]<br /> * [http://support.amd.com/us/Processor_TechDocs/25848.PDF AMD Duron™ Processor Model 8 Data Sheet]<br /> * [http://support.amd.com/us/Processor_TechDocs/24310.pdf AMD Duron™ Processor Model 7 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/24806.pdf AMD Duron™ Processor Model 7 Revision Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/23802.pdf AMD Duron™ Processor Model 3 Data Sheet]<br /> ** [http://support.amd.com/us/Processor_TechDocs/23865.pdf AMD Duron™ Processor Model 3 Revision Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]<br /> <br /> === Socket specs ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/25766.pdf AMD Socket 940 Design Specification]<br /> ** [http://support.amd.com/us/Processor_TechDocs/31412.pdf AMD Functional Data Sheet, 940 Pin Package]<br /> ** [http://support.amd.com/us/Processor_TechDocs/30353.pdf AMD Socket 940 Qualification Plan]<br /> * [http://support.amd.com/us/Processor_TechDocs/31700.pdf Socket F (1207) Design Specification]<br /> ** [http://support.amd.com/us/Processor_TechDocs/32800.pdf Thermal Design Guide for Socket F (1207) Processors]<br /> * [http://support.amd.com/us/Processor_TechDocs/31875.pdf Socket AM2 Design Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/40523.pdf Socket AM3 Design Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/31839.pdf Low-Profile Socket S1 Design Specification]<br /> * [http://support.amd.com/us/Processor_TechDocs/31410.pdf AMD Functional Data Sheet, 754 Pin Package]<br /> ** [http://support.amd.com/us/Processor_TechDocs/24850.PDF Socket 754 Design and Qualification Requirements]<br /> * [http://support.amd.com/us/Processor_TechDocs/31411.pdf AMD Functional Data Sheet, 939-Pin Package]<br /> * [http://support.amd.com/us/Processor_TechDocs/23986.pdf Socket A AMD Processor and Heatsink Installation Guide]<br /> <br /> === Misc ===<br /> <br /> * [http://support.amd.com/us/Processor_TechDocs/20734.pdf AMD Processor Recognition Application Note]<br /> * [http://support.amd.com/us/Processor_TechDocs/22466.pdf AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets Manual]<br /> * [http://support.amd.com/us/Processor_TechDocs/21928.pdf 3DNow!™Technology Manual]<br /> ** [http://support.amd.com/us/Processor_TechDocs/22621.pdf 3DNow!™ Instruction Porting Guide Application Note]<br /> * [http://support.amd.com/us/Processor_TechDocs/23794.pdf AMD Thermal, Mechanical, and Chassis Cooling Design Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/30579_3_74.pdf AMD Processor Performance Evaluation Guide]<br /> * [http://support.amd.com/us/Processor_TechDocs/32035.pdf Compiler Usage Guidelines for AMD64 Platforms Application Note]<br /> * [http://support.amd.com/us/Processor_TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors]<br /> * [http://support.amd.com/us/Processor_TechDocs/26951.pdf Thermal Interface Material Comparison: Thermal Pads vs. Thermal Grease]<br /> * [http://support.amd.com/us/Processor_TechDocs/26003.pdf Builders Guide for Desktop/Tower Systems]<br /> * [http://support.amd.com/us/Processor_TechDocs/26698.pdf Linux Kernel Issue with Systems Using AGP Graphics]<br /> * [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft&amp;reg; Windows&amp;reg; XP and Windows&amp;reg; Server 2003 Processor Speed Reporting]<br /> * [http://support.amd.com/us/Processor_TechDocs/30887.pdf Building AMD64 Applications with the Microsoft Platform SDK]<br /> * [http://support.amd.com/us/Processor_TechDocs/30888.pdf Creating an AMD64 Build Enviroment for DirectX-Based Applations]<br /> * [http://support.amd.com/us/Processor_TechDocs/33609.pdf Processor Utilization with Microsoft&amp;reg; Windows&amp;reg; Media Center Edition on Systems Enabled with Cool'n'Quiet&amp;trade; and AMD PowerNow&amp;trade; Technologies]<br /> * [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]<br /> * [http://support.amd.com/us/Processor_TechDocs/tn17.pdf Microsoft Windows® 2000 Patch for AGP Applications on AMD Athlon™ and AMD Duron™ Processors]<br /> <br /> == Intel ==<br /> <br /> === Intel Pentium III ===<br /> <br /> * [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii Highlights/Overview]<br /> * [http://ark.intel.com/ProductCollection.aspx?familyID=590&amp;MarketSegment=DT List of Pentium III models, steppings, etc.]<br /> * [http://www.intel.com/support/processors/pentiumiii/sb/CS-023730.htm Intel® Pentium® III Processor: Datasheets]<br /> ** [http://download.intel.com/support/processors/pentiumiii/sb/24965705.pdf Intel® Pentium® III Processor with 512-KB L2 Cache at 1.13GHz to 1.40 GHz Datasheet] (PDF)<br /> ** [http://download.intel.com/support/processors/pentiumiii/sb/24976503.pdf Intel® Pentium® III Processor Based on 0.13 Micron Process Up to 1.33 GHz Datasheet] (PDF)<br /> ** [http://download.intel.com/support/processors/pentiumiii/sb/24526408.pdf Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz] (PDF)<br /> ** [http://download.intel.com/support/processors/pentiumiii/sb/24445209.pdf Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet] (PDF)<br /> ** [http://download.intel.com/support/processors/pentiumiii/sb/27367306.pdf Low Voltage Intel® Pentium® III Processor 512-KB] (PDF)<br /> * [http://www.intel.com/design/intarch/specupdt/244453.htm Intel® Pentium® III Processor Specification Update] ([http://download.intel.com/design/intarch/specupdt/24445358.pdf PDF])<br /> <br /> Mobile:<br /> * [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-m Highlights/Overview]<br /> * [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023739.htm Mobile Intel® Pentium® III Processor - M Datasheet] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/29834006.pdf PDF])<br /> * [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023740.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/24530659.pdf PDF])<br /> * [http://www.intel.com/design/intarch/specupdt/245306.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/design/intarch/specupdt/24530663.pdf PDF])<br /> * [http://developer.intel.com/design/mobile/datashts/245302.htm Mobile Pentium® III Processor in BGA2 and Micro-PGA2 Packages] ([http://download.intel.com/design/mobile/datashts/24530202.pdf PDF])<br /> <br /> Embedded:<br /> * [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii.htm Embedded Intel® Architecture Processors: Intel® Pentium® III Processors: Technical Documents]<br /> ** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_pga370.htm Intel® Pentium® III Processor - PGA370]<br /> ** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_low.htm Intel® Pentium® III Processor - Low Power]<br /> ** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_vol.htm Low Voltage Intel® Pentium® III Processor]<br /> <br /> Xeon:<br /> * [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-xeon Highlights/Overview]<br /> <br /> == VIA ==<br /> <br /> === VIA Padlock ===<br /> <br /> * [http://linux.via.com.tw/support/beginDownload.action?eleid=181&amp;fid=281 Security Application note]<br /> * [http://linux.via.com.tw/support/beginDownload.action?eleid=181&amp;fid=261 PadLock Programming Guide]<br /> <br /> = Northbridge =<br /> <br /> == AMD ==<br /> <br /> === AMD RS880 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/46143_rs880_BDG_pub_3.00.pdf AMD RS880 Family BIOS Developer's Guide] (BDG)<br /> * [http://support.amd.com/us/Embedded_TechDocs/46141_rs880_rpr_pub_3.00.pdf AMD RS880 Family Register Programming Requirements] (RPR)<br /> * [http://support.amd.com/us/Embedded_TechDocs/46142_rs880_rrg_pub_3.00.pdf AMD RS880 Family Register Reference Guide] (RRG)<br /> <br /> === AMD RD890 ===<br /> <br /> Not public (yet?). However, some of the information may be contained in the public docs in the RS880 section.<br /> <br /> * AMD RD890 BIOS Developer's Guide (Publication #43606)<br /> * AMD RD890 Register Reference Guide (Publication #43607)<br /> <br /> === AMD RS780 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/43734_rs780_bdg_pub_1.01.pdf AMD 780G Family BIOS Developer’s Guide] (BDG)<br /> * [http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf AMD 780G Family Register Programming Requirements] (RPR)<br /> * [http://support.amd.com/us/Embedded_TechDocs/43451_rs780_rrg_pub_1.01.pdf AMD 780G Family Register Reference Guide] (RRG)<br /> * [http://support.amd.com/us/Embedded_TechDocs/45732_rs780e_ds_pub_3.10.pdf AMD 780E Databook]<br /> * [http://support.amd.com/us/Embedded_TechDocs/48319.pdf AMD 780 Product Errata]<br /> <br /> Apparently there are other docs as well, not sure if they provide any additional information or if they are part of the public documents above:<br /> <br /> * AMD RD780 Register Reference Guide<br /> * AMD RX780 Register Reference Guide<br /> * AMD RS780M Hybrid Graphics – System BIOS Detailed Design Document (Publication #44969)<br /> * AMD RD790 Register Programming Requirements (Publication #42462)<br /> * AMD RD790 Register Reference Guide (Publication #42988)<br /> * AMD RD790 BIOS Developer's Guide (Publication #43093)<br /> <br /> === AMD RS690 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/43372_rs690_rrg_3.00o.pdf AMD RS690 Register Reference Guide] (RRG)<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41977_rs690_ds_3.06.pdf AMD 690G Databook]<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41978_rs690m_ds_3.06.pdf AMD M690 Databook (Notebook Solutions)]<br /> * [http://support.amd.com/us/Embedded_TechDocs/42437_m690t_ds_3_08.pdf AMD M690T/M690E Databook]<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD690Series_LogoGuide.pdf AMD 690 Chipset Logos]<br /> <br /> === Misc ===<br /> <br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD_7-Series_Chipsets_-_Guidelines.pdf AMD 7-Series Chipsets - Guidelines.pdf]<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD Model S1 DBM690T, Socket S1 and M690T/SB600 Chipset Development Board]<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMDCrossFire_LogoGuide.pdf AMD 480X Chipset Logos]<br /> <br /> == Intel ==<br /> <br /> === Intel Atom Z5xx and SCH US15Wx ===<br /> <br /> * [http://ark.intel.com/ProductCollection.aspx?codeName=24973 Overview of products formerly named Poulsbo]<br /> * [http://edc.intel.com/Platforms/Atom-Z5xx/#hardware Overview: Intel® Atom™ Processor Z5xx Series and Intel® System Controller Hub US15Wx]<br /> ** [http://edc.intel.com/Link.aspx?id=1387 Datasheet: Intel® System Controller Hub (Intel® SCH)] (PDF)<br /> ** [http://edc.intel.com/Link.aspx?id=1905 Datasheet: Intel® System Controller Hub (Intel® SCH) (large form factor)] (PDF)<br /> <br /> === Intel NM10 Express ===<br /> <br /> * [http://www.intel.com/Products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm Overview]<br /> ** [http://www.intel.com/Assets/PDF/datasheet/322896.pdf Intel® NM10 Express Chipset Datasheet]<br /> ** [http://www.intel.com/Assets/PDF/specupdate/322897.pdf Intel® NM10 Express Chipset Specification Update]<br /> <br /> === Intel 860 ===<br /> <br /> * [http://www.intel.com/design/archives/chipsets/860/index.htm Hardware Design: Archives - Intel&amp;reg; 860 Chipset Family Technical Documentation]<br /> ** [http://www.intel.com/design/chipsets/datashts/290713.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Datasheet]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]<br /> *** [http://www.intel.com/design/chipsets/specupdt/290715.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Specification Update]: [http://www.intel.com/design/chipsets/specupdt/29071501.pdf PDF]<br /> ** [http://www.intel.com/design/chipsets/applnots/292269.htm Intel® 860 Chipset Thermal Considerations Application Note (AP-721)]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]<br /> ** [http://www.intel.com/design/chipsets/designex/298252.htm Intel® Xeon® Processor and Intel® 860 Chipset Platform Design Guide]: [http://download.intel.com/design/chipsets/designex/29825204.pdf PDF]<br /> ** [http://www.intel.com/design/chipsets/designex/298302.htm Intel® 860 Chipset Memory Expansion Card (MEC) Design Guide]: [http://download.intel.com/design/chipsets/designex/29830201.pdf PDF]<br /> ** [http://www.intel.com/design/chipsets/schematics/860_crb.htm Intel 860 Chipset CRB Schematics]: [http://download.intel.com/design/chipsets/schematics/860_crb.pdf PDF]<br /> <br /> === Intel 82815E ===<br /> <br /> * [http://download.intel.com/design/chipsets/datashts/29068801.pdf 82815 Chipset Family]<br /> * [http://download.intel.com/design/chipsets/designex/29823401.pdf 82815E Chipset Platform Design Guide]<br /> * [http://download.intel.com/design/chipsets/designex/29824906.pdf 82815E Chipset Platform Design Guide update]<br /> <br /> === Intel 440BX ===<br /> <br /> * [http://download.intel.com/design/chipsets/datashts/29063301.pdf Datasheet]<br /> * [http://download.intel.com/design/chipsets/datashts/27321903.pdf Electrical and Thermal Timing Specification]<br /> <br /> === Intel 440LX ===<br /> <br /> * [http://download.intel.com/design/chipsets/datashts/29056402.pdf Datasheet]<br /> * [http://www.intel.com/design/chipsets/specupdt/29765505.pdf Spec update]<br /> <br /> == VIA ==<br /> <br /> VIA has a [http://linux.via.com.tw portal] with some source code and datasheets.<br /> <br /> === VIA VX800 ===<br /> <br /> * [http://linux.via.com.tw/support/beginDownload.action?eleid=161&amp;fid=241 VIA VX800 Programming Manual]<br /> <br /> === VIA CX700M/VX700 ===<br /> <br /> * [http://linux.via.com.tw/support/beginDownload.action?eleid=141&amp;fid=221 VIA CX700M/VX700 Programming Manual]<br /> <br /> = Southbridge =<br /> <br /> == AMD ==<br /> <br /> === AMD SB820M ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/47283.pdf AMD SB820M Southbridge Databook]<br /> <br /> === AMD SB810/SB850 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/44758.pdf AMD SB810/SB850 Southbridge Databook]<br /> <br /> === AMD SB800 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/45482.pdf AMD SB800-Series Southbridges Register Reference Guide] (RRG)<br /> * [http://support.amd.com/us/Embedded_TechDocs/45481.pdf AMD SB800-Series Southbridges Register Programming Requirements] (RPR)<br /> * [http://support.amd.com/us/Embedded_TechDocs/45483.pdf AMD SB800-Series BIOS Developers Guide] (BDG)<br /> <br /> === AMD SB700/SB710/SB750 ===<br /> <br /> * [http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf AMD SB700/710/750 BIOS Developer’s Guide] (BDG)<br /> * [http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf AMD SB700/710/750 Register Reference Guide] (RRG)<br /> * [http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf AMD SB700/710/750 Register Programming Requirements] (RPR)<br /> * [http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf AMD SB710 Databook]<br /> * [http://developer.amd.com/assets/46837.pdf AMD SB700 Family Product Errata]<br /> <br /> === AMD SB600 ===<br /> <br /> * [http://support.amd.com/us/Embedded_TechDocs/46157_sb600_bdg_pub.3.00.pdf AMD SB600 BIOS Developer's Guide] (BDG)<br /> * [http://support.amd.com/us/Embedded_TechDocs/46155_sb600_rrg_pub_3.03.pdf AMD SB600 Register Reference Manual] (RRG)<br /> * [http://support.amd.com/us/Embedded_TechDocs/46156_sb600_rpr_pub_3.02b.pdf AMD SB600 Register Programming Requirements] (RPR)<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42119_sb600_ds_3.05.pdf AMD SB600 Databook] (rev. 3.05)<br /> * [http://support.amd.com/us/Embedded_TechDocs/42119_sb600_ds_pub_3.07.pdf AMD SB600 Databook] (rev. 3.07)<br /> <br /> === AMD 8111 ===<br /> <br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/24674.pdf AMD-8111™ HyperTransport™ I/O Hub Data Sheet]<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/26036.pdf AMD-8111™ HyperTransport™ I/O Hub Product Brief]<br /> * [http://support.amd.com/us/ChipsetMotherboard_TechDocs/25720.pdf AMD-8111™ HyperTransport™ I/O Hub Revision Guide]<br /> <br /> == Intel ==<br /> <br /> === Intel 82801BA/BAM (ICH2) ===<br /> <br /> * [http://developer.intel.com/design/chipsets/datashts/290687.htm Datasheet]<br /> <br /> = Super I/O =<br /> <br /> == ITE ==<br /> <br /> * [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&amp;ID=5 PC Desktop/Notebook Super I/Os]<br /> ** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&amp;ID=5 Desktop Super I/Os]<br /> ** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&amp;ID=6 Notebook Super I/Os]<br /> <br /> == Winbond / Nuvoton ==<br /> <br /> * [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/ISASuperIO/ ISA Super I/Os]<br /> * [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/LPCSuperIOforDesktopAndServer/ LPC Super I/O for Desktop &amp; Server]<br /> * [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforDesktop/ Advanced Super I/O for Desktop]<br /> * [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforNotebook/ Advanced Super I/O for Notebook]<br /> <br /> == Fintek ==<br /> <br /> * [http://www.fintek.com.tw/eng/products.asp?BID=1&amp;SID=17&amp;layer=0 Super Hardware Monitor + SIO]<br /> <br /> == NSC ==<br /> <br /> (bought by Winbond, now Nuvoton)<br /> <br /> == ALi ==<br /> <br /> == SMSC ==<br /> <br /> * [http://www.smsc.com/main/catalog/ioprods.html Products / datasheets overview]<br /> * [http://www.smsc.com/main/datasheet.html Various product datasheets]<br /> <br /> = Other =<br /> <br /> == ACPI ==<br /> <br /> * http://www.acpi.info<br /> <br /> == USB ==<br /> <br /> == Misc ==<br /> <br /> * [http://support.amd.com/us/Pages/techdocs.aspx AMD public documents]<br /> ** The [http://www.amd.com/us/products/embedded/develop-and-design/Pages/processor-chipset-linux-supprt.aspx AMD64 Embedded Processors and Chipset Linux Support] web page features links to supported projects (like coreboot) and links to documentation.<br /> <br /> = Resources =<br /> <br /> There are many datasheet archives on the web which may have other (usually older) datasheets which already disappeared from vendor websites.</div>

Stuge http://www.coreboot.org/Download_coreboot 2011-07-13T02:50:20Z

<p>Stuge: /* Source code browsing */</p> <hr /> <div>__NOTOC__<br /> '''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br /> <br /> There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, OS X and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br /> <br /> == Snapshots ==<br /> <br /> There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br /> <br /> = Git =<br /> <br /> coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and gerrit in coreboot.<br /> <br /> Old subversion repository references that still apply will continue to be kept here.<br /> <br /> == Git clone ==<br /> <br /> coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br /> <br /> === Anonymous access ===<br /> <br /> To clone the coreboot repository (ca. 210 MB data as of 07/2011):<br /> <br /> $ git clone http://review.coreboot.org/p/coreboot<br /> <br /> If you want the &lt;span style=&quot;color: #ff0000&quot;&gt;obsolete, unsupported, and experimental&lt;/span&gt; '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br /> <br /> $ svn co svn://coreboot.org/repository/coreboot-v3<br /> <br /> If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br /> <br /> $ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br /> <br /> === Developer access with write permission ===<br /> <br /> Please see our wiki page about [[Git]] for all the details.<br /> <br /> == Source code browsing ==<br /> <br /> You can browse the coreboot Git repository online using [http://review.coreboot.org/gitweb?p=coreboot.git gitweb] including it's [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree tree view] for accessing the files.<br /> <br /> == Repositories on coreboot.org ==<br /> <br /> '''coreboot current Git tree:'''<br /> * &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> '''coreboot v1 (obsolete):'''<br /> * svn://coreboot.org/coreboot/branches/coreboot-v1<br /> * &lt;nowiki&gt;https://svn.coreboot.org/coreboot/branches/coreboot-v1&lt;/nowiki&gt;<br /> <br /> '''coreboot v3 (obsolete):'''<br /> * svn://coreboot.org/repository/coreboot-v3<br /> * &lt;nowiki&gt;https://svn.coreboot.org/repository/coreboot-v3&lt;/nowiki&gt;<br /> <br /> '''[[FILO]]:'''<br /> * svn://coreboot.org/filo/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/filo/&lt;/nowiki&gt;<br /> <br /> '''[[Buildrom]]:'''<br /> * svn://coreboot.org/buildrom/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/buildrom/&lt;/nowiki&gt;<br /> <br /> '''[[Distributed and Automated Testsystem]]:'''<br /> * svn://coreboot.org/testsystem<br /> * &lt;nowiki&gt;https://svn.coreboot.org/testsystem/&lt;/nowiki&gt;</div>

Stuge http://www.coreboot.org/Download_coreboot 2011-07-13T02:49:31Z

<p>Stuge: /* Git */</p> <hr /> <div>__NOTOC__<br /> '''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br /> <br /> There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, OS X and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br /> <br /> == Snapshots ==<br /> <br /> There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br /> <br /> = Git =<br /> <br /> coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and gerrit in coreboot.<br /> <br /> Old subversion repository references that still apply will continue to be kept here.<br /> <br /> == Git clone ==<br /> <br /> coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br /> <br /> === Anonymous access ===<br /> <br /> To clone the coreboot repository (ca. 210 MB data as of 07/2011):<br /> <br /> $ git clone http://review.coreboot.org/p/coreboot<br /> <br /> If you want the &lt;span style=&quot;color: #ff0000&quot;&gt;obsolete, unsupported, and experimental&lt;/span&gt; '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br /> <br /> $ svn co svn://coreboot.org/repository/coreboot-v3<br /> <br /> If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br /> <br /> $ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br /> <br /> === Developer access with write permission ===<br /> <br /> Please see our wiki page about [[Git]] for all the details.<br /> <br /> == Source code browsing ==<br /> <br /> You can browse the coreboot Git repository online using [http://review.coreboot.org/gitweb?p=coreboot.git gitweb] including it's [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree tree view].<br /> <br /> == Repositories on coreboot.org ==<br /> <br /> '''coreboot current Git tree:'''<br /> * &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> '''coreboot v1 (obsolete):'''<br /> * svn://coreboot.org/coreboot/branches/coreboot-v1<br /> * &lt;nowiki&gt;https://svn.coreboot.org/coreboot/branches/coreboot-v1&lt;/nowiki&gt;<br /> <br /> '''coreboot v3 (obsolete):'''<br /> * svn://coreboot.org/repository/coreboot-v3<br /> * &lt;nowiki&gt;https://svn.coreboot.org/repository/coreboot-v3&lt;/nowiki&gt;<br /> <br /> '''[[FILO]]:'''<br /> * svn://coreboot.org/filo/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/filo/&lt;/nowiki&gt;<br /> <br /> '''[[Buildrom]]:'''<br /> * svn://coreboot.org/buildrom/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/buildrom/&lt;/nowiki&gt;<br /> <br /> '''[[Distributed and Automated Testsystem]]:'''<br /> * svn://coreboot.org/testsystem<br /> * &lt;nowiki&gt;https://svn.coreboot.org/testsystem/&lt;/nowiki&gt;</div>

Stuge http://www.coreboot.org/Download_coreboot 2011-07-13T02:47:18Z

<p>Stuge: </p> <hr /> <div>__NOTOC__<br /> '''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br /> <br /> There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, OS X and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br /> <br /> == Snapshots ==<br /> <br /> There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br /> <br /> = Git =<br /> <br /> coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and Gerrit.<br /> <br /> Old subversion repository references that still apply will continue to be kept here.<br /> <br /> == Git clone ==<br /> <br /> coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br /> <br /> === Anonymous access ===<br /> <br /> To clone the coreboot repository (ca. 210 MB data as of 07/2011):<br /> <br /> $ git clone http://review.coreboot.org/p/coreboot<br /> <br /> If you want the &lt;span style=&quot;color: #ff0000&quot;&gt;obsolete, unsupported, and experimental&lt;/span&gt; '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br /> <br /> $ svn co svn://coreboot.org/repository/coreboot-v3<br /> <br /> If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br /> <br /> $ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br /> <br /> === Developer access with write permission ===<br /> <br /> Please see our wiki page about [[Git]] for all the details.<br /> <br /> == Source code browsing ==<br /> <br /> You can browse the coreboot Git repository online using [http://review.coreboot.org/gitweb?p=coreboot.git gitweb] including it's [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree tree view].<br /> <br /> == Repositories on coreboot.org ==<br /> <br /> '''coreboot current Git tree:'''<br /> * &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> '''coreboot v1 (obsolete):'''<br /> * svn://coreboot.org/coreboot/branches/coreboot-v1<br /> * &lt;nowiki&gt;https://svn.coreboot.org/coreboot/branches/coreboot-v1&lt;/nowiki&gt;<br /> <br /> '''coreboot v3 (obsolete):'''<br /> * svn://coreboot.org/repository/coreboot-v3<br /> * &lt;nowiki&gt;https://svn.coreboot.org/repository/coreboot-v3&lt;/nowiki&gt;<br /> <br /> '''[[FILO]]:'''<br /> * svn://coreboot.org/filo/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/filo/&lt;/nowiki&gt;<br /> <br /> '''[[Buildrom]]:'''<br /> * svn://coreboot.org/buildrom/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/buildrom/&lt;/nowiki&gt;<br /> <br /> '''[[Distributed and Automated Testsystem]]:'''<br /> * svn://coreboot.org/testsystem<br /> * &lt;nowiki&gt;https://svn.coreboot.org/testsystem/&lt;/nowiki&gt;</div>

Stuge http://www.coreboot.org/Download_coreboot 2011-07-13T02:42:41Z

<p>Stuge: </p> <hr /> <div>__NOTOC__<br /> '''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br /> <br /> There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, OS X and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br /> <br /> == Snapshots ==<br /> <br /> There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br /> <br /> = Git =<br /> <br /> coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and Gerrit.<br /> <br /> Old subversion repository references that still apply will continue to be kept here.<br /> <br /> == Git clone ==<br /> <br /> coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br /> <br /> === Anonymous access ===<br /> <br /> To clone the coreboot repository (ca. 210 MB data as of 07/2011):<br /> <br /> $ git clone http://review.coreboot.org/p/coreboot<br /> <br /> If you want the &lt;span style=&quot;color: #ff0000&quot;&gt;obsolete, unsupported, and experimental&lt;/span&gt; '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br /> <br /> $ svn co svn://coreboot.org/repository/coreboot-v3<br /> <br /> If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br /> <br /> $ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br /> <br /> === Developer access with write permission ===<br /> <br /> Please see our wiki page about [[Git]] for all the details.<br /> <br /> == Source code browsing ==<br /> <br /> You can browse the coreboot Git repository online using [http://review.coreboot.org/gitweb?p=coreboot.git gitweb].<br /> <br /> == Repositories on coreboot.org ==<br /> <br /> '''coreboot current Git tree:'''<br /> * &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> '''coreboot v1 (obsolete):'''<br /> * svn://coreboot.org/coreboot/branches/coreboot-v1<br /> * &lt;nowiki&gt;https://svn.coreboot.org/coreboot/branches/coreboot-v1&lt;/nowiki&gt;<br /> <br /> '''coreboot v3 (obsolete):'''<br /> * svn://coreboot.org/repository/coreboot-v3<br /> * &lt;nowiki&gt;https://svn.coreboot.org/repository/coreboot-v3&lt;/nowiki&gt;<br /> <br /> '''[[FILO]]:'''<br /> * svn://coreboot.org/filo/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/filo/&lt;/nowiki&gt;<br /> <br /> '''[[Buildrom]]:'''<br /> * svn://coreboot.org/buildrom/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/buildrom/&lt;/nowiki&gt;<br /> <br /> '''[[Distributed and Automated Testsystem]]:'''<br /> * svn://coreboot.org/testsystem<br /> * &lt;nowiki&gt;https://svn.coreboot.org/testsystem/&lt;/nowiki&gt;</div>

Stuge http://www.coreboot.org/Download_coreboot 2011-07-13T02:40:56Z

<p>Stuge: </p> <hr /> <div>__NOTOC__<br /> '''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br /> <br /> There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, OS X and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br /> <br /> == Snapshots ==<br /> <br /> There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br /> <br /> = Git =<br /> <br /> coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and Gerrit.<br /> <br /> Old subversion repository references that still apply will continue to be kept here.<br /> <br /> == Git clone ==<br /> <br /> coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br /> <br /> === Anonymous access ===<br /> <br /> To clone the coreboot repository (ca. 210 MB data as of 07/2011):<br /> <br /> $ git clone http://review.coreboot.org/p/coreboot<br /> <br /> If you want the &lt;span style=&quot;color: #ff0000&quot;&gt;obsolete, unsupported, and experimental&lt;/span&gt; '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br /> <br /> $ svn co svn://coreboot.org/repository/coreboot-v3<br /> <br /> If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br /> <br /> $ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br /> <br /> === Developer access with write permission ===<br /> <br /> Please see our wiki page about [[Git]] for all the details.<br /> <br /> == Source code browsing ==<br /> <br /> You can browse the coreboot Git repository online using the [http://tracker.coreboot.org/trac/coreboot/browser Trac interface] or [http://review.coreboot.org/gitweb?p=coreboot.git gitweb].<br /> <br /> == Repositories on coreboot.org ==<br /> <br /> '''coreboot current Git tree:'''<br /> * &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> '''coreboot v1 (obsolete):'''<br /> * svn://coreboot.org/coreboot/branches/coreboot-v1<br /> * &lt;nowiki&gt;https://svn.coreboot.org/coreboot/branches/coreboot-v1&lt;/nowiki&gt;<br /> <br /> '''coreboot v3 (obsolete):'''<br /> * svn://coreboot.org/repository/coreboot-v3<br /> * &lt;nowiki&gt;https://svn.coreboot.org/repository/coreboot-v3&lt;/nowiki&gt;<br /> <br /> '''[[FILO]]:'''<br /> * svn://coreboot.org/filo/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/filo/&lt;/nowiki&gt;<br /> <br /> '''[[Buildrom]]:'''<br /> * svn://coreboot.org/buildrom/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/buildrom/&lt;/nowiki&gt;<br /> <br /> '''[[Distributed and Automated Testsystem]]:'''<br /> * svn://coreboot.org/testsystem<br /> * &lt;nowiki&gt;https://svn.coreboot.org/testsystem/&lt;/nowiki&gt;</div>

Stuge http://www.coreboot.org/Download_coreboot 2011-07-13T02:40:08Z

<p>Stuge: coreboot has switched to using Git for version control.</p> <hr /> <div>__NOTOC__<br /> '''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br /> <br /> There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, OS X and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br /> <br /> == Snapshots ==<br /> <br /> There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br /> <br /> = Git =<br /> <br /> coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and Gerrit.<br /> <br /> Old subversion repository references that still apply will continue to be kept here.<br /> <br /> == Git clone ==<br /> <br /> coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br /> <br /> === Anonymous access ===<br /> <br /> To clone the coreboot repository (ca. 210 MB data as of 07/2011):<br /> <br /> $ git clone http://review.coreboot.org/p/coreboot<br /> <br /> If you want the &lt;span style=&quot;color: #ff0000&quot;&gt;obsolete, unsupported, and experimental&lt;/span&gt; '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br /> <br /> $ svn co svn://coreboot.org/repository/coreboot-v3<br /> <br /> If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br /> <br /> $ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br /> <br /> === Developer access with write permission ===<br /> <br /> Please see our wiki page about [[Git]] for all the details.<br /> <br /> == Source code browsing ==<br /> <br /> You can browse the coreboot Git repository online using the [http://tracker.coreboot.org/trac/coreboot/browser Trac interface] or [http://review.coreboot.org/gitweb?p=coreboot.git gitweb].<br /> <br /> == Repositories on coreboot.org ==<br /> <br /> '''coreboot current tree:'''<br /> * &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> '''coreboot v1 (obsolete):'''<br /> * svn://coreboot.org/coreboot/branches/coreboot-v1<br /> * &lt;nowiki&gt;https://svn.coreboot.org/coreboot/branches/coreboot-v1&lt;/nowiki&gt;<br /> <br /> '''coreboot v3 (obsolete):'''<br /> * svn://coreboot.org/repository/coreboot-v3<br /> * &lt;nowiki&gt;https://svn.coreboot.org/repository/coreboot-v3&lt;/nowiki&gt;<br /> <br /> '''[[FILO]]:'''<br /> * svn://coreboot.org/filo/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/filo/&lt;/nowiki&gt;<br /> <br /> '''[[Buildrom]]:'''<br /> * svn://coreboot.org/buildrom/<br /> * &lt;nowiki&gt;https://svn.coreboot.org/buildrom/&lt;/nowiki&gt;<br /> <br /> '''[[Distributed and Automated Testsystem]]:'''<br /> * svn://coreboot.org/testsystem<br /> * &lt;nowiki&gt;https://svn.coreboot.org/testsystem/&lt;/nowiki&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-13T13:31:00Z

<p>Stuge: /* Commit messages */</p> <hr /> <div>= Gerrit =<br /> As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone &lt;nowiki&gt;http://review.coreboot.org/p/coreboot&lt;/nowiki&gt;<br /> <br /> = Authenticated read/write access =<br /> <br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> <br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> Alternatively, you could also just run<br /> <br /> make gitconfig<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...<br /> <br /> make gitconfig<br /> <br /> ...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[Git#Authenticated read/write access|Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> <br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> <br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> <br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> <br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> <br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> <br /> git log origin/master..<br /> <br /> before '''git push''' to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].<br /> <br /> == Evolving patches ==<br /> <br /> Often it might happen that the patch you sent for approval is not good enough from the first attempt. Gerrit and git make it easy to track patch evolution during the review process until patches meet our quality standards and are ready for approval.<br /> <br /> You can easily modify a patch sent to gerrit by you or even by someone else. Just apply it locally using one of the possible ways to do it, make a new local commit that fixes the issues reported by the reviewers, then rebase the change by preserving the same Change-ID. We recommend you to use the git rebase command in interactive mode, ''git rebase -i master'', then commit and push the updated patch.<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at some of these documents:<br /> * http://git-scm.com/<br /> * http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html<br /> * http://git.or.cz/course/svn.html<br /> * and in particular the [http://progit.org/ Pro Git book]<br /> <br /> Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:22:21Z

<p>Stuge: /* Commit messages */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:21:51Z

<p>Stuge: /* Commit messages */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which automatically adds a Change-Id: when the commit message is saved.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:20:56Z

<p>Stuge: </p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|mentioned above]], which automatically creates the Change-Id: when the commit is created.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:20:07Z

<p>Stuge: /* Commit messages */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|mentioned above]], which automatically creates the Change-Id: when the commit is created.<br /> <br /> You can verify that all your commits have a Change-Id: line by running:<br /> git log origin/master..<br /> <br /> before you push code to gerrit.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:17:46Z

<p>Stuge: /* Commit messages */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|mentioned above]], which automatically creates the Change-Id:.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:14:32Z

<p>Stuge: /* Commit messages */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing a Change-Id line. This is OK because the commit-msg hook [[#Authenticated_read/write_access|mentioned above]] has been set up, and will create an appropriate Change-Id automatically.<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:13:19Z

<p>Stuge: /* Commit messages */ Explain why example well-formatted commit message lacks Change-Id:</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> The example is missing the Change-Id footer field, since it will be created automatically by the commit-msg hook [[#Authenticated_read/write_access|mentioned above]].<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:06:26Z

<p>Stuge: /* Authenticated read/write access */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg &lt;nowiki&gt;http://review.coreboot.org/tools/hooks/commit-msg&lt;/nowiki&gt; &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:04:14Z

<p>Stuge: /* Authenticated read/write access */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:04:01Z

<p>Stuge: /* Authenticated read/write access */</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg &amp;&amp; \<br /> chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T05:03:24Z

<p>Stuge: Add chmod +x after hook download command so hook is actually activated</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg &amp;&amp; chmod +x .git/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T04:47:33Z

<p>Stuge: </p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> ...after which you then push changes with any of the configured branches checked out with a simple:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br /> <br /> '''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br /> git log origin/master..<br /> before git push to verify which commits you are about to send for review.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> Please also feel free to ask Git questions in the coreboot IRC channel or on the mailing list.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T04:42:12Z

<p>Stuge: Fix numbering in commit message guidelines</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> # The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> # The second line is empty (no whitespace at all)<br /> # The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> # The next line is empty (no whitespace at all)<br /> # A Change-Id: line to let gerrit track this logical change<br /> # A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from one particular branch it is further convenient to run:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> And then you push changes simply by:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. '''NB!''' If you have applied patches from gerrit on a branch and you push that branch gerrit will think you are submitting new versions of those patches. This may or may not be what you intend, so please run git log origin/master.. before git push and verify that you are will submit the intended commits.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-09T04:40:31Z

<p>Stuge: </p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> 1. The first line of the commit message has a short (less than 65 characters, absmax 75) summary<br /> 2. The second line is empty (no whitespace at all)<br /> 3. The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> 4. The next line is empty (no whitespace at all)<br /> 5. A Change-Id: line to let gerrit track this logical change<br /> 6. A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> ..and remember to always use git commit -s to have git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a well-formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from one particular branch it is further convenient to run:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> And then you push changes simply by:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. '''NB!''' If you have applied patches from gerrit on a branch and you push that branch gerrit will think you are submitting new versions of those patches. This may or may not be what you intend, so please run git log origin/master.. before git push and verify that you are will submit the intended commits.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Git 2011-06-08T23:37:51Z

<p>Stuge: Link to Peter's Git intro on the mailing list, describe correct commit message format, and add tips and information for pushing commits</p> <hr /> <div>= Gerrit =<br /> As part of our move to gerrit, git was introduced as primary SCM.<br /> <br /> == Register with gerrit ==<br /> For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br /> You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings<br /> <br /> === OpenID ===<br /> It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br /> <br /> == Gerrit workflow ==<br /> Gerrit interprets each Git commit as an individual change. Changes are autobuilt by Jenkins, and can be reviewed by developers. Once a change has gotten a positive review and have no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br /> <br /> Reviews grant points on a scale from -2 to 2. The meaning is:<br /> * -2: Do not merge (blocks gerrit from merging)<br /> * -1: I'd prefer you don't merge it<br /> * 0: neutral<br /> * +1: Looks good, but I won't make the last call on it<br /> * +2: Looks good, go ahead and merge (gerrit provides a &quot;submit&quot; function once it has a +2 vote)<br /> <br /> -2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br /> <br /> === Gerrit and CLI ===<br /> Reviews normally happens through the website.<br /> <br /> Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br /> <br /> === Gerrit and Email ===<br /> Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br /> <br /> This gateway will provide:<br /> * no patch submission mechanism (&quot;git push&quot; is CLI friendly)<br /> * patch review (maybe openpgp signed &quot;Acked-by&quot; mails)<br /> * patch submission (automatically with Acked-by?)<br /> * maybe patch rejection? (openpgp signed &quot;Nacked-by&quot; mails)<br /> <br /> = Anonymous read access =<br /> Read-only access is available anonymously:<br /> git clone http://review.coreboot.org/p/coreboot<br /> <br /> = Authenticated read/write access =<br /> git clone ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br /> wget -O .git/hooks/commit-msg http://review.coreboot.org/tools/hooks/commit-msg<br /> <br /> = Working with Git =<br /> <br /> Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to use Git was announced on the mailing list.<br /> <br /> == Commit messages ==<br /> Git does not enforce a commit message style, although maybe it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br /> <br /> 1. The first line of the commit message has a short (less than 65 characters) summary<br /> 2. The second line is empty (no whitespace at all)<br /> 3. The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br /> 4. The next line is empty (no whitespace at all)<br /> 5. A Change-Id: line is added to let gerrit track this logical change<br /> 6. A Signed-off-by: line is added according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br /> <br /> Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-hook as described [[#Authenticated_read/write_access|above]] or by running:<br /> make gitconfig<br /> <br /> And remember to always use git commit -s to make git add your Signed-off-by: automatically.<br /> <br /> Here is an example of a correctly formatted commit message:<br /> examplecomponent: Refactor duplicated setup into a function<br /> <br /> Setting up the demo device correctly requires the exact same register<br /> values to be written into each of the PCI device functions. Moving the<br /> writes into a function allows also otherexamplecomponent to use them.<br /> <br /> Signed-off-by: Joe Hacker &lt;joe@hacker.email&gt;<br /> <br /> == Pushing changes ==<br /> First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see Authenticated read/write access above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br /> git config remote.origin.url ssh://&lt;username&gt;@review.coreboot.org:29418/coreboot<br /> <br /> Then run the following command once to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br /> git config remote.origin.push HEAD:refs/for/master<br /> <br /> After this, the command to push your changes is:<br /> git push origin<br /> <br /> If you always push from one particular branch it is further convenient to run:<br /> git config branch.&lt;particularbranchname&gt;.remote origin<br /> <br /> And then you push changes simply by:<br /> git push<br /> <br /> Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. '''NB!''' If you have applied patches from gerrit on a branch and you push that branch gerrit will think you are submitting new versions of those patches. This may or may not be what you intend, so please run git log origin/master.. before git push and verify that you are will submit the intended commits.<br /> <br /> For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create<br /> <br /> == Further Git reading ==<br /> There are tons of git tutorials out there. Take a look at http://git-scm.com/, http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html, http://git.or.cz/course/svn.html and in particular the http://progit.org/ book.<br /> <br /> = Browsing =<br /> <br /> There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br /> &lt;!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --&gt;</div>

Stuge http://www.coreboot.org/Current_events 2011-05-04T01:32:27Z

<p>Stuge: Mention flashrom in LinuxTag 2011 event</p> <hr /> <div>Please contact [[User:Stepan|Stefan Reinauer]], [[User:Rminnich|Ronald Minnich]] or [[User:Stuge|Peter Stuge]] for more information on the events.<br /> <br /> == Upcoming Events ==<br /> <br /> '''2011'''<br /> <br /> * coreboot and flashrom exhibit at [http://www.linuxtag.org/ LinuxTag] in Berlin on May 11-14, 2011.<br /> <br /> == Past Events ==<br /> <br /> '''2011'''<br /> <br /> * coreboot and flashrom shared a booth at [[FOSDEM 2011]] in Brussels on February 5-6, 2011, and several presentations were held by [[User:Ruik|Rudolf Marek]] and [[User:Hailfinger|Carl-Daniel Hailfinger]].<br /> <br /> <br /> '''2010'''<br /> <br /> * coreboot exhibited at [http://www.linuxtag.org/ LinuxTag 2010] in Berlin on June 9-12, 2010.<br /> * coreboot had its [[FOSDEM 2010|very first DevRoom]] at [http://www.fosdem.org/ FOSDEM] in Brussels on February 6, 2010.<br /> <br /> '''2009'''<br /> <br /> * [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2009/Fahrplan/events/3661.en.html coreboot] at [http://events.ccc.de/congress/2009/ the 26th Chaos Communication Congress (26C3)] in Berlin on December 27, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented [http://www.databadge.net/ifsec2009/reg/lin/show_sessions.php coreboot] at [http://www.linux-world.nl/nl-NL/Bezoeker.aspx?sc_lang=en LinuxWorld Conference &amp; Expo] in Utrecht on November 4, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented [https://har2009.org/program/events/210.en.html coreboot] at [https://wiki.har2009.org/page/Main_Page HAR2009] in Vierhouten on August 13, 2009.<br /> * coreboot had a booth at [[LinuxTag 2009|LinuxTag]] in Berlin on June 24-27, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at [http://freedomhectaipei.pbworks.com/ FreedomHEC Taipei] on June 11, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at [http://goopen2009.friprog.no/ GoOpen 2009] in Oslo on April 16-17, 2009.<br /> * [[User:Stepan|Stefan Reinauer]], [[User:Stuge|Peter Stuge]] and [[User:Ruik|Rudolf Marek]] made a visit at [http://www.embedded-world.de/ embedded world 2009] in Nürnberg on March 3-5.<br /> * [[User:Rminnich|Ron Minnich]] had a [http://scale7x.socallinuxexpo.org/dotorg/coreboot coreboot booth] at the [http://scale7x.socallinuxexpo.org/ Southern California Linux Expo] (SCALE 7x) on February 20-22, 2009.<br /> <br /> '''2008'''<br /> <br /> * [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2008/Fahrplan/events/2970.en.html coreboot: Beyond The Final Frontier] and held a coreboot workshop at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)] on December 27-30.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at the [http://www.nluug.nl/events/nj08/ NLUUG Autumn Conference on Mobile Computing] and [http://www.embeddedlinuxconference.com/elc_europe08/ CE Linux Forum - Embedded Linux conference Europe 2008] on November 6-7.<br /> * [[User:Rminnich|Ronald Minnich]], [[User:Stuge|Peter Stuge]] and [[User:Stepan|Stefan Reinauer]] presented coreboot in a [[Screenshots#Google_Tech_Talks_2008:_coreboot_.28aka_LinuxBIOS.29:_The_Free.2FOpen-Source_x86_Firmware|Google TechTalk]] on October 30.<br /> * [[User:Stuge|Peter Stuge]] presented [http://fscons.org/events/?action=event&amp;id=32 coreboot] at the [http://fscons.org/ Free Society Conference and Nordic Summit 2008] on October 24-26.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at the [http://slackathon.se/2008/ Slackathon 2008] OpenBSD meeting in September.<br /> * Coreboot was exhibiting at [[LinuxTag 2008]] in Berlin on May 28-31.<br /> * The [[Coreboot Symposium 2008|coreboot symposium 2008]] was held in Denver, April 3 – 5, 2008 during the High Performance Computer Science Week [http://www.hpcsw.org HPCSW].<br /> <br /> '''2007'''<br /> <br /> * There was a [[News#2007.2F05.2F23_LinuxBIOS_booth_at_LinuxTag_in_Berlin.2C_29.2F5-2.2F6|LinuxBIOS booth at the LinuxTag in Berlin, May 29 - June 6, 2007]], as well as a hands-on workshop by Peter Stuge.<br /> * Ron Minnich gave [http://www.fosdem.org/2007/schedule/events/linuxbios a talk about LinuxBIOS] on February 24, 2007 at [http://www.fosdem.org/2007/ FOSDEM 2007].<br /> <br /> '''2006'''<br /> <br /> * The [[LinuxBIOS Symposium 2006]] took place on October 1-3, 2006 in Hamburg, Germany.<br /> <br /> '''2005'''<br /> <br /> * The [[LinuxBIOS Summit 2005]] took place on October 11-13 in Santa Fe, NM.</div>

Stuge http://www.coreboot.org/Welcome_to_coreboot 2011-05-04T01:31:01Z

<p>Stuge: Add LinuxTag booth and delete old 8th news item</p> <hr /> <div>&lt;table width=&quot;100%&quot; valign=&quot;top&quot;&gt;&lt;tr valign=&quot;top&quot;&gt;&lt;td width=&quot;80%&quot;&gt;<br /> <br /> &lt;div style=&quot;margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;&quot;&gt;<br /> '''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes what is called a [[Payloads|payload]].<br /> <br /> &lt;small&gt;<br /> With this separation of hardware initialization and later boot logic, coreboot can scale from specialized applications run directly from firmware, operating systems in flash, and custom bootloaders to implementations of firmware standards like PCBIOS and EFI without having to carry features not necessary in the target application, reducing the amount of code and flash space required.<br /> &lt;/small&gt;<br /> <br /> We currently support '''[[Supported Motherboards|230]]''' different mainboards.<br /> &lt;/div&gt;<br /> <br /> &lt;div style=&quot;margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;&quot;&gt;<br /> Is your PC / server / laptop / mainboard supported? Check out our [[Support]] page to find out.<br /> &lt;/div&gt;<br /> <br /> &lt;div style=&quot;margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;&quot;&gt;<br /> coreboot now has a [[git]] mirror.<br /> &lt;/div&gt;<br /> <br /> {| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align=&quot;top&quot; width=100%<br /> |-<br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {{Box|<br /> BORDER = #8898bf|<br /> BACKGROUND = yellow|<br /> WIDTH = 100%|<br /> ICON = &lt;small&gt;[[Benefits|More...]]&lt;/small&gt;|<br /> HEADING = &lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Benefits]]&lt;/span&gt;|<br /> CONTENT =<br /> &lt;small&gt;<br /> * 100% Free Software (GPL), no royalties, no license fees!<br /> * Fast boot times (3 seconds to Linux console)<br /> &lt;!-- * Avoids the need for a slow/buggy/proprietary BIOS --&gt;<br /> &lt;!-- * Runs in 32-Bit protected mode almost from the start --&gt;<br /> &lt;!-- * Written in C, contains virtually no assembly code --&gt;<br /> * Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br /> &lt;!-- * Further features: netboot, serial console, remote flashing, ... --&gt;<br /> &lt;/small&gt;<br /> }}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {{Box|<br /> BORDER = #8898bf|<br /> BACKGROUND = #d1adf6|<br /> WIDTH = 100%|<br /> ICON = &lt;small&gt;[[Use Cases|More...]]&lt;/small&gt;|<br /> HEADING = &lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Use Cases]]&lt;/span&gt;|<br /> CONTENT =<br /> &lt;small&gt;<br /> * Desktop PCs, servers, [[Laptop|laptops]]<br /> * [[Clusters]]<br /> &lt;!-- * Set-Top-Boxes, thin clients --&gt;<br /> * Embedded solutions<br /> &lt;!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --&gt;<br /> &lt;!-- * No-moving-parts solutions (ROM chip as &quot;disk&quot;) --&gt;<br /> &lt;!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --&gt;<br /> &lt;/small&gt;<br /> }}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {{Box|<br /> BORDER = #8898bf|<br /> BACKGROUND = lime|<br /> WIDTH = 100%|<br /> ICON = &lt;small&gt;[[Payloads|More...]]&lt;/small&gt;|<br /> HEADING = &lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Payloads]]&lt;/span&gt;|<br /> CONTENT =<br /> &lt;small&gt;<br /> * [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] &lt;!-- / [[OpenFirmware]] / [[OpenBIOS]] --&gt;<br /> * [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] &lt;!-- / [http://openbsd.org/ OpenBSD]--&gt;<br /> * [[Etherboot]] / [[GPXE]] / [[Payloads|...]]<br /> &lt;!--* [[Memtest86]]<br /> * [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--&gt;<br /> &lt;/small&gt;<br /> }}<br /> <br /> |}<br /> <br /> {| cellspacing=5 cellpadding=15 border=0 valign=&quot;top&quot; width=100%<br /> | width=50% style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_cb.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;About&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Find out more about coreboot.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]&lt;/small&gt;<br /> |}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_devel.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Developers&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Get involved! Help us make coreboot better.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]] | [[Distributed and Automated Testsystem|Testsystem]]&lt;/small&gt;<br /> |}<br /> <br /> |-<br /> | width=50% style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_status.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Status&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Find out whether your hardware is already supported.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]&lt;/small&gt;<br /> |}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_tools.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Related Tools&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Tools and libraries related to coreboot.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]&lt;/small&gt;<br /> |}<br /> <br /> |-<br /> | width=50% style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_101.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Getting Started&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Download coreboot and get started.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]&lt;/small&gt;<br /> |}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_support.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Support&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Learn how to contact us and find help and support.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]&lt;/small&gt;<br /> |}<br /> <br /> |}<br /> &lt;/td&gt;&lt;td width=&quot;20%&quot;&gt;<br /> <br /> [[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br /> <br /> &lt;br clear=all /&gt;<br /> <br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[News]]&lt;/span&gt;'''&lt;hr /&gt;<br /> &lt;!-- Please always make this list 7 items long (7 most recent news items). --&gt;<br /> &lt;small&gt;<br /> * '''2011/04/28:''' [[News#2011.2F4.2F28_Lenovo_ThinkPad_T60_now_supported|Lenovo ThinkPad T60 supported]]<br /> * '''2011/03/27:''' [[News#2011.2F3.2F27_AMD_releases_C32.2FRS56x0.2FSB5100_coreboot_support_on_H8SCM_platform|AMD releases C32/RS56x0/SB5100 coreboot support on H8SCM platform]]<br /> * '''2011/02/28:''' [[News#2011.2F2.2F28_AMD_blogs_about_coreboot|AMD blogs about coreboot]]<br /> * '''2011/02/22:''' [[News#2011.2F2.2F22_Thinkpad_X60s_now_supported|Lenovo Thinkpad X60 supported]]<br /> * '''2011/02/14:''' [[News#2011.2F2.2F14_AMD_submits_coreboot_support_for_AMD_Embedded_G-Series_Platforms|AMD submits coreboot support for AMD Embedded G-Series Platforms]]<br /> * '''2010/12/18:''' [[News#2010.2F12.2F18_Intel_Poulsbo.2FSCH.2FAtom_and_iWave_iW-RainboW-G6_now_supported|Intel Poulsbo/SCH/Atom &amp; iWave iW-RainboW-G6 support]]<br /> * '''2010/12/13:''' [[News#2010.2F12.2F13_ASUS_M2N-E_now_supported|ASUS M2N-E support]]<br /> &lt;/small&gt;<br /> <br /> <br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Current events|Upcoming Events]]&lt;/span&gt;'''&lt;hr /&gt;<br /> &lt;!-- List of upcoming events (remove events after they have taken place). --&gt;<br /> &lt;small&gt;<br /> &lt;!-- * '''2011/mon/day:''' coreboot event at [[Link]] in somecity --&gt;<br /> * '''2011/05/11-14:''' coreboot and [[Flashrom|flashrom]] booths at [http://www.linuxtag.org/ LinuxTag] in Berlin<br /> * [[GSoC|2011 Google Summer of Code]]<br /> &lt;/small&gt;<br /> <br /> <br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[http://blogs.coreboot.org blog news]&lt;/span&gt;'''&lt;hr /&gt;<br /> &lt;small&gt;<br /> &lt;rss max=5&gt;http://blogs.coreboot.org/feed&lt;/rss&gt;<br /> &lt;/small&gt;<br /> <br /> <br /> &lt;br clear=all /&gt;<br /> {{#widget:Ohloh Project|id=coreboot|type=partner_badge}}<br /> {{#widget:Ohloh Project|id=coreboot|type=cocomo}}<br /> <br /> <br /> &lt;/td&gt;&lt;/tr&gt;&lt;/table&gt;<br /> <br /> __NOTOC__<br /> __NOEDITSECTION__</div>

Stuge http://www.coreboot.org/Current_events 2011-05-04T01:23:43Z

<p>Stuge: Move FOSDEM 2011 to past events, add info about LinuxTag 2011</p> <hr /> <div>Please contact [[User:Stepan|Stefan Reinauer]], [[User:Rminnich|Ronald Minnich]] or [[User:Stuge|Peter Stuge]] for more information on the events.<br /> <br /> == Upcoming Events ==<br /> <br /> '''2011'''<br /> <br /> * coreboot exhibits at [http://www.linuxtag.org/ LinuxTag 2011] in Berlin on May 11-14, 2011.<br /> <br /> == Past Events ==<br /> <br /> '''2011'''<br /> <br /> * coreboot and flashrom shared a booth at [[FOSDEM 2011]] in Brussels on February 5-6, 2011, and several presentations were held by [[User:Ruik|Rudolf Marek]] and [[User:Hailfinger|Carl-Daniel Hailfinger]].<br /> <br /> <br /> '''2010'''<br /> <br /> * coreboot exhibited at [http://www.linuxtag.org/ LinuxTag 2010] in Berlin on June 9-12, 2010.<br /> * coreboot had its [[FOSDEM 2010|very first DevRoom]] at [http://www.fosdem.org/ FOSDEM] in Brussels on February 6, 2010.<br /> <br /> '''2009'''<br /> <br /> * [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2009/Fahrplan/events/3661.en.html coreboot] at [http://events.ccc.de/congress/2009/ the 26th Chaos Communication Congress (26C3)] in Berlin on December 27, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented [http://www.databadge.net/ifsec2009/reg/lin/show_sessions.php coreboot] at [http://www.linux-world.nl/nl-NL/Bezoeker.aspx?sc_lang=en LinuxWorld Conference &amp; Expo] in Utrecht on November 4, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented [https://har2009.org/program/events/210.en.html coreboot] at [https://wiki.har2009.org/page/Main_Page HAR2009] in Vierhouten on August 13, 2009.<br /> * coreboot had a booth at [[LinuxTag 2009|LinuxTag]] in Berlin on June 24-27, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at [http://freedomhectaipei.pbworks.com/ FreedomHEC Taipei] on June 11, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at [http://goopen2009.friprog.no/ GoOpen 2009] in Oslo on April 16-17, 2009.<br /> * [[User:Stepan|Stefan Reinauer]], [[User:Stuge|Peter Stuge]] and [[User:Ruik|Rudolf Marek]] made a visit at [http://www.embedded-world.de/ embedded world 2009] in Nürnberg on March 3-5.<br /> * [[User:Rminnich|Ron Minnich]] had a [http://scale7x.socallinuxexpo.org/dotorg/coreboot coreboot booth] at the [http://scale7x.socallinuxexpo.org/ Southern California Linux Expo] (SCALE 7x) on February 20-22, 2009.<br /> <br /> '''2008'''<br /> <br /> * [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2008/Fahrplan/events/2970.en.html coreboot: Beyond The Final Frontier] and held a coreboot workshop at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)] on December 27-30.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at the [http://www.nluug.nl/events/nj08/ NLUUG Autumn Conference on Mobile Computing] and [http://www.embeddedlinuxconference.com/elc_europe08/ CE Linux Forum - Embedded Linux conference Europe 2008] on November 6-7.<br /> * [[User:Rminnich|Ronald Minnich]], [[User:Stuge|Peter Stuge]] and [[User:Stepan|Stefan Reinauer]] presented coreboot in a [[Screenshots#Google_Tech_Talks_2008:_coreboot_.28aka_LinuxBIOS.29:_The_Free.2FOpen-Source_x86_Firmware|Google TechTalk]] on October 30.<br /> * [[User:Stuge|Peter Stuge]] presented [http://fscons.org/events/?action=event&amp;id=32 coreboot] at the [http://fscons.org/ Free Society Conference and Nordic Summit 2008] on October 24-26.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at the [http://slackathon.se/2008/ Slackathon 2008] OpenBSD meeting in September.<br /> * Coreboot was exhibiting at [[LinuxTag 2008]] in Berlin on May 28-31.<br /> * The [[Coreboot Symposium 2008|coreboot symposium 2008]] was held in Denver, April 3 – 5, 2008 during the High Performance Computer Science Week [http://www.hpcsw.org HPCSW].<br /> <br /> '''2007'''<br /> <br /> * There was a [[News#2007.2F05.2F23_LinuxBIOS_booth_at_LinuxTag_in_Berlin.2C_29.2F5-2.2F6|LinuxBIOS booth at the LinuxTag in Berlin, May 29 - June 6, 2007]], as well as a hands-on workshop by Peter Stuge.<br /> * Ron Minnich gave [http://www.fosdem.org/2007/schedule/events/linuxbios a talk about LinuxBIOS] on February 24, 2007 at [http://www.fosdem.org/2007/ FOSDEM 2007].<br /> <br /> '''2006'''<br /> <br /> * The [[LinuxBIOS Symposium 2006]] took place on October 1-3, 2006 in Hamburg, Germany.<br /> <br /> '''2005'''<br /> <br /> * The [[LinuxBIOS Summit 2005]] took place on October 11-13 in Santa Fe, NM.</div>

Stuge http://www.coreboot.org/Logo 2010-11-10T02:47:11Z

<p>Stuge: Add credit due to Spooky Panda for post design logo work</p> <hr /> <div>''They are very fast moving. The European Brown Hare (Lepus europaeus) can run at speeds of up to 72 km/h (45 mph).'' --[http://en.wikipedia.org/wiki/Hare Wikipedia]<br /> <br /> == coreboot Logo License ==<br /> <br /> The logo for the coreboot project is released under the following license.<br /> <br /> :Copyright © 2008 Konsult Stuge<br /> :Copyright © 2008 coresystems GmbH<br /> <br /> :This logo or a modified version may be used by anyone to refer to the coreboot project, but does not indicate endorsement by the project.<br /> <br /> In particular, we encourage you to use the logo for the purpose of advertising support for coreboot. This includes, but is not limited to, the following uses:<br /> <br /> * computer systems that come preloaded with coreboot and such that support coreboot through a flash upgrade.<br /> * enhancements and projects related to coreboot such as payloads, coreboot ports to new systems and utilities that are to be used in systems also using coreboot<br /> * coreboot documentation<br /> * posters, clothing, presentations and other promotion material referring to the coreboot project<br /> <br /> Please make the image a link to http://www.coreboot.org/ if you use it on a web page.<br /> <br /> == Graphical usage guidelines ==<br /> <br /> The logo is in sharp contrast with the background. The normal appearance is black on white. When the logo must be used on dark background, a white or bright area surrounds it, or it is inverted to white on black instead of the normal black on white.<br /> <br /> == Logo kit archive ==<br /> <br /> [[Media:Coreboot_logo_kit.zip|Coreboot_logo_kit.zip]] contains all files on this page in a convenient archive.<br /> <br /> == Individual files ==<br /> <br /> You can also download individual files that suit your usage.<br /> <br /> === Full logo with name ===<br /> <br /> [[Image:Coreboot_full_web.png]]<br /> <br /> Download [[Media:Coreboot_full.svg|SVG]], [[Media:Coreboot_full_highres.png|high-resolution PNG]] or [[Media:Coreboot_full_web.png|low-resolution PNG]].<br /> <br /> === Logo without name ===<br /> <br /> [[Image:Coreboot_hare_web.png]]<br /> <br /> Download [[Media:Coreboot_hare.svg|SVG]], [[Media:Coreboot_hare_highres.png|high-resolution PNG]] or [[Media:Coreboot_hare_web.png|low-resolution PNG]].<br /> <br /> === Name only ===<br /> <br /> [[Image:Coreboot_name_web.png]]<br /> <br /> Download [[Media:Coreboot_name.svg|SVG]], [[Media:Coreboot_name_highres.png|high-resolution PNG]] or [[Media:Coreboot_name_web.png|low-resolution PNG]].<br /> <br /> === Page footer with stripe and name ===<br /> <br /> [[Image:Coreboot_footer_web.png]]<br /> <br /> Download [[Media:Coreboot_footer.svg|SVG]], [[Media:Coreboot_footer_highres.png|high-resolution PNG]] or [[Media:Coreboot_footer_web.png|low-resolution PNG]].<br /> <br /> === Combination logo with name and thick stripe ===<br /> <br /> [[Image:Coreboot_combo_web.png]]<br /> <br /> Download [[Media:Coreboot_combo.svg|SVG]], [[Media:Coreboot_combo_highres.png|high-resolution PNG]] or [[Media:Coreboot_combo_web.png|low-resolution PNG]].<br /> <br /> == Credits ==<br /> <br /> Image and typography was created by [http://www.breakfastdesign.nu/ Breakfast Design]. Post design work was done by [http://spookypanda.se/ Spooky Panda]. The coreboot logo was sponsored by:<br /> <br /> * [http://stuge.se/ Konsult Stuge]<br /> * [http://www.coresystems.de/ coresystems GmbH]<br /> * [http://kwlug.org/ Kitchener Waterloo Linux User Group] and Richard Weait</div>

Stuge http://www.coreboot.org/GCI2010 2010-10-31T06:57:18Z

<p>Stuge: </p> <hr /> <div>We hope to participate in Google Code-in 2010 (basically Google Summer of code for 13-18 year old students)<br /> <br /> Please note that the task list is not finished, and we will add more tasks once we know how long individual tasks are supposed to take.<br /> <br /> See http://www.flashrom.org/GCI2010 for a huge list of flashrom related tasks.<br /> <br /> = Code: writing or refactoring code =<br /> <br /> = Documentation: creating/editing documents =<br /> * Update the FAQ wiki page, maybe restructure it<br /> <br /> = Outreach: community management and outreach/marketing =<br /> <br /> = Quality Assurance: testing and ensuring code is of high quality =<br /> * Design a coreboot tester product, hardware and software<br /> The test system is severely under-utilized. It would likely help to have a simple tester product or package that can be used to hook up mainboards to the test system. FPGA + ARM with Ethernet?<br /> <br /> = Research: studying a problem and recommending solutions =<br /> <br /> = Training: helping others learn more =<br /> * Create a FAQ entry with a high-level overview of coreboot code<br /> * Create a wiki page about devicetree.cb files<br /> <br /> = Translation: localization =<br /> <br /> = User Interface: user experience research or user interface design and interaction =</div>

Stuge http://www.coreboot.org/GCI2010 2010-10-31T06:56:05Z

<p>Stuge: </p> <hr /> <div>We hope to participate in Google Code-in 2010 (basically Google Summer of code for 13-18 year old students)<br /> <br /> Please note that the task list is not finished, and we will add more tasks once we know how long individual tasks are supposed to take.<br /> <br /> See http://www.flashrom.org/GCI2010 for a huge list of flashrom related tasks.<br /> <br /> = Code: Tasks related to writing or refactoring code =<br /> <br /> = Documentation: Tasks related to creating/editing documents =<br /> * Update the FAQ wiki page, maybe restructure it<br /> * Create a FAQ entry with a high-level overview of coreboot code<br /> * Create a wiki page about devicetree.cb files<br /> <br /> = Outreach: Tasks related to community management and outreach/marketing =<br /> <br /> = Quality Assurance: Tasks related to testing and ensuring code is of high quality =<br /> * Design a coreboot tester product, hardware and software<br /> The test system is severely under-utilized. It would likely help to have a simple tester product or package that can be used to hook up mainboards to the test system. FPGA + ARM with Ethernet?<br /> <br /> = Research: Tasks related to studying a problem and recommending solutions =<br /> <br /> = Training: Tasks related to helping others learn more =<br /> <br /> = Translation: Tasks related to localization =<br /> <br /> = User Interface: Tasks related to user experience research or user interface design and interaction =</div>

Stuge http://www.coreboot.org/GCI2010 2010-10-31T06:55:50Z

<p>Stuge: </p> <hr /> <div>We hope to participate in Google Code-in 2010 (basically Google Summer of code for 13-18 year old students)<br /> <br /> Please note that the task list is not finished, and we will add more tasks once we know how long individual tasks are supposed to take.<br /> <br /> See http://www.flashrom.org/GCI2010 for a huge list of flashrom related tasks.<br /> <br /> We hope to participate in Google Code-in 2010 (basically Google Summer of code for 13-18 year old students)<br /> <br /> = Code: Tasks related to writing or refactoring code =<br /> <br /> = Documentation: Tasks related to creating/editing documents =<br /> * Update the FAQ wiki page, maybe restructure it<br /> * Create a FAQ entry with a high-level overview of coreboot code<br /> * Create a wiki page about devicetree.cb files<br /> <br /> = Outreach: Tasks related to community management and outreach/marketing =<br /> <br /> = Quality Assurance: Tasks related to testing and ensuring code is of high quality =<br /> * Design a coreboot tester product, hardware and software<br /> The test system is severely under-utilized. It would likely help to have a simple tester product or package that can be used to hook up mainboards to the test system. FPGA + ARM with Ethernet?<br /> <br /> = Research: Tasks related to studying a problem and recommending solutions =<br /> <br /> = Training: Tasks related to helping others learn more =<br /> <br /> = Translation: Tasks related to localization =<br /> <br /> = User Interface: Tasks related to user experience research or user interface design and interaction =</div>

Stuge http://www.coreboot.org/Products 2010-10-01T08:04:27Z

<p>Stuge: Add TechNexion</p> <hr /> <div>Here's a list of vendors and their products or services related to coreboot. Please [[Mailinglist|contact us]] if you wish to add your product/company to the list. <br /> <br /> == Artec Group ==<br /> <br /> [http://www.artecgroup.com Artec Group] runs coreboot on their Geode LX based [http://www.thincan.com DBE61 ThinCan] system.<br /> <br /> == Cluster Labs ==<br /> <br /> [http://www.cluster-labs.com/ Cluster Labs] sells a 1.1 GHz PIII cluster node with 1 GB memory, fast ethernet, and boots coreboot. <br /> <br /> == corehost ==<br /> <br /> [http://corehost.us corehost] is the first hosting provider in the world to deploy hardware that runs coreboot. You can rent virtual or dedicated servers based on hardware that runs coreboot.<br /> <br /> == coresystems GmbH ==<br /> <br /> [http://www.coresystems.de/ coresystems GmbH] is offering coreboot based services and products. If you are a hardware/appliance vendor and want your system running coreboot, contact coresystems. As a coreboot contributor, coresystems is hosting the coreboot development repository, mailing list and web page.<br /> <br /> == Cray ==<br /> <br /> The Cray [http://www.cray.com/products/xd1/ Xd1] is an Opteron-based system which runs coreboot. <br /> <br /> == CW Linux ==<br /> <br /> [http://www.cwlinux.com CW Linux] offers pre-installed coreboot motherboards, SDK and related hardware for people want to use or develop applications on coreboot. It also provides professional services for custom coreboot-based system development. <br /> <br /> == i-TECH Corp. ==<br /> <br /> [http://www.i-tech.com/ i-TECH] is selling test and analysis tools with coreboot, including all its &quot;Satellite&quot; Fibre Channel analyzers (IFC-3016, IFC-4016, IFC-30, IFC40) and &quot;PassPort&quot;-based test and analysis tools. <br /> <br /> == Linutop ==<br /> <br /> [http://linutop.com/ Linutop] is going to ship coreboot on their diskless computers.<br /> <br /> == Linux Labs ==<br /> <br /> [http://www.linuxlabs.com Linux Labs] is selling [http://www.linuxlabs.com/starterclusters.html LinuxBIOS Beowulf clusters] comprised of 1U x86-based nodes with LinuxBIOS installed. <br /> <br /> == Linux NetworX ==<br /> <br /> [http://www.linuxnetworx.com Linux NetworX], a major contributor to the coreboot project, used to sell a variety of cluster solutions with coreboot installed. LNXI was recently bought by Cray.<br /> <br /> == LUCIDA ==<br /> <br /> [http://www.lucidatech.com LUCIDA] is shipping several of their thin clients, e.g. the [http://www.lucidatech.com/product/lt2610.htm LT2610] and the [http://www.lucidatech.com/product/lt3712.htm LT3712] with coreboot, according to their website.<br /> <br /> == MikroTik ==<br /> <br /> [http://www.routerboard.com MikroTik] is offering the [http://216.239.59.104/search?q=cache:pT2IZCrEZEsJ:www.routerboard.com/pdf/RouterBOARD200SeriesA4-3-0.pdf+routerboard+linuxbios&amp;hl=de&amp;ct=clnk&amp;cd=1&amp;gl=de Routerboard 200 series] which seems to be shipped with coreboot (devices from other Routerboard series might use coreboot, too).<br /> <br /> == O.N.E. Technologies ==<br /> <br /> [http://www.onelabs.com/ O.N.E. Technologies] offers coreboot on all their x86 products and offers coreboot development services.<br /> <br /> == Sage Electronic Engineering ==<br /> <br /> [http://se-eng.com Sage Electronic Engineering] has developed the Sage SmartProbe and EDK for AMD systems development and debug. Sage also offers coreboot, Linux, and systems development services.<br /> <br /> == Silicon Mechanics ==<br /> <br /> [http://siliconmechanics.com Silicon Mechanics] will ship their [http://www.siliconmechanics.com/i7045/opteron-server.php Rackform nServ A236] with coreboot preinstalled if requested. See [http://coreboot.org/News#2008.2F04.2F04_Silicon_Mechanics_to_ship_servers_with_coreboot_preinstalled our news item from 2008/04/04]. The [http://www.siliconmechanics.com/i9226/quad-core-opteron.php Rackform nServ A255] uses the same motherboard, and is also available with coreboot.<br /> <br /> == TechNexion ==<br /> <br /> [http://www.technexion.com/ TechNexion] offers [http://www.technexion.com/index.php/amd-linux-solutions embedded mainboards with coreboot] which have 32Mbit (4Mbyte) boot flash so that a Linux kernel can easily be used as payload.<br /> <br /> == VIA ==<br /> <br /> [http://www.via.com.tw VIA] is helping the coreboot community support new EPIA mainboards and VIA chipsets with several code donations and open programming guides. With key input from VIA, coreboot will soon support over 30 Mini-ITX mainboards. These mainboards are made by VIA, Jetway, Phitronics and MSI featuring the VIA C7 CPU, CN700 and VT8237 chipset.<br /> <br /> The [http://linux.via.com.tw/support/downloadFiles.action Linux VIA Portal] aims to expand cooperation with open source communities by providing drivers, chipset programming manuals and source code for select Linux distributions to technical software developers.<br /> <br /> __NOTOC__</div>

Stuge http://www.coreboot.org/Build_from_Windows 2010-09-29T06:31:45Z

<p>Stuge: s/linux/bare metal hardware/</p> <hr /> <div>Coreboot firmware is most often built from the linux environment. Because many bios developers are more familiar with Windows than linux, it is useful to know how to build coreboot on a Windows system.<br /> <br /> ==Setup the coreboot build environment (long method)==<br /> <br /> The gnu tools needed to build coreboot have already been ported to Windows. They must be downloaded, customized, and installed. Here are the steps:<br /> <br /> #Download and install a native msys+mingw environment on your Windows computer. <br /> #Build and install cross compile versions of binutils and gcc that run on Windows and target 32-bit x86 bare metal hardware.<br /> <br /> <br /> Step 1 involves downloading and decompressing mingw and msys, both of which contain several components. See [http://mingw.org/ mingw.org] for details. You may need to gather utilities and commands from various locations in order to end up with everything needed for building coreboot projects. <br /> <br /> Step 2: Once msys+mingw is installed, download and build cross compiler versions of gcc and binutils that produce elf output for 32-bit x86. Use &lt;tt&gt;util/crossgcc/buildgcc&lt;/tt&gt; for this purpose. Use msys.bat to start the msys+mingw environment, then execute these commands. In this example, &lt;tt&gt;buildgcc&lt;/tt&gt; has been edited so that gcc 4.5.0 is built instead of gcc 4.4.4:<br /> <br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;~&lt;/font&gt;<br /> $ &lt;b&gt;mkdir /gcc450&lt;/b&gt;&lt;br&gt;<br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;~&lt;/font&gt;<br /> $ &lt;b&gt;cd /gcc450&lt;/b&gt;/&lt;br&gt;<br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;/gcc450&lt;/font&gt;<br /> $ &lt;b&gt;/d/tmp/xgcc/coreboot/util/crossgcc/buildgcc&lt;/b&gt;<br /> &lt;font color=&quot;#000080&quot;&gt;Welcome to the &lt;/font&gt;&lt;font color=&quot;#800000&quot;&gt;coresystems&lt;/font&gt;&lt;font color=&quot;#000080&quot;&gt; cross toolchain builder v1.01 (May 18th, 2010)&lt;/font&gt;&lt;br&gt;<br /> Downloading tar balls ...<br /> * gmp-5.0.1.tar.bz2 (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> * mpfr-2.4.2.tar.bz2 (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> * mpc-0.8.2.tar.gz (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> * libelf-0.8.13.tar.gz (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> * gcc-core-4.5.0.tar.bz2 (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> * binutils-2.20.1.tar.bz2 (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> * gdb-7.1.tar.bz2 (downloading)SYSTEM_WGETRC = c:/progra~1/wget/etc/wgetrc<br /> syswgetrc = D:\tmp\xgcc\msys/etc/wgetrc&lt;br&gt;<br /> Downloaded tar balls ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Unpacking and patching ...<br /> * gmp-5.0.1.tar.bz2<br /> * mpfr-2.4.2.tar.bz2<br /> * mpc-0.8.2.tar.gz<br /> * libelf-0.8.13.tar.gz<br /> * gcc-core-4.5.0.tar.bz2<br /> * binutils-2.20.1.tar.bz2<br /> * gdb-7.1.tar.bz2<br /> Unpacked and patched ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building GMP 5.0.1 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building MPFR 2.4.2 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building MPC 0.8.2 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building libelf 0.8.13 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building binutils 2.20.1 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building GCC 4.5.0 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Building GDB 7.1 ... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;<br /> Cleaning up... &lt;font color=&quot;#008000&quot;&gt;ok&lt;/font&gt;&lt;br&gt;<br /> &lt;font color=&quot;#008000&quot;&gt;You can now run your i386-elf cross toolchain from /gcc450/xgcc.&lt;/font&gt;<br /> <br /> ==Setup the coreboot build environment (shortcut method)==<br /> <br /> Getting through steps 1 and 2 from scratch takes a bit of work. As a shortcut, a coreboot-ready msys+mingw is included in the [http://notabs.org/coreboot/windows-build.htm sample project]. Decompress the sample project into any directory on your Windows computer. Note: Avoid the use of spaces in the project path and directory name. In the top level of the sample project is directory &lt;tt&gt;msys&lt;/tt&gt;. This is the complete coreboot-ready msys+mingw. The &lt;tt&gt;msys.bat&lt;/tt&gt; file in this directory starts the msys+mingw build environment. Use the standard tool names to generate output that targets the local Windows environment. To produce the i386-elf output used by coreboot, use the tools in the gcc444 or gcc450 directory. For example, &lt;tt&gt;gcc -c hello.c&lt;/tt&gt; builds a Windows object, while &lt;tt&gt;/gcc450/xgcc/bin/i386-elf-gcc hello.c&lt;/tt&gt; builds an i386-elf object.<br /> <br /> In addition to the coreboot ready msys+mingw build environment, the sample project contains:<br /> <br /> #'''coreboot''' directory. Replace this sample coreboot source code with the one you want to build.<br /> #'''seabios''' directory. This directory contains seabios source code, used to build the sample payload.<br /> #'''simnow''' directory. Helper files for testing on the AMD simnow simulator (AMD projects only).<br /> #'''tools''' directory. This directory contains needed tools that are not part of coreboot, msys, or mingw.<br /> #'''go.bat'''. This batch file sets up environment variables needed for cross compiling, and switches to the coreboot directory.<br /> <br /> ==Build the coreboot project==<br /> Here are step-by-step instructions for building a coreboot based bios on a windows machine using the shortcut build environment setup method:<br /> <br /> :1. Decompress the [http://notabs.org/coreboot/windows-build.htm sample project] into any directory. Note: Avoid the use of spaces in the project path and directory name. Use [http://7-zip.org/ 7-zip] for decompression.<br /> :2. Replace the sample &lt;tt&gt;coreboot&lt;/tt&gt; [svn://coreboot.org/coreboot/trunk source code] (rev 5775) with your own. The directory must be named &lt;tt&gt;coreboot&lt;/tt&gt;. <br /> :3. Using Windows explorer, click on &lt;tt&gt;go.bat&lt;/tt&gt; to start the build environment. It will look something like this:<br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;/D/tmp/win-build-env-002/coreboot&lt;/font&gt;<br /> $ _<br /> :4. First, build the seabios payload:<br /> $ &lt;b&gt;cd ../seabios/seabios-for-coreboot&lt;/b&gt;&lt;br&gt;<br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;/D/tmp/win-build-env-002/seabios/seabios-for-coreboot&lt;/font&gt;<br /> $ &lt;b&gt;make&lt;/b&gt;<br /> &amp;nbsp; Compiling whole program out/ccode.16.s<br /> &amp;nbsp; Compiling to assembler out/asm-offsets.s<br /> &amp;nbsp; Generating offset file out/asm-offsets.h<br /> &amp;nbsp; Compiling (16bit) out/code16.o<br /> &amp;nbsp; Compiling whole program out/ccode32flat.o<br /> src/coreboot.c: In function 'ulzma':<br /> src/coreboot.c:329:9: warning: format '%d' expects type 'int', but argument 3 has type 'long unsigned int'<br /> &amp;nbsp; Compiling whole program out/code32seg.o<br /> &amp;nbsp; Building ld scripts (version &amp;quot;0.6.1-20100928_165201-m3a78&amp;quot;)<br /> Fixed space: 0xe05b-0x10000 total: 8101 slack: 2 Percent slack: 0.0%<br /> 16bit size: 37760<br /> 32bit segmented size: 2416<br /> 32bit flat size: 50752<br /> &amp;nbsp; Linking out/rom16.o<br /> &amp;nbsp; Stripping out/rom16.strip.o<br /> &amp;nbsp; Linking out/rom32seg.o<br /> &amp;nbsp; Stripping out/rom32seg.strip.o<br /> &amp;nbsp; Linking out/rom.o<br /> &amp;nbsp; Prepping out/bios.bin<br /> Total size: 90928 Free space: 40144 Percent used: 69.4% (128KiB rom)<br /> :5. Now configure coreboot:<br /> $ &lt;b&gt;cd ../../coreboot&lt;/b&gt;&lt;br&gt;<br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;/D/tmp/win-build-env-002/coreboot&lt;/font&gt;<br /> $ &lt;b&gt;make oldconfig&lt;/b&gt;<br /> <br /> Answer the configuration questions. For this example, defaults were used for all questions except:<br /> mainboard vendor : 3 AMD<br /> mainboard model : 9 Serengeti Cheetah (Fam10)<br /> rom chip size : 3 512 KB<br /> add a payload : 2 An ELF executable payload<br /> Payload path and filename: ../seabios/seabios-for-coreboot/out/bios.bin.elf<br /> <br /> :6. At the &lt;tt&gt;$&lt;/tt&gt; prompt, type &lt;tt&gt;make&lt;/tt&gt;. After a few seconds, the build should complete:<br /> CC cpu/x86/mtrr/mtrr.o<br /> CC cpu/x86/pae/pgtbl.o<br /> AR coreboot.a<br /> CC coreboot_ram.o<br /> CC coreboot_ram<br /> CBFS coreboot.rom<br /> PAYLOAD ../seabios/seabios-for-coreboot/out/bios.bin.elf (compression: LZMA)<br /> CBFSPRINT coreboot.rom&lt;br&gt;<br /> coreboot.rom: 512 kB, bootblocksize 2390, romsize 524288, offset 0x0<br /> Alignment: 64 bytes&lt;br&gt;<br /> Name Offset Type Size<br /> fallback/romstage 0x0 stage 69016<br /> fallback/coreboot_ram 0x10e00 stage 47261<br /> fallback/payload 0x1c700 payload 45815<br /> (empty) 0x27a40 null 359458&lt;br&gt;<br /> &lt;font color=&quot;#008000&quot;&gt;Administrator@M3A78&lt;/font&gt; &lt;font color=&quot;#808000&quot;&gt;/D/tmp/win-build-env-002/coreboot&lt;/font&gt;<br /> $ _<br /> <br /> The final bios image is in file coreboot\build\coreboot.rom:<br /> &lt;pre&gt;<br /> Directory of D:\tmp\win-build-env-001\coreboot\build<br /> <br /> 09/03/10 12:23 PM 524,288 coreboot.rom<br /> &lt;/pre&gt;<br /> <br /> ==Test using simnow (optional, AMD projects only)==<br /> The AMD simnow application is a software simulation of an AMD processor and reference board. Its accuracy is impressive, allowing it to boot an unmodified bios and operating system. To test the bios, download and install the public version of AMD's [http://developer.amd.com/cpu/simnow/Pages/default.aspx simnow]. This example uses version &lt;tt&gt;simnow-win64-4.6.2pub.exe&lt;/tt&gt;, a recent public version for Windows. Note that simnow requires a 64-bit operating system. Add an environment variable named &lt;tt&gt;simnow&lt;/tt&gt; that points to the directory where simnow is installed:<br /> [[Image:winbuild-simnow-env.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> From Windows explorer, launch &lt;tt&gt;coreboot\simnow\simnow.bat&lt;/tt&gt;. This will open 3 windows:<br /> [[Image:winbuild-simnow-main.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> [[Image:winbuild-simnow-cmd.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> [[Image:winbuild-putty0.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> Optionally, setup a boot cd-rom, floppy, or hard disk image:<br /> [[Image:winbuild-drive-image.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> Now, start the simulation by clicking the 'Run Simulation' button.<br /> [[Image:winbuild-simnow-run.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> Putty will capture serial debug messages:<br /> [[Image:winbuild-putty-output.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> After a few seconds, video will appear:<br /> [[Image:winbuild-vbios-banner.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> At this point, the simulation hesitates while waiting for a keyboard response. Press a key while the mouse cursor is in the simnow window to avoid the delay. Alternatively, modify [http://www.coreboot.org/pipermail/coreboot/2010-September/060046.html keyboard.c].<br /> <br /> Next, the seabios payload executes:<br /> [[Image:winbuild-seabios.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> If the optional disk image was supplied, seabios will attempt to boot it:<br /> [[Image:winbuild-windows1.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> Looking good...<br /> [[Image:winbuild-windows2.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> Oops, some ACPI debugging is needed here...<br /> [[Image:winbuild-windows3.png|left]]<br /> &lt;br clear=&quot;all&quot;/&gt;<br /> <br /> ===Known problems with this demo===<br /> <br /> #An unwanted stack access by an AP core during cache as ram disable causes a crash. The work-around used in the sample project is to remove AP cores from the simnow model. A proper fix is being [http://www.coreboot.org/pipermail/coreboot/2010-September/060090.html developed].<br /> #PS/2 Keyboard init timeout causes boot delay ([http://www.coreboot.org/pipermail/coreboot/2010-September/060046.html workaround]).<br /> #PS/2 keyboard not working.<br /> <br /> ===Known problems with windows building===<br /> <br /> #Libncurses is not available, which prevents &lt;tt&gt;make menuconfig&lt;/tt&gt; from building. Work-around: use &lt;tt&gt;make oldconfig&lt;/tt&gt; instead.</div>

Stuge http://www.coreboot.org/Supported_Motherboards 2010-09-03T23:52:38Z

<p>Stuge: MS-6147 has socketed flash</p> <hr /> <div>{| border=&quot;0&quot; valign=&quot;top&quot; width=&quot;100%&quot;<br /> | valign=&quot;top&quot;|<br /> See the page [[Confirmed working svn revisions]] for a table of which revision to start testing with on your particular mainboard. Click on the Status column bellow to learn more info about the board.<br /> <br /> '''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards. For AMD Geode LX targets, '''coreboot v3''' might be better than coreboot v4 in some minor aspects, but most features should be ported to v4 by now.<br /> * If a mainboard is not supported by coreboot v4, try [[Supported_Motherboards#Motherboards_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Motherboards#Motherboards_supported_in_coreboot_v3|coreboot v3]] for support.<br /> * However, in general it is '''not''' recommended to use coreboot v3 &amp;mdash; this was an experimental development tree which is gradually being merged into v4.<br /> * Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.<br /> <br /> See also [[Supported Chipsets and Devices|Supported Chipsets &amp; Devices]].<br /> <br /> | valign=&quot;top&quot; align=&quot;right&quot;|<br /> <br /> '''Color Legend'''<br /> {| border=&quot;1&quot; style=&quot;font-size: smaller&quot;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | style=&quot;background:red&quot; | Motherboard is work in progress, unfinished, or on hold.<br /> |-<br /> | style=&quot;background:yellow&quot; | Motherboard mostly works, but some issues remain.<br /> |-<br /> | style=&quot;background:lime&quot; | Motherboard is fully supported.<br /> |}<br /> <br /> |}<br /> <br /> == Motherboards supported in coreboot v4 ==<br /> <br /> {| border=&quot;0&quot; style=&quot;font-size: smaller&quot;<br /> |- bgcolor=&quot;#6699ff&quot;<br /> ! align=&quot;left&quot; | Vendor<br /> ! align=&quot;left&quot; | Mainboard<br /> ! align=&quot;left&quot; | Northbridge<br /> ! align=&quot;left&quot; | Southbridge<br /> ! align=&quot;left&quot; | Super&amp;nbsp;I/O<br /> ! align=&quot;left&quot; | CPU<br /> ! align=&quot;left&quot; | Socket<br /> ! align=&quot;left&quot; | Status<br /> ! align=&quot;left&quot; | &lt;span title=&quot;ROM chip package&quot;&gt;ROM&amp;nbsp;&lt;sup&gt;35&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;ROM chip protocol&quot;&gt;P&amp;nbsp;&lt;sup&gt;36&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;ROM chip socketed?&quot;&gt;S&amp;nbsp;&lt;sup&gt;37&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;Board supported by Flashrom?&quot;&gt;F&amp;nbsp;&lt;sup&gt;38&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;Vendor Cooperation Score&quot;&gt;VCS&lt;sup&gt;4&lt;/sup&gt;&lt;/span&gt;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Desktops / Workstations'''<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Abit<br /> | [http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAME=BE6-II+V2.0&amp;fMTYPE=Slot+1 Abit BE6-II V2.0]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | ?<br /> | &amp;mdash;<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | ASRock<br /> | [http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&amp;s=939 939A785GMH/128M]<br /> | AMD&amp;nbsp;K8<br /> | AMD&amp;reg;&amp;nbsp;RS785/SB710<br /> | Winbond&amp;trade;&amp;nbsp;W83627DHG<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket 939<br /> | style=&quot;background:yellow&quot; | [[ASRock 939A785GMH-128M|WIP...]]<br /> | DIP8<br /> | SPI<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com.tw/products.aspx?l1=3&amp;l2=15&amp;l3=171&amp;l4=0&amp;model=455&amp;modelmenu=2 A8N-E]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;939<br /> | style=&quot;background:lime&quot; | [[ASUS A8N-E|OK...]]&lt;sup&gt;25&lt;/sup&gt;<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK A8N-SLI]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;939<br /> | style=&quot;background:lime&quot; | [[ASUS_A8N-SLI|OK...]]&lt;sup&gt;25&lt;/sup&gt;<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com/products.aspx?modelmenu=1&amp;model=596&amp;l1=3&amp;l2=15&amp;l3=207 A8N5X]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;939<br /> | style=&quot;background:lime&quot; | [[ASUS A8N5X|OK...]]&lt;sup&gt;25&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com.tw/products.aspx?l1=3&amp;l2=15&amp;l3=143&amp;l4=0&amp;model=576&amp;modelmenu=1 A8V-E SE]<br /> | AMD&amp;nbsp;K8<br /> | VIA&amp;nbsp;K8T890 / VT8237R<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;939<br /> | style=&quot;background:lime&quot; | [[ASUS A8V-E SE|OK...]]<br /> | PLCC<br /> | LPC<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com.tw/products.aspx?l1=3&amp;l2=15&amp;l3=143&amp;l4=0&amp;model=376&amp;modelmenu=1 A8V-E Deluxe]<br /> | AMD&amp;nbsp;K8<br /> | VIA&amp;nbsp;K8T890 / VT8237R<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;939<br /> | style=&quot;background:lime&quot; | [[ASUS A8V-E Deluxe|OK...]]<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com/products.aspx?l1=3&amp;l2=101&amp;l3=496&amp;l4=0&amp;model=1568&amp;modelmenu=1 M2A-VM]<br /> | AMD&amp;nbsp;690G<br /> | ATI&amp;nbsp;SB600<br /> | ITE&amp;trade;&amp;nbsp;IT8716F<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;AM2(+)<br /> | style=&quot;background:lime&quot; | [[ASUS M2A-VM|OK...]]<br /> | PLCC<br /> | LPC<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.asus.com/products.aspx?l1=3&amp;l2=101&amp;l3=324&amp;l4=0&amp;model=1807&amp;modelmenu=1 M2V-MX SE]<br /> | AMD&amp;nbsp;K8<br /> | VIA&amp;nbsp;K8M890 / VT8237S<br /> | ITE&amp;trade;&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:lime&quot; | [[ASUS M2V-MX SE|OK...]]<br /> | DIP8<br /> | SPI<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> &lt;!--<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | MEDION2001<br /> | &lt;span title=&quot;VIA Apollo Pro133A&quot;&gt;VIA VT82C694X&lt;/span&gt;<br /> | VIA VT82C686A<br /> | integrated<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;,&amp;nbsp;VIA&amp;nbsp;C3&amp;trade;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:red&quot; | [[ASUS MEDION2001|WIP...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:red&quot; | N<br /> | &amp;mdash;<br /> --&gt;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ MEW-AM]<br /> | Intel&amp;reg;&amp;nbsp;82810<br /> | Intel&amp;reg;&amp;nbsp;82801AA&amp;nbsp;(ICH)<br /> | SMSC&amp;reg;&amp;nbsp;LPC47B272<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[ASUS MEW-AM|OK...]]<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:red&quot; | N<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm MEW-VM]<br /> | Intel&amp;reg;&amp;nbsp;82810<br /> | Intel&amp;reg;&amp;nbsp;82801AA&amp;nbsp;(ICH)<br /> | SMSC&amp;reg;&amp;nbsp;LPC47B272<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:yellow&quot; | WIP&lt;sup&gt;28&lt;/sup&gt;<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:red&quot; | N<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ P2B]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[ASUS P2B|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ P2B-F]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[ASUS P2B-F|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ P2B-D]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | 2x Slot 1<br /> | style=&quot;background:lime&quot; | [[ASUS P2B-D|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ P2B-DS]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | 2x Slot 1<br /> | style=&quot;background:lime&quot; | [[ASUS P2B-DS|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ P2B-LS]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[ASUS P2B-LS|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | ...&lt;sup&gt;43&lt;/sup&gt;<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASUS<br /> | [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ P3B-F]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[ASUS P3B-F|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:red&quot; | N<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | A-Trend<br /> | [http://www.motherboard.cz/mb/atrend/atc6220.htm ATC-6220]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | A-Trend<br /> | [http://active-hardware.com/english/reviews/mainboard/atc6240.htm ATC-6240]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AZZA<br /> | [http://web.tiscali.it/acorp/?http://web.archive.org/web/20050426181911/http://web.tiscali.it/acorp/mobo_spec/azza/pt-6ibd/pt-6ibd.htm PT-6IBD]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[AZZA PT-6IBD|OK...]]<br /> | DIP32<br /> | Parallel<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Biostar<br /> | [http://www.motherboard.cz/mb/biostar/M6TBA.htm M6TBA]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | SMSC&amp;nbsp;FDC37M60x<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[Biostar M6TBA|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:red&quot; | N<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Compaq<br /> | Deskpro EN SFF P600<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | NSC&amp;nbsp;PC97307<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> &lt;!--<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | DFI<br /> | P2XLX<br /> | Intel&amp;reg;&amp;nbsp;440LX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:yellow&quot; | [[DFI P2XLX|WIP]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> | &amp;mdash;<br /> --&gt;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ECS<br /> | P6IWP-Fe<br /> | Intel&amp;reg;&amp;nbsp;82810<br /> | Intel&amp;reg;&amp;nbsp;82801AA&amp;nbsp;(ICH)<br /> | ITE&amp;nbsp;IT8712F<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[ECS P6IWP-Fe|OK]]<br /> | PLCC<br /> | FWH<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | GIGABYTE<br /> | [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | ITE&amp;nbsp;IT8671F<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[GIGABYTE GA-6BXC|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> <br /> |-<br /> | &amp;mdash;| GIGABYTE<br /> | [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1430 GA-6BXE]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | ITE&amp;nbsp;IT8671F<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[GIGABYTE GA-6BXE|OK...]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | GIGABYTE<br /> | [http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/ GA-2761GXDK] (Churchill)<br /> | AMD&amp;nbsp;K8<br /> | SiS761GX/SiS966<br /> | ITE&amp;nbsp;IT8716F<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / FX / X2 (?)<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:lime&quot; | [[GIGABYTE GA-2761GXDK|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |-<br /> | GIGABYTE<br /> | [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&amp;ModelName=GA-M57SLI-S4 GA-M57SLI-S4]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;MCP55<br /> | ITE&amp;nbsp;IT8716F<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:lime&quot; | [[GIGABYTE GA-M57SLI-S4|OK...]]<br /> | ?<br /> | ?<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:yellow; text-align:center&quot; | [[Gigabyte m57sli Vendor Cooperation Score|3]]<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Intel<br /> | [http://support.gateway.com/s/MOTHERBD/INTEL/2514906/2514906nv.shtml D810E2CB]<br /> | Intel&amp;reg;&amp;nbsp;82810E<br /> | Intel&amp;reg;&amp;nbsp;82801BA&amp;nbsp;(ICH2)<br /> | SMSC&amp;nbsp;LPC47M102<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[INTEL_D810E2CB|OK...]]<br /> | PLCC<br /> | FWH<br /> | N<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Intel<br /> | [http://www.intel.com/Products/Desktop/Motherboards/D945GCLF/D945GCLF-overview.htm D945GCLF]<br /> | Intel&amp;reg;&amp;nbsp;945GC<br /> | Intel&amp;reg;&amp;nbsp;ICH7<br /> | SMSC&amp;nbsp;LPC47M15x<br /> | Intel&amp;reg;&amp;nbsp;Atom&amp;trade;<br /> | Socket&amp;nbsp;441<br /> | style=&quot;background:red&quot; | WIP&lt;sup&gt;44&lt;sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Mitac<br /> | [http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/products/tyan/6513wu/6513wu.htm 6513WU]<br /> | Intel&amp;reg;&amp;nbsp;82810E<br /> | Intel&amp;reg;&amp;nbsp;82801AB&amp;nbsp;(ICH0)<br /> | SMSC&amp;nbsp;LPC47U332<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[Mitac 6513WU|OK...]]<br /> | PLCC<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://global.msi.com.tw/index.php?func=proddesc&amp;prod_no=332&amp;maincat_no=1 MS-6119]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://global.msi.com.tw/index.php?func=proddesc&amp;maincat_no=1&amp;prod_no=335 MS-6147]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/Boards/Motherboards/MicroStar/Ms6156/MS6156.htm MS-6156]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://www.msi-technology.de/index.php?func=proddesc&amp;prod_no=343&amp;maincat_no=1 MS-6178]<br /> | Intel&amp;reg;&amp;nbsp;82810<br /> | Intel&amp;reg;&amp;nbsp;82801AB&amp;nbsp;(ICH0)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[MSI MS-6178|OK...]]<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://global.msi.com.tw/index.php?func=proddesc&amp;prod_no=170&amp;maincat_no=1 MS-7135 (K8N Neo3)]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;CK804<br /> | Winbond&amp;reg;&amp;nbsp;W83627THF<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / Turion&amp;trade;&amp;nbsp;64<br /> | Socket&amp;nbsp;754<br /> | style=&quot;background:yellow&quot; | [[MSI MS-7135|WIP...]]&lt;sup&gt;29&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://global.msi.com.tw/index.php?func=proddesc&amp;prod_no=255&amp;maincat_no=1&amp;cat2_no=171 MS-7260 (K9N Neo)]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / X2<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:lime&quot; | [[MSI MS-7260|OK...]]<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:yellow&quot; | ...&lt;sup&gt;39&lt;/sup&gt;<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | NEC<br /> | [http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ PowerMate 2000]<br /> | Intel&amp;reg;&amp;nbsp;82810<br /> | Intel&amp;reg;&amp;nbsp;82801AB&amp;nbsp;(ICH0)<br /> | SMSC&amp;reg;&amp;nbsp;LPC47B27x<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[NEC PowerMate 2000|OK...]]<br /> | ?<br /> | ?<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Shuttle<br /> | [http://global.shuttle.com/product_detail.jsp?PI=89 SN25P]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / X2 / Opteron&amp;trade;&amp;nbsp;1XX<br /> | Socket&amp;nbsp;939<br /> | style=&quot;background:red&quot; | [[Shuttle SN25P|WIP...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Soyo<br /> | Soyo SY-6BA+ III<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | ITE&amp;nbsp;IT8671F<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot 1<br /> | style=&quot;background:lime&quot; | [[Soyo SY-6BA Plus III|OK]]<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Sun<br /> | [http://www.sun.com/desktop/workstation/ultra40/index.xml Ultra 40]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | SMSC&amp;reg;&amp;nbsp;LPC47B397<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami&amp;nbsp;ATX&amp;nbsp;(S1846)]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | NSC&amp;nbsp;PC87309<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot&amp;nbsp;1<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tigerk8w.html Tiger&amp;nbsp;K8W&amp;nbsp;(S2875)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8151&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8w.html Thunder&amp;nbsp;K8W&amp;nbsp;(S2885)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;,&amp;nbsp;8151&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8we.html Thunder&amp;nbsp;K8WE&amp;nbsp;(S2895)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8131&amp;trade;,&amp;nbsp;NVIDIA CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | SMSC&amp;reg;&amp;nbsp;LPC47B397<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Servers'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | ag&amp;aacute;mi<br /> | [http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-6000-series Aruma/AIS6000 series]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | Serengeti&amp;nbsp;Cheetah<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8151&amp;trade;,&amp;nbsp;8132&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | Serengeti&amp;nbsp;Cheetah<br /> | AMD&amp;nbsp;Fam10h<br /> | AMD-8111&amp;trade;,&amp;nbsp;8151&amp;trade;,&amp;nbsp;8132&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Arima<br /> | [http://web.archive.org/web/20080127024444/http://www.arima.com.tw/server/Product/ViewProduct.asp?View=HDAMA HDAMA]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | NSC PC87360<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Dell<br /> | [http://support.dell.com/support/edocs/systems/pe1850/en/index.htm PowerEdge 1850]<br /> | Intel&amp;reg;&amp;nbsp;E7520<br /> | Intel&amp;reg;&amp;nbsp;82801ER&amp;nbsp;(ICH5R)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket 604 <br /> | style=&quot;background:yellow&quot; | WIP&lt;sup&gt;2&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | HP<br /> | [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&amp;lang=en&amp;cc=us&amp;taskId=101&amp;prodSeriesId=3219755&amp;prodTypeId=15351 ProLiant DL145 G3]<br /> | AMD&amp;nbsp;K8<br /> | Broadcom&amp;nbsp;BCM5785/5780<br /> | NSC&amp;nbsp;PC87417<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | [[HP DL145 G3|OK]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | HP<br /> | e-Vectra P2706T<br /> | Intel&amp;nbsp;82810E<br /> | Intel&amp;nbsp;82801AA (ICH)<br /> | NSC&amp;nbsp;PC87364<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III&amp;nbsp;/&amp;nbsp;Celeron&amp;reg;<br /> | PGA370<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | IBM<br /> | [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&amp;lndocid=MIGR-53255 eServer 325]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | NSC PC87366<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | IBM<br /> | [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&amp;lndocid=MIGR-58655 eServer 326]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | NSC PC87366<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Intel<br /> | [http://www.intel.com/support/motherboards/server/se7520jr2/ Jarrell (SE7520JR2)]<br /> | Intel&amp;reg;&amp;nbsp;E7520<br /> | Intel&amp;reg;&amp;nbsp;82801ER&amp;nbsp;(ICH5R)<br /> | NSC PC87427<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | IWILL<br /> | [http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 DK8-HTX]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | [[IWILL DK8-HTX|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | IWILL<br /> | [http://web.archive.org/web/20060509143427/http://www.iwill.net/product_2.asp?p_id=42&amp;sp=Y DK8S2]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | IWILL<br /> | [http://web.archive.org/web/20060213163325/http://www.iwill.net/product_2.asp?p_id=28 DK8X]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx K9SD&amp;nbsp;Master-S2R&amp;nbsp;(MS-9185)]<br /> | AMD&amp;nbsp;K8<br /> | Broadcom&amp;nbsp;BCM5785/5780<br /> | NSC&amp;nbsp;PC87417<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;12&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | MSI<br /> | [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 K9SD&amp;nbsp;Master&amp;nbsp;(MS-9282)]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;15&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Newisys<br /> | [http://web.archive.org/web/20070922231423/http://www.newisys.com/core/2100e.html 2100&amp;nbsp;Server] (SUN&amp;nbsp;Fire&amp;nbsp;v20z)<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | NSC PC87360<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;7&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Nokia<br /> | [http://press.nokia.com/PR/200103/813151_5.html IP530]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;FDC37C878<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Socket 370<br /> | style=&quot;background:lime&quot; | OK<br /> | DIP32<br /> | Parallel<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | NVIDIA<br /> | l1_2pvv<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;MCP55+IO55<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;14&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]<br /> | AMD&amp;nbsp;Fam10h<br /> | NVIDIA MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm H8DME-2]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;41&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DAi-G]<br /> | Intel&amp;reg;&amp;nbsp;E7525<br /> | Intel&amp;reg;&amp;nbsp;E7525, ESB6300<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DHE-G]<br /> | Intel&amp;reg;&amp;nbsp;E7520<br /> | Intel&amp;reg;&amp;nbsp;E7520, ESB6300<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHE-G2.cfm X6DHE-G2]<br /> | Intel&amp;reg;&amp;nbsp;E7520<br /> | Intel&amp;reg;&amp;nbsp;82801ER&amp;nbsp;(ICH5R), ESB6300<br /> | NSC PC87427<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG.cfm X6DHR-iG]<br /> | Intel&amp;reg;&amp;nbsp;E7520<br /> | Intel&amp;reg;&amp;nbsp;82801ER&amp;nbsp;(ICH5R)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG2.cfm X6DHR-iG2]<br /> | Intel&amp;reg;&amp;nbsp;E7520<br /> | Intel&amp;reg;&amp;nbsp;82801ER&amp;nbsp;(ICH5R)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tigeri7501r.html Tiger&amp;nbsp;i7501R&amp;nbsp;(S2735)]<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801ER&amp;nbsp;(ICH5R)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tomcatk8s.html Tomcat&amp;nbsp;K8S&amp;nbsp;(S2850)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8s.html Thunder&amp;nbsp;K8S&amp;nbsp;(S2880)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8sr.html Thunder&amp;nbsp;K8SR&amp;nbsp;(S2881)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | [[Tyan S2881|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8spro.html Thunder&amp;nbsp;K8S&amp;nbsp;Pro&amp;nbsp;(S2882)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | [[Tyan S2882|OK...]]&lt;sup&gt;20&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8sre.html Thunder&amp;nbsp;K8SRE&amp;nbsp;(S2891)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8131&amp;trade;,&amp;nbsp;NVIDIA CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | [[Tyan S2891|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8se.html Thunder&amp;nbsp;K8SE&amp;nbsp;(S2892)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8131&amp;trade;,&amp;nbsp;NVIDIA CK804&lt;sup&gt;1&lt;/sup&gt;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | [[Tyan S2892|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder&amp;nbsp;n3600R&amp;nbsp;(S2912)]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | [[Tyan S2912|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder&amp;nbsp;n3600R&amp;nbsp;(S2912)]<br /> | AMD&amp;nbsp;Fam10h<br /> | NVIDIA&amp;nbsp;MCP55<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:lime&quot; | [[Tyan S2912|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8qs.html Thunder&amp;nbsp;K8QS&amp;nbsp;(S4880)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk8qspro.html Thunder&amp;nbsp;K8QS&amp;nbsp;Pro&amp;nbsp;(S4882)]<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8131&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;940<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Laptops'''<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Getac<br /> | [http://en.getac.com/products/P470/P470_overview.html P470]<br /> | Intel&amp;reg;&amp;nbsp;945<br /> | Intel&amp;reg;&amp;nbsp;ICH7<br /> | SMSC&amp;reg;&amp;nbsp;FDC37N972 + SIO10N268<br /> | Intel&amp;reg;&amp;nbsp;Core 2 Duo T7200<br /> | ?<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | OLPC<br /> | btest<br /> | AMD&amp;nbsp;GX&lt;sup&gt;9&lt;/sup&gt;<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | OLPC<br /> | rev_a<br /> | AMD&amp;nbsp;GX&lt;sup&gt;9&lt;/sup&gt;<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Roda<br /> | [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html RK886EX (Rocky III+)]<br /> | Intel&amp;reg;&amp;nbsp;945<br /> | Intel&amp;reg;&amp;nbsp;ICH7<br /> | SMSC&amp;reg;&amp;nbsp;LPC47N227<br /> | Intel&amp;reg;&amp;nbsp;Core 2 Duo Mobile T5500<br /> | ?<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Embedded / SBC / PC/104 / Half-size boards'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Advantech<br /> | [http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8 PCM-5820]<br /> | AMD&amp;nbsp;GX1<br /> | AMD CS5530A<br /> | Winbond&amp;reg;&amp;nbsp;W83977AF<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[Advantech PCM-5820|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | Rumba<br /> | AMD&amp;nbsp;GX&lt;sup&gt;9&lt;/sup&gt;<br /> | AMD&amp;nbsp;CS5536<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Geode&amp;trade;GX&lt;sup&gt;9&lt;/sup&gt;<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | DIGITAL-LOGIC<br /> | [http://www.digitallogic.com/english/products/datasheets/ecm855.asp smartModule855]<br /> | Intel&amp;reg;&amp;nbsp;855PM<br /> | Intel&amp;reg;&amp;nbsp;82801DBM (ICH4-M)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:red&quot; | WIP&lt;sup&gt;13&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | DIGITAL-LOGIC<br /> | [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG MSM586SEG]<br /> | integrated<br /> | integrated<br /> | integrated<br /> | AMD&amp;nbsp;&amp;Eacute;lan&amp;trade;SC520<br /> | &amp;mdash;<br /> | style=&quot;background:yellow&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | DIGITAL-LOGIC<br /> | [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV MSM800SEV]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;22&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | EagleLion<br /> | 5BCM<br /> | AMD&amp;nbsp;GX1<br /> | AMD&amp;nbsp;&amp;nbsp;CS5530<br /> | NSC&amp;nbsp;PC97317<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | IEI<br /> | [http://www.icpamerica.com/products/single_board_computers/5_25_NOVA/NOVA-4899.html NOVA-4899R]<br /> | AMD&amp;nbsp;GX1<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5530A<br /> | Winbond&amp;trade;&amp;nbsp;W83977TF<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:yellow&quot; | WIP&lt;sup&gt;17&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | IEI<br /> | [http://www.ieiworld.com/en/news_content.asp?id=erbium/projectOBJ00150613 JUKI-511P]<br /> | AMD&amp;nbsp;GX1<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5530A<br /> | Winbond&amp;trade;&amp;nbsp;W83977F<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[IEI JUKI 511P|OK...]]&lt;sup&gt;27&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | IEI<br /> | [http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX IEI PCISA-LX-800-R10]<br /> | AMD&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[IEI LX 800|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | IEI<br /> | [http://www.ieiworld.com/en/product_IPC.asp?model=ROCKY-512 ROCKY-512]<br /> | AMD&amp;nbsp;GX1<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5530A<br /> | Winbond&amp;trade;&amp;nbsp;W83977F<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[IEI ROCKY 512|OK...]]&lt;sup&gt;27&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | LiPPERT<br /> | [http://www.lippertembedded.com/cool-frontrunner.html Cool Frontrunner]<br /> | AMD&amp;nbsp;GX&lt;sup&gt;9&lt;/sup&gt;<br /> | AMD&amp;nbsp;CS5535<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX<br /> | &amp;mdash;<br /> | style=&quot;background:red&quot; | WIP&lt;sup&gt;2&lt;/sup&gt;<br /> | PLCC<br /> | FWH<br /> | style=&quot;background:lime&quot; | Y<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | LiPPERT<br /> | [http://www.lippertembedded.com/cool-spacerunner-lx800.html Cool SpaceRunner-LX]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | SOIC8<br /> | SPI<br /> | style=&quot;background:red&quot; | N<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | LiPPERT<br /> | [http://www.lippertembedded.com/cool-roadrunner-lx800.html Cool RoadRunner-LX]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | PLCC<br /> | FWH<br /> | style=&quot;background:lime&quot; | Y<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PC&amp;nbsp;Engines<br /> | [http://pcengines.ch/alix1c.htm ALIX.1C]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | Winbond&amp;reg;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[PC Engines ALIX.1C|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime; text-align:center&quot; | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | TechNexion<br /> | [http://www.technexion.com/index.php/tim-5690 TIM-5690]<br /> | AMD&amp;nbsp;M690E<br /> | ATI&amp;nbsp;SB600<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Sempron<br /> | Socket&amp;nbsp;AM2(+)<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | TechNexion<br /> | [http://www.technexion.com/index.php/tim-8690 TIM-8690]<br /> | AMD&amp;nbsp;M690E<br /> | ATI&amp;nbsp;SB600<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / X2<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Traverse Technologies<br /> | [http://www.traverse.com.au/productview.php?product_id=117 Geos]<br /> | AMD&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | TS&lt;sup&gt;31&lt;/sup&gt;<br /> | [http://www.embeddedarm.com/epc/ts5300-spec-h.html TS-5300]<br /> | integrated<br /> | integrated<br /> | integrated<br /> | AMD&amp;nbsp;&amp;Eacute;lan&amp;trade;SC520<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Mini-ITX / Micro-ITX / Nano-ITX'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Jetway<br /> | [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R(P)<br /> | Fintek&amp;nbsp;F71805F<br /> | VIA&amp;nbsp;C7&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[Jetway J7F2|OK...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Jetway<br /> | [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&amp;proname=J7F4K1G2E J7F4K1G2E]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R(P)<br /> | Fintek&amp;nbsp;F71805F<br /> | VIA&amp;nbsp;C7&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[Jetway J7F4K1G2E|OK...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Jetway<br /> | [http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&amp;proname=J7F4K1G5D J7F4K1G5D]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R(P)<br /> | Fintek&amp;nbsp;F71805F<br /> | VIA&amp;nbsp;C7&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[Jetway J7F4K1G5D|OK...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Kontron<br /> | [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]<br /> | Intel&amp;reg;&amp;nbsp;945<br /> | Intel&amp;reg;&amp;nbsp;ICH7<br /> | 2x&amp;nbsp;Winbond&amp;reg;&amp;nbsp;W83627THG<br /> | Intel&amp;reg;&amp;nbsp;Core&amp;trade;&amp;nbsp;2&amp;nbsp;Duo&amp;nbsp;Mobile,&lt;br /&gt;Core&amp;trade;&amp;nbsp;Duo/Solo, Celeron&amp;reg;&amp;nbsp;M<br /> | mPGA478<br /> | style=&quot;background:lime&quot; | [[Kontron 986LCD-M mITX|OK...]]<br /> | PLCC<br /> | FWH<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Kontron<br /> | [http://us.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx.html KT690/mITX]<br /> | AMD&amp;nbsp;M690T<br /> | ATI&amp;nbsp;SB600<br /> | Winbond&amp;trade;&amp;nbsp;W83627DHG<br /> | AMD&amp;nbsp;Turion64&amp;trade;&amp;nbsp;dual&amp;nbsp;core / AMD&amp;nbsp;Sempron<br /> | Socket&amp;nbsp;AM2(+)<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | MSI<br /> | [http://global.msi.com.tw/index.php?func=proddesc&amp;prod_no=1054&amp;maincat_no=388# Fuzzy CN700]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R(P)<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | VIA&amp;nbsp;C7&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:yellow&quot; | [[MSI FUZZY CN700|WIP...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]<br /> | VIA&amp;nbsp;VT8601<br /> | VIA&amp;nbsp;VT8231<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | VIA&amp;nbsp;C3&amp;trade;,&amp;nbsp;VIA&amp;nbsp;EDEN&amp;trade;<br /> | &amp;mdash;<br /> | style=&quot;background:yellow&quot; | [[EPIA|WIP...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]<br /> | VIA&amp;nbsp;VT8623<br /> | VIA&amp;nbsp;VT8235<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C3&amp;trade;,&amp;nbsp;VIA&amp;nbsp;EDEN&amp;trade;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[VIA EPIA-M|OK...]]&lt;sup&gt;10&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | EPIA-M700<br /> | VIA&amp;nbsp;VX800<br /> | VIA&amp;nbsp;VX800<br /> | Winbond&amp;nbsp;W83697HF/F/HG<br /> | ?<br /> | ?<br /> | style=&quot;background:red&quot; | [[VIA EPIA-M700|WIP...]]<br /> | SOIC8<br /> | SPI<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=202 EPIA-MII]<br /> | VIA&amp;nbsp;VT8623<br /> | VIA&amp;nbsp;VT8235,&amp;nbsp;Ricoh&amp;nbsp;RL5C476<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C3&amp;trade;,&amp;nbsp;VIA&amp;nbsp;EDEN&amp;trade;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[VIA EPIA-MII|OK...]]&lt;sup&gt;8&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=301 EPIA-ML]<br /> | VIA&amp;nbsp;VT8623<br /> | VIA&amp;nbsp;VT8235<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C3&amp;trade;,&amp;nbsp;VIA&amp;nbsp;EDEN&amp;trade;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | [[VIA EPIA-ML|OK...]]&lt;sup&gt;10&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN10000EG]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[VIA EPIA-CN|OK...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN13000G]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[VIA EPIA-CN|OK...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN12000EG]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:yellow&quot; | [[VIA EPIA-EN|WIP...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN15000G]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | Winbond&amp;trade;&amp;nbsp;W83627EHG<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:yellow&quot; | [[VIA EPIA-EN|WIP...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=473 EPIA-LN10000EG/EAG]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[VIA EPIA-LN|OK...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7400]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:yellow&quot; | [[VIA NAB7400|WIP...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7410]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:yellow&quot; | [[VIA NAB7410|WIP...]]&lt;sup&gt;30&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.idot.com.tw/en/products/mb-pc2500e/ pc2500e]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | ITE&amp;nbsp;IT8716F<br /> | VIA&amp;nbsp;C7&amp;trade;, VIA&amp;nbsp;Esther&amp;nbsp;C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:lime&quot; | [[VIA pc2500e|OK...]]<br /> | PLCC<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | [http://www.idotpc.com/TheStore/pc/viewCategories.asp?idCategory=56 EPIA-N]<br /> | VIA&amp;nbsp;CN400<br /> | VIA&amp;nbsp;VT8237R<br /> | Winbond&amp;nbsp;W83697HF<br /> | ?<br /> | ?<br /> | style=&quot;background:yellow&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Set-top-boxes / Thin clients'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Artec&amp;nbsp;Group<br /> | [http://www.artecgroup.com/thincan/index.php?option=com_content&amp;task=blogcategory&amp;id=15&amp;Itemid=34 DBE61]<br /> | AMD&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:red&quot; | Broken&lt;sup&gt;40&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASI<br /> | MB-5BLGP&lt;sup&gt;32&lt;/sup&gt;<br /> | AMD&amp;nbsp;GX1<br /> | AMD CS5530<br /> | NSC&amp;nbsp;PC87351<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[ASI MB-5BLGP|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | ASI<br /> | [http://www.hojerteknik.com/winnet.htm MB-5BMLP]&lt;sup&gt;33&lt;/sup&gt;<br /> | AMD&amp;nbsp;GX1<br /> | AMD CS5530<br /> | NSC&amp;nbsp;PC87351<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[ASI MB-5BLMP|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AXUS<br /> | [http://www.keyton.co.jp/products/UAXT/TC-320.html TC320]<br /> | AMD&amp;nbsp;GX1<br /> | AMD CS5530A<br /> | NSC&amp;nbsp;PC97317<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[AXUS TC320|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | BCOM<br /> | [http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_compact.htm WinNET100]&lt;sup&gt;34&lt;/sup&gt;<br /> | AMD&amp;nbsp;GX1<br /> | AMD CS5530A<br /> | NSC&amp;nbsp;PC97317<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[BCOM WINNET100|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | BCOM<br /> | WinNET P680<br /> | VIA CN700<br /> | VIA VT8237R Plus<br /> | Winbond&amp;trade; W83697HG<br /> | Via C7&amp;trade;<br /> | &amp;mdash;<br /> | style = &quot;background:yellow&quot; | [[BCOM WinNET P680|WIP...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Linutop<br /> | [http://linutop.com/ Linutop]<br /> | AMD&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;19&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | RCA<br /> | [http://www.settoplinux.org/index.php?title=RCA_RM4100 RM4100]<br /> | Intel&amp;reg;&amp;nbsp;82830M<br /> | Intel&amp;reg;&amp;nbsp;82801DB&amp;nbsp;(ICH4)<br /> | SMSC&amp;reg;&amp;nbsp;LPC47M192<br /> | Intel&amp;reg;&amp;nbsp;Mobile&amp;nbsp;Celeron<br /> | Socket&amp;nbsp;479<br /> | style=&quot;background:lime&quot; | [[RCA RM4100|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | TeleVideo<br /> | [http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm TC7020]<br /> | AMD&amp;nbsp;GX1<br /> | AMD&amp;nbsp;CS5530A<br /> | NSC&amp;nbsp;PC97317<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[TeleVideo TC7020|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Thomson<br /> | [http://www.settoplinux.org/index.php?title=Thomson_IP1000 IP1000]<br /> | Intel&amp;reg;&amp;nbsp;82830M<br /> | Intel&amp;reg;&amp;nbsp;82801DB&amp;nbsp;(ICH4)<br /> | SMSC&amp;reg;&amp;nbsp;LPC47M192<br /> | Low Voltage Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III<br /> | Socket&amp;nbsp;479<br /> | style=&quot;background:lime&quot; | [[Thomson IP1000|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Wyse<br /> | [http://www.wyse.de/products/hardware/thinclients/S50/index.asp S50]<br /> | AMD&amp;nbsp;GX2<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;GX2<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | PLCC<br /> | LPC<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Devel/Eval Boards'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AMD<br /> | [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800]&amp;nbsp;(Salsa)<br /> | AMD&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AMD<br /> | Norwich<br /> | AMD&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;21&lt;/sup&gt;<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AMD<br /> | [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T]&amp;nbsp;(Herring)<br /> | AMD&amp;nbsp;K8<br /> | AMD&amp;nbsp;RS690/SB600<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Turion&amp;trade;&amp;nbsp;/ X2 &amp;nbsp;Sempron&amp;trade;<br /> | Socket&amp;nbsp;S1G1<br /> | style=&quot;background:lime&quot; | [[AMD DBM690T|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AMD<br /> | Pistachio<br /> | AMD&amp;nbsp;K8<br /> | AMD&amp;nbsp;RS690/SB600<br /> | &amp;mdash;<br /> | ?<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AMD<br /> | Tilapia<br /> | AMD&amp;nbsp;Fam10h<br /> | AMD&amp;nbsp;RS780/SB700<br /> | ITE&amp;nbsp;IT8718F<br /> | ?<br /> | Socket&amp;nbsp;AM3<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Broadcom<br /> | Blast<br /> | AMD&amp;nbsp;K8<br /> | Broadcom&amp;nbsp;BCM5785/5780<br /> | NSC&amp;nbsp;PC87417<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Intel<br /> | 3100 devkit (Mt. Arvon)<br /> | Intel&amp;reg;&amp;nbsp;3100<br /> | Intel&amp;reg;&amp;nbsp;3100<br /> | Intel&amp;reg;&amp;nbsp;3100<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;M<br /> | Socket 479<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Intel<br /> | EagleHeights<br /> | Intel&amp;reg;&amp;nbsp;3100<br /> | Intel&amp;reg;&amp;nbsp;3100<br /> | Intel&amp;reg;&amp;nbsp;3100<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;M<br /> | ?<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Intel<br /> | EP80579 devkit (Truxton)<br /> | Intel&amp;reg;&amp;nbsp;EP80579<br /> | Intel&amp;reg;&amp;nbsp;EP80579<br /> | Intel&amp;reg;&amp;nbsp;EP80579<br /> | Intel&amp;reg;&amp;nbsp;EP80579<br /> | Intel&amp;reg;&amp;nbsp;EP80579<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Intel<br /> | XE7501devkit<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S)<br /> | SMSC&amp;reg; LPC47B272<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | VIA<br /> | VT8454c<br /> | VIA&amp;nbsp;CX700<br /> | integrated<br /> | integrated<br /> | VIA&amp;nbsp;C7&amp;trade;<br /> | ?<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;13&quot; | '''Miscellaneous'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Emulation<br /> | [http://fabrice.bellard.free.fr/qemu/ QEMU x86]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | &amp;mdash;<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III (?)<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[QEMU Build Tutorial|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> <br /> |}<br /> <br /> &lt;small&gt;<br /> &lt;sup&gt;1&lt;/sup&gt; NVIDIA nForce&amp;trade; Professional 2200 (CK804).&lt;br /&gt;<br /> &lt;sup&gt;2&lt;/sup&gt; Work in progress.&lt;br /&gt;<br /> &lt;sup&gt;3&lt;/sup&gt; This was an AMD64 reference board.&lt;br /&gt;<br /> &lt;sup&gt;4&lt;/sup&gt; Vendor Cooperation Score.&lt;br /&gt;<br /> &lt;sup&gt;7&lt;/sup&gt; LSI1030 SCSI controller can not be used to boot the machine.&lt;br /&gt;<br /> &lt;sup&gt;8&lt;/sup&gt; Use the ''epia-m'' code for now. The on-board PCMCIA and CF sockets work. coreboot can boot from CF (the stock BIOS can't). [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016448.html Some problems] remain, though.&lt;br /&gt;<br /> &lt;sup&gt;9&lt;/sup&gt; The AMD GX (internally known as GX2 for some time) is actually the successor to the GX1.&lt;br /&gt;<br /> &lt;sup&gt;10&lt;/sup&gt; Use the ''epia-m'' code for now (plus [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016423.html a few hacks], e.g. disable Firewire/CF slot,<br /> because they're not present on the board).&lt;br /&gt;<br /> &lt;sup&gt;12&lt;/sup&gt; Except for some [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016463.html possible problems with SATA2 ports], everything should work.&lt;br /&gt;<br /> &lt;sup&gt;13&lt;/sup&gt; See also http://www.linuxbios.org/pipermail/linuxbios/2006-November/017065.html.&lt;br /&gt;<br /> &lt;sup&gt;14&lt;/sup&gt; These boards ''should'' work fine, but we have no confirmed reports on the [[Mailinglist|mailing list]] so far, so we cannot tell for sure.&lt;br /&gt;<br /> &lt;sup&gt;15&lt;/sup&gt; See http://www.openbios.org/pipermail/linuxbios/2007-February/018299.html.&lt;br /&gt;<br /> &lt;sup&gt;17&lt;/sup&gt; Seems to be [http://www.linuxbios.org/pipermail/linuxbios/2006-November/016651.html partially working], specifically eth0, eth2, the PCI slot, the USB ports, and the serial console [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021226.html are working]. Other parts are not yet finished.&lt;br /&gt;<br /> &lt;sup&gt;19&lt;/sup&gt; The Linutop does not ship with coreboot, but [http://linutop.com/wiki/index.php/Developers#Upgrading_to_LinuxBIOS the code should work].&lt;br /&gt;<br /> &lt;sup&gt;20&lt;/sup&gt; Fan-control doesn't work yet.&lt;br /&gt;<br /> &lt;sup&gt;21&lt;/sup&gt; This is ''the'' AMD Geode LX reference board and coreboot reference implementation on the AMD Geode LX, contributed and maintained by AMD engineers.&lt;br /&gt;<br /> &lt;sup&gt;22&lt;/sup&gt; The board can boot a Linux kernel currently, but there's [http://www.linuxbios.org/pipermail/linuxbios/2007-May/020770.html no VGA support, yet].&lt;br /&gt;<br /> &lt;sup&gt;25&lt;/sup&gt; [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021280.html Works fine], only smaller issues remain to be fixed. A [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021308.html list of known issues] is available.&lt;br /&gt;<br /> &lt;sup&gt;27&lt;/sup&gt; The JUKI-511P and ROCKY-512 both use the same code and target (targets/iei/juki-511p). Thus, both [http://www.linuxbios.org/pipermail/linuxbios/2007-June/021862.html support the same features and have the same limitations]: IDE, USB, ethernet, serial, keyboard and sound work, but there are problems booting from IDE1 ([http://www.linuxbios.org/pipermail/linuxbios/2007-June/021996.html this patch] may help), and VGA video doesn't work, yet.&lt;br /&gt;<br /> &lt;sup&gt;28&lt;/sup&gt; Partially supported, almost boots a Linux kernel. [http://www.linuxbios.org/pipermail/linuxbios/2007-June/022217.html Some issues] still remain to be fixed, though.&lt;br /&gt;<br /> &lt;sup&gt;29&lt;/sup&gt; See also http://www.coreboot.org/pipermail/coreboot/2008-February/031102.html.&lt;br /&gt;<br /> &lt;sup&gt;30&lt;/sup&gt; The irq table in CN is from VIA. You may need to run getpir to generate your own irq table.&lt;br /&gt;<br /> &lt;sup&gt;31&lt;/sup&gt; Technologic Systems.&lt;br /&gt;<br /> &lt;sup&gt;32&lt;/sup&gt; Used in the Neoware Eon 4000s thin client.&lt;br /&gt;<br /> &lt;sup&gt;33&lt;/sup&gt; Used in the IGEL WinNET III thin client.&lt;br /&gt;<br /> &lt;sup&gt;34&lt;/sup&gt; Used in the IGEL-316 thin client.&lt;br /&gt;<br /> &lt;sup&gt;35&lt;/sup&gt; ROM chip package (PLCC, DIP32, DIP8, SOIC8).&lt;br /&gt;<br /> &lt;sup&gt;36&lt;/sup&gt; ROM chip protocol/type (parallel flash, LPC, FWH, SPI).&lt;br /&gt;<br /> &lt;sup&gt;37&lt;/sup&gt; ROM chip socketed (Y/N)?&lt;br /&gt;<br /> &lt;sup&gt;38&lt;/sup&gt; Board supported by [[Flashrom]] (Y/N)?&lt;br /&gt;<br /> &lt;sup&gt;39&lt;/sup&gt; Interestingly [[flashrom]] does not work when the vendor BIOS is booted, but it does work flawlessly when the machine is booted with coreboot.&lt;br /&gt;<br /> &lt;sup&gt;40&lt;/sup&gt; Broken v4 port, try the v3 port instead. The v4 version will be fixed at some point.&lt;br /&gt;<br /> &lt;sup&gt;41&lt;/sup&gt; RAM must be matched exactly in each bank.&lt;br /&gt;<br /> &lt;sup&gt;43&lt;/sup&gt; Works. Until flashrom officially supports this board, force it with ASUS P2B-F as the mainboard target.&lt;br /&gt;<br /> &lt;sup&gt;44&lt;/sup&gt; Boots MS-DOS fine using SeaBIOS, might boot Linux.&lt;br /&gt;<br /> &lt;/small&gt;<br /> <br /> == Motherboards supported in coreboot v3 ==<br /> <br /> &lt;div style=&quot;color: #ff0000&quot;&gt;coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 have been integrated in what now became v4.&lt;/div&gt;<br /> <br /> {| border=&quot;0&quot; style=&quot;font-size: smaller&quot;<br /> |- bgcolor=&quot;#6699ff&quot;<br /> ! align=&quot;left&quot; | Vendor<br /> ! align=&quot;left&quot; | Mainboard<br /> ! align=&quot;left&quot; | Northbridge<br /> ! align=&quot;left&quot; | Southbridge<br /> ! align=&quot;left&quot; | Super&amp;nbsp;I/O<br /> ! align=&quot;left&quot; | CPU<br /> ! align=&quot;left&quot; | Socket<br /> ! align=&quot;left&quot; | Status<br /> ! align=&quot;left&quot; | &lt;span title=&quot;ROM chip package&quot;&gt;ROM&amp;nbsp;&lt;sup&gt;1&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;ROM chip protocol&quot;&gt;P&amp;nbsp;&lt;sup&gt;2&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;ROM chip socketed?&quot;&gt;S&amp;nbsp;&lt;sup&gt;3&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;Board supported by Flashrom?&quot;&gt;F&amp;nbsp;&lt;sup&gt;4&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;Vendor Cooperation Score&quot;&gt;VCS&lt;sup&gt;5&lt;/sup&gt;&lt;/span&gt;<br /> ! align=&quot;left&quot; | &lt;span title=&quot;v3&quot;&gt;v3 only&amp;nbsp;&lt;sup&gt;7&lt;/sup&gt;&lt;/span&gt;<br /> <br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Advanced Digital Logic<br /> | [http://www.adlogic-pc104.com/products/cpu/datasheets/MSM800SEV_SEL.pdf MSM800SEV]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:orange&quot; | WIP<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | DB800<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | ?<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T]&amp;nbsp;(Herring)<br /> | AMD&amp;nbsp;K8 <br /> | AMD&amp;nbsp;RS690/SB600<br /> | ITE&amp;nbsp;IT8712F<br /> | AMD&amp;nbsp;Turion&amp;trade;&amp;nbsp;/ X2 &amp;nbsp;Sempron&amp;trade;<br /> | Socket&amp;nbsp;S1G1<br /> | style=&quot;background:orange&quot; | WIP<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | Norwich<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | AMD<br /> | Serengeti&amp;nbsp;Cheetah<br /> | AMD&amp;nbsp;K8<br /> | AMD-8111&amp;trade;,&amp;nbsp;8151&amp;trade;,&amp;nbsp;8132&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Opteron&amp;trade;<br /> | Socket&amp;nbsp;F<br /> | style=&quot;background:orange&quot; | WIP<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | AMP<br /> | TinyGX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | ITE&amp;nbsp;IT8716F<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:orange&quot; | WIP<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:red&quot; | Y<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Artec&amp;nbsp;Group<br /> | [http://www.artecgroup.com/thincan/index.php?option=com_content&amp;task=blogcategory&amp;id=15&amp;Itemid=34 DBE61]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:orange&quot; | WIP<br /> | TSOP32<br /> | LPC<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Artec&amp;nbsp;Group<br /> | [http://www.artecgroup.com/thincan/index.php?option=com_content&amp;task=blogcategory&amp;id=15&amp;Itemid=34 DBE62]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[Artec Group DBE62|OK...]]<br /> | TSOP32<br /> | FWH<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:lime; text-align:center&quot; | [[Artec Group DBE62 Vendor Cooperation Score|4]]<br /> | style=&quot;background:red&quot; | Y<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Emulation<br /> | [http://fabrice.bellard.free.fr/qemu/ QEMU x86]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | &amp;mdash;<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III (?)<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | OK<br /> | &amp;mdash;<br /> | ?<br /> | &amp;mdash;<br /> | &amp;mdash;<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | GIGABYTE<br /> | [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&amp;ModelName=GA-M57SLI-S4 GA-M57SLI-S4]<br /> | AMD&amp;nbsp;K8<br /> | NVIDIA&amp;nbsp;MCP55<br /> | ITE&amp;nbsp;IT8716F<br /> | AMD&amp;nbsp;Sempron&amp;trade; / Athlon&amp;trade;&amp;nbsp;64 / FX / X2<br /> | Socket&amp;nbsp;AM2<br /> | style=&quot;background:orange&quot; | WIP<br /> | ...&lt;sup&gt;6&lt;/sup&gt;<br /> | ?<br /> | style=&quot;background:red&quot; | N<br /> | style=&quot;background:lime&quot; | Y<br /> | style=&quot;background:yellow; text-align:center&quot; | [[Gigabyte m57sli Vendor Cooperation Score|3]]<br /> | style=&quot;background:lime&quot; | N<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Jetway<br /> | [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R(P)<br /> | Fintek&amp;nbsp;F71805F<br /> | VIA&amp;nbsp;C7&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:orange&quot; | WIP<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:red&quot; | Y<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Kontron<br /> | [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]<br /> | Intel&amp;reg;&amp;nbsp;945<br /> | Intel&amp;reg;&amp;nbsp;ICH7<br /> | 2x&amp;nbsp;Winbond&amp;reg;&amp;nbsp;W83627THG<br /> | Intel&amp;reg;&amp;nbsp;Core&amp;trade;&amp;nbsp;2&amp;nbsp;Duo&amp;nbsp;Mobile,&lt;br /&gt;Core&amp;trade;&amp;nbsp;Duo/Solo, Celeron&amp;reg;&amp;nbsp;M<br /> | mPGA478<br /> | style=&quot;background:orange&quot; | WIP<br /> | PLCC<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | PC&amp;nbsp;Engines<br /> | [http://pcengines.ch/alix1c.htm ALIX.1C]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | Winbond&amp;reg;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[PC Engines ALIX.1C|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:lime; text-align:center&quot; | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]<br /> | style=&quot;background:lime&quot; | N<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | PC&amp;nbsp;Engines<br /> | [http://pcengines.ch/alix2c3.htm ALIX.2C3]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[PC Engines ALIX.2CX|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:red&quot; | Y<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | PC&amp;nbsp;Engines<br /> | [http://pcengines.ch/alix2c2.htm ALIX.2C2]<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;CS5536<br /> | &amp;mdash;<br /> | AMD&amp;nbsp;Geode&amp;trade;&amp;nbsp;LX<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | [[PC Engines ALIX.2CX|OK...]]<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:red&quot; | Y<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | VIA<br /> | EPIA-CN<br /> | VIA&amp;nbsp;CN700<br /> | VIA&amp;nbsp;VT8237R<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C7&amp;trade;,&amp;nbsp;VIA&amp;nbsp; Esther C5J&amp;trade;<br /> | NanoBGA2<br /> | style=&quot;background:orange&quot; | WIP<br /> | ?<br /> | ?<br /> | ?<br /> | ?<br /> | &amp;mdash;<br /> | style=&quot;background:lime&quot; | N<br /> <br /> |}<br /> <br /> &lt;small&gt;<br /> &lt;sup&gt;1&lt;/sup&gt; ROM chip package (PLCC, DIP32, DIP8, SOIC8).&lt;br /&gt;<br /> &lt;sup&gt;2&lt;/sup&gt; ROM chip protocol/type (parallel flash, LPC, FWH, SPI).&lt;br /&gt;<br /> &lt;sup&gt;3&lt;/sup&gt; ROM chip socketed (Y/N)?&lt;br /&gt;<br /> &lt;sup&gt;4&lt;/sup&gt; Board supported by [[Flashrom]] (Y/N)?&lt;br /&gt;<br /> &lt;sup&gt;5&lt;/sup&gt; Vendor Cooperation Score.&lt;br /&gt;<br /> &lt;sup&gt;6&lt;/sup&gt; There are two versions of the [[GIGABYTE GA-M57SLI-S4]], one with a soldered PLCC chip, one with a soldered SOIC8 chip.&lt;br /&gt;<br /> &lt;sup&gt;7&lt;/sup&gt; Board is only available in v3, not yet in v4?&lt;br /&gt;<br /> <br /> &lt;/small&gt;<br /> <br /> == Motherboards supported in coreboot v1 ==<br /> <br /> Not all motherboards have been ported from coreboot v1 to coreboot v4, yet (check the CBv4 field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br /> <br /> {| border=&quot;0&quot; style=&quot;font-size: smaller&quot;<br /> |- bgcolor=&quot;#6699dd&quot;<br /> ! align=&quot;left&quot; | Vendor<br /> ! align=&quot;left&quot; | Mainboard<br /> ! align=&quot;left&quot; | Northbridge<br /> ! align=&quot;left&quot; | Southbridge<br /> ! align=&quot;left&quot; | Super&amp;nbsp;I/O<br /> ! align=&quot;left&quot; | CPU<br /> ! align=&quot;left&quot; | Socket<br /> ! align=&quot;left&quot; | Status<br /> ! align=&quot;left&quot; | CBv4?<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;9&quot; | '''Desktops / Workstations'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | ASUS<br /> | A7M<br /> | AMD&amp;nbsp;AMD76x<br /> | VIA&amp;nbsp;VT82C686<br /> | VIA&amp;nbsp;VT82C686<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | ASUS<br /> | [http://www.ciao.co.uk/ASUS_ALi_Chipset_CUA__5410161 CUA]<br /> | Acer&amp;nbsp;M1631&amp;nbsp;(ALADDiN&amp;nbsp;TNT2)<br /> | Acer&amp;nbsp;M1535<br /> | Acer&amp;nbsp;M1535<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | ASUS<br /> | [http://www.dealtime.com/xPF-ASUS-ASUS-Intel-Socket7-PNP586-Motherboard TX97-LE]<br /> | Intel&amp;reg;&amp;nbsp;430TX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | SMC&amp;nbsp;FDC37C67X<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;, Pentium&amp;reg;&amp;nbsp;MMX, AMD&amp;nbsp;K5<br /> | Socket&amp;nbsp;7<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Bitworks<br /> | IMS<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | NSC&amp;nbsp;PC87351<br /> | ?<br /> | Slot1&amp;nbsp;1<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Chaintech<br /> | [http://www.xbitlabs.com/articles/mainboards/display/chaintech-7kjd.html CT-7KJD]<br /> | AMD-761&amp;trade;<br /> | VIA&amp;nbsp;VT8231<br /> | VIA&amp;nbsp;VT8231<br /> | AMD&amp;nbsp;Athlon&amp;trade; / Duron&amp;trade;<br /> | Socket&amp;nbsp;462<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Elitegroup (ECS)<br /> | [http://www.ecsusa.com/products/k7sem_v3.html K7SEM]<br /> | SiS730S<br /> | SiS730S<br /> | SiS730S<br /> | AMD&amp;nbsp;Athlon&amp;trade; / Athlon&amp;trade;&amp;nbsp;XP / Duron&amp;trade;<br /> | Socket&amp;nbsp;462<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Elitegroup (ECS)<br /> | [http://www.ecsusa.com/downloads/manual_p6s.html P6STP-FL]<br /> | SiS630<br /> | SiS630<br /> | SiS950<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;III, Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | GIGABYTE<br /> | [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | ITE&amp;nbsp;IT8671F<br /> | Intel&amp;reg; Pentium&amp;reg;&amp;nbsp;II/III, Celeron&amp;reg;<br /> | Slot1&amp;nbsp;1<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:lime&quot; | Yes<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | GIGABYTE<br /> | GA-6OXE<br /> | Intel&amp;reg;&amp;nbsp;815EP<br /> | Intel&amp;reg;&amp;nbsp;82801<br /> | ITE&amp;nbsp;IT8712F<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Leadtek<br /> | [http://web.archive.org/web/20000616073856/http://www.leadtek.com.tw/e6300MAX.htm WinFast 6300MAX]<br /> | SiS630<br /> | SiS630<br /> | SiS950<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;III, Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Matsonic<br /> | [http://web.archive.org/web/20000619011053/www.matsonic.com/index_2.htm MS7308E]<br /> | SiS630<br /> | SiS630<br /> | SiS950<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;III, Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;3&lt;/sup&gt;<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PCCHIPS<br /> | [http://www.pcchipsusa.com/prod-m754lmr.asp M754LMR]<br /> | Acer&amp;nbsp;M1631<br /> | Acer&amp;nbsp;M1535<br /> | Acer&amp;nbsp;M1535<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;III, Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PCCHIPS<br /> | [http://www.pcchipsusa.com/prod-m758mr.asp M758LMR(+)]<br /> | SiS630<br /> | SiS630<br /> | SiS950<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;III, Celeron&amp;reg;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PCCHIPS<br /> | [http://www.pcchipsusa.com/prod-m787cl%2B.asp M787CL+]<br /> | SiS630<br /> | SiS630<br /> | SiS950<br /> | VIA&amp;nbsp;C3&amp;trade;<br /> | Socket&amp;nbsp;370<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PCCHIPS<br /> | [http://www.pcchipsusa.com/prod-m810lmr.asp M810LMR]<br /> | SiS670<br /> | SiS670<br /> | SiS950<br /> | AMD&amp;nbsp;Athlon&amp;trade; / Duron&amp;trade;<br /> | Socket&amp;nbsp;462<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PCCHIPS<br /> | M810LR<br /> | SiS670<br /> | SiS670<br /> | SiS950<br /> | AMD&amp;nbsp;Athlon&amp;trade; / Duron&amp;trade;<br /> | Socket&amp;nbsp;462<br /> | style=&quot;background:lime&quot; | [[PCCHIPS M810LR|???]]<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | PCCHIPS<br /> | [http://www.pcchipsusa.com/prod-m830lmr.asp M830L(M)R]<br /> | SiS735<br /> | SiS735<br /> | SiS950<br /> | AMD&amp;nbsp;Athlon&amp;trade; / Athlon&amp;trade;&amp;nbsp;XP / Duron&amp;trade;<br /> | Socket&amp;nbsp;462<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon/860/P4DC6.cfm P4DC6]<br /> | Intel&amp;reg;&amp;nbsp;82860<br /> | Intel&amp;reg;&amp;nbsp;82801,&amp;nbsp;82806<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | P4DC6P<br /> | Intel&amp;reg;&amp;nbsp;82860<br /> | Intel&amp;reg;&amp;nbsp;82801,&amp;nbsp;82806<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | TigerMPX<br /> | AMD-76x&amp;trade;<br /> | AMD-768&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | guiness<br /> | AMD-76x&amp;trade;<br /> | AMD-766&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tiger133.html Tiger&amp;nbsp;133&amp;nbsp;(S1834)]<br /> | VIA&amp;nbsp;VT8601<br /> | ?<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;II/III<br /> | Slot&amp;nbsp;1<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami&amp;nbsp;ATX&amp;nbsp;(S1846)]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | NSC&amp;nbsp;PC87309<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;II/III,&amp;nbsp;Celeron&amp;reg;<br /> | Slot&amp;nbsp;1<br /> | style=&quot;background:lime&quot; | OK<br /> | style=&quot;background:lime&quot; | Yes<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tigermpx.html Tiger&amp;nbsp;MPX&amp;nbsp;(S2466)]<br /> | AMD-762&amp;trade;<br /> | AMD-768&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Athlon&amp;reg;&amp;nbsp;MP<br /> | Socket 462<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/thunderk7xpro.html Thunder&amp;nbsp;K7X&amp;nbsp;Pro&amp;nbsp;(S2469)]<br /> | AMD-762&amp;trade;<br /> | AMD-768&amp;trade;<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | AMD&amp;nbsp;Athlon&amp;reg;&amp;nbsp;MP<br /> | Socket 462<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;9&quot; | '''Servers'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | ASUS<br /> | [http://www.asus.de/products.aspx?l1=9&amp;l2=39&amp;l3=103&amp;model=113&amp;modelmenu=1 PU-DLS]<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S)<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Compaq<br /> | DS10<br /> | Alpha&amp;nbsp;Tsunami<br /> | Acer&amp;nbsp;M1543<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Intel<br /> | clearwater<br /> | Intel&amp;reg;&amp;nbsp;E7500<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Intel<br /> | clearwater533<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | RLX<br /> | [http://web.archive.org/web/20040413125915/rlxtechnologies.com/index.php?se=servers&amp;id=3 ServerBlade 800i]<br /> | Micron&amp;nbsp;21PAD<br /> | Acer&amp;nbsp;M1535<br /> | Acer&amp;nbsp;M1535<br /> | ?<br /> | ?<br /> | style=&quot;background:lime&quot; | OK&lt;sup&gt;2&lt;/sup&gt;<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE.cfm P4DPE]<br /> | Intel&amp;reg;&amp;nbsp;E7500<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE-G2.cfm P4DPE-G2]<br /> | Intel&amp;reg;&amp;nbsp;E7500<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | P4DPR<br /> | Intel&amp;reg;&amp;nbsp;E7500<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon/E7505/X5DAE.cfm X5DAE]<br /> | Intel&amp;reg;&amp;nbsp;E7505<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S), 82801DB&amp;nbsp;(ICH4),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | [http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DPE-G2.cfm X5DPE-G2]<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Supermicro<br /> | X5DPR<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Tyan<br /> | [http://www.tyan.com/archive/products/html/tigeri7501.html Tiger&amp;nbsp;i7501&amp;nbsp;(S2723)]<br /> | Intel&amp;reg;&amp;nbsp;E7501<br /> | Intel&amp;reg;&amp;nbsp;82801CA&amp;nbsp;(ICH3-S),&amp;nbsp;82870<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | Intel&amp;reg;&amp;nbsp;Xeon&amp;reg;<br /> | Socket&amp;nbsp;604<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;9&quot; | '''Laptops'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | IBM<br /> | [http://www.thinkwiki.org/wiki/Category:T23 ThinkPad T23]<br /> | Intel&amp;reg;&amp;nbsp;82830<br /> | Intel&amp;reg;&amp;nbsp;82801<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;10&quot; | '''Embedded / SBC / PC/104'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Advantech<br /> | pcm-5823<br /> | NSC&amp;nbsp;GX1<br /> | NSC&amp;nbsp;CS5530<br /> | SMC&amp;nbsp;FDC37B72X<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Advantech<br /> | pcm-9574<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Cocom<br /> | voyager2<br /> | NSC&amp;nbsp;GX1<br /> | NSC&amp;nbsp;CS5530<br /> | NSC&amp;nbsp;PC97317<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | DigitalLogic<br /> | smartcore-p3<br /> | <br /> | <br /> | <br /> | <br /> | <br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | DigitalLogic<br /> | smartcore-p5<br /> | <br /> | <br /> | <br /> | <br /> | <br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Lanner<br /> | [http://www.embedded-computing.com/products/search/fm/id/?10784 EM-370]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83977EF<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;III / Celeron&amp;reg;<br /> | Slot&amp;nbsp;370<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Lippert<br /> | [http://web.archive.org/web/20031204180239/www.lippert-at.com/pc104plus.html Cool RoadRunner II]<br /> | NSC&amp;nbsp;GX1<br /> | NSC&amp;nbsp;CS5530<br /> | SMC&amp;nbsp;FDC37B72X<br /> | NSC&amp;nbsp;Geode&amp;nbsp;GX1<br /> | &amp;mdash;<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Nano<br /> | nano<br /> | NSC&amp;nbsp;GX1<br /> | NSC&amp;nbsp;SCX200<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | STMicroelectronics<br /> | [http://mcu.st.com/mcu/modules.php?name=mcu&amp;file=familiesdocs&amp;FAM=75 STPC&amp;reg;&amp;nbsp;Consumer-II]<br /> | integrated<br /> | integrated<br /> | SMC&amp;nbsp;FDC37B78X<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | STMicroelectronics<br /> | [http://mcu.st.com/mcu/modules.php?name=mcu&amp;file=familiesdocs&amp;FAM=75 STPC&amp;reg;&amp;nbsp;Elite]<br /> | integrated<br /> | integrated<br /> | SMC&amp;nbsp;FDC37B78X<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Supertek<br /> | ST3-WT<br /> | NSC GX1<br /> | NSC CS5535<br /> | NSC PC97317<br /> | Geode<br /> | ?<br /> | style=&quot;background:lime&quot; | OK&amp;nbsp;([[User:Stepan|SR]])<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Technoland<br /> | [http://web.archive.org/web/20040406003346/technoland.com/tl_embsbc710.htm TL-EmbSBC 710]<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | Winbond&amp;trade;&amp;nbsp;W83877EF<br /> | Intel&amp;reg;&amp;nbsp;Pentium&amp;reg;&amp;nbsp;III / Celeron&amp;reg;<br /> | Slot&amp;nbsp;1<br /> | style=&quot;background:lime&quot; | [[Technoland SBC 710|???]]<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;9&quot; | '''Mini-ITX'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]<br /> | VIA&amp;nbsp;VT8601<br /> | VIA&amp;nbsp;VT8231<br /> | Winbond&amp;trade;&amp;nbsp;W83627HF<br /> | VIA&amp;nbsp;C3&amp;trade;&amp;nbsp;/&amp;nbsp;EDEN&amp;trade;<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:lime&quot; | Yes<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | VIA<br /> | [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]<br /> | VIA&amp;nbsp;VT8623<br /> | VIA&amp;nbsp;VT8235<br /> | VIA&amp;nbsp;VT1211<br /> | VIA&amp;nbsp;C3&amp;trade;&amp;nbsp;/&amp;nbsp;EDEN&amp;trade;<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:lime&quot; | Yes<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;9&quot; | '''Set-top-boxes / Thin clients'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Lex<br /> | [http://www.lex.com.tw:8080/product/CV860A.htm CV860A]<br /> | VIA&amp;nbsp;VT8601A<br /> | VIA&amp;nbsp;VT82C686B<br /> | VIA&amp;nbsp;VT82C686B<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | RCN<br /> | Dc1100s<br /> | VIA&amp;nbsp;VT694<br /> | VIA&amp;nbsp;VT82C686<br /> | VIA&amp;nbsp;VT82C686<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;10&quot; | '''Devel/Eval Boards'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | Motorola<br /> | Sandpoint<br /> | Motorola&amp;nbsp;MPC107<br /> | Winbond&amp;trade;&amp;nbsp;W83C553<br /> | NSC&amp;nbsp;PC97307<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:lime&quot; | Yes<br /> <br /> |- bgcolor=&quot;#6699ff&quot;<br /> | colspan=&quot;9&quot; | '''Miscellaneous'''<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | BCM<br /> | e100<br /> | SiS550<br /> | SiS550<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | Dell<br /> | 350<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | SMC&amp;nbsp;FDC37B907<br /> | ?<br /> | Slot&amp;nbsp;1<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | irobot<br /> | Proto1<br /> | Intel&amp;reg;&amp;nbsp;440BX<br /> | Intel&amp;reg;&amp;nbsp;82371EB&amp;nbsp;(PIIX4E)<br /> | SMS&amp;nbsp;FDC37N769<br /> | ?<br /> | Slot&amp;nbsp;1<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#dddddd&quot;<br /> | SiS<br /> | 540 (?)<br /> | SiS540<br /> | SiS540<br /> | SiS950<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | SiS<br /> | 550 (?)<br /> | SiS550<br /> | SiS550<br /> | ?<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | SiS<br /> | 635 (?)<br /> | ?<br /> | SiS635<br /> | SiS950<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#dddddd&quot;<br /> | SiS<br /> | 735 (?)<br /> | SiS735<br /> | SiS735<br /> | SiS950<br /> | ?<br /> | ?<br /> | style=&quot;background:#dddddd&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> <br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | VIA<br /> | vt5292<br /> | VIA&amp;nbsp;VT8601<br /> | VIA&amp;nbsp;VT82C686<br /> | VIA&amp;nbsp;VT82C686<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |- bgcolor=&quot;#eeeeee&quot;<br /> | VIA<br /> | vt5426<br /> | VIA&amp;nbsp;VT8601<br /> | VIA&amp;nbsp;VT82C686<br /> | VIA&amp;nbsp;VT82C686<br /> | ?<br /> | ?<br /> | style=&quot;background:#eeeeee&quot; | ?<br /> | style=&quot;background:red&quot; | No<br /> |}<br /> <br /> &lt;small&gt;<br /> &lt;sup&gt;1&lt;/sup&gt; Work in progress.&lt;br /&gt;<br /> &lt;sup&gt;2&lt;/sup&gt; http://www.linuxbios.org/pipermail/linuxbios/2002-October/000743.html&lt;br /&gt;<br /> &lt;sup&gt;3&lt;/sup&gt; http://www.linuxbios.org/pipermail/linuxbios/2003-September/005385.html&lt;br /&gt;<br /> &lt;/small&gt;<br /> <br /> __FORCETOC__</div>

Stuge http://www.coreboot.org/Welcome_to_coreboot 2010-04-23T21:59:21Z

<p>Stuge: Add LinuxTag booth and remove GSoC student application open date which is passed</p> <hr /> <div>&lt;table width=&quot;100%&quot; valign=&quot;top&quot;&gt;&lt;tr valign=&quot;top&quot;&gt;&lt;td width=&quot;80%&quot;&gt;<br /> <br /> &lt;div style=&quot;margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;&quot;&gt;<br /> '''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].<br /> <br /> With this separation of hardware initialization and later boot logic, coreboot is capable of scaling from specialized applications run directly from firmware, operating systems in Flash, and custom bootloaders to implementations of firmware standards like PCBIOS and EFI without having to carry features not necessary in the target application, reducing the amount of code and flash space required.<br /> <br /> We currently support '''[[Supported Motherboards|215]]''' different mainboards.<br /> <br /> &lt;/div&gt;<br /> <br /> {| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align=&quot;top&quot; width=100%<br /> |-<br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {{Box|<br /> BORDER = #8898bf|<br /> BACKGROUND = yellow|<br /> WIDTH = 100%|<br /> ICON = &lt;small&gt;[[Benefits|More...]]&lt;/small&gt;|<br /> HEADING = &lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Benefits]]&lt;/span&gt;|<br /> CONTENT =<br /> &lt;small&gt;<br /> * 100% Free Software (GPL), no royalties, no license fees!<br /> * Fast boot times (3 seconds to Linux console)<br /> &lt;!-- * Avoids the need for a slow/buggy/proprietary BIOS --&gt;<br /> &lt;!-- * Runs in 32-Bit protected mode almost from the start --&gt;<br /> &lt;!-- * Written in C, contains virtually no assembly code --&gt;<br /> * Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br /> &lt;!-- * Further features: netboot, serial console, remote flashing, ... --&gt;<br /> &lt;/small&gt;<br /> }}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {{Box|<br /> BORDER = #8898bf|<br /> BACKGROUND = #d1adf6|<br /> WIDTH = 100%|<br /> ICON = &lt;small&gt;[[Use Cases|More...]]&lt;/small&gt;|<br /> HEADING = &lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Use Cases]]&lt;/span&gt;|<br /> CONTENT =<br /> &lt;small&gt;<br /> * Desktop PCs and servers<br /> * [[Clusters]]<br /> &lt;!-- * Set-Top-Boxes, thin clients --&gt;<br /> * Embedded solutions<br /> &lt;!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --&gt;<br /> &lt;!-- * No-moving-parts solutions (ROM chip as &quot;disk&quot;) --&gt;<br /> &lt;!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --&gt;<br /> &lt;/small&gt;<br /> }}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {{Box|<br /> BORDER = #8898bf|<br /> BACKGROUND = lime|<br /> WIDTH = 100%|<br /> ICON = &lt;small&gt;[[Payloads|More...]]&lt;/small&gt;|<br /> HEADING = &lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Payloads]]&lt;/span&gt;|<br /> CONTENT =<br /> &lt;small&gt;<br /> * [[FILO]] / [http://grub.enbug.org/CoreBoot GRUB2] &lt;!-- / [[OpenFirmware]] / [[OpenBIOS]] --&gt;<br /> * [[Linux]] / [[Booting Windows using coreboot|Windows]] / [[Booting FreeBSD using coreboot|FreeBSD]]&lt;!-- / [[Coreboot and NetBSD|NetBSD]] / [http://openbsd.org/ OpenBSD]--&gt;<br /> * [[Etherboot]]<br /> &lt;!--* [[SeaBIOS]] / [[Memtest86]]<br /> * [[Etherboot]] / [[GPXE]]<br /> * [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--&gt;<br /> &lt;/small&gt;<br /> }}<br /> <br /> |}<br /> <br /> {| cellspacing=5 cellpadding=15 border=0 valign=&quot;top&quot; width=100%<br /> | width=50% style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_cb.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;About&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Find out more about coreboot.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Clusters]] | [[Vendors]]&lt;/small&gt;<br /> |}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_devel.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Developers&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Get involved! Help us make coreboot better.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[SerialICE]] | [[Flag Days]]&lt;/small&gt;<br /> |}<br /> <br /> |-<br /> | width=50% style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_status.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Status&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Find out whether your hardware is already supported.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [http://qa.coreboot.org Build Status]&lt;/small&gt;<br /> |}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_tools.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Related Tools&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Tools and libraries related to coreboot.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]]&lt;/small&gt;<br /> |}<br /> <br /> |-<br /> | width=50% style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_101.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Getting Started&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Download coreboot and get started.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[:Category:Tutorials|Board Tutorials]] | [[QEMU]] | [[AMD SimNow]]&lt;/small&gt;<br /> |}<br /> <br /> |style=&quot;vertical-align:top&quot;|<br /> <br /> {|<br /> |style=&quot;vertical-align:top&quot;|<br /> [[Image:chip_support.png]]<br /> |style=&quot;vertical-align:top&quot;|<br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:150%&quot;&gt;Support&lt;/span&gt;'''&lt;br /&gt;&lt;small&gt;Learn how to contact us and find help and support.&lt;/small&gt;&lt;small&gt;&lt;hr /&gt;[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]&lt;/small&gt;<br /> |}<br /> <br /> |}<br /> &lt;/td&gt;&lt;td width=&quot;20%&quot;&gt;<br /> <br /> [[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br /> <br /> &lt;br clear=all /&gt;<br /> <br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[News]]&lt;/span&gt;'''&lt;hr /&gt;<br /> &lt;!-- Please always make this list 7 items long (7 most recent news items). --&gt;<br /> &lt;small&gt;<br /> * '''2010/03/15:''' [[News#2010.2F03.2F15_AMD_RS780_and_SB700_now_supported|AMD RS780/SB700 support]]<br /> * '''2010/03/05:''' [[News#2010.2F03.2F05_ASUS_P2B-LS_now_supported|ASUS P2B-LS support]]<br /> * '''2010/01/17:''' [[News#2010.2F01.2F17_Roda_RK886EX_.28Rocky_III.2B.29_now_supported|Roda RK886EX (Rocky III+) support]]<br /> * '''2009/10/21:''' [[News#2009.2F10.2F21_HP_e-Vectra_P2706T_now_supported|HP e-Vectra P2706T support]]<br /> * '''2009/10/13:''' [[News#2009.2F10.2F13_MSI_MS-6156_now_supported|MSI MS-6156 support]]<br /> * '''2009/10/13:''' [[News#2009.2F10.2F13_TechNexion_TIM-5690_now_supported|TechNexion TIM-5690 support]]<br /> * '''2009/09/25:''' [[News#2009.2F09.2F25_coreboot_on_the_cover_of_the_Linux_Journal|coreboot @ Linux Journal]]<br /> &lt;/small&gt;<br /> <br /> <br /> '''&lt;span style=&quot;font-variant:small-caps; font-size:120%&quot;&gt;[[Current events|Upcoming Events]]&lt;/span&gt;'''&lt;hr /&gt;<br /> &lt;!-- List of upcoming events (remove events after they have taken place). --&gt;<br /> &lt;small&gt;<br /> &lt;!-- * '''2010/mon/day:''' coreboot event at [[Link]] in somecity --&gt;<br /> &lt;div style=&quot;color: #ff0000&quot;&gt;<br /> * '''2010/04/09:''' [[GSoC|Google Summer of Code 2010]] student application deadline!<br /> &lt;/div&gt;<br /> * '''2010/06/09-12:''' coreboot exhibits at [http://www.linuxtag.org/ LinuxTag] in Berlin<br /> &lt;/small&gt;<br /> <br /> &lt;/td&gt;&lt;/tr&gt;&lt;/table&gt;<br /> <br /> __NOTOC__<br /> __NOEDITSECTION__</div>

Stuge http://www.coreboot.org/Current_events 2010-04-23T21:55:29Z

<p>Stuge: add linuxtag 2010</p> <hr /> <div>Please contact [[User:Stepan|Stefan Reinauer]], [[User:Rminnich|Ronald Minnich]] or [[User:Stuge|Peter Stuge]] for more information on the events.<br /> <br /> == Upcoming Events ==<br /> <br /> * coreboot will exhibit at [http://www.linuxtag.org/ LinuxTag 2010] in Berlin on June 9-12, 2010.<br /> <br /> == Past Events ==<br /> <br /> '''2010'''<br /> <br /> * coreboot had its [[FOSDEM 2010|very first DevRoom]] at [http://www.fosdem.org/ FOSDEM] in Brussels on February 6, 2010.<br /> <br /> '''2009'''<br /> <br /> * [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2009/Fahrplan/events/3661.en.html coreboot] at [http://events.ccc.de/congress/2009/ the 26th Chaos Communication Congress (26C3)] in Berlin on December 27, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented [http://www.databadge.net/ifsec2009/reg/lin/show_sessions.php coreboot] at [http://www.linux-world.nl/nl-NL/Bezoeker.aspx?sc_lang=en LinuxWorld Conference &amp; Expo] in Utrecht on November 4, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented [https://har2009.org/program/events/210.en.html coreboot] at [https://wiki.har2009.org/page/Main_Page HAR2009] in Vierhouten on August 13, 2009.<br /> * coreboot had a booth at [[LinuxTag 2009|LinuxTag]] in Berlin on June 24-27, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at [http://freedomhectaipei.pbworks.com/ FreedomHEC Taipei] on June 11, 2009.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at [http://goopen2009.friprog.no/ GoOpen 2009] in Oslo on April 16-17, 2009.<br /> * [[User:Stepan|Stefan Reinauer]], [[User:Stuge|Peter Stuge]] and [[User:Ruik|Rudolf Marek]] made a visit at [http://www.embedded-world.de/ embedded world 2009] in Nürnberg on March 3-5.<br /> * [[User:Rminnich|Ron Minnich]] had a [http://scale7x.socallinuxexpo.org/dotorg/coreboot coreboot booth] at the [http://scale7x.socallinuxexpo.org/ Southern California Linux Expo] (SCALE 7x) on February 20-22, 2009.<br /> <br /> '''2008'''<br /> <br /> * [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2008/Fahrplan/events/2970.en.html coreboot: Beyond The Final Frontier] and held a coreboot workshop at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)] on December 27-30.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at the [http://www.nluug.nl/events/nj08/ NLUUG Autumn Conference on Mobile Computing] and [http://www.embeddedlinuxconference.com/elc_europe08/ CE Linux Forum - Embedded Linux conference Europe 2008] on November 6-7.<br /> * [[User:Rminnich|Ronald Minnich]], [[User:Stuge|Peter Stuge]] and [[User:Stepan|Stefan Reinauer]] presented coreboot in a [[Screenshots#Google_Tech_Talks_2008:_coreboot_.28aka_LinuxBIOS.29:_The_Free.2FOpen-Source_x86_Firmware|Google TechTalk]] on October 30.<br /> * [[User:Stuge|Peter Stuge]] presented [http://fscons.org/events/?action=event&amp;id=32 coreboot] at the [http://fscons.org/ Free Society Conference and Nordic Summit 2008] on October 24-26.<br /> * [[User:Stuge|Peter Stuge]] presented coreboot at the [http://slackathon.se/2008/ Slackathon 2008] OpenBSD meeting in September.<br /> * Coreboot was exhibiting at [[LinuxTag 2008]] in Berlin on May 28-31.<br /> * The [[Coreboot Symposium 2008|coreboot symposium 2008]] was held in Denver, April 3 – 5, 2008 during the High Performance Computer Science Week [http://www.hpcsw.org HPCSW].<br /> <br /> '''2007'''<br /> <br /> * There was a [[News#2007.2F05.2F23_LinuxBIOS_booth_at_LinuxTag_in_Berlin.2C_29.2F5-2.2F6|LinuxBIOS booth at the LinuxTag in Berlin, May 29 - June 6, 2007]], as well as a hands-on workshop by Peter Stuge.<br /> * Ron Minnich gave [http://www.fosdem.org/2007/schedule/events/linuxbios a talk about LinuxBIOS] on February 24, 2007 at [http://www.fosdem.org/2007/ FOSDEM 2007].<br /> <br /> '''2006'''<br /> <br /> * The [[LinuxBIOS Symposium 2006]] took place on October 1-3, 2006 in Hamburg, Germany.<br /> <br /> '''2005'''<br /> <br /> * The [[LinuxBIOS Summit 2005]] took place on October 11-13 in Santa Fe, NM.</div>

Stuge http://www.coreboot.org/Talk:FOSDEM_2010 2010-01-18T05:06:22Z

<p>Stuge: Add APIC system link</p> <hr /> <div>=== Peter intro ===<br /> * what is coreboot - history - motivation<br /> * payloads and compression<br /> * v2/v3<br /> * cbfs<br /> * other software in same and related fields<br /> * sibling projects and utilities: seabios serialice coreinfo bayou libpayload buildrom mkelfImage nvramtool superiotool inteltool msrtool flashrom<br /> * security issues<br /> <br /> === Peter technical details ===<br /> * modern pc architecture<br /> * CPU i/o (ports/memory)<br /> * registers in hardware, &quot;ISA&quot; and PCI<br /> * NVRAM<br /> * interrupts<br /> * PIC APIC PIRQ/MP tables [[Media:ApicSystem.svg]]<br /> * ram init<br /> * cache-as-ram<br /> * gcc vs. romcc<br /> * real mode, protected mode, system management mode<br /> * mention embedded controllers and capabilities and tasks<br /> <br /> === Rudolf acpi ===<br /> * what for is ACPI<br /> * Sleep states in more detail - S1 S2 S3 S4 S5<br /> * CPU power modes C1/C2/C3<br /> * hardware side - PM regs<br /> * software architecture of ACPI<br /> * Tables in more detail<br /> * Some tour through it acpiextract iasl<br /> * Coreboot specific stuff - perhaps the ACPIgen<br /> * and SSDT generation<br /> * suspend/resume from HW point of view - memory controller stuff too<br /> * SW flow through coreboot + ram preservation issues<br /> <br /> === Rudolf board porting ===<br /> * Get to know your HW (lspci, superiotool)<br /> * serial setup + troubles wrong OSC speeds<br /> * GPIO setup<br /> * watchdogs - yes ite has default on :)<br /> * IRQ routing in ACPI? maybe some ideas...<br /> * ACPI specific stuff for each board<br /> * porting on supported chipset - describe the early setup for mainboard + directory content for the board<br /> * some ideas for porting on new unsupported chipset<br /> <br /> === Carl-Daniel flashrom ===<br /> <br /> === Luc board enable reverse engineering ===</div>

Stuge http://www.coreboot.org/FOSDEM_2010 2010-01-18T01:39:34Z

<p>Stuge: /* Talks */</p> <hr /> <div>== Time and Place ==<br /> <br /> Saturday, 6th of February 2010, at FOSDEM2010 in Brussels, Belgium.<br /> <br /> == FOSDEM? ==<br /> <br /> [http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 10 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).<br /> <br /> == Coreboot DevRoom ==<br /> <br /> Coreboot will have its very first DevRoom at FOSDEM this year. We will have [http://archive.fosdem.org/2009/maps/campus AW.124], which can hold 60 people, from 13:00 to 19:00. We will have talks and hands-on sessions there and generally be very cool and interesting :)<br /> <br /> === Schedule ===<br /> <br /> * 13:00 : Peter Stuge - coreboot introduction<br /> * 14:00 : Peter Stuge - coreboot and PC technical details<br /> * 15:00 : Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> * 16:00 : Rudolf Marek - coreboot board porting.<br /> * 17:00 : Carl-Daniel Hailfinger - Flashrom.<br /> * 18:00 : Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> === Talks ===<br /> <br /> * Peter Stuge - coreboot introduction<br /> <br /> The BIOS and it's successor EFI are considered by many to be the final frontier for open source software in commodity PCs. This talk introduces the open source BIOS replacement coreboot (formerly known as LinuxBIOS) and the projects that surround it, including many popular payloads that combine with coreboot to make up an innovative firmware for PCs. The talk also looks at the 10 year long history of the project, describes the current state of development and considers some possibilities for the future.<br /> <br /> * Peter Stuge - coreboot and PC technical details<br /> <br /> A modern PC is quite different from the 1980s original, and while the BIOS still lingers after 30 years it must now solve many tricky problems. When the original PC with it's pre-ISA expansion bus was powered on, it was almost immediately ready to run an application. Today's PC can have several multicore CPUs interconnected by HyperTransport, Front Side Bus or QuickPath, DDR3 RAM on each CPU, and a large number of buses and peripherals. Many components require increasingly complex initialization to be implemented in software. This talk describes the technical challenges encountered by coreboot developers and their solutions.<br /> <br /> * Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> <br /> Ever wanted to know more about ACPI? The aim of this talk is to introduce the software part of ACPI as well as provide the necessary hardware details to get the bigger picture. A tour through the Coreboot ACPI implementation will be given, and the suspend and resume procedure will be presented with all nifty details explained.<br /> <br /> * Rudolf Marek - coreboot board porting<br /> <br /> You don't like your BIOS? Want coreboot instead? Here is my story... This talk introduces some strategies for porting coreboot to new hardware. We go over the information gathering stage, data-mining, datasheet usage and common gotchas. The porting of new motherboard but with existing chipset support is explained.<br /> Kickstarts to new chipsets ports included.<br /> <br /> * Carl-Daniel Hailfinger - Flashrom.<br /> <br /> * Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> Many board makers provide extra write protection for their bioschips. The developers at the flashrom project have to devote part of their time on finding out what protection is provided and how this can be disabled. Some of this information comes from the BIOS itself, and the procedures for some common BIOSes, and the tools involved will be introduced in this talk. Half of the time will be spent on digging through an actual BIOS with a crude tool like ndisasm.<br /> <br /> === Information for Speakers ===<br /> <br /> A DevRoom at FOSDEM contains a sometimes working network (several thousand people are trying to use wireless at the same time), power, an LCD projector and some whiteboards. Next to that, the room will be filled with highly interested free software people, some of which you know or will get to know after your talk. It always is a very friendly and highly interested audience that can handle very technical information well. Talks should not be kept shallow at all as little pandering is needed. Talks should generally last about 45 minutes, so that there is some time for people to move in and out of the room or to come and talk to you directly.<br /> <br /> If you want to give a talk at this DevRoom (and as you can see, there are plenty of slots still available), please contact Luc Verhaegen (libv) by dropping him an email at libv at skynet dot be.<br /> <br /> == Further information ==<br /> <br /> The [http://www.fosdem.org FOSDEM website] contains tons of information on the event itself, transportation, getting around in brussels, finding hotels, pretty much everything you need. Next to that, there are [http://www.fosdem.org/2010/archives archives] of the website for the previous years, where you can find out about previous talks and shedules.</div>

Stuge http://www.coreboot.org/FOSDEM_2010 2010-01-18T01:38:34Z

<p>Stuge: /* Talks */</p> <hr /> <div>== Time and Place ==<br /> <br /> Saturday, 6th of February 2010, at FOSDEM2010 in Brussels, Belgium.<br /> <br /> == FOSDEM? ==<br /> <br /> [http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 10 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).<br /> <br /> == Coreboot DevRoom ==<br /> <br /> Coreboot will have its very first DevRoom at FOSDEM this year. We will have [http://archive.fosdem.org/2009/maps/campus AW.124], which can hold 60 people, from 13:00 to 19:00. We will have talks and hands-on sessions there and generally be very cool and interesting :)<br /> <br /> === Schedule ===<br /> <br /> * 13:00 : Peter Stuge - coreboot introduction<br /> * 14:00 : Peter Stuge - coreboot and PC technical details<br /> * 15:00 : Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> * 16:00 : Rudolf Marek - coreboot board porting.<br /> * 17:00 : Carl-Daniel Hailfinger - Flashrom.<br /> * 18:00 : Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> === Talks ===<br /> <br /> * Peter Stuge - coreboot introduction<br /> <br /> The BIOS and it's successor EFI are considered by many to be the final frontier for open source software in commodity PCs. This talk introduces the open source BIOS replacement coreboot (formerly known as LinuxBIOS) and the projects that surround it, including many popular payloads that combine with coreboot to make up an incredibly full-featured firmware for PCs. The talk also looks at the 10 year long history of the project, describes the current state of development and considers some possibilities for the future.<br /> <br /> * Peter Stuge - coreboot and PC technical details<br /> <br /> A modern PC is quite different from the 1980s original, and while the BIOS still lingers after 30 years it must now solve many tricky problems. When the original PC with it's pre-ISA expansion bus was powered on, it was almost immediately ready to run an application. Today's PC can have several multicore CPUs interconnected by HyperTransport, Front Side Bus or QuickPath, DDR3 RAM on each CPU, and a large number of buses and peripherals. Many components require increasingly complex initialization to be implemented in software. This talk describes the technical challenges encountered by coreboot developers and their solutions.<br /> <br /> * Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> <br /> Ever wanted to know more about ACPI? The aim of this talk is to introduce the software part of ACPI as well as provide the necessary hardware details to get the bigger picture. A tour through the Coreboot ACPI implementation will be given, and the suspend and resume procedure will be presented with all nifty details explained.<br /> <br /> * Rudolf Marek - coreboot board porting<br /> <br /> You don't like your BIOS? Want coreboot instead? Here is my story... This talk introduces some strategies for porting coreboot to new hardware. We go over the information gathering stage, data-mining, datasheet usage and common gotchas. The porting of new motherboard but with existing chipset support is explained.<br /> Kickstarts to new chipsets ports included.<br /> <br /> * Carl-Daniel Hailfinger - Flashrom.<br /> <br /> * Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> Many board makers provide extra write protection for their bioschips. The developers at the flashrom project have to devote part of their time on finding out what protection is provided and how this can be disabled. Some of this information comes from the BIOS itself, and the procedures for some common BIOSes, and the tools involved will be introduced in this talk. Half of the time will be spent on digging through an actual BIOS with a crude tool like ndisasm.<br /> <br /> === Information for Speakers ===<br /> <br /> A DevRoom at FOSDEM contains a sometimes working network (several thousand people are trying to use wireless at the same time), power, an LCD projector and some whiteboards. Next to that, the room will be filled with highly interested free software people, some of which you know or will get to know after your talk. It always is a very friendly and highly interested audience that can handle very technical information well. Talks should not be kept shallow at all as little pandering is needed. Talks should generally last about 45 minutes, so that there is some time for people to move in and out of the room or to come and talk to you directly.<br /> <br /> If you want to give a talk at this DevRoom (and as you can see, there are plenty of slots still available), please contact Luc Verhaegen (libv) by dropping him an email at libv at skynet dot be.<br /> <br /> == Further information ==<br /> <br /> The [http://www.fosdem.org FOSDEM website] contains tons of information on the event itself, transportation, getting around in brussels, finding hotels, pretty much everything you need. Next to that, there are [http://www.fosdem.org/2010/archives archives] of the website for the previous years, where you can find out about previous talks and shedules.</div>

Stuge http://www.coreboot.org/FOSDEM_2010 2010-01-18T01:37:38Z

<p>Stuge: /* Talks */</p> <hr /> <div>== Time and Place ==<br /> <br /> Saturday, 6th of February 2010, at FOSDEM2010 in Brussels, Belgium.<br /> <br /> == FOSDEM? ==<br /> <br /> [http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 10 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).<br /> <br /> == Coreboot DevRoom ==<br /> <br /> Coreboot will have its very first DevRoom at FOSDEM this year. We will have [http://archive.fosdem.org/2009/maps/campus AW.124], which can hold 60 people, from 13:00 to 19:00. We will have talks and hands-on sessions there and generally be very cool and interesting :)<br /> <br /> === Schedule ===<br /> <br /> * 13:00 : Peter Stuge - coreboot introduction<br /> * 14:00 : Peter Stuge - coreboot and PC technical details<br /> * 15:00 : Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> * 16:00 : Rudolf Marek - coreboot board porting.<br /> * 17:00 : Carl-Daniel Hailfinger - Flashrom.<br /> * 18:00 : Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> === Talks ===<br /> <br /> * Peter Stuge - coreboot introduction<br /> <br /> The BIOS and it's successor EFI are considered by many to be the final frontier for open source software in commodity PCs. This talk introduces the open source BIOS replacement coreboot (formerly LinuxBIOS) and the projects that surround it, including many popular payloads that combine with coreboot to make up an incredibly full-featured firmware for PCs. The talk also looks at the 10 year long history of the project, describes the current state of development and considers some possibilities for the future.<br /> <br /> * Peter Stuge - coreboot and PC technical details<br /> <br /> A modern PC is quite different from the 1980s original, and while the BIOS still lingers after 30 years it must now solve many tricky problems. When the original PC with it's pre-ISA expansion bus was powered on, it was almost immediately ready to run an application. Today's PC can have several multicore CPUs interconnected by HyperTransport, Front Side Bus or QuickPath, DDR3 RAM on each CPU, and a large number of buses and peripherals. Many components require increasingly complex initialization to be implemented in software. This talk describes the technical challenges encountered by coreboot developers and their solutions.<br /> <br /> * Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> <br /> Ever wanted to know more about ACPI? The aim of this talk is to introduce the software part of ACPI as well as provide the necessary hardware details to get the bigger picture. A tour through the Coreboot ACPI implementation will be given, and the suspend and resume procedure will be presented with all nifty details explained.<br /> <br /> * Rudolf Marek - coreboot board porting<br /> <br /> You don't like your BIOS? Want coreboot instead? Here is my story... This talk introduces some strategies for porting coreboot to new hardware. We go over the information gathering stage, data-mining, datasheet usage and common gotchas. The porting of new motherboard but with existing chipset support is explained.<br /> Kickstarts to new chipsets ports included.<br /> <br /> * Carl-Daniel Hailfinger - Flashrom.<br /> <br /> * Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> Many board makers provide extra write protection for their bioschips. The developers at the flashrom project have to devote part of their time on finding out what protection is provided and how this can be disabled. Some of this information comes from the BIOS itself, and the procedures for some common BIOSes, and the tools involved will be introduced in this talk. Half of the time will be spent on digging through an actual BIOS with a crude tool like ndisasm.<br /> <br /> === Information for Speakers ===<br /> <br /> A DevRoom at FOSDEM contains a sometimes working network (several thousand people are trying to use wireless at the same time), power, an LCD projector and some whiteboards. Next to that, the room will be filled with highly interested free software people, some of which you know or will get to know after your talk. It always is a very friendly and highly interested audience that can handle very technical information well. Talks should not be kept shallow at all as little pandering is needed. Talks should generally last about 45 minutes, so that there is some time for people to move in and out of the room or to come and talk to you directly.<br /> <br /> If you want to give a talk at this DevRoom (and as you can see, there are plenty of slots still available), please contact Luc Verhaegen (libv) by dropping him an email at libv at skynet dot be.<br /> <br /> == Further information ==<br /> <br /> The [http://www.fosdem.org FOSDEM website] contains tons of information on the event itself, transportation, getting around in brussels, finding hotels, pretty much everything you need. Next to that, there are [http://www.fosdem.org/2010/archives archives] of the website for the previous years, where you can find out about previous talks and shedules.</div>

Stuge http://www.coreboot.org/FOSDEM_2010 2010-01-18T01:29:28Z

<p>Stuge: Add abstracts for Peter's talks</p> <hr /> <div>== Time and Place ==<br /> <br /> Saturday, 6th of February 2010, at FOSDEM2010 in Brussels, Belgium.<br /> <br /> == FOSDEM? ==<br /> <br /> [http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 10 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).<br /> <br /> == Coreboot DevRoom ==<br /> <br /> Coreboot will have its very first DevRoom at FOSDEM this year. We will have [http://archive.fosdem.org/2009/maps/campus AW.124], which can hold 60 people, from 13:00 to 19:00. We will have talks and hands-on sessions there and generally be very cool and interesting :)<br /> <br /> === Schedule ===<br /> <br /> * 13:00 : Peter Stuge - coreboot introduction<br /> * 14:00 : Peter Stuge - coreboot and PC technical details<br /> * 15:00 : Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> * 16:00 : Rudolf Marek - coreboot board porting.<br /> * 17:00 : Carl-Daniel Hailfinger - Flashrom.<br /> * 18:00 : Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> === Talks ===<br /> <br /> * Peter Stuge - coreboot introduction<br /> <br /> The BIOS and it's successor EFI are considered by many to be the final frontier for open source software in commodity PCs. This talk introduces the open source BIOS replacement coreboot (formerly LinuxBIOS) and the projects that surround it, including many popular payloads that combine with coreboot to make up an incredibly full-featured firmware for PCs. The talk also looks at the 10 year long history of the project, describes the current state of development and considers some possibilities for the future.<br /> <br /> * Peter Stuge - coreboot and PC technical details<br /> <br /> A modern PC is quite different from the 1980s original, and even if the BIOS lingers after 30 years it must now take on many complex challenges. When the original PC with it's pre-ISA expansion bus was powered on, the system was almost immediately ready to run an application. Today's PC can have several multicore CPUs interconnected by HyperTransport, Front Side Bus or QuickPath, DDR3 RAM on each CPU, and a large number of buses and peripherals, most of which require initialization with varying degrees of complexity to be implemented in software. This talk describes the technical challenges encountered by coreboot developers and their solutions.<br /> <br /> * Rudolf Marek - ACPI and Suspend/Resume under coreboot.<br /> <br /> Ever wanted to know more about ACPI? The aim of this talk is to introduce the software part of ACPI as well as provide the necessary hardware details to get the bigger picture. A tour through the Coreboot ACPI implementation will be given, and the suspend and resume procedure will be presented with all nifty details explained.<br /> <br /> * Rudolf Marek - coreboot board porting<br /> <br /> You don't like your BIOS? Want coreboot instead? Here is my story... This talk introduces some strategies for porting coreboot to new hardware. We go over the information gathering stage, data-mining, datasheet usage and common gotchas. The porting of new motherboard but with existing chipset support is explained.<br /> Kickstarts to new chipsets ports included.<br /> <br /> * Carl-Daniel Hailfinger - Flashrom.<br /> <br /> * Luc Verhaegen - Flash Enable BIOS Reverse Engineering.<br /> <br /> Many board makers provide extra write protection for their bioschips. The developers at the flashrom project have to devote part of their time on finding out what protection is provided and how this can be disabled. Some of this information comes from the BIOS itself, and the procedures for some common BIOSes, and the tools involved will be introduced in this talk. Half of the time will be spent on digging through an actual BIOS with a crude tool like ndisasm.<br /> <br /> === Information for Speakers ===<br /> <br /> A DevRoom at FOSDEM contains a sometimes working network (several thousand people are trying to use wireless at the same time), power, an LCD projector and some whiteboards. Next to that, the room will be filled with highly interested free software people, some of which you know or will get to know after your talk. It always is a very friendly and highly interested audience that can handle very technical information well. Talks should not be kept shallow at all as little pandering is needed. Talks should generally last about 45 minutes, so that there is some time for people to move in and out of the room or to come and talk to you directly.<br /> <br /> If you want to give a talk at this DevRoom (and as you can see, there are plenty of slots still available), please contact Luc Verhaegen (libv) by dropping him an email at libv at skynet dot be.<br /> <br /> == Further information ==<br /> <br /> The [http://www.fosdem.org FOSDEM website] contains tons of information on the event itself, transportation, getting around in brussels, finding hotels, pretty much everything you need. Next to that, there are [http://www.fosdem.org/2010/archives archives] of the website for the previous years, where you can find out about previous talks and shedules.</div>

Stuge http://www.coreboot.org/Talk:FOSDEM_2010 2010-01-18T00:51:50Z

<p>Stuge: </p> <hr /> <div>=== Peter intro ===<br /> * what is coreboot - history - motivation<br /> * payloads and compression<br /> * v2/v3<br /> * cbfs<br /> * other software in same and related fields<br /> * sibling projects and utilities: seabios serialice coreinfo bayou libpayload buildrom mkelfImage nvramtool superiotool inteltool msrtool flashrom<br /> * security issues<br /> <br /> === Peter technical details ===<br /> * modern pc architecture<br /> * CPU i/o (ports/memory)<br /> * registers in hardware, &quot;ISA&quot; and PCI<br /> * NVRAM<br /> * interrupts, PIC APIC PIRQ/MP tables<br /> * ram init<br /> * cache-as-ram<br /> * gcc vs. romcc<br /> * real mode, protected mode, system management mode<br /> * mention embedded controllers and capabilities and tasks<br /> <br /> === Rudolf acpi ===<br /> * what for is ACPI<br /> * Sleep states in more detail - S1 S2 S3 S4 S5<br /> * CPU power modes C1/C2/C3<br /> * hardware side - PM regs<br /> * software architecture of ACPI<br /> * Tables in more detail<br /> * Some tour through it acpiextract iasl<br /> * Coreboot specific stuff - perhaps the ACPIgen<br /> * and SSDT generation<br /> * suspend/resume from HW point of view - memory controller stuff too<br /> * SW flow through coreboot + ram preservation issues<br /> <br /> === Rudolf board porting ===<br /> * Get to know your HW (lspci, superiotool)<br /> * serial setup + troubles wrong OSC speeds<br /> * GPIO setup<br /> * watchdogs - yes ite has default on :)<br /> * IRQ routing in ACPI? maybe some ideas...<br /> * ACPI specific stuff for each board<br /> * porting on supported chipset - describe the early setup for mainboard + directory content for the board<br /> * some ideas for porting on new unsupported chipset<br /> <br /> === Carl-Daniel flashrom ===<br /> <br /> === Luc board enable reverse engineering ===</div>

Stuge http://www.coreboot.org/Talk:FOSDEM_2010 2010-01-18T00:26:33Z

<p>Stuge: </p> <hr /> <div>=== Peter intro ===<br /> * what is coreboot - history - motivation<br /> * payloads and compression<br /> * v2/v3<br /> * cbfs<br /> * other software in same and related fields<br /> * sibling projects and utilities: seabios serialice coreinfo bayou libpayload buildrom mkelfImage nvramtool superiotool inteltool msrtool flashrom<br /> * security issues<br /> <br /> === Peter technical details ===<br /> * modern pc architecture<br /> * interrupts, PIC APIC PIRQ/MP tables<br /> * ram init<br /> * cache-as-ram<br /> * gcc vs. romcc<br /> * real mode, protected mode, system management mode<br /> * mention embedded controllers and capabilities and tasks<br /> <br /> === Rudolf acpi ===<br /> * what for is ACPI<br /> * Sleep states in more detail - S1 S2 S3 S4 S5<br /> * CPU power modes C1/C2/C3<br /> * hardware side - PM regs<br /> * software architecture of ACPI<br /> * Tables in more detail<br /> * Some tour through it acpiextract iasl<br /> * Coreboot specific stuff - perhaps the ACPIgen<br /> * and SSDT generation<br /> * suspend/resume from HW point of view - memory controller stuff too<br /> * SW flow through coreboot + ram preservation issues<br /> <br /> === Rudolf board porting ===<br /> * Get to know your HW (lspci, superiotool)<br /> * serial setup + troubles wrong OSC speeds<br /> * GPIO setup<br /> * watchdogs - yes ite has default on :)<br /> * IRQ routing<br /> * ACPI specific stuff for each board<br /> * porting on supported chipset - describe the early setup for mainboard + directory content for the board<br /> * some ideas for porting on new unsupported chipset<br /> <br /> === Carl-Daniel flashrom ===<br /> <br /> === Luc board enable reverse engineering ===</div>

Stuge http://www.coreboot.org/Talk:FOSDEM_2010 2010-01-18T00:19:44Z

<p>Stuge: /* Peter intro */</p> <hr /> <div>=== Peter intro ===<br /> * what is coreboot - history - motivation<br /> * payloads and compression<br /> * v2/v3<br /> * cbfs<br /> * other software in same and related fields<br /> * sibling projects and utilities: seabios serialice coreinfo bayou libpayload buildrom mkelfImage nvramtool superiotool inteltool msrtool flashrom<br /> * security issues<br /> <br /> === Peter technical details ===<br /> * modern pc architecture<br /> * ram init<br /> * cache-as-ram<br /> * gcc vs. romcc<br /> * real mode, protected mode, system management mode<br /> * mention embedded controllers and capabilities and tasks<br /> <br /> === Rudolf acpi ===<br /> * what for is ACPI<br /> * Sleep states in more detail - S1 S2 S3 S4 S5<br /> * CPU power modes C1/C2/C3<br /> * hardware side - PM regs<br /> * software architecture of ACPI<br /> * Tables in more detail<br /> * Some tour through it acpiextract iasl<br /> * Coreboot specific stuff - perhaps the ACPIgen<br /> * and SSDT generation<br /> * suspend/resume from HW point of view - memory controller stuff too<br /> * SW flow through coreboot + ram preservation issues<br /> <br /> === Rudolf board porting ===<br /> * Get to know your HW (lspci, superiotool)<br /> * serial setup + troubles wrong OSC speeds<br /> * GPIO setup<br /> * watchdogs - yes ite has default on :)<br /> * IRQ routing<br /> * ACPI specific stuff for each board<br /> * porting on supported chipset - describe the early setup for mainboard + directory content for the board<br /> * some ideas for porting on new unsupported chipset<br /> <br /> === Carl-Daniel flashrom ===<br /> <br /> === Luc board enable reverse engineering ===</div>

Stuge