coreboot - User contributions [en]

Download coreboot

2012-04-12T18:32:48Z

Uwe:

__NOTOC__
'''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.'''

There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, Mac OS X, and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!

== Snapshots ==

There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.

= Git =

coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and gerrit in coreboot.

Old subversion repository references that still apply will continue to be kept here.

== Git clone ==

coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.

=== Anonymous access ===

To clone the coreboot repository (ca. 120 MB data as of 04/2012):

$ git clone http://review.coreboot.org/p/coreboot

If you want the obsolete, unsupported, and experimental '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):

$ svn co svn://coreboot.org/repository/coreboot-v3

If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):

$ svn co svn://coreboot.org/coreboot/branches/coreboot-v1

=== Developer access with write permission ===

Please see our wiki page about [[Git]] for all the details.

== Source code browsing ==

You can browse the coreboot Git repository online using [http://review.coreboot.org/gitweb?p=coreboot.git gitweb] including its [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree tree view] for accessing the files.

== Repositories on coreboot.org ==

'''coreboot current Git tree:'''
* <nowiki>http://review.coreboot.org/p/coreboot</nowiki>

'''coreboot v1 (obsolete):'''
* svn://coreboot.org/coreboot/branches/coreboot-v1
* <nowiki>https://svn.coreboot.org/coreboot/branches/coreboot-v1</nowiki>

'''coreboot v3 (obsolete):'''
* svn://coreboot.org/repository/coreboot-v3
* <nowiki>https://svn.coreboot.org/repository/coreboot-v3</nowiki>

'''[[FILO]]:'''
* svn://coreboot.org/filo/
* <nowiki>https://svn.coreboot.org/filo/</nowiki>

'''[[Buildrom]]:'''
* svn://coreboot.org/buildrom/
* <nowiki>https://svn.coreboot.org/buildrom/</nowiki>

'''[[Distributed and Automated Testsystem]]:'''
* svn://coreboot.org/testsystem
* <nowiki>https://svn.coreboot.org/testsystem/</nowiki>

Coreboot Options

2011-10-13T22:46:45Z

Uwe: Update.

This is an automatically generated list of '''coreboot compile-time options'''.

Last update: 2011/10/14 00:44:39. (runknown)
{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Option
! align="left" | Source
! align="left" | Format
! align="left" | Short Description
! align="left" | Description
|- bgcolor="#6699dd"
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
| EXPERT || toplevel || bool || Expert mode ||
This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are
doing! You have been warned!

||
|- bgcolor="#eeeeee"
| LOCALVERSION || toplevel || string || Local version string ||
Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler ||
This option allows you to select the compiler used for building
coreboot.

||
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||
Changes the build process to scan-build is used.
Requires scan-build in path.

||
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||
Where the scan-build report should be stored

||
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || ccache ||
Enables the use of ccache for faster builds.
Requires ccache in path.

||
|- bgcolor="#eeeeee"
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||
Enable this option if you are working on the sconfig
device tree parser and made changes to sconfig.l and
sconfig.y.
Otherwise, say N.

||
|- bgcolor="#eeeeee"
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.

||
|- bgcolor="#eeeeee"
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow Link (i.e. SPI)

||
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||
Include in CBFS the coreboot config file that was used to compile the ROM image

||

|- bgcolor="#6699dd"
! align="left" | Menu: Mainboard || || || ||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||
The following X60 series ThinkPad machines have been verified to
work correctly:

ThinkPad X60s (Model 1702, 1703)
ThinkPad X60 (Model 1709)

||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||
The following T60 series ThinkPad machines have been verified to
work correctly:

Thinkpad T60p (Model 2007)

||
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
Look on the bottom side for a number like 406-0001-30. The last 2
digits state the PCB revision (3.0 in this example). For 2.0 or older
boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to
power on automatically. You may enable the button only after this
jumper has been removed. New revision boards are not restricted
in this way, and always have the power button enabled.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
If selected, the on-board SSD will act as IDE Slave instead of Master.

||
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8qgi || hex || ||
though UARTs are on the NUVOTON BMC, port 0x164E
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

||
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||
Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file
of the matching size.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
Choose this option if you have a 128 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
Choose this option if you have a 256 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
Choose this option if you have a 512 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
Choose this option if you have a 1024 KB (1 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
Choose this option if you have a 2048 KB (2 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
Choose this option if you have a 4096 KB (4 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
Choose this option if you have a 8192 KB (8 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
Choose this option if you have a 16384 KB (16 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
The selected mainboard can optionally have the power button tied
to ground with a jumper so that the button appears to be
constantly depressed. If this option is enabled and the jumper is
installed then the board will turn on, but turn off again after a
short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an
actual power button. Select N if you have the jumper installed.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Architecture (x86) || || || ||
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Chipset || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||
Select this to apply patches to the CPU microcode provided by
AMD without source, and distributed with coreboot, to address
issues in the CPU post production.

Microcode updates distributed with coreboot are not necessarily
the latest version available from AMD. Updates are only applied
if they are newer than the microcode already in your CPU.

Unselect this to let Fam10h CPUs run with microcode as shipped
from factory. No binary microcode patches will be included in the
coreboot image in that case, which can help with creating an image
for which complete source code is available, which in turn might
simplify license compliance.

Microcode updates intend to solve issues that have been discovered
after CPU production. The common case is that systems work as
intended with updated microcode, but we have also seen cases where
issues were solved by not applying the microcode updates.

Note that some operating system include these same microcode
patches, so you may need to also disable microcode updates in
your operating system in order for this option to matter.

||
||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||
Select this option if you have an AMD Geode GX2 vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||
Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

||
|- bgcolor="#eeeeee"
| SMP || cpu || bool || ||
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.

||
|- bgcolor="#eeeeee"
| MMX || cpu || bool || ||
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.

||
|- bgcolor="#eeeeee"
| SSE || cpu || bool || ||
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.

||
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool || ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.

||
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool || ||
Unset this if you don't want the MTRR code to use
subtractive MTRRs

||
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

||
|- bgcolor="#6699dd"
! align="left" | Menu: HyperTransport setup || || || ||
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||
This option sets the maximum permissible HyperTransport link
frequency.

Use of this option will only limit the autodetected HT frequency.
It will not (and cannot) increase the frequency beyond the
autodetected limits.

This is primarily used to work around poorly designed or laid out
HT traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||
This option sets the maximum permissible HyperTransport
downlink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||
This option sets the maximum permissible HyperTransport
uplink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||

|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||
This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.

If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.

||
||
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.

||
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Geode GX1 video support || || || ||

|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||
Select if RS690 should be setup to support MMCONF.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||
Select the mode in which SATA should be driven. IDE or AHCI.
The default is IDE.

config SATA_MODE_IDE
bool "IDE"

config SATA_MODE_AHCI
bool "AHCI"
||
|- bgcolor="#eeeeee"
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
If Combined Mode is enabled. IDE controller is exposed and
SATA controller has control over Port0 through Port3,
IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and
SATA controller has full control of all 6 Ports when operating in non-IDE mode.

||
|- bgcolor="#eeeeee"
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.

||
|- bgcolor="#eeeeee"
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
NATIVE is the default mode and does not require a ROM.

||
|- bgcolor="#eeeeee"
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.

||
|- bgcolor="#eeeeee"
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
sb800 RAID mode must have the two required ROM files.

||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.

||
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||
0x0 = Native IDE mode.
0x1 = RAID mode.
0x2 = AHCI mode.
0x3 = Legacy IDE mode.
0x4 = IDE->AHCI mode.
0x5 = AHCI mode as 7804 ID (AMD driver).
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

||
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || ||
n = Disable PCI Bridge Device 14 Function 4.
y = Enable PCI Bridge Device 14 Function 4.

||
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||
Set SCI IRQ to 9.

||
|- bgcolor="#eeeeee"
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
Select this option to add a CMC state machine binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

||
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
The path and filename of the file to use as CMC state machine
binary.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
this unless you're sure you don't want the briges setup for VGA.

||
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
Execute VGA option ROMs, if found. This is required to enable
PCI/AGP/PCI-E video cards.

||
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
Execute non-VGA PCI option ROMs, if found.

Examples include IDE/SATA controller option ROMs and option ROMs
for network cards (NICs).

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||
If you select this option, PCI option ROMs will be executed
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.

This option prevents option ROMs from doing dirty tricks with the
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native option ROM initialization
method.

This is the default choice for non-x86 systems.

||
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||
Per default, YABEL only allows option ROMs to access the PCI device
that they are associated with. However, this causes trouble for some
onboard graphics chips whose option ROM needs to reconfigure the
north bridge.

||
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||
YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.

||
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||
YABEL consists of two parts: It uses x86emu for the CPU emulation and
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).

When choosing this option, x86emu will pass through all hardware
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||
ACPI Embedded Controller interface. Mostly found in laptops.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Generic Drivers || || || ||
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 will work.
NOTE: Right now you have to set the base address of your OXPCIe952
card to exactly the value that the device allocator would set them
later on, or serial console functionality will stop as soon as the
resource allocator assigns a new base address to the device.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
for the OXPCIe952 controller.

||

||
||
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Console || || || ||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
Send coreboot debug output to an I/O mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||
Send coreboot debug output to a memory mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
Serial console on COM1/ttyS0 at I/O port 0x3f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
Serial console on COM2/ttyS1 at I/O port 0x2f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
Serial console on COM3/ttyS2 at I/O port 0x3e8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
Serial console on COM4/ttyS3 at I/O port 0x2e8.

||
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex || ||
Map the COM port names to the respective I/O port.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
Set serial port Baud rate to 115200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
Set serial port Baud rate to 57600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
Set serial port Baud rate to 38400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
Set serial port Baud rate to 19200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
Set serial port Baud rate to 9600.

||
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int || ||
Map the Baud rates to an integer.

||
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||
This option allows you to use a so-called USB EHCI Debug device
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Linux "EHCI Debug Device gadget" driver found in recent kernel)
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI
Debug Port capability.

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||
This option selects which physical USB port coreboot will try to
use as EHCI Debug Port first (valid values are: 1-15).

If coreboot doesn't detect an EHCI Debug Port dongle on this port,
it will try all the other ports one after the other. This will take
a few seconds of time though, and thus slow down the booting process.

Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
actual port on your mainboard (potentially also USB pin headers
on your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.

||
|- bgcolor="#eeeeee"
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||
If not selected, the last adapter found will be used.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
Send coreboot debug output to a Ethernet console, it works
same way as Linux netconsole, packets are received to UDP
port 6666 on IP/MAC specified with options bellow.
Use following netcat command: nc -u -l -p 6666

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
Type in either MAC address of logging system or MAC address
of the router.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
This is IP adress of the system running for example
netcat command to dump the packets.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
This is the IP of the coreboot system

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
This is the IO port address for the IO port
on the card, please select some non-conflicting region,
32 bytes of IO spaces will be used (and align on 32 bytes
boundary, qemu needs broader align)

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||
If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the debug console.

||

|- bgcolor="#eeeeee"
| HAVE_HARD_RESET || toplevel || bool || ||
This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.

||
|- bgcolor="#eeeeee"
| HAVE_OPTION_TABLE || toplevel || bool || ||
This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.

||
|- bgcolor="#eeeeee"
| VGA || toplevel || bool || ||
Build board-specific VGA code.

||
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool || ||
Enable Unified Memory Architecture for graphics.

||
|- bgcolor="#eeeeee"
| HAVE_ACPI_TABLES || toplevel || bool || ||
This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
is configurable by the user via GENERATE_ACPI_TABLES.

||
|- bgcolor="#eeeeee"
| HAVE_MP_TABLE || toplevel || bool || ||
This variable specifies whether a given board has MP table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the MP table is actually generated by coreboot
is configurable by the user via GENERATE_MP_TABLE.

||
|- bgcolor="#eeeeee"
| HAVE_PIRQ_TABLE || toplevel || bool || ||
This variable specifies whether a given board has PIRQ table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.

||
|- bgcolor="#6699dd"
! align="left" | Menu: System tables || || || ||
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
Generate ACPI tables for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
Generate a PIRQ table for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||
Generate SMBIOS tables for this board.

If unsure, say Y.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Payload || || || ||
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
Select this option if you have a payload image (an ELF file)
which coreboot should run as soon as the basic hardware
initialization is completed.

You will be able to specify the location and file name of the
payload image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||
Select this option if you want to build a coreboot image
with a SeaBIOS payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| PAYLOAD_FILO || toplevel || bool || FILO ||
Select this option if you want to build a coreboot image
with a FILO payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || stable ||
Stable SeaBIOS version
||
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||
Newest SeaBIOS version
||
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||
Stable FILO version
||
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||
Newest FILO version
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||
The path and filename of the ELF executable file to use as payload.

||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.

||

|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
Select this option if you have a VGA BIOS image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
The path and filename of the file to use as VGA BIOS.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).

||
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||
Select this option if you have an Intel MBI image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| MBI_FILE || toplevel || string || Intel MBI path and filename ||
The path and filename of the file to use as VGA BIOS.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Display || || || ||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || toplevel || bool || Set VESA framebuffer mode ||
Set VESA framebuffer mode (needed for bootsplash)

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||
This option sets the resolution used for the coreboot framebuffer (and
bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
some day make this a "choice".

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_KEEP_VESA_MODE || toplevel || bool || Keep VESA framebuffer ||
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||
This option shows a graphical bootsplash screen. The grapics are
loaded from the CBFS file bootsplash.jpg.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
||

|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.

||
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
This option enables additional CAR related debug messages.
||
|- bgcolor="#eeeeee"
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
This option enables additional SMM handler relocation related
debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||
This option enables additional ACPI related debug messages.

Note: This option will slightly increase the size of the coreboot image.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
Print messages related to accesses to certain areas of the virtual
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
Print memory accesses made by option ROM.
Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| LLSHELL || toplevel || bool || Built-in low-level shell ||
If enabled, you will have a low level shell to examine your machine.
Put llshell() in your (romstage) code to start the shell.
See src/arch/x86/llshell/llshell.inc for details.

||
|- bgcolor="#eeeeee"
| TRACE || toplevel || bool || Trace function calls ||
If enabled, every function will print information to console once
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
of calling function. Please note some printk releated functions
are omitted from trace to have good looking console dumps.
||

|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex || ||
Select when the board has a power button which can optionally be
disabled by the user.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex || ||
Select when the board has a power button which can optionally be
enabled by the user, e.g. when the board ships with a jumper over
the power switch contacts.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex || ||
Select when the board requires that the power button is always
enabled.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex || ||
Select when the board requires that the power button is always
disabled, e.g. when it has been hardwired to ground.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool || ||
Internal option that controls ENABLE_POWER_BUTTON visibility.

||
|- bgcolor="#6699dd"
! align="left" | Menu: Deprecated || || || ||
|- bgcolor="#eeeeee"
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a reset.c
file containing a hard_reset() function.

||
|- bgcolor="#eeeeee"
| BOARD_HAS_FADT || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a board-local
FADT in fadt.c. Long-term, those should be moved to appropriate
chipset components (eg. southbridge).

||
|- bgcolor="#eeeeee"
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a get_bus_conf.c
file containing information about bus routing.

||
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init ||
Enable this option to initialize PS/2 keyboards found connected
to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads
(eg, SeaBIOS, Linux) do not require it.
Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require
this option, then you can say N here to speed up boot time.
Otherwise say Y.

||
|- bgcolor="#eeeeee"
| PCIE_TUNING || toplevel.deprecated_options || bool || ||
This variable enables certain PCIe optimizations. Right now it's
only ASPM and it's untested.

||

|}

Build HOWTO

2011-10-13T22:44:36Z

Uwe: /* Building coreboot */

[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]

This page describes how you can build a coreboot image for your specific mainboard.

== Requirements ==

* gcc / g++
* make
* ncurses-dev (for '''make menuconfig''')

Optional:

* doxygen (for generating/viewing documentation)
* iasl (for targets with ACPI support)
* gdb (for better debugging facilities on some targets)
* flex and bison (for regenerating parsers)

== Building a payload ==

First you need to download the source code for the [[Payloads|payload]] of your choice and build it.

Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.

The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).

== Building coreboot ==

First, get the latest coreboot version from [[Git|our git repository]]:

$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''
$ '''cd coreboot'''

In the coreboot directory you can configure the build-time options of coreboot:

$ '''make menuconfig'''

In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:

* Enter the '''Mainboard''' menu.
** In '''Mainboard vendor''' select the vendor of your board.
** In '''Mainboard model''' select your exact mainboard name.
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.
* Enter the '''Payload''' menu.
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.
*** Then, specify the file name and path to your payload file (which you built before).

That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:

$ '''make'''

The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.

== Known issue ==

With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:

src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards

This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run

$ '''make crossgcc'''

Then remove the '''.xcompile''' file and retry the compilation process:

$ '''rm .xcompile'''
$ '''make'''

== Flashing coreboot ==

You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.

Superiotool

2011-09-11T22:35:15Z

Uwe: /* Support of various devices */ Fintek F71889 log.

'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.

This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.

<gallery>
Image:Ite it8705f.jpg|ITE IT8705F
Image:Winbond w83977ef.jpg|Winbond W83977EF
</gallery>

== Support of various devices ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ALi
| M1535/M1535D/M1535+/M1535D+
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5105
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5107
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5109
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5113
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5119
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M512x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513x
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xB
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M514x
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ASUS
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]
| —

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71862FG / F71863FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71889
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/attachments/20110515/b04d0142/attachment-0005.ksh 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71872F/FG / F71806F/FG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71882FG/F71883FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F8000
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C711
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C712
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C721
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C735
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8228E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8502E/F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8510E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8511E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8512E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8661F/IT8770F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F/IT8687R
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8673F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT86793
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8702F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8703F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8705F/AF / IT8700F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8706R
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8708F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8710F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8711F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8718F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8720F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8721F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8722F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8726F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8761E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8780F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| HMC
| HMC83755
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Holtek
| HT6552IR
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS307
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS308
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS309
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS317
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS338
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS351
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97307
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87309
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87360
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87351
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87364
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87365
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87363
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87366
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87382
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8739x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87591x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8741x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87372
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8374L
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87427
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87373
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| WPCE775x / NPCE781x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| WPCM450
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| NCT6776F (B)
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| NCT6776F (C)
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xFR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N971
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N972
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N252
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M172
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xAPM
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C67x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B80x/FDC37M707
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N958FR
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B77x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B78x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M602
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M60x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B72x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M81x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B27x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B37x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47U33x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B34x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S42x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M10x/112/13x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B357
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M14x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M15x/192/997
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S45x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M292
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B387
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B397
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M182
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M584
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| MEC1308
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| DME1737
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5504
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N217
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5514D-NS
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3112
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3114
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3116
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5317
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5027
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH4307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669FR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N237
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N769
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N3869/FDC37N869
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N227
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SIO10N268
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C665GT/IR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C666GT
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| SiS
| SIS6801
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS950
| style="background:red" | No
| style="background:red" | No
| —
| —

|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686A/VT82C686B
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977CTF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977EF/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83527HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627SF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697HF/F/HG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83L517D/D-F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83637HF/HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627THF/THG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG-P/-PT
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627UHG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83667HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977F-A/G-A/AF-A/AG-A
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977AF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977TF
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627HF/F/HG/G
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697SF/UF/UG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627EHF/EF/EHG/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877AF
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877TF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| WPCD376I
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| UMC
| UM82C862
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8663BF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8669
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8670
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

|}

'''Extended dumps (EC, HWM) available for:'''

Use the '''--extra-dump''' option to see the contents of these registers.

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| Winbond
| W83627THF/THG HWM
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|- bgcolor="#eeeeee" valign="top"
| SMSC
| LPC47N227 runtime register block
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}


1 Previosly National Semiconductor, now bought by Winbond. 
2 Register dump output from a running coreboot system (vs. proprietary BIOS). 


== Installation ==

'''Manual installation'''

$ git clone http://review.coreboot.org/p/coreboot
$ cd coreboot/util/superiotool
$ make
$ sudo make install

'''Debian / Ubuntu'''

$ apt-get install superiotool

'''Fedora'''

$ yum install superiotool

== Usage ==

Probe/detect the Super I/O in your mainboard:

$ superiotool

Register dump as table of hex-values (if the Super I/O is detected):

$ superiotool -d

Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.

{{GPL}}

ASRock E350M1

2011-07-02T19:43:06Z

Uwe: Small fixes.

== Status ==

{{Status|

|CPU_status = OK
|CPU_comments =
|CPU_L1_status = OK
|CPU_L1_comments =
|CPU_L2_status = OK
|CPU_L2_comments =
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = OK
|CPU_multicore_comments = Both cores seem to be detected.
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = N/A
|RAM_DDR3_status = WIP
|RAM_DDR3_comments = 2GB working properly, >=4GB reported incorrectly. Work in progress.
|RAM_dualchannel_status = N/A
|RAM_ecc_status = N/A
|RAM_ecc_comments =

|Onboard_SCSI_status = N/A
|IDE_status = N/A
|IDE_comments =
|IDE_25_status = N/A
|IDE_CF_status = Untested
|CDROM_DVD_status = Untested
|SATA_status = OK
|USB_status = WIP
|USB_comments = Mass storage devices will seldom mount and generate errors in dmesg.
|Onboard_VGA_status = OK
|Onboard_VGA_comments = Must add VBIOS.
|Onboard_ethernet_status = OK
|Onboard_audio_status = OK
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A

|Mini_PCI_cards_status = N/A
|PCIX_cards_status = N/A
|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = N/A
|PCIE_x1_status = Untested
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = ?
|PCIE_x16_comments =
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = N/A
|COM1_status = OK
|COM2_status = N/A
|PS2_keyboard_status = Untested
|PS2_mouse_status = Untested
|PP_status = N/A
|PP_comments =
|Game_port_status = N/A
|IR_status = ?
|Speaker_status = ?
|DiskOnChip_status = N/A

|Sensors_status = OK
|Sensors_comments = CPU temperature seems to be displayed properly by lm-sensors.
|CAN_bus_status = N/A
|CPUfreq_status = Untested
|CPUfreq_comments = CPU might report (or have) wrong frequency.
|Powersave_status = ?
|ACPI_status = ?
|ACPI_comments =
|Reboot_status = OK
|Poweroff_status = OK
|LEDs_status = N/A
|HPET_status = Unknown
|RNG_status = ?
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = OK

}}

Welcome to coreboot

2011-06-24T16:49:28Z

Uwe: Use gitweb for "Browse Source", svn is obsolete.

<table width="100%" valign="top"><tr valign="top"><td width="80%">

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
'''coreboot''' is a Free Software project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.


coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029133.html LinuxBIOS].

</div>

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
coreboot recently switched to [[git]] and [http://review.coreboot.org gerrit] is now used as patch review tool.
</div>

{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%
|-
|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = yellow|
WIDTH = 100%|
ICON = [[Benefits|More...]]|
HEADING = [[Benefits]]|
CONTENT =

* 100% Free Software (GPL), no royalties, no license fees!
* Fast boot times (3 seconds to Linux console)



* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]


}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = #d1adf6|
WIDTH = 100%|
ICON = [[Use Cases|More...]]|
HEADING = [[Use Cases]]|
CONTENT =

* Desktop PCs, servers, [[Laptop|laptops]]
* [[Clusters]]

* Embedded solutions




}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = lime|
WIDTH = 100%|
ICON = [[Payloads|More...]]|
HEADING = [[Payloads]]|
CONTENT =

* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] 
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] 
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]


}}

|}

{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_cb.png]]
|style="vertical-align:top"|
'''About''' Find out more about coreboot.<hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_devel.png]]
|style="vertical-align:top"|
'''Developers''' Get involved! Help us make coreboot better.<hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree Browse Source] | [[GSoC]] | [[Flag Days]] | [[Distributed and Automated Testsystem|Testsystem]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_status.png]]
|style="vertical-align:top"|
'''Status''' Find out whether your hardware is already supported.<hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_tools.png]]
|style="vertical-align:top"|
'''Related Tools''' Tools and libraries related to coreboot.<hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_101.png]]
|style="vertical-align:top"|
'''Getting Started''' Download coreboot and get started.<hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_support.png]]
|style="vertical-align:top"|
'''Support''' Learn how to contact us and find help and support.<hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]
|}

|}
</td><td width="20%">

[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]

 

'''[http://blogs.coreboot.org News (blog)]'''<hr />

<rss max=5>http://blogs.coreboot.org/feed/</rss>


'''[[Current events|Upcoming Events]]'''<hr />



* '''2011/05/11-14:''' coreboot and [[Flashrom|flashrom]] booths at [http://www.linuxtag.org/ LinuxTag] in Berlin
* [[GSoC|2011 Google Summer of Code]]


 
{{#widget:Ohloh Project|id=coreboot|type=partner_badge}}
{{#widget:Ohloh Project|id=coreboot|type=cocomo}}

</td></tr></table>

__NOTOC__
__NOEDITSECTION__

Coreboot Options

2011-06-23T16:49:18Z

Uwe: Update coreboot option list.

This is an automatically generated list of '''coreboot compile-time options'''.

Last update: 2011/06/23 18:44:41.
{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Option
! align="left" | Source
! align="left" | Format
! align="left" | Short Description
! align="left" | Description
|- bgcolor="#6699dd"
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
| EXPERT || toplevel || bool || Expert mode ||
This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are
doing! You have been warned!

||
|- bgcolor="#eeeeee"
| LOCALVERSION || toplevel || string || Local version string ||
Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler ||
This option allows you to select the compiler used for building
coreboot.

||
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||
Changes the build process to scan-build is used.
Requires scan-build in path.

||
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||
Where the scan-build report should be stored

||
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || ccache ||
Enables the use of ccache for faster builds.
Requires ccache in path.

||
|- bgcolor="#eeeeee"
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||
Enable this option if you are working on the sconfig
device tree parser and made changes to sconfig.l and
sconfig.y.
Otherwise, say N.

||
|- bgcolor="#eeeeee"
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.

||
|- bgcolor="#eeeeee"
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow Link (i.e. SPI)

||
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||
Include in CBFS the coreboot config file that was used to compile the ROM image

||

|- bgcolor="#6699dd"
! align="left" | Menu: Mainboard || || || ||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||
The following X60 series ThinkPad machines have been verified to
work correctly:

ThinkPad X60s (Model 1702, 1703)
ThinkPad X60 (Model 1709)

||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||
The following T60 series ThinkPad machines have been verified to
work correctly:

Thinkpad T60p (Model 2007)

||
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
Look on the bottom side for a number like 406-0001-30. The last 2
digits state the PCB revision (3.0 in this example). For 2.0 or older
boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to
power on automatically. You may enable the button only after this
jumper has been removed. New revision boards are not restricted
in this way, and always have the power button enabled.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
If selected, the on-board SSD will act as IDE Slave instead of Master.

||
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||
Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file
of the matching size.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
Choose this option if you have a 128 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
Choose this option if you have a 256 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
Choose this option if you have a 512 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
Choose this option if you have a 1024 KB (1 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
Choose this option if you have a 2048 KB (2 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
Choose this option if you have a 4096 KB (4 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
Choose this option if you have a 8192 KB (8 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
Choose this option if you have a 16384 KB (16 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
The selected mainboard can optionally have the power button tied
to ground with a jumper so that the button appears to be
constantly depressed. If this option is enabled and the jumper is
installed then the board will turn on, but turn off again after a
short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an
actual power button. Select N if you have the jumper installed.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Architecture (x86) || || || ||
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Chipset || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||
Select this to apply patches to the CPU microcode provided by
AMD without source, and distributed with coreboot, to address
issues in the CPU post production.

Microcode updates distributed with coreboot are not necessarily
the latest version available from AMD. Updates are only applied
if they are newer than the microcode already in your CPU.

Unselect this to let Fam10h CPUs run with microcode as shipped
from factory. No binary microcode patches will be included in the
coreboot image in that case, which can help with creating an image
for which complete source code is available, which in turn might
simplify license compliance.

Microcode updates intend to solve issues that have been discovered
after CPU production. The common case is that systems work as
intended with updated microcode, but we have also seen cases where
issues were solved by not applying the microcode updates.

Note that some operating system include these same microcode
patches, so you may need to also disable microcode updates in
your operating system in order for this option to matter.

||
||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||
Select this option if you have an AMD Geode GX2 vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||
Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| SMP || cpu || bool || ||
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.

||
|- bgcolor="#eeeeee"
| MMX || cpu || bool || ||
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.

||
|- bgcolor="#eeeeee"
| SSE || cpu || bool || ||
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.

||
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool || ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.

||
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool || ||
Unset this if you don't want the MTRR code to use
subtractive MTRRs

||
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

||
|- bgcolor="#6699dd"
! align="left" | Menu: HyperTransport setup || || || ||
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||
This option sets the maximum permissible HyperTransport link
frequency.

Use of this option will only limit the autodetected HT frequency.
It will not (and cannot) increase the frequency beyond the
autodetected limits.

This is primarily used to work around poorly designed or laid out
HT traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||
This option sets the maximum permissible HyperTransport
downlink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||
This option sets the maximum permissible HyperTransport
uplink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||

|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||
This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.

If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.

||
||
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.

||
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Geode GX1 video support || || || ||

|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||
Select if RS690 should be setup to support MMCONF.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||
Select the mode in which SATA should be driven. IDE or AHCI.
The default is IDE.

config SATA_MODE_IDE
bool "IDE"

config SATA_MODE_AHCI
bool "AHCI"
||
|- bgcolor="#eeeeee"
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
Select this option to add a CMC state machine binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

||
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
The path and filename of the file to use as CMC state machine
binary.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
this unless you're sure you don't want the briges setup for VGA.

||
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
Execute VGA option ROMs, if found. This is required to enable
PCI/AGP/PCI-E video cards.

||
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
Execute non-VGA PCI option ROMs, if found.

Examples include IDE/SATA controller option ROMs and option ROMs
for network cards (NICs).

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||
If you select this option, PCI option ROMs will be executed
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.

This option prevents option ROMs from doing dirty tricks with the
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native option ROM initialization
method.

This is the default choice for non-x86 systems.

||
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||
Per default, YABEL only allows option ROMs to access the PCI device
that they are associated with. However, this causes trouble for some
onboard graphics chips whose option ROM needs to reconfigure the
north bridge.

||
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||
YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.

||
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||
YABEL consists of two parts: It uses x86emu for the CPU emulation and
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).

When choosing this option, x86emu will pass through all hardware
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||
ACPI Embedded Controller interface. Mostly found in laptops.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Generic Drivers || || || ||
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 will work.
NOTE: Right now you have to set the base address of your OXPCIe952
card to exactly the value that the device allocator would set them
later on, or serial console functionality will stop as soon as the
resource allocator assigns a new base address to the device.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
for the OXPCIe952 controller.

||

||
||
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Console || || || ||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
Send coreboot debug output to an I/O mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||
Send coreboot debug output to a memory mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
Serial console on COM1/ttyS0 at I/O port 0x3f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
Serial console on COM2/ttyS1 at I/O port 0x2f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
Serial console on COM3/ttyS2 at I/O port 0x3e8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
Serial console on COM4/ttyS3 at I/O port 0x2e8.

||
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex || ||
Map the COM port names to the respective I/O port.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
Set serial port Baud rate to 115200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
Set serial port Baud rate to 57600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
Set serial port Baud rate to 38400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
Set serial port Baud rate to 19200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
Set serial port Baud rate to 9600.

||
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int || ||
Map the Baud rates to an integer.

||
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||
This option allows you to use a so-called USB EHCI Debug device
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Linux "EHCI Debug Device gadget" driver found in recent kernel)
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI
Debug Port capability.

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||
This option selects which physical USB port coreboot will try to
use as EHCI Debug Port first (valid values are: 1-15).

If coreboot doesn't detect an EHCI Debug Port dongle on this port,
it will try all the other ports one after the other. This will take
a few seconds of time though, and thus slow down the booting process.

Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
actual port on your mainboard (potentially also USB pin headers
on your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.

||
|- bgcolor="#eeeeee"
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||
If not selected, the last adapter found will be used.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
Send coreboot debug output to a Ethernet console, it works
same way as Linux netconsole, packets are received to UDP
port 6666 on IP/MAC specified with options bellow.
Use following netcat command: nc -u -l -p 6666

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
Type in either MAC address of logging system or MAC address
of the router.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
This is IP adress of the system running for example
netcat command to dump the packets.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
This is the IP of the coreboot system

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
This is the IO port address for the IO port
on the card, please select some non-conflicting region,
32 bytes of IO spaces will be used (and align on 32 bytes
boundary, qemu needs broader align)

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||
If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the debug console.

||

|- bgcolor="#eeeeee"
| HAVE_HARD_RESET || toplevel || bool || ||
This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.

||
|- bgcolor="#eeeeee"
| HAVE_OPTION_TABLE || toplevel || bool || ||
This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.

||
|- bgcolor="#eeeeee"
| VGA || toplevel || bool || ||
Build board-specific VGA code.

||
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool || ||
Enable Unified Memory Architecture for graphics.

||
|- bgcolor="#eeeeee"
| HAVE_ACPI_TABLES || toplevel || bool || ||
This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
is configurable by the user via GENERATE_ACPI_TABLES.

||
|- bgcolor="#eeeeee"
| HAVE_MP_TABLE || toplevel || bool || ||
This variable specifies whether a given board has MP table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the MP table is actually generated by coreboot
is configurable by the user via GENERATE_MP_TABLE.

||
|- bgcolor="#eeeeee"
| HAVE_PIRQ_TABLE || toplevel || bool || ||
This variable specifies whether a given board has PIRQ table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.

||
|- bgcolor="#6699dd"
! align="left" | Menu: System tables || || || ||
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
Generate ACPI tables for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
Generate a PIRQ table for this board.

If unsure, say Y.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Payload || || || ||
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
Select this option if you have a payload image (an ELF file)
which coreboot should run as soon as the basic hardware
initialization is completed.

You will be able to specify the location and file name of the
payload image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||
Select this option if you want to build a coreboot image
with a SeaBIOS payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| PAYLOAD_FILO || toplevel || bool || FILO ||
Select this option if you want to build a coreboot image
with a FILO payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || stable ||
Stable SeaBIOS version
||
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||
Newest SeaBIOS version
||
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||
Stable FILO version
||
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||
Newest FILO version
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||
The path and filename of the ELF executable file to use as payload.

||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.

||

|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
Select this option if you have a VGA BIOS image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
The path and filename of the file to use as VGA BIOS.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).

||
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||
Select this option if you have an Intel MBI image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| MBI_FILE || toplevel || string || Intel MBI path and filename ||
The path and filename of the file to use as VGA BIOS.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Bootsplash || || || ||
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||
This option shows a graphical bootsplash screen. The grapics are
loaded from the CBFS file bootsplash.jpg.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||
This option sets the resolution used for the coreboot framebuffer and
bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
some day make this a "choice".

||
|- bgcolor="#eeeeee"
| COREBOOT_KEEP_FRAMEBUFFER || toplevel || bool || Keep VESA framebuffer ||
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.

||
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
This option enables additional CAR related debug messages.
||
|- bgcolor="#eeeeee"
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
This option enables additional SMM handler relocation related
debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
Print messages related to accesses to certain areas of the virtual
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
Print memory accesses made by option ROM.
Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| LLSHELL || toplevel || bool || Built-in low-level shell ||
If enabled, you will have a low level shell to examine your machine.
Put llshell() in your (romstage) code to start the shell.
See src/arch/x86/llshell/llshell.inc for details.

||

|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex || ||
Select when the board has a power button which can optionally be
disabled by the user.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex || ||
Select when the board has a power button which can optionally be
enabled by the user, e.g. when the board ships with a jumper over
the power switch contacts.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex || ||
Select when the board requires that the power button is always
enabled.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex || ||
Select when the board requires that the power button is always
disabled, e.g. when it has been hardwired to ground.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool || ||
Internal option that controls ENABLE_POWER_BUTTON visibility.

||
|- bgcolor="#6699dd"
! align="left" | Menu: Deprecated || || || ||
|- bgcolor="#eeeeee"
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a reset.c
file containing a hard_reset() function.

||
|- bgcolor="#eeeeee"
| BOARD_HAS_FADT || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a board-local
FADT in fadt.c. Long-term, those should be moved to appropriate
chipset components (eg. southbridge).

||
|- bgcolor="#eeeeee"
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a get_bus_conf.c
file containing information about bus routing.

||
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init ||
Enable this option to initialize PS/2 keyboards found connected
to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads
(eg, SeaBIOS, Linux) do not require it.
Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require
this option, then you can say N here to speed up boot time.
Otherwise say Y.

||
|- bgcolor="#eeeeee"
| PCIE_TUNING || toplevel.deprecated_options || bool || ||
This variable enables certain PCIe optimizations. Right now it's
only ASPM and it's untested.

||

|}

Build HOWTO

2011-06-23T15:22:16Z

Uwe: /* Known issue */ Remove .xcompile before rebuild.

[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]

This page describes how you can build a coreboot image for your specific mainboard.

== Requirements ==

* gcc / g++
* make
* ncurses-dev (for '''make menuconfig''')

Optional:

* doxygen (for generating/viewing documentation)
* iasl (for targets with ACPI support)
* gdb (for better debugging facilities on some targets)
* flex and bison (for regenerating parsers)

== Building a payload ==

First you need to download the source code for the [[Payloads|payload]] of your choice and build it.

Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.

The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).

== Building coreboot ==

First, get the latest coreboot version from [[Git|our git repository]]:

$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''
$ '''cd coreboot'''

In the coreboot directory you can configure the build-time options of coreboot:

$ '''make menuconfig'''

In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:

* Enter the '''Mainboard''' menu.
** In '''Mainboard vendor''' select the vendor of your board.
** In '''Mainboard model''' select your exact mainboard name.
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.
* Enter the '''Payload''' menu.
** Set the '''Add a payload''' option to '''An ELF executable payload'''.
** Then, specify the file name and path to your payload file (which you built before).

That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:

$ '''make'''

The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.

== Known issue ==

With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:

src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards

This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run

$ '''make crossgcc'''

Then remove the '''.xcompile''' file and retry the compilation process:

$ '''rm .xcompile'''
$ '''make'''

== Flashing coreboot ==

You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.

Build HOWTO

2011-06-23T15:20:23Z

Uwe: Small fixes.

[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]

This page describes how you can build a coreboot image for your specific mainboard.

== Requirements ==

* gcc / g++
* make
* ncurses-dev (for '''make menuconfig''')

Optional:

* doxygen (for generating/viewing documentation)
* iasl (for targets with ACPI support)
* gdb (for better debugging facilities on some targets)
* flex and bison (for regenerating parsers)

== Building a payload ==

First you need to download the source code for the [[Payloads|payload]] of your choice and build it.

Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.

The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).

== Building coreboot ==

First, get the latest coreboot version from [[Git|our git repository]]:

$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''
$ '''cd coreboot'''

In the coreboot directory you can configure the build-time options of coreboot:

$ '''make menuconfig'''

In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:

* Enter the '''Mainboard''' menu.
** In '''Mainboard vendor''' select the vendor of your board.
** In '''Mainboard model''' select your exact mainboard name.
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.
* Enter the '''Payload''' menu.
** Set the '''Add a payload''' option to '''An ELF executable payload'''.
** Then, specify the file name and path to your payload file (which you built before).

That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:

$ '''make'''

The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.

== Known issue ==

With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:

src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards

This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run

$ '''make crossgcc'''

Then retry the compilation process:

$ '''make'''

== Flashing coreboot ==

You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.

Datasheets

2011-06-10T07:44:13Z

Uwe: /* AMD */ Fix dead URL.

This page lists '''publically available datasheets''' and programming guides from various vendors. It includes CPU, chipset, Super I/O, and many other datasheets.

= x86 architecture =

== AMD ==

AMD provides their [http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.1&product=5.7&contentType=Tech+Doc+Processor&ostype=&keywords=&items=20 AMD64 Architecture and Software manuals], which are a very useful reference for AMD systems, of course (but also explain lots of non-AMD-specific x86 stuff too):

* [http://support.amd.com/us/Processor_TechDocs/24592.pdf Volume 1: Application Programming]
* [http://support.amd.com/us/Processor_TechDocs/24593.pdf Volume 2: System Programming 24593]
* [http://support.amd.com/us/Processor_TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26568.pdf Volume 4: 128-Bit Media Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26569.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions]
* [http://support.amd.com/us/Processor_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions]

Other AMD documents:
* [http://support.amd.com/us/Processor_TechDocs/43724.pdf Lightweight Profiling Specification]
* [http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf AMD I/O Virtualization Technology (IOMMU) Specification]
* [http://support.amd.com/us/Processor_TechDocs/32200.pdf Open Platform Management Architecture Specification]
* [http://support.amd.com/us/Processor_TechDocs/25481.pdf CPUID Specification]
* [http://support.amd.com/us/Processor_TechDocs/41918.pdf Advanced Platform Management Link (APML) Specification]

== Intel ==

Intel provides their [http://developer.intel.com/products/processor/manuals/index.htm Intel® 64 and IA-32 Architectures Software Developer's Manuals] which are a very useful reference to the x86 architecture in general:

* [http://developer.intel.com/Assets/PDF/manual/253665.pdf Volume 1: Basic Architecture]
* [http://developer.intel.com/Assets/PDF/manual/253666.pdf Volume 2A: Instruction Set Reference, A-M]
* [http://developer.intel.com/Assets/PDF/manual/253667.pdf Volume 2B: Instruction Set Reference, N-Z]
* [http://developer.intel.com/Assets/PDF/manual/253668.pdf Volume 3A: System Programming Guide]
* [http://developer.intel.com/Assets/PDF/manual/253669.pdf Volume 3B: System Programming Guide]
* [http://www.intel.com/Assets/PDF/manual/252046.pdf Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes]

Other Intel documents:

* [http://www.intel.com/Assets/PDF/manual/318148.pdf Intel® 64 Architecture x2APIC Specification]
* [http://www.intel.com/Assets/PDF/manual/248966.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual]
* [http://www.intel.com/Assets/PDF/manual/323640.pdf Intel® Carry-Less Multiplication Instruction and its Usage for Computing the GCM Mode White Paper]
* [http://www.intel.com/Assets/PDF/manual/323641.pdf Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Set White Paper]
* [http://www.intel.com/Assets/PDF/manual/323850.pdf Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) Application Note]

= CPU =

== AMD ==

=== AMD Fam14 ===

* [http://support.amd.com/us/Embedded_TechDocs/43170.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Processors]
** [http://support.amd.com/us/Embedded_TechDocs/47534.pdf Revision Guide for AMD Family 14h Processors]

=== AMD Fam11h ===

* [http://support.amd.com/us/Processor_TechDocs/41256.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/41788.pdf Revision Guide for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/43373.pdf AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks]

Turion64:
* [http://support.amd.com/us/Processor_TechDocs/32816.pdf AMD Turion™ 64 Mobile Technology Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/41407.pdf AMD Turion™ 64 X2 Mobile Technology Dual-Core Processor Product Data Sheet]

Athlon64:
* [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]

=== AMD Fam10h ===

* [http://support.amd.com/us/Processor_TechDocs/31116.pdf BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h]
** [http://support.amd.com/us/Processor_TechDocs/41322.pdf Revision Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/40546-PUB-Optguide_3-11_5-21-09.pdf Software Optimization Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/43374.pdf AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/43375.pdf AMD Family 10h Desktop Processor Power and Thermal Data Sheet]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/40036.pdf Family 10h AMD Opteron Processor Product Data Sheet]

Phenom:
* [http://support.amd.com/us/Processor_TechDocs/44109.pdf Family 10h AMD Phenom™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/46878.pdf Family 10h AMD Phenom™ II Processor Product Data Sheet]

=== AMD K8 ===

Athlon64/Opteron:
* [http://support.amd.com/us/Processor_TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/25759.pdf Revision Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/26633_5649.pdf AMD Athlon™ and AMD Opteron™ Processors Thermal Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/40555.pdf Performance Guidelines for AMD Athlon™ and AMD Opteron™ ccNUMA Multiprocessor Systems]
* [http://support.amd.com/us/Processor_TechDocs/24707_PUB.PDF Clock Generator Specification for AMD Athlon™ and AMD Opteron™ Processors]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/23932.pdf AMD Opteron™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30417.pdf AMD Opteron™ Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/40820_PUB_AMD_Opteron_Processor_Production_Notice_rev_3_08.pdf AMD Opteron™ x52 and x54 Production Notice]
* [http://support.amd.com/us/Processor_TechDocs/30925.pdf Builders Guide for AMD Opteron™ Processor-Based Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/33340.pdf AMD Opteron™ Multiprocessor Systems Running Linux Technical Bulletin for AMD OEMs and Partners]

Family 0Fh:
* [http://support.amd.com/us/Processor_TechDocs/32559.pdf BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/33610.pdf Revision Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/31119.pdf AMD NPT Family 0Fh Processor Electrical Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/33954.pdf AMD NPT Family 0Fh Desktop Processor Power and Thermal Data Sheet]

=== Athlon64 ===

* [http://support.amd.com/us/Processor_TechDocs/24659.pdf AMD Athlon™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31783.pdf AMD Athlon™ Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/43042.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/33425.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet] (ver 3.10, 1/21/2007)
** [http://support.amd.com/us/Processor_TechDocs/42989.pdf AMD Athlon™ X2 Dual-Core Processor for Notebooks Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/30431.pdf AMD Athlon™ FX Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31366.pdf AMD Athlon™ FX-60 Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31225.pdf Mobile AMD Athlon™ Processor 3400+ Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31684.pdf Builder's Guide for AMD Athlon™ Processor-Based Desktops and Workstations]

=== Athlon (32bit) ===

* [http://support.amd.com/us/Processor_TechDocs/21016.pdf AMD Athlon™ Processor Module Data Sheet] (rev. M-0, 5/31/2000)
** [http://support.amd.com/us/Processor_TechDocs/22054.pdf AMD Athlon™ Processor Technical Brief]
* [http://support.amd.com/us/Processor_TechDocs/26237.PDF AMD Athlon™ XP Processor Model 10 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/27375.pdf AMD Athlon XP Processor Model 10 with 256K L2 Cache]
** [http://support.amd.com/us/Processor_TechDocs/27532.pdf AMD Athlon™ Processor Model 10 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/26426.PDF AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/25175.pdf AMD Athlon™ XP Processor Model 8 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/25703.pdf AMD Athlon™ Processor Model 8 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25722.pdf AMD Athlon™ MP Processor Model 8 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/24685.pdf AMD Athlon™ MP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24309.pdf AMD Athlon™ XP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24332.pdf AMD Athlon™ Processor Model 6 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25480.pdf AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/23792.pdf AMD Athlon™ Processor Model 4 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23614.pdf AMD Athlon™ Processor Model 4 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/22651.pdf AMD Athlon™ Processor Voltage Regulation Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23811.pdf AMD Athlon™ Processor Module Signal and Power-Up Requirements Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25823.pdf Builder’s Guide for 2P Capable Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/25325.pdf System Considerations for Dual AMD Athlon™ MP Processors in Tower and 1U Form Factors]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]
* [http://support.amd.com/us/Processor_TechDocs/24228.pdf Methodologies for Measuring Temperature on AMD Athlon™ and AMD Duron™ Processors]
* [http://support.amd.com/us/Processor_TechDocs/22007.pdf AMD Athlon™ Processor x86 Code Optimization Guide]

=== Sempron ===

* [http://support.amd.com/us/Processor_TechDocs/31805.pdf AMD Sempron™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31994.pdf AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31993.pdf AMD Sempron™ Processor Model 10 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31693.pdf AMD Sempron™ Processor Model 8 Data Sheet]

=== Duron ===

* [http://support.amd.com/us/Processor_TechDocs/TN13.pdf AMD Duron™ Processor Rev. A0: CPUID Reporting of L2 Cache Size]
* [http://support.amd.com/us/Processor_TechDocs/25848.PDF AMD Duron™ Processor Model 8 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/24310.pdf AMD Duron™ Processor Model 7 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24806.pdf AMD Duron™ Processor Model 7 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/23802.pdf AMD Duron™ Processor Model 3 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23865.pdf AMD Duron™ Processor Model 3 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]

=== Socket specs ===

* [http://support.amd.com/us/Processor_TechDocs/25766.pdf AMD Socket 940 Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/31412.pdf AMD Functional Data Sheet, 940 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/30353.pdf AMD Socket 940 Qualification Plan]
* [http://support.amd.com/us/Processor_TechDocs/31700.pdf Socket F (1207) Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/32800.pdf Thermal Design Guide for Socket F (1207) Processors]
* [http://support.amd.com/us/Processor_TechDocs/31875.pdf Socket AM2 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/40523.pdf Socket AM3 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31839.pdf Low-Profile Socket S1 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31410.pdf AMD Functional Data Sheet, 754 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/24850.PDF Socket 754 Design and Qualification Requirements]
* [http://support.amd.com/us/Processor_TechDocs/31411.pdf AMD Functional Data Sheet, 939-Pin Package]
* [http://support.amd.com/us/Processor_TechDocs/23986.pdf Socket A AMD Processor and Heatsink Installation Guide]

=== Misc ===

* [http://support.amd.com/us/Processor_TechDocs/20734.pdf AMD Processor Recognition Application Note]
* [http://support.amd.com/us/Processor_TechDocs/22466.pdf AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets Manual]
* [http://support.amd.com/us/Processor_TechDocs/21928.pdf 3DNow!™Technology Manual]
** [http://support.amd.com/us/Processor_TechDocs/22621.pdf 3DNow!™ Instruction Porting Guide Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23794.pdf AMD Thermal, Mechanical, and Chassis Cooling Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/30579_3_74.pdf AMD Processor Performance Evaluation Guide]
* [http://support.amd.com/us/Processor_TechDocs/32035.pdf Compiler Usage Guidelines for AMD64 Platforms Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors]
* [http://support.amd.com/us/Processor_TechDocs/26951.pdf Thermal Interface Material Comparison: Thermal Pads vs. Thermal Grease]
* [http://support.amd.com/us/Processor_TechDocs/26003.pdf Builders Guide for Desktop/Tower Systems]
* [http://support.amd.com/us/Processor_TechDocs/26698.pdf Linux Kernel Issue with Systems Using AGP Graphics]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/30887.pdf Building AMD64 Applications with the Microsoft Platform SDK]
* [http://support.amd.com/us/Processor_TechDocs/30888.pdf Creating an AMD64 Build Enviroment for DirectX-Based Applations]
* [http://support.amd.com/us/Processor_TechDocs/33609.pdf Processor Utilization with Microsoft® Windows® Media Center Edition on Systems Enabled with Cool'n'Quiet™ and AMD PowerNow™ Technologies]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/tn17.pdf Microsoft Windows® 2000 Patch for AGP Applications on AMD Athlon™ and AMD Duron™ Processors]

== Intel ==

=== Intel Pentium III ===

* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii Highlights/Overview]
* [http://ark.intel.com/ProductCollection.aspx?familyID=590&MarketSegment=DT List of Pentium III models, steppings, etc.]
* [http://www.intel.com/support/processors/pentiumiii/sb/CS-023730.htm Intel® Pentium® III Processor: Datasheets]
** [http://download.intel.com/support/processors/pentiumiii/sb/24965705.pdf Intel® Pentium® III Processor with 512-KB L2 Cache at 1.13GHz to 1.40 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24976503.pdf Intel® Pentium® III Processor Based on 0.13 Micron Process Up to 1.33 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24526408.pdf Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24445209.pdf Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/27367306.pdf Low Voltage Intel® Pentium® III Processor 512-KB] (PDF)
* [http://www.intel.com/design/intarch/specupdt/244453.htm Intel® Pentium® III Processor Specification Update] ([http://download.intel.com/design/intarch/specupdt/24445358.pdf PDF])

Mobile:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-m Highlights/Overview]
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023739.htm Mobile Intel® Pentium® III Processor - M Datasheet] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/29834006.pdf PDF])
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023740.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/24530659.pdf PDF])
* [http://www.intel.com/design/intarch/specupdt/245306.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/design/intarch/specupdt/24530663.pdf PDF])
* [http://developer.intel.com/design/mobile/datashts/245302.htm Mobile Pentium® III Processor in BGA2 and Micro-PGA2 Packages] ([http://download.intel.com/design/mobile/datashts/24530202.pdf PDF])

Embedded:
* [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii.htm Embedded Intel® Architecture Processors: Intel® Pentium® III Processors: Technical Documents]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_pga370.htm Intel® Pentium® III Processor - PGA370]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_low.htm Intel® Pentium® III Processor - Low Power]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_vol.htm Low Voltage Intel® Pentium® III Processor]

Xeon:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-xeon Highlights/Overview]

== VIA ==

=== VIA Padlock ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=281 Security Application note]
* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 PadLock Programming Guide]

= Northbridge =

== AMD ==

=== AMD RS880 ===

* [http://support.amd.com/us/Embedded_TechDocs/46143_rs880_BDG_pub_3.00.pdf AMD RS880 Family BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46141_rs880_rpr_pub_3.00.pdf AMD RS880 Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/46142_rs880_rrg_pub_3.00.pdf AMD RS880 Family Register Reference Guide] (RRG)

=== AMD RD890 ===

Not public (yet?). However, some of the information may be contained in the public docs in the RS880 section.

* AMD RD890 BIOS Developer's Guide (Publication #43606)
* AMD RD890 Register Reference Guide (Publication #43607)

=== AMD RS780 ===

* [http://support.amd.com/us/Embedded_TechDocs/43734_rs780_bdg_pub_1.01.pdf AMD 780G Family BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf AMD 780G Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/43451_rs780_rrg_pub_1.01.pdf AMD 780G Family Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/45732_rs780e_ds_pub_3.10.pdf AMD 780E Databook]
* [http://support.amd.com/us/Embedded_TechDocs/48319.pdf AMD 780 Product Errata]

Apparently there are other docs as well, not sure if they provide any additional information or if they are part of the public documents above:

* AMD RD780 Register Reference Guide
* AMD RX780 Register Reference Guide
* AMD RS780M Hybrid Graphics – System BIOS Detailed Design Document (Publication #44969)
* AMD RD790 Register Programming Requirements (Publication #42462)
* AMD RD790 Register Reference Guide (Publication #42988)
* AMD RD790 BIOS Developer's Guide (Publication #43093)

=== AMD RS690 ===

* [http://support.amd.com/us/Embedded_TechDocs/43372_rs690_rrg_3.00o.pdf AMD RS690 Register Reference Guide] (RRG)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41977_rs690_ds_3.06.pdf AMD 690G Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41978_rs690m_ds_3.06.pdf AMD M690 Databook (Notebook Solutions)]
* [http://support.amd.com/us/Embedded_TechDocs/42437_m690t_ds_3_08.pdf AMD M690T/M690E Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD690Series_LogoGuide.pdf AMD 690 Chipset Logos]

=== Misc ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD_7-Series_Chipsets_-_Guidelines.pdf AMD 7-Series Chipsets - Guidelines.pdf]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD Model S1 DBM690T, Socket S1 and M690T/SB600 Chipset Development Board]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMDCrossFire_LogoGuide.pdf AMD 480X Chipset Logos]

== Intel ==

=== Intel Atom Z5xx and SCH US15Wx ===

* [http://ark.intel.com/ProductCollection.aspx?codeName=24973 Overview of products formerly named Poulsbo]
* [http://edc.intel.com/Platforms/Atom-Z5xx/#hardware Overview: Intel® Atom™ Processor Z5xx Series and Intel® System Controller Hub US15Wx]
** [http://edc.intel.com/Link.aspx?id=1387 Datasheet: Intel® System Controller Hub (Intel® SCH)] (PDF)
** [http://edc.intel.com/Link.aspx?id=1905 Datasheet: Intel® System Controller Hub (Intel® SCH) (large form factor)] (PDF)

=== Intel NM10 Express ===

* [http://www.intel.com/Products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm Overview]
** [http://www.intel.com/Assets/PDF/datasheet/322896.pdf Intel® NM10 Express Chipset Datasheet]
** [http://www.intel.com/Assets/PDF/specupdate/322897.pdf Intel® NM10 Express Chipset Specification Update]

=== Intel 860 ===

* [http://www.intel.com/design/archives/chipsets/860/index.htm Hardware Design: Archives - Intel® 860 Chipset Family Technical Documentation]
** [http://www.intel.com/design/chipsets/datashts/290713.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Datasheet]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
*** [http://www.intel.com/design/chipsets/specupdt/290715.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Specification Update]: [http://www.intel.com/design/chipsets/specupdt/29071501.pdf PDF]
** [http://www.intel.com/design/chipsets/applnots/292269.htm Intel® 860 Chipset Thermal Considerations Application Note (AP-721)]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298252.htm Intel® Xeon® Processor and Intel® 860 Chipset Platform Design Guide]: [http://download.intel.com/design/chipsets/designex/29825204.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298302.htm Intel® 860 Chipset Memory Expansion Card (MEC) Design Guide]: [http://download.intel.com/design/chipsets/designex/29830201.pdf PDF]
** [http://www.intel.com/design/chipsets/schematics/860_crb.htm Intel 860 Chipset CRB Schematics]: [http://download.intel.com/design/chipsets/schematics/860_crb.pdf PDF]

=== Intel 82815E ===

* [http://download.intel.com/design/chipsets/datashts/29068801.pdf 82815 Chipset Family]
* [http://download.intel.com/design/chipsets/designex/29823401.pdf 82815E Chipset Platform Design Guide]
* [http://download.intel.com/design/chipsets/designex/29824906.pdf 82815E Chipset Platform Design Guide update]

=== Intel 440BX ===

* [http://download.intel.com/design/chipsets/datashts/29063301.pdf Datasheet]
* [http://download.intel.com/design/chipsets/datashts/27321903.pdf Electrical and Thermal Timing Specification]

=== Intel 440LX ===

* [http://download.intel.com/design/chipsets/datashts/29056402.pdf Datasheet]
* [http://www.intel.com/design/chipsets/specupdt/29765505.pdf Spec update]

== VIA ==

VIA has a [http://linux.via.com.tw portal] with some source code and datasheets.

=== VIA VX800 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241 VIA VX800 Programming Manual]

=== VIA CX700M/VX700 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 VIA CX700M/VX700 Programming Manual]

= Southbridge =

== AMD ==

=== AMD SB820M ===

* [http://support.amd.com/us/Embedded_TechDocs/47283.pdf AMD SB820M Southbridge Databook]

=== AMD SB810/SB850 ===

* [http://support.amd.com/us/Embedded_TechDocs/44758.pdf AMD SB810/SB850 Southbridge Databook]

=== AMD SB800 ===

* [http://support.amd.com/us/Embedded_TechDocs/45482.pdf AMD SB800-Series Southbridges Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/45481.pdf AMD SB800-Series Southbridges Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/45483.pdf AMD SB800-Series BIOS Developers Guide] (BDG)

=== AMD SB700/SB710/SB750 ===

* [http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf AMD SB700/710/750 BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf AMD SB700/710/750 Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/42413_sb7xx_rpr_pub_1.00.pdf AMD SB700/710/750 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/45215_sb710_ds_pub_1.25.pdf AMD SB710 Databook]
* [http://support.amd.com/us/Embedded_TechDocs/46837.pdf AMD SB700 Family Product Errata]

=== AMD SB600 ===

* [http://support.amd.com/us/Embedded_TechDocs/46157_sb600_bdg_pub.3.00.pdf AMD SB600 BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46155_sb600_rrg_pub_3.03.pdf AMD SB600 Register Reference Manual] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/46156_sb600_rpr_pub_3.02b.pdf AMD SB600 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42119_sb600_ds_3.05.pdf AMD SB600 Databook] (rev. 3.05)
* [http://support.amd.com/us/Embedded_TechDocs/42119_sb600_ds_pub_3.07.pdf AMD SB600 Databook] (rev. 3.07)

=== AMD 8111 ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/24674.pdf AMD-8111™ HyperTransport™ I/O Hub Data Sheet]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/26036.pdf AMD-8111™ HyperTransport™ I/O Hub Product Brief]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/25720.pdf AMD-8111™ HyperTransport™ I/O Hub Revision Guide]

== Intel ==

=== Intel 82801BA/BAM (ICH2) ===

* [http://developer.intel.com/design/chipsets/datashts/290687.htm Datasheet]

= Super I/O =

== ITE ==

* [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 PC Desktop/Notebook Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 Desktop Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=6 Notebook Super I/Os]

== Winbond / Nuvoton ==

* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/ISASuperIO/ ISA Super I/Os]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/LPCSuperIOforDesktopAndServer/ LPC Super I/O for Desktop & Server]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforDesktop/ Advanced Super I/O for Desktop]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforNotebook/ Advanced Super I/O for Notebook]

== Fintek ==

* [http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17&layer=0 Super Hardware Monitor + SIO]

== NSC ==

(bought by Winbond, now Nuvoton)

== ALi ==

== SMSC ==

* [http://www.smsc.com/main/catalog/ioprods.html Products / datasheets overview]
* [http://www.smsc.com/main/datasheet.html Various product datasheets]

= Other =

== ACPI ==

* http://www.acpi.info

== USB ==

== Misc ==

* [http://support.amd.com/us/Pages/techdocs.aspx AMD public documents]
** The [http://www.amd.com/us/products/embedded/develop-and-design/Pages/processor-chipset-linux-supprt.aspx AMD64 Embedded Processors and Chipset Linux Support] web page features links to supported projects (like coreboot) and links to documentation.

= Resources =

There are many datasheet archives on the web which may have other (usually older) datasheets which already disappeared from vendor websites.

SeaBIOS

2011-06-09T18:56:08Z

Uwe: /* Windows */

[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard [https://secure.wikimedia.org/wikipedia/en/wiki/BIOS BIOS] calling interfaces that a typical x86 proprietary BIOS implements.

This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and [http://bochs.sourceforge.net/ bochs] — see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.

= Use cases =

Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).

SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.

== Windows ==

SeaBIOS has been tested with Windows XP, Windows 2008, Windows Vista (64/32 bit), Windows 7 (32 bit and 64 bit).

However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).

So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.

== Linux ==

SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.

== Other ==

SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.

Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.

= Building =

== Building via coreboot's menuconfig ==

Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:

<source lang="bash">
$ make menuconfig
$ make
</source>

Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.

== Manual build ==

One can download the latest version of SeaBIOS through a git repository:

<source lang="bash">
$ git clone git://git.seabios.org/seabios.git seabios
$ cd seabios
</source>

There's also a [http://code.coreboot.org/p/seabios/source/changes/master/ gitweb] facility to browse the latest source code online.

Run '''make menuconfig''' and set the following variables:

* CONFIG_COREBOOT 1
* CONFIG_DEBUG_SERIAL 1

Then:

<source lang="bash">
$ make
</source>

The final SeaBIOS payload file is '''out/bios.bin.elf'''.

== coreboot ==

For best results, configure coreboot with '''CONFIG_WRITE_HIGH_TABLES''' and '''CONFIG_VGA_BRIDGE_SETUP''' both enabled, and '''CONFIG_VGA_ROM_RUN''' and '''CONFIG_PCI_ROM_RUN''' both disabled.

Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.

= SeaBIOS and CBFS =

SeaBIOS can read the coreboot flash filesystem and extract files.

When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').

SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.

Further, SeaBIOS can obtain configuration information from CBFS. A file '''bootorder''' determines the order of devices and methods to attempt to boot the system from.

The examples below show some common uses of these features.

== Adding a VGA option ROM ==

It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.

The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':

<source lang="bash">
$ lspci -vnn
...
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])
</source>

In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw
$ ./build/cbfstool coreboot.rom print
</source>

Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:

<source lang="bash">
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma
$ ./build/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw
$ ./build/cbfstool coreboot.rom print
</source>

After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.

== Adding gpxe support ==

A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:

<source lang="bash">
$ lspci -vnn
...
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)
</source>

Then one can build a gpxe option ROM. For example:

<source lang="bash">
$ cd /path/to/gpxe/src/
$ make bin/10ec8167.rom
</source>

And add it to the coreboot image. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw
$ ./build/cbfstool coreboot.rom print
</source>

As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.

In addition to gpxe, other option ROMs can be added in the same manner.

== Adding sgabios support ==

An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.

If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly — the sgabios ROM can fill this requirement.

Place the sgabios ROM file in the '''vgaroms/''' directory of CBFS. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/sgabios.bin vgaroms/sgabios.bin raw
$ ./build/cbfstool coreboot.rom print
</source>

When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice — once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates unset '''CONFIG_SCREEN_AND_DEBUG''' in '''make menuconfig'''.

== Adding a graphical "bootsplash" image ==

SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw
$ ./build/cbfstool coreboot.rom print
</source>

The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.

SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''CONFIG_BOOTMENU_WAIT''' in '''make menuconfig'''.

The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting|Trouble reporting]] section if a valid image isn't displayed properly.

== Adding payloads ==

Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l
$ ./build/cbfstool coreboot.rom print
</source>

During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.

SeaBIOS supports both uncompressed and LZMA compressed payloads.

== Adding a floppy image ==

It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:

<source lang="bash">
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma
$ ./build/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw
$ ./build/cbfstool coreboot.rom print
</source>

Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.

The floppy image will appear as writable to the system, however all writes are discarded on reboot.

When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.

== Configuring boot order ==

Place a file in CBFS with the name '''bootorder''' to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an [https://secure.wikimedia.org/wikipedia/en/wiki/Open_firmware Open Firmware] device path format. SeaBIOS will attempt to boot from each item in the file — first line of the file first.

The easiest way to find the available boot methods is to look for "Searching bootorder for" in the SeaBIOS serial output. For example, one may see lines similar to:

Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0
Searching bootorder for: /pci@i0cf8/*@f,1/drive@2/disk@1
Searching bootorder for: /pci@i0cf8/usb@10,4/*@2

The above represents the patterns SeaBIOS will search for in the bootorder file. However, it's safe to just copy and paste the pattern into bootorder. For example, the file:

/pci@i0cf8/usb@10,4/*@2
/pci@i0cf8/*@f/drive@1/disk@0

will instruct SeaBIOS to attempt to boot from the given USB drive first and then attempt the given ATA harddrive second.

Once a file has been created, add it to CBFS with the name '''bootorder'''. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add mybootlist.txt bootorder raw
$ ./build/cbfstool coreboot.rom print
</source>

= Trouble reporting =

If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by running '''make menuconfig''' and setting '''CONFIG_DEBUG_LEVEL''' to a higher value. A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).

To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].

SeaBIOS

2011-06-09T18:27:58Z

Uwe: Small fixes.

[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard [https://secure.wikimedia.org/wikipedia/en/wiki/BIOS BIOS] calling interfaces that a typical x86 proprietary BIOS implements.

This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and [http://bochs.sourceforge.net/ bochs] — see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.

= Use cases =

Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).

SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.

== Windows ==

SeaBIOS has been tested with Windows XP, Windows Vista (64/32 bit), and Windows 7 Beta (64 bit).

However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).

So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.

== Linux ==

SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.

== Other ==

SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.

Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.

= Building =

== Building via coreboot's menuconfig ==

Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:

<source lang="bash">
$ make menuconfig
$ make
</source>

Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.

== Manual build ==

One can download the latest version of SeaBIOS through a git repository:

<source lang="bash">
$ git clone git://git.seabios.org/seabios.git seabios
$ cd seabios
</source>

There's also a [http://code.coreboot.org/p/seabios/source/changes/master/ gitweb] facility to browse the latest source code online.

Run '''make menuconfig''' and set the following variables:

* CONFIG_COREBOOT 1
* CONFIG_DEBUG_SERIAL 1

Then:

<source lang="bash">
$ make
</source>

The final SeaBIOS payload file is '''out/bios.bin.elf'''.

== coreboot ==

For best results, configure coreboot with '''CONFIG_WRITE_HIGH_TABLES''' and '''CONFIG_VGA_BRIDGE_SETUP''' both enabled, and '''CONFIG_VGA_ROM_RUN''' and '''CONFIG_PCI_ROM_RUN''' both disabled.

Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.

= SeaBIOS and CBFS =

SeaBIOS can read the coreboot flash filesystem and extract files.

When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').

SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.

Further, SeaBIOS can obtain configuration information from CBFS. A file '''bootorder''' determines the order of devices and methods to attempt to boot the system from.

The examples below show some common uses of these features.

== Adding a VGA option ROM ==

It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.

The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':

<source lang="bash">
$ lspci -vnn
...
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])
</source>

In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw
$ ./build/cbfstool coreboot.rom print
</source>

Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:

<source lang="bash">
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma
$ ./build/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw
$ ./build/cbfstool coreboot.rom print
</source>

After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.

== Adding gpxe support ==

A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:

<source lang="bash">
$ lspci -vnn
...
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)
</source>

Then one can build a gpxe option ROM. For example:

<source lang="bash">
$ cd /path/to/gpxe/src/
$ make bin/10ec8167.rom
</source>

And add it to the coreboot image. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw
$ ./build/cbfstool coreboot.rom print
</source>

As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.

In addition to gpxe, other option ROMs can be added in the same manner.

== Adding sgabios support ==

An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.

If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly — the sgabios ROM can fill this requirement.

Place the sgabios ROM file in the '''vgaroms/''' directory of CBFS. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/sgabios.bin vgaroms/sgabios.bin raw
$ ./build/cbfstool coreboot.rom print
</source>

When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice — once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates unset '''CONFIG_SCREEN_AND_DEBUG''' in '''make menuconfig'''.

== Adding a graphical "bootsplash" image ==

SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw
$ ./build/cbfstool coreboot.rom print
</source>

The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.

SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''CONFIG_BOOTMENU_WAIT''' in '''make menuconfig'''.

The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting|Trouble reporting]] section if a valid image isn't displayed properly.

== Adding payloads ==

Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l
$ ./build/cbfstool coreboot.rom print
</source>

During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.

SeaBIOS supports both uncompressed and LZMA compressed payloads.

== Adding a floppy image ==

It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:

<source lang="bash">
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma
$ ./build/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw
$ ./build/cbfstool coreboot.rom print
</source>

Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.

The floppy image will appear as writable to the system, however all writes are discarded on reboot.

When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.

== Configuring boot order ==

Place a file in CBFS with the name '''bootorder''' to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an [https://secure.wikimedia.org/wikipedia/en/wiki/Open_firmware Open Firmware] device path format. SeaBIOS will attempt to boot from each item in the file — first line of the file first.

The easiest way to find the available boot methods is to look for "Searching bootorder for" in the SeaBIOS serial output. For example, one may see lines similar to:

Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0
Searching bootorder for: /pci@i0cf8/*@f,1/drive@2/disk@1
Searching bootorder for: /pci@i0cf8/usb@10,4/*@2

The above represents the patterns SeaBIOS will search for in the bootorder file. However, it's safe to just copy and paste the pattern into bootorder. For example, the file:

/pci@i0cf8/usb@10,4/*@2
/pci@i0cf8/*@f/drive@1/disk@0

will instruct SeaBIOS to attempt to boot from the given USB drive first and then attempt the given ATA harddrive second.

Once a file has been created, add it to CBFS with the name '''bootorder'''. For example:

<source lang="bash">
$ ./build/cbfstool coreboot.rom add mybootlist.txt bootorder raw
$ ./build/cbfstool coreboot.rom print
</source>

= Trouble reporting =

If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by running '''make menuconfig''' and setting '''CONFIG_DEBUG_LEVEL''' to a higher value. A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).

To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].

ARM

2011-06-09T18:01:54Z

Uwe:

coreboot on ARM is a work-in-progress. coreboot currently does not support ARM.

ARM SOCs with PCIe are now on the market for tablets, netbooks and servers. These systems can take advantage of coreboot's strength in properly configuring PCI, SAS, SATA and SCSI devices; fast boot times; and payload support.

Marvell will have the first ARM devices supported by coreboot.

== ARM SOCs ==

* [http://www.marvell.com/products/processors/armada.html Marvell Armada 300, 510, 1000 with PCIe]
* [http://www.marvell.com/products/processors/embedded/armada_xp/ Marvell Armada XP]
* [http://www.marvell.com/products/processors/embedded/discovery_innovation/ Marvell Discovery Innovation Series with PCIe]
* [http://www.marvell.com/products/processors/embedded/kirkwood/ Marvell Kirkwood Series with PCIe]
* [http://www.st.com/internet/mcu/product/250658.jsp STMicroelectronics SPEAr1310 with PCIe]
* [http://www.st.com/internet/mcu/product/251211.jsp STMicroelectronics SPEAr1340 with PCIe]
* [http://focus.ti.com/dsp/docs/dspplatformscontento.tsp?sectionId=2&familyId=1875&tabId=2643 TI Sitara with PCIe]
* [http://www.caviumnetworks.com/ECONA_CNS3XXX.html Cavium Networks ECONA CNS3XXX]
* [http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=844&partnum=Exynos%204210&xFmly_id=229 Samsung Exynos 4210 with PCIe]
* [http://www.nvidia.com/object/tegra.html NVIDIA TEGRA]
* [http://www.semicon.panasonic.co.jp/en/catalog/uniphier/index.html Panasonic UniPhier MN2WS0220]
* [http://www.ziilabs.com/products/processors/zms20.aspx ZiiLabs ZMS-20]

== Platforms ==

* [http://www.globalscaletechnologies.com/t-openrdudetails.aspx OpenRD Ultimate with Marvell 88F6281]
* [http://www.marvell.com/platforms/open_rd.html OpenRD Platforms with Marvell 88F6281]
* [http://www.wyse.com/products/hardware/thinclients/T50/ WYSE T50 Marvell Thin Client]
* [http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/12454-12454-321959-338927-3640405-4063703.html HP t5325 Marvell Thin Client]
* [http://www.ztsystems.com/Portals/0/ZTSystems_R1801e.pdf ZTSystems R1801e rackmount server with STMicroelectronics SPEAr 1310 with dual ARM® CortexTM-A9 cores]
* [http://pandaboard.org/ PandaBoard Dual-core ARM® Cortex™-A9 MPCore™ mobile dev board]
* [http://www.origenboard.org origenBOARD Exynos 4210 dev board]
* [http://www.toradex.com/Products/Colibri/Modules/Colibri-Tegra-2 Colibri T20 cpu module with NVIDIA Dual Core ARM Cortex A9 Processor]
* [http://trimslice.com/ Trimslice NVIDIA Tegra 2 dual-core ARM Cortex A9 @ 1 GHz 0.6" thin desktop]

ARM

2011-06-09T18:01:45Z

Uwe:

coreboot on ARM is a work-in-progress. coreboot currently does not support ARM.

ARM SOCs with PCIe are now on the market for tablets, netbooks and servers. These systems can take advantage of coreboot's strength in properly configuring PCI, SAS, SATA and SCSI devices; fast boot times; and payload support.

Marvell will have the first ARM devices supported by coreboot.

== ARM SOC's ==

* [http://www.marvell.com/products/processors/armada.html Marvell Armada 300, 510, 1000 with PCIe]
* [http://www.marvell.com/products/processors/embedded/armada_xp/ Marvell Armada XP]
* [http://www.marvell.com/products/processors/embedded/discovery_innovation/ Marvell Discovery Innovation Series with PCIe]
* [http://www.marvell.com/products/processors/embedded/kirkwood/ Marvell Kirkwood Series with PCIe]
* [http://www.st.com/internet/mcu/product/250658.jsp STMicroelectronics SPEAr1310 with PCIe]
* [http://www.st.com/internet/mcu/product/251211.jsp STMicroelectronics SPEAr1340 with PCIe]
* [http://focus.ti.com/dsp/docs/dspplatformscontento.tsp?sectionId=2&familyId=1875&tabId=2643 TI Sitara with PCIe]
* [http://www.caviumnetworks.com/ECONA_CNS3XXX.html Cavium Networks ECONA CNS3XXX]
* [http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=844&partnum=Exynos%204210&xFmly_id=229 Samsung Exynos 4210 with PCIe]
* [http://www.nvidia.com/object/tegra.html NVIDIA TEGRA]
* [http://www.semicon.panasonic.co.jp/en/catalog/uniphier/index.html Panasonic UniPhier MN2WS0220]
* [http://www.ziilabs.com/products/processors/zms20.aspx ZiiLabs ZMS-20]

== Platforms ==

* [http://www.globalscaletechnologies.com/t-openrdudetails.aspx OpenRD Ultimate with Marvell 88F6281]
* [http://www.marvell.com/platforms/open_rd.html OpenRD Platforms with Marvell 88F6281]
* [http://www.wyse.com/products/hardware/thinclients/T50/ WYSE T50 Marvell Thin Client]
* [http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/12454-12454-321959-338927-3640405-4063703.html HP t5325 Marvell Thin Client]
* [http://www.ztsystems.com/Portals/0/ZTSystems_R1801e.pdf ZTSystems R1801e rackmount server with STMicroelectronics SPEAr 1310 with dual ARM® CortexTM-A9 cores]
* [http://pandaboard.org/ PandaBoard Dual-core ARM® Cortex™-A9 MPCore™ mobile dev board]
* [http://www.origenboard.org origenBOARD Exynos 4210 dev board]
* [http://www.toradex.com/Products/Colibri/Modules/Colibri-Tegra-2 Colibri T20 cpu module with NVIDIA Dual Core ARM Cortex A9 Processor]
* [http://trimslice.com/ Trimslice NVIDIA Tegra 2 dual-core ARM Cortex A9 @ 1 GHz 0.6" thin desktop]

Welcome to coreboot

2011-06-09T17:58:50Z

Uwe:

<table width="100%" valign="top"><tr valign="top"><td width="80%">

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
'''coreboot''' is a Free Software project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.


coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029133.html LinuxBIOS].

</div>

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
coreboot recently switched to [[git]] and [http://review.coreboot.org gerrit] is now used as patch review tool.
</div>

{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%
|-
|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = yellow|
WIDTH = 100%|
ICON = [[Benefits|More...]]|
HEADING = [[Benefits]]|
CONTENT =

* 100% Free Software (GPL), no royalties, no license fees!
* Fast boot times (3 seconds to Linux console)



* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]


}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = #d1adf6|
WIDTH = 100%|
ICON = [[Use Cases|More...]]|
HEADING = [[Use Cases]]|
CONTENT =

* Desktop PCs, servers, [[Laptop|laptops]]
* [[Clusters]]

* Embedded solutions




}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = lime|
WIDTH = 100%|
ICON = [[Payloads|More...]]|
HEADING = [[Payloads]]|
CONTENT =

* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] 
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] 
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]


}}

|}

{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_cb.png]]
|style="vertical-align:top"|
'''About''' Find out more about coreboot.<hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_devel.png]]
|style="vertical-align:top"|
'''Developers''' Get involved! Help us make coreboot better.<hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]] | [[Distributed and Automated Testsystem|Testsystem]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_status.png]]
|style="vertical-align:top"|
'''Status''' Find out whether your hardware is already supported.<hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_tools.png]]
|style="vertical-align:top"|
'''Related Tools''' Tools and libraries related to coreboot.<hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_101.png]]
|style="vertical-align:top"|
'''Getting Started''' Download coreboot and get started.<hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_support.png]]
|style="vertical-align:top"|
'''Support''' Learn how to contact us and find help and support.<hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]
|}

|}
</td><td width="20%">

[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]

 

'''[http://blogs.coreboot.org News (blog)]'''<hr />

<rss max=5>http://blogs.coreboot.org/feed/</rss>


'''[[Current events|Upcoming Events]]'''<hr />



* '''2011/05/11-14:''' coreboot and [[Flashrom|flashrom]] booths at [http://www.linuxtag.org/ LinuxTag] in Berlin
* [[GSoC|2011 Google Summer of Code]]


 
{{#widget:Ohloh Project|id=coreboot|type=partner_badge}}
{{#widget:Ohloh Project|id=coreboot|type=cocomo}}

</td></tr></table>

__NOTOC__
__NOEDITSECTION__

Git

2011-06-09T17:54:46Z

Uwe: /* Pushing changes */

= Gerrit =
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.

== Register with gerrit ==
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.

=== OpenID ===
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.

== Gerrit workflow ==
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.

Reviews grant points on a scale from -2 to 2. The meaning is:
* -2: Do not merge (blocks gerrit from merging)
* -1: I'd prefer you don't merge it
* 0: neutral
* +1: Looks good, but I won't make the last call on it
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)

-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.

=== Gerrit and CLI ===
Reviews normally happens through the website.

Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.

=== Gerrit and Email ===
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.

This gateway will provide:
* no patch submission mechanism ("git push" is CLI friendly)
* patch review (maybe openpgp signed "Acked-by" mails)
* patch submission (automatically with Acked-by?)
* maybe patch rejection? (openpgp signed "Nacked-by" mails)

= Anonymous read access =
Read-only access is available anonymously:
git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>

= Authenticated read/write access =

git clone ssh://<username>@review.coreboot.org:29418/coreboot

Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with

wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \
chmod +x .git/hooks/commit-msg

Alternatively, you could also just run

make gitconfig

= Working with Git =

Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.

== Commit messages ==
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:

# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary
# The second line is empty (no whitespace at all)
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.
# The next line is empty (no whitespace at all)
# A Change-Id: line to let gerrit track this logical change
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]

Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...

make gitconfig

...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.

Here is an example of a well-formatted commit message:
examplecomponent: Refactor duplicated setup into a function.

Setting up the demo device correctly requires the exact same register
values to be written into each of the PCI device functions. Moving the
writes into a function allows also otherexamplecomponent to use them.

Signed-off-by: Joe Hacker <joe@hacker.email>

The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.

== Pushing changes ==
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[Git#Authenticated read/write access|Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:

git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot

Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:

git config remote.origin.push HEAD:refs/for/master

After this, the command to push your changes is:

git push origin

If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:

git config branch.<particularbranchname>.remote origin

...after which you then push changes with any of the configured branches checked out with a simple:

git push

Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit.

'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run

git log origin/master..

before '''git push''' to verify which commits you are about to send for review.

For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].

== Further Git reading ==
There are tons of git tutorials out there. Take a look at some of these documents:
* http://git-scm.com/
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html
* http://git.or.cz/course/svn.html
* and in particular the [http://progit.org/ Pro Git book]

Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].

= Browsing =

There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.

Git

2011-06-09T17:44:56Z

Uwe: /* Authenticated read/write access */ Mention "make gitconfig" in the resp. chapter.

= Gerrit =
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.

== Register with gerrit ==
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.

=== OpenID ===
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.

== Gerrit workflow ==
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.

Reviews grant points on a scale from -2 to 2. The meaning is:
* -2: Do not merge (blocks gerrit from merging)
* -1: I'd prefer you don't merge it
* 0: neutral
* +1: Looks good, but I won't make the last call on it
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)

-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.

=== Gerrit and CLI ===
Reviews normally happens through the website.

Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.

=== Gerrit and Email ===
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.

This gateway will provide:
* no patch submission mechanism ("git push" is CLI friendly)
* patch review (maybe openpgp signed "Acked-by" mails)
* patch submission (automatically with Acked-by?)
* maybe patch rejection? (openpgp signed "Nacked-by" mails)

= Anonymous read access =
Read-only access is available anonymously:
git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>

= Authenticated read/write access =

git clone ssh://<username>@review.coreboot.org:29418/coreboot

Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with

wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \
chmod +x .git/hooks/commit-msg

Alternatively, you could also just run

make gitconfig

= Working with Git =

Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.

== Commit messages ==
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:

# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary
# The second line is empty (no whitespace at all)
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.
# The next line is empty (no whitespace at all)
# A Change-Id: line to let gerrit track this logical change
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]

Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...

make gitconfig

...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.

Here is an example of a well-formatted commit message:
examplecomponent: Refactor duplicated setup into a function.

Setting up the demo device correctly requires the exact same register
values to be written into each of the PCI device functions. Moving the
writes into a function allows also otherexamplecomponent to use them.

Signed-off-by: Joe Hacker <joe@hacker.email>

The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.

== Pushing changes ==
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[#Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:

git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot

Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:

git config remote.origin.push HEAD:refs/for/master

After this, the command to push your changes is:

git push origin

If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:

git config branch.<particularbranchname>.remote origin

...after which you then push changes with any of the configured branches checked out with a simple:

git push

Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit.

'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run

git log origin/master..

before '''git push''' to verify which commits you are about to send for review.

For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].

== Further Git reading ==
There are tons of git tutorials out there. Take a look at some of these documents:
* http://git-scm.com/
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html
* http://git.or.cz/course/svn.html
* and in particular the [http://progit.org/ Pro Git book]

Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].

= Browsing =

There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.

Git

2011-06-09T17:43:47Z

Uwe: Random fixes.

= Gerrit =
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.

== Register with gerrit ==
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.

=== OpenID ===
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.

== Gerrit workflow ==
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.

Reviews grant points on a scale from -2 to 2. The meaning is:
* -2: Do not merge (blocks gerrit from merging)
* -1: I'd prefer you don't merge it
* 0: neutral
* +1: Looks good, but I won't make the last call on it
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)

-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.

=== Gerrit and CLI ===
Reviews normally happens through the website.

Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.

=== Gerrit and Email ===
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.

This gateway will provide:
* no patch submission mechanism ("git push" is CLI friendly)
* patch review (maybe openpgp signed "Acked-by" mails)
* patch submission (automatically with Acked-by?)
* maybe patch rejection? (openpgp signed "Nacked-by" mails)

= Anonymous read access =
Read-only access is available anonymously:
git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>

= Authenticated read/write access =
git clone ssh://<username>@review.coreboot.org:29418/coreboot

Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with
wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \
chmod +x .git/hooks/commit-msg

= Working with Git =

Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.

== Commit messages ==
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:

# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary
# The second line is empty (no whitespace at all)
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.
# The next line is empty (no whitespace at all)
# A Change-Id: line to let gerrit track this logical change
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]

Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...

make gitconfig

...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.

Here is an example of a well-formatted commit message:
examplecomponent: Refactor duplicated setup into a function.

Setting up the demo device correctly requires the exact same register
values to be written into each of the PCI device functions. Moving the
writes into a function allows also otherexamplecomponent to use them.

Signed-off-by: Joe Hacker <joe@hacker.email>

The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.

== Pushing changes ==
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[#Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:

git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot

Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:

git config remote.origin.push HEAD:refs/for/master

After this, the command to push your changes is:

git push origin

If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:

git config branch.<particularbranchname>.remote origin

...after which you then push changes with any of the configured branches checked out with a simple:

git push

Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit.

'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run

git log origin/master..

before '''git push''' to verify which commits you are about to send for review.

For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].

== Further Git reading ==
There are tons of git tutorials out there. Take a look at some of these documents:
* http://git-scm.com/
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html
* http://git.or.cz/course/svn.html
* and in particular the [http://progit.org/ Pro Git book]

Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].

= Browsing =

There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.

Superiotool

2011-06-03T20:38:46Z

Uwe: Partial update to r6543: Nuvoton WPCM450, ITE IT8721F, NSC PC87382, ITE IT8720F, SMSC MEC1308, NSC PC87364, W83627DHG-P/-PT, Nuvoton NCT6776F (B/C).

'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.

This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.

<gallery>
Image:Ite it8705f.jpg|ITE IT8705F
Image:Winbond w83977ef.jpg|Winbond W83977EF
</gallery>

== Support of various devices ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ALi
| M1535/M1535D/M1535+/M1535D+
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5105
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5107
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5109
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5113
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5119
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M512x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513x
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xB
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M514x
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ASUS
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]
| —

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71862FG / F71863FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71889
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71872F/FG / F71806F/FG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71882FG/F71883FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F8000
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C711
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C712
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C721
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C735
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8228E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8502E/F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8510E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8511E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8512E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8661F/IT8770F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F/IT8687R
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8673F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT86793
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8702F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8703F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8705F/AF / IT8700F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8706R
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8708F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8710F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8711F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8718F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8720F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8721F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8722F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8726F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8761E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8780F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| HMC
| HMC83755
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Holtek
| HT6552IR
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS307
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS308
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS309
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS317
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS338
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS351
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97307
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87309
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87360
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87351
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87364
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87365
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87363
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87366
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87382
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8739x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87591x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8741x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87372
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8374L
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87427
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87373
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| WPCE775x / NPCE781x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| WPCM450
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| NCT6776F (B)
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Nuvoton
| NCT6776F (C)
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xFR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N971
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N972
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N252
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M172
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xAPM
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C67x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B80x/FDC37M707
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N958FR
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B77x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B78x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M602
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M60x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B72x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M81x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B27x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B37x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47U33x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B34x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S42x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M10x/112/13x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B357
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M14x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M15x/192/997
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S45x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M292
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B387
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B397
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M182
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M584
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| MEC1308
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| DME1737
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5504
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N217
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5514D-NS
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3112
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3114
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3116
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5317
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5027
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH4307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669FR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N237
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N769
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N3869/FDC37N869
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N227
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SIO10N268
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C665GT/IR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C666GT
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| SiS
| SIS6801
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS950
| style="background:red" | No
| style="background:red" | No
| —
| —

|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686A/VT82C686B
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977CTF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977EF/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83527HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627SF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697HF/F/HG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83L517D/D-F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83637HF/HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627THF/THG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG-P/-PT
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627UHG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83667HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977F-A/G-A/AF-A/AG-A
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977AF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977TF
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627HF/F/HG/G
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697SF/UF/UG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627EHF/EF/EHG/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877AF
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877TF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| WPCD376I
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| UMC
| UM82C862
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8663BF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8669
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8670
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

|}

'''Extended dumps (EC, HWM) available for:'''

Use the '''--extra-dump''' option to see the contents of these registers.

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| Winbond
| W83627THF/THG HWM
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|- bgcolor="#eeeeee" valign="top"
| SMSC
| LPC47N227 runtime register block
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}


1 Previosly National Semiconductor, now bought by Winbond. 
2 Register dump output from a running coreboot system (vs. proprietary BIOS). 


== Installation ==

'''Manual installation'''

$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool
$ cd superiotool
$ make
$ sudo make install

'''Debian / Ubuntu'''

$ apt-get install superiotool

'''Fedora'''

$ yum install superiotool

== Usage ==

Probe/detect the Super I/O in your mainboard:

$ superiotool

Register dump as table of hex-values (if the Super I/O is detected):

$ superiotool -d

Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.

{{GPL}}

Developer Manual

2011-05-16T13:25:59Z

Uwe: /* View From The CPU: Intel Architecture */ Fix typo.

<div style="color: red">'''This is work in progress!'''</div>

This manual is intended for aspiring coreboot developers to help them get up to speed with the code base and the tasks required to add support for new chipsets, devices, and mainboards. It covers coreboot v4.

== Recommended hardware and software tools ==

See [[Developer Manual/Tools]] for a list of recommended tools which are useful for coreboot users and developers.

== Hardware Overview ==

=== Intel Architecture ===

==== Hardware Reset ====

From Intel's "64 and IA-32 Architectures Software Developer’s Manual" (doc 253668-021 October 2006), Volume 3A, Section 9.1.4:

<blockquote>
The first instruction that is fetched and executed following a hardware reset is located at '''physical address 0xFFFFFFF0'''. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the software-initialization code must be located at this address.
 
The address 0xFFFFFFF0 is beyond the 1-MByte addressable range of the processor while in real-address mode. The processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In real-address mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with 0xF000 and the base address is loaded with 0xFFFF0000. The starting address is thus formed by adding the base address to the value in the EIP register (that is, 0xFFFF0000 + 0xFFF0 = 0xFFFFFFF0).
 
The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To insure that the base address in the CS register remains unchanged until the EPROM based software-initialization code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would cause the CS selector value to be changed).
</blockquote>

==== FWH/LPC Flash Memory ====

Modern mainboards are often equipped with Firmware Hub (FWH) or Low Pin Count (LPC) flash memory used to store the system bootloader ("BIOS"). Execution begins by fetching instructions 16 bytes below the flash memory's uppermost physical address.

== coreboot Overview ==

=== View From The CPU: Intel Architecture ===

# At '''0xFFFFFFF0''', start execution at '''reset_vector''' from '''src/cpu/x86/16bit/reset16.inc''', which simply jumps to '''_start'''.
# '''_start''' from '''src/cpu/x86/16bit/entry16.inc''', invalidates the TLBs, sets up a GDT for selector 0x08 (code) and 0x10 (data), switches to protected mode, and jumps to '''__protected_start''' (setting the CS to the new selector 0x08). The selectors provide full flat access to the entire physical memory map.
# '''__protected_start''' from '''src/cpu/x86/32bit/entry32.inc''', sets all other segment registers to the 0x10 selector.
# Execution continues with various '''mainboardinit''' fragments:
## '''__fpu_start''' from '''cpu/x86/fpu_enable.inc'''.
## '''(unlabeled)''' from '''cpu/x86/enable_sse.inc'''
## Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. '''cpu/amd/model_lx/cache_as_ram.inc'''.
# The final '''mainboardinit''' fragment is mainboard-specific, in C, called '''romstage.c'''. For non-cache-as-RAM targets, it is compiled with '''romcc'''. It includes and uses other C-code fragments for:
## Initializing MSRs, MTRRs, APIC.
## Setting up the southbridge minimally ("early setup").
## Setting up Super I/O serial.
## Initializing the console.
## Initializing RAM controller and RAM itself.
# Execution continues at '''__main''' from '''src/arch/x86/init/crt0_romcc_epilogue.inc''', where the non-romcc C coreboot code is copied (possibly decompressed) to RAM, then the RAM entry point is jumped to.
# The RAM entry point is '''_start''' in '''src/arch/x86/lib/c_start.S''', where new descriptor tables are set up, the stack and BSS are cleared, the IDT is initialized, and '''hardwaremain()''' is called (operation is now full 32-bit protected mode C program with stack).
# '''hardwaremain()''' is from '''src/boot/hardwaremain.c''', the console is initialized, devices are enumerated and initialized, configured and enabled.
# The payload is called, either via '''elfboot()''' from '''boot/elfboot.c''', or '''filo()''' from '''boot/filo.c'''.

== Failover/Fallback/Normal images overview ==

See [[Developer Manual/Bootblock]]

== Memory map ==

On x86 systems, many memory ranges are reserved for special purposes or have some other peculiar properties. The article [[Developer Manual/Memory map]] has details about this fact.

== Serial output and the Super I/O ==

See [[Developer Manual/Super IO]].

== Northbridge ==

== RAM init ==

See [[Developer Manual/RAM init]].

== Southbridge ==

== Mainboard ==

=== devicetree.cb ===

The mainboard's '''devicetree.cb''' file contains many build and platform configuration settings. One of the most important items is the mainboard device list.

A device needs to be listed in the mainboard '''devicetree.cb''' if it requires more setup than standard PCI initialization (resource allocation). Typically, that includes the CPU, northbridge, southbridge, and Super I/O. These devices are usually required for system specific configuration as well as indicate the system bus structure ('''pci_domain''').

When a device in '''devicetree.cb''' is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the '''device_operations''' and the '''chip_operations''' structures. You will find these structures in the devices source files.

=== irq_table.c ===

See [[Creating Valid IRQ Tables]].

== Creating a new target ==

To create a new mainboard target you have to add several files.

* Multiple files in src/mainboard/''vendorname''/''mainboardname'' (replace ''vendorname'' and ''mainboardname'', of course).

== Documentation and datasheets ==

=== Useful hardware/concepts documentation for developers ===

These external documents and slides explain fundamental concepts of hardware that coreboot supports.

'''Interrupts'''

* [http://www.bsdcan.org/2007/schedule/attachments/13-PCI_Interrupts_for_x86_Machines_under_FreeBSD_John_Baldwin PCI Interrupts on x86 machines] from John Baldwin
* [http://www.microsoft.com/taiwan/whdc/archive/ACPI-MP.mspx PCI IRQ Routing on a Multiprocessor ACPI System] at Microsoft's Windows Hardware Developer Central

'''System Managment Mode'''

* [http://www.rcollins.org/ddj/Jan97/Jan97.html System Managment Mode Overview] by Robery R. Collins

=== Specific datasheets ===

See [[Datasheets]].

{{GPL}}

SeaBIOS

2011-01-03T18:25:17Z

Uwe: Various fixes, esp. location of cbfstool.

[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard BIOS calling interfaces that a typical x86 proprietary BIOS implements.

This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and bochs — see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.

= Use cases =

Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).

SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.

== Windows ==

SeaBIOS has been tested with Windows XP, Windows Vista (64/32 bit), and Windows 7 Beta (64 bit).

However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).

So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.

== Linux ==

SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.

== Other ==

SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.

Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.

= Building =

== Building via coreboot's menuconfig ==

Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:

<source lang="bash">
$ make menuconfig
$ make
</source>

Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.

== Manual build ==

One can download the latest version of SeaBIOS through a git repository:

<source lang="bash">
$ git clone git://git.linuxtogo.org/home/kevin/seabios.git seabios
$ cd seabios
</source>

There's also a [http://git.linuxtogo.org/?p=kevin/seabios.git;a=summary gitweb] facility to browse the latest source code online.

Edit '''src/config.h''' and set the following values:

<source lang="C">
#define CONFIG_COREBOOT 1
#define CONFIG_DEBUG_SERIAL 1
#define CONFIG_VGAHOOKS 1
</source>

Then:

<source lang="bash">
$ make
</source>

The final SeaBIOS payload file is '''out/bios.bin.elf'''.

=== Compiled SeaBIOS images ===

It is also possible to download a compiled SeaBIOS image. The latest released version compiled for coreboot is: http://www.linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.1

Other versions are also available at: http://www.linuxtogo.org/~kevin/SeaBIOS/

== coreboot ==

For best results, configure coreboot with CONFIG_WRITE_HIGH_TABLES and CONFIG_VGA_BRIDGE_SETUP both enabled, and CONFIG_VGA_ROM_RUN and CONFIG_PCI_ROM_RUN both disabled.

Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.

= SeaBIOS and CBFS =

SeaBIOS can read the coreboot flash filesystem and extract files.

When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').

SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.

The examples below show some common uses of this feature.

== Adding a VGA option ROM ==

It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.

The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':

<source lang="bash">
$ lspci -vnn
...
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])
</source>

In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:

<source lang="bash">
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:

<source lang="bash">
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma
$ ./build/util/cbfstool/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.

== Adding gpxe support ==

A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:

<source lang="bash">
$ lspci -vnn
...
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)
</source>

Then one can build a gpxe option ROM. For example:

<source lang="bash">
$ cd /path/to/gpxe/src/
$ make bin/10ec8167.rom
</source>

And add it to the coreboot image. For example:

<source lang="bash">
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.

In addition to gpxe, other option ROMs can be added in the same manner.

== Adding sgabios support ==

An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.

If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly — the sgabios ROM can fill this requirement.

The current version of sgabios (as of 20090617) does not implement a proper checksum. As a work around, a tool from the SeaBIOS source repo can fix the checksum:
<source lang="bash">
$ /path/to/seabios/tools/buildrom.py /path/to/sgabios.bin sgabios-fixed.bin
</source>

Once the above is done, place the ROM file in the '''vgaroms/''' directory of CBFS. For example:

<source lang="bash">
$ ./build/util/cbfstool/cbfstool coreboot.rom add sgabios-fixed.bin vgaroms/sgabios.bin raw
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice — once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates one can edit the SeaBIOS '''src/config.h''' file and set the following:

<source lang="C">
#define CONFIG_SCREEN_AND_DEBUG 0
</source>

== Adding a graphical "bootsplash" image ==

SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:

<source lang="bash">
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.

SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''src/config.h''' file and changing the '''CONFIG_BOOTMENU_WAIT''' setting.

The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting]] section if a valid image isn't displayed properly.

== Adding payloads ==

Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:

<source lang="bash">
$ ./build/util/cbfstool/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.

SeaBIOS supports both uncompressed and LZMA compressed payloads.

== Adding a floppy image ==

It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:

<source lang="bash">
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma
$ ./build/util/cbfstool/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw
$ ./build/util/cbfstool/cbfstool coreboot.rom print
</source>

Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.

The floppy image will appear as writable to the system, however all writes are discarded on reboot.

When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.

= Trouble reporting =

If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by editing the '''src/config.h''' file and setting the debug level to a higher number (for example '''8'''):

<source lang="C">
#define CONFIG_DEBUG_LEVEL 8
</source>

A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).

To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].

Datasheets

2011-01-01T15:47:48Z

Uwe: /* AMD */ AMD SB810/SB850

This page lists '''publically available datasheets''' and programming guides from various vendors. It includes CPU, chipset, Super I/O, and many other datasheets.

= x86 architecture =

== AMD ==

AMD provides their [http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.1&product=5.7&contentType=Tech+Doc+Processor&ostype=&keywords=&items=20 AMD64 Architecture and Software manuals], which are a very useful reference for AMD systems, of course (but also explain lots of non-AMD-specific x86 stuff too):

* [http://support.amd.com/us/Processor_TechDocs/24592.pdf Volume 1: Application Programming]
* [http://support.amd.com/us/Processor_TechDocs/24593.pdf Volume 2: System Programming 24593]
* [http://support.amd.com/us/Processor_TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26568.pdf Volume 4: 128-Bit Media Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26569.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions]
* [http://support.amd.com/us/Processor_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions]

Other AMD documents:
* [http://support.amd.com/us/Processor_TechDocs/43724.pdf Lightweight Profiling Specification]
* [http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf AMD I/O Virtualization Technology (IOMMU) Specification]
* [http://support.amd.com/us/Processor_TechDocs/32200.pdf Open Platform Management Architecture Specification]
* [http://support.amd.com/us/Processor_TechDocs/25481.pdf CPUID Specification]
* [http://support.amd.com/us/Processor_TechDocs/41918.pdf Advanced Platform Management Link (APML) Specification]

== Intel ==

Intel provides their [http://developer.intel.com/products/processor/manuals/index.htm Intel® 64 and IA-32 Architectures Software Developer's Manuals] which are a very useful reference to the x86 architecture in general:

* [http://developer.intel.com/Assets/PDF/manual/253665.pdf Volume 1: Basic Architecture]
* [http://developer.intel.com/Assets/PDF/manual/253666.pdf Volume 2A: Instruction Set Reference, A-M]
* [http://developer.intel.com/Assets/PDF/manual/253667.pdf Volume 2B: Instruction Set Reference, N-Z]
* [http://developer.intel.com/Assets/PDF/manual/253668.pdf Volume 3A: System Programming Guide]
* [http://developer.intel.com/Assets/PDF/manual/253669.pdf Volume 3B: System Programming Guide]
* [http://www.intel.com/Assets/PDF/manual/252046.pdf Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes]

Other Intel documents:

* [http://www.intel.com/Assets/PDF/manual/318148.pdf Intel® 64 Architecture x2APIC Specification]
* [http://www.intel.com/Assets/PDF/manual/248966.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual]
* [http://www.intel.com/Assets/PDF/manual/323640.pdf Intel® Carry-Less Multiplication Instruction and its Usage for Computing the GCM Mode White Paper]
* [http://www.intel.com/Assets/PDF/manual/323641.pdf Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Set White Paper]
* [http://www.intel.com/Assets/PDF/manual/323850.pdf Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) Application Note]

= CPU =

== AMD ==

=== AMD Fam11h ===

* [http://support.amd.com/us/Processor_TechDocs/41256.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/41788.pdf Revision Guide for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/43373.pdf AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks]

Turion64:
* [http://support.amd.com/us/Processor_TechDocs/32816.pdf AMD Turion™ 64 Mobile Technology Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/41407.pdf AMD Turion™ 64 X2 Mobile Technology Dual-Core Processor Product Data Sheet]

Athlon64:
* [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]

=== AMD Fam10h ===

* [http://support.amd.com/us/Processor_TechDocs/31116.pdf BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h]
** [http://support.amd.com/us/Processor_TechDocs/41322.pdf Revision Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/40546-PUB-Optguide_3-11_5-21-09.pdf Software Optimization Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/43374.pdf AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/43375.pdf AMD Family 10h Desktop Processor Power and Thermal Data Sheet]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/40036.pdf Family 10h AMD Opteron Processor Product Data Sheet]

Phenom:
* [http://support.amd.com/us/Processor_TechDocs/44109.pdf Family 10h AMD Phenom™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/46878.pdf Family 10h AMD Phenom™ II Processor Product Data Sheet]

=== AMD K8 ===

Athlon64/Opteron:
* [http://support.amd.com/us/Processor_TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/25759.pdf Revision Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/26633_5649.pdf AMD Athlon™ and AMD Opteron™ Processors Thermal Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/40555.pdf Performance Guidelines for AMD Athlon™ and AMD Opteron™ ccNUMA Multiprocessor Systems]
* [http://support.amd.com/us/Processor_TechDocs/24707_PUB.PDF Clock Generator Specification for AMD Athlon™ and AMD Opteron™ Processors]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/23932.pdf AMD Opteron™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30417.pdf AMD Opteron™ Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/40820_PUB_AMD_Opteron_Processor_Production_Notice_rev_3_08.pdf AMD Opteron™ x52 and x54 Production Notice]
* [http://support.amd.com/us/Processor_TechDocs/30925.pdf Builders Guide for AMD Opteron™ Processor-Based Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/33340.pdf AMD Opteron™ Multiprocessor Systems Running Linux Technical Bulletin for AMD OEMs and Partners]

Family 0Fh:
* [http://support.amd.com/us/Processor_TechDocs/32559.pdf BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/33610.pdf Revision Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/31119.pdf AMD NPT Family 0Fh Processor Electrical Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/33954.pdf AMD NPT Family 0Fh Desktop Processor Power and Thermal Data Sheet]

=== Athlon64 ===

* [http://support.amd.com/us/Processor_TechDocs/24659.pdf AMD Athlon™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31783.pdf AMD Athlon™ Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/43042.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/33425.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet] (ver 3.10, 1/21/2007)
** [http://support.amd.com/us/Processor_TechDocs/42989.pdf AMD Athlon™ X2 Dual-Core Processor for Notebooks Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/30431.pdf AMD Athlon™ FX Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31366.pdf AMD Athlon™ FX-60 Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31225.pdf Mobile AMD Athlon™ Processor 3400+ Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31684.pdf Builder's Guide for AMD Athlon™ Processor-Based Desktops and Workstations]

=== Athlon (32bit) ===

* [http://support.amd.com/us/Processor_TechDocs/21016.pdf AMD Athlon™ Processor Module Data Sheet] (rev. M-0, 5/31/2000)
** [http://support.amd.com/us/Processor_TechDocs/22054.pdf AMD Athlon™ Processor Technical Brief]
* [http://support.amd.com/us/Processor_TechDocs/26237.PDF AMD Athlon™ XP Processor Model 10 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/27375.pdf AMD Athlon XP Processor Model 10 with 256K L2 Cache]
** [http://support.amd.com/us/Processor_TechDocs/27532.pdf AMD Athlon™ Processor Model 10 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/26426.PDF AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/25175.pdf AMD Athlon™ XP Processor Model 8 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/25703.pdf AMD Athlon™ Processor Model 8 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25722.pdf AMD Athlon™ MP Processor Model 8 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/24685.pdf AMD Athlon™ MP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24309.pdf AMD Athlon™ XP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24332.pdf AMD Athlon™ Processor Model 6 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25480.pdf AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/23792.pdf AMD Athlon™ Processor Model 4 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23614.pdf AMD Athlon™ Processor Model 4 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/22651.pdf AMD Athlon™ Processor Voltage Regulation Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23811.pdf AMD Athlon™ Processor Module Signal and Power-Up Requirements Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25823.pdf Builder’s Guide for 2P Capable Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/25325.pdf System Considerations for Dual AMD Athlon™ MP Processors in Tower and 1U Form Factors]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]
* [http://support.amd.com/us/Processor_TechDocs/24228.pdf Methodologies for Measuring Temperature on AMD Athlon™ and AMD Duron™ Processors]
* [http://support.amd.com/us/Processor_TechDocs/22007.pdf AMD Athlon™ Processor x86 Code Optimization Guide]

=== Sempron ===

* [http://support.amd.com/us/Processor_TechDocs/31805.pdf AMD Sempron™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31994.pdf AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31993.pdf AMD Sempron™ Processor Model 10 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31693.pdf AMD Sempron™ Processor Model 8 Data Sheet]

=== Duron ===

* [http://support.amd.com/us/Processor_TechDocs/TN13.pdf AMD Duron™ Processor Rev. A0: CPUID Reporting of L2 Cache Size]
* [http://support.amd.com/us/Processor_TechDocs/25848.PDF AMD Duron™ Processor Model 8 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/24310.pdf AMD Duron™ Processor Model 7 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24806.pdf AMD Duron™ Processor Model 7 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/23802.pdf AMD Duron™ Processor Model 3 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23865.pdf AMD Duron™ Processor Model 3 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]

=== Socket specs ===

* [http://support.amd.com/us/Processor_TechDocs/25766.pdf AMD Socket 940 Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/31412.pdf AMD Functional Data Sheet, 940 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/30353.pdf AMD Socket 940 Qualification Plan]
* [http://support.amd.com/us/Processor_TechDocs/31700.pdf Socket F (1207) Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/32800.pdf Thermal Design Guide for Socket F (1207) Processors]
* [http://support.amd.com/us/Processor_TechDocs/31875.pdf Socket AM2 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/40523.pdf Socket AM3 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31839.pdf Low-Profile Socket S1 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31410.pdf AMD Functional Data Sheet, 754 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/24850.PDF Socket 754 Design and Qualification Requirements]
* [http://support.amd.com/us/Processor_TechDocs/31411.pdf AMD Functional Data Sheet, 939-Pin Package]
* [http://support.amd.com/us/Processor_TechDocs/23986.pdf Socket A AMD Processor and Heatsink Installation Guide]

=== Misc ===

* [http://support.amd.com/us/Processor_TechDocs/20734.pdf AMD Processor Recognition Application Note]
* [http://support.amd.com/us/Processor_TechDocs/22466.pdf AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets Manual]
* [http://support.amd.com/us/Processor_TechDocs/21928.pdf 3DNow!™Technology Manual]
** [http://support.amd.com/us/Processor_TechDocs/22621.pdf 3DNow!™ Instruction Porting Guide Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23794.pdf AMD Thermal, Mechanical, and Chassis Cooling Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/30579_3_74.pdf AMD Processor Performance Evaluation Guide]
* [http://support.amd.com/us/Processor_TechDocs/32035.pdf Compiler Usage Guidelines for AMD64 Platforms Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors]
* [http://support.amd.com/us/Processor_TechDocs/26951.pdf Thermal Interface Material Comparison: Thermal Pads vs. Thermal Grease]
* [http://support.amd.com/us/Processor_TechDocs/26003.pdf Builders Guide for Desktop/Tower Systems]
* [http://support.amd.com/us/Processor_TechDocs/26698.pdf Linux Kernel Issue with Systems Using AGP Graphics]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/30887.pdf Building AMD64 Applications with the Microsoft Platform SDK]
* [http://support.amd.com/us/Processor_TechDocs/30888.pdf Creating an AMD64 Build Enviroment for DirectX-Based Applations]
* [http://support.amd.com/us/Processor_TechDocs/33609.pdf Processor Utilization with Microsoft® Windows® Media Center Edition on Systems Enabled with Cool'n'Quiet™ and AMD PowerNow™ Technologies]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/tn17.pdf Microsoft Windows® 2000 Patch for AGP Applications on AMD Athlon™ and AMD Duron™ Processors]

== Intel ==

=== Intel Pentium III ===

* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii Highlights/Overview]
* [http://ark.intel.com/ProductCollection.aspx?familyID=590&MarketSegment=DT List of Pentium III models, steppings, etc.]
* [http://www.intel.com/support/processors/pentiumiii/sb/CS-023730.htm Intel® Pentium® III Processor: Datasheets]
** [http://download.intel.com/support/processors/pentiumiii/sb/24965705.pdf Intel® Pentium® III Processor with 512-KB L2 Cache at 1.13GHz to 1.40 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24976503.pdf Intel® Pentium® III Processor Based on 0.13 Micron Process Up to 1.33 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24526408.pdf Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24445209.pdf Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/27367306.pdf Low Voltage Intel® Pentium® III Processor 512-KB] (PDF)
* [http://www.intel.com/design/intarch/specupdt/244453.htm Intel® Pentium® III Processor Specification Update] ([http://download.intel.com/design/intarch/specupdt/24445358.pdf PDF])

Mobile:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-m Highlights/Overview]
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023739.htm Mobile Intel® Pentium® III Processor - M Datasheet] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/29834006.pdf PDF])
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023740.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/24530659.pdf PDF])
* [http://www.intel.com/design/intarch/specupdt/245306.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/design/intarch/specupdt/24530663.pdf PDF])
* [http://developer.intel.com/design/mobile/datashts/245302.htm Mobile Pentium® III Processor in BGA2 and Micro-PGA2 Packages] ([http://download.intel.com/design/mobile/datashts/24530202.pdf PDF])

Embedded:
* [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii.htm Embedded Intel® Architecture Processors: Intel® Pentium® III Processors: Technical Documents]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_pga370.htm Intel® Pentium® III Processor - PGA370]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_low.htm Intel® Pentium® III Processor - Low Power]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_vol.htm Low Voltage Intel® Pentium® III Processor]

Xeon:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-xeon Highlights/Overview]

== VIA ==

=== VIA Padlock ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=281 Security Application note]
* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 PadLock Programming Guide]

= Northbridge =

== AMD ==

=== AMD RS880 ===

* [http://support.amd.com/us/Embedded_TechDocs/46143_rs880_BDG_pub_3.00.pdf AMD RS880 Family BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46141_rs880_rpr_pub_3.00.pdf AMD RS880 Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/46142_rs880_rrg_pub_3.00.pdf AMD RS880 Family Register Reference Guide] (RRG)

=== AMD RD890 ===

Not public (yet?). However, some of the information may be contained in the public docs in the RS880 section.

* AMD RD890 BIOS Developer's Guide (Publication #43606)
* AMD RD890 Register Reference Guide (Publication #43607)

=== AMD RS780 ===

* [http://support.amd.com/us/Embedded_TechDocs/43734_rs780_bdg_pub_1.01.pdf AMD 780G Family BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf AMD 780G Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/43451_rs780_rrg_pub_1.01.pdf AMD 780G Family Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/45732_rs780e_ds_pub_3.10.pdf AMD 780E Databook]
* [http://support.amd.com/us/Embedded_TechDocs/48319.pdf AMD 780 Product Errata]

Apparently there are other docs as well, not sure if they provide any additional information or if they are part of the public documents above:

* AMD RD780 Register Reference Guide
* AMD RX780 Register Reference Guide
* AMD RS780M Hybrid Graphics – System BIOS Detailed Design Document (Publication #44969)
* AMD RD790 Register Programming Requirements (Publication #42462)
* AMD RD790 Register Reference Guide (Publication #42988)
* AMD RD790 BIOS Developer's Guide (Publication #43093)

=== AMD RS690 ===

* [http://support.amd.com/us/Embedded_TechDocs/43372_rs690_rrg_3.00o.pdf AMD RS690 Register Reference Guide] (RRG)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41977_rs690_ds_3.06.pdf AMD 690G Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41978_rs690m_ds_3.06.pdf AMD M690 Databook (Notebook Solutions)]
* [http://support.amd.com/us/Embedded_TechDocs/42437_m690t_ds_3_08.pdf AMD M690T/M690E Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD690Series_LogoGuide.pdf AMD 690 Chipset Logos]

=== Misc ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD_7-Series_Chipsets_-_Guidelines.pdf AMD 7-Series Chipsets - Guidelines.pdf]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD Model S1 DBM690T, Socket S1 and M690T/SB600 Chipset Development Board]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMDCrossFire_LogoGuide.pdf AMD 480X Chipset Logos]

== Intel ==

=== Intel Atom Z5xx and SCH US15Wx ===

* [http://ark.intel.com/ProductCollection.aspx?codeName=24973 Overview of products formerly named Poulsbo]
* [http://edc.intel.com/Platforms/Atom-Z5xx/#hardware Overview: Intel® Atom™ Processor Z5xx Series and Intel® System Controller Hub US15Wx]
** [http://edc.intel.com/Link.aspx?id=1387 Datasheet: Intel® System Controller Hub (Intel® SCH)] (PDF)
** [http://edc.intel.com/Link.aspx?id=1905 Datasheet: Intel® System Controller Hub (Intel® SCH) (large form factor)] (PDF)

=== Intel NM10 Express ===

* [http://www.intel.com/Products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm Overview]
** [http://www.intel.com/Assets/PDF/datasheet/322896.pdf Intel® NM10 Express Chipset Datasheet]
** [http://www.intel.com/Assets/PDF/specupdate/322897.pdf Intel® NM10 Express Chipset Specification Update]

=== Intel 860 ===

* [http://www.intel.com/design/archives/chipsets/860/index.htm Hardware Design: Archives - Intel® 860 Chipset Family Technical Documentation]
** [http://www.intel.com/design/chipsets/datashts/290713.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Datasheet]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
*** [http://www.intel.com/design/chipsets/specupdt/290715.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Specification Update]: [http://www.intel.com/design/chipsets/specupdt/29071501.pdf PDF]
** [http://www.intel.com/design/chipsets/applnots/292269.htm Intel® 860 Chipset Thermal Considerations Application Note (AP-721)]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298252.htm Intel® Xeon® Processor and Intel® 860 Chipset Platform Design Guide]: [http://download.intel.com/design/chipsets/designex/29825204.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298302.htm Intel® 860 Chipset Memory Expansion Card (MEC) Design Guide]: [http://download.intel.com/design/chipsets/designex/29830201.pdf PDF]
** [http://www.intel.com/design/chipsets/schematics/860_crb.htm Intel 860 Chipset CRB Schematics]: [http://download.intel.com/design/chipsets/schematics/860_crb.pdf PDF]

=== Intel 82815E ===

* [http://download.intel.com/design/chipsets/datashts/29068801.pdf 82815 Chipset Family]
* [http://download.intel.com/design/chipsets/designex/29823401.pdf 82815E Chipset Platform Design Guide]
* [http://download.intel.com/design/chipsets/designex/29824906.pdf 82815E Chipset Platform Design Guide update]

=== Intel 440BX ===

* [http://download.intel.com/design/chipsets/datashts/29063301.pdf Datasheet]
* [http://download.intel.com/design/chipsets/datashts/27321903.pdf Electrical and Thermal Timing Specification]

=== Intel 440LX ===

* [http://download.intel.com/design/chipsets/datashts/29056402.pdf Datasheet]
* [http://www.intel.com/design/chipsets/specupdt/29765505.pdf Spec update]

== VIA ==

VIA has a [http://linux.via.com.tw portal] with some source code and datasheets.

=== VIA VX800 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241 VIA VX800 Programming Manual]

=== VIA CX700M/VX700 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 VIA CX700M/VX700 Programming Manual]

= Southbridge =

== AMD ==

=== AMD SB820M ===

* [http://support.amd.com/us/Embedded_TechDocs/47283_sb820m_ds_pub_2.00.pdf AMD SB820M Southbridge Databook]

=== AMD SB810/SB850 ===

* [http://support.amd.com/us/Embedded_TechDocs/44758.pdf AMD SB810/SB850 Southbridge Databook]

=== AMD SB800 ===

Not available yet, but here are the numbers for the documents we'd like to get. I found these numbers with a creative Internet search.

* AMD SB800 Databook (Publication #44758)

=== AMD SB700/SB710/SB750 ===

* [http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf AMD SB700/710/750 BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf AMD SB700/710/750 Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/42413_sb7xx_rpr_pub_1.00.pdf AMD SB700/710/750 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/45215_sb710_ds_pub_1.25.pdf AMD SB710 Databook]
* [http://support.amd.com/us/Embedded_TechDocs/46837.pdf AMD SB700 Family Product Errata]

=== AMD SB600 ===

* [http://support.amd.com/us/Embedded_TechDocs/46157_sb600_bdg_pub.3.00.pdf AMD SB600 BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46155_sb600_rrg_pub_3.03.pdf AMD SB600 Register Reference Manual] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/46156_sb600_rpr_pub_3.02b.pdf AMD SB600 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42119_sb600_ds_3.05.pdf AMD SB600 Databook] (rev. 3.05)
* [http://support.amd.com/us/Embedded_TechDocs/42119_sb600_ds_pub_3.07.pdf AMD SB600 Databook] (rev. 3.07)

=== AMD 8111 ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/24674.pdf AMD-8111™ HyperTransport™ I/O Hub Data Sheet]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/26036.pdf AMD-8111™ HyperTransport™ I/O Hub Product Brief]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/25720.pdf AMD-8111™ HyperTransport™ I/O Hub Revision Guide]

== Intel ==

=== Intel 82801BA/BAM (ICH2) ===

* [http://developer.intel.com/design/chipsets/datashts/290687.htm Datasheet]

= Super I/O =

== ITE ==

* [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 PC Desktop/Notebook Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 Desktop Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=6 Notebook Super I/Os]

== Winbond / Nuvoton ==

* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/ISASuperIO/ ISA Super I/Os]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/LPCSuperIOforDesktopAndServer/ LPC Super I/O for Desktop & Server]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforDesktop/ Advanced Super I/O for Desktop]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforNotebook/ Advanced Super I/O for Notebook]

== Fintek ==

* [http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17&layer=0 Super Hardware Monitor + SIO]

== NSC ==

(bought by Winbond, now Nuvoton)

== ALi ==

== SMSC ==

* [http://www.smsc.com/main/catalog/ioprods.html Products / datasheets overview]
* [http://www.smsc.com/main/datasheet.html Various product datasheets]

= Other =

== ACPI ==

* http://www.acpi.info

== USB ==

== Misc ==

* [http://support.amd.com/us/Pages/techdocs.aspx AMD public documents]
** The [http://www.amd.com/us/products/embedded/develop-and-design/Pages/processor-chipset-linux-supprt.aspx AMD64 Embedded Processors and Chipset Linux Support] web page features links to supported projects (like coreboot) and links to documentation.

= Resources =

There are many datasheet archives on the web which may have other (usually older) datasheets which already disappeared from vendor websites.

GIGABYTE GA-6BXC

2010-12-24T11:56:40Z

Uwe:

This page describes how to use coreboot on the [http://www.gigabyte.com/products/product-page.aspx?pid=1445 GIGABYTE GA-6BXC] mainboard.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status = OK
|CPU_L2_status = WIP
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it.
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = N/A

|RAM_EDO_status = WIP
|RAM_SDRAM_status = OK
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = N/A
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = N/A
|RAM_ecc_status = WIP
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.

|IDE_status = OK
|IDE_25_status = N/A
|SATA_status = N/A
|USB_status = OK
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = N/A
|Onboard_audio_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A
|Onboard_SCSI_status = N/A

|ISA_cards_status = Untested
|AMR_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Tested: PCI NIC in all PCI slots.
|Mini_PCI_cards_status = N/A
|PCIX_cards_status = N/A
|AGP_cards_status = OK
|PCIE_cards_status = N/A
|PCIE_x1_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = N/A
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = WIP
|COM1_status = OK
|COM2_status = OK
|PP_status = OK
|PP_comments = Doing '''modprobe ppdev''' seems to work, everything else is untested.
|PS2_keyboard_status = WIP
|PS2_keyboard_comments = Doesn't seem to work, yet. This is being investigated.
|PS2_mouse_status = WIP
|Game_port_status = N/A
|IR_status = Untested
|Speaker_status = OK
|DiskOnChip_status = N/A

|Sensors_status = Untested
|Watchdog_status = N/A
|SMBus_status = N/A
|CAN_bus_status = N/A
|CPUfreq_status = N/A
|Powersave_status = N/A
|ACPI_status = No
|ACPI_comments = There is no ACPI implementation for this board, yet.
|Reboot_status = OK
|Poweroff_status = No
|Poweroff_comments = Needs ACPI.
|LEDs_status = Untested
|HPET_status = N/A
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = No
|WakeOnLAN_comments = NIC is powered off when the system is off.
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = OK

}}

{{PD-self}}

Supported Motherboards

2010-12-23T23:19:37Z

Uwe: /* Motherboards supported in coreboot v4 */ Fix typo, thanks aladds on IRC for pointing it out.

{| border="0" valign="top" width="100%"
| valign="top"|
See the page [[Confirmed working svn revisions]] for a table of which revision to start testing with on your particular mainboard. Click on the Status column bellow to learn more info about the board.

'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards. For AMD Geode LX targets, '''coreboot v3''' might be better than coreboot v4 in some minor aspects, but most features should be ported to v4 by now.
* If a mainboard is not supported by coreboot v4, try [[Supported_Motherboards#Motherboards_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Motherboards#Motherboards_supported_in_coreboot_v3|coreboot v3]] for support.
* However, in general it is '''not''' recommended to use coreboot v3 — this was an experimental development tree which is gradually being merged into v4.
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.

See also [[Supported Chipsets and Devices|Supported Chipsets & Devices]].

| valign="top" align="right"|

'''Color Legend'''
{| border="1" style="font-size: smaller"
|- bgcolor="#eeeeee"
| style="background:red" | Motherboard is work in progress, unfinished, or on hold.
|-
| style="background:yellow" | Motherboard mostly works, but some issues remain.
|-
| style="background:lime" | Motherboard is fully supported.
|}

|}

== Motherboards supported in coreboot v4 ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | ROM 35
! align="left" | P 36
! align="left" | S 37
! align="left" | F 38
! align="left" | VCS4

|- bgcolor="#6699ff"
| colspan="13" | '''Desktops / Workstations'''

|- bgcolor="#dddddd"
| Abit
| [http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAME=BE6-II+V2.0&fMTYPE=Slot+1 Abit BE6-II V2.0]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| —
| —

|- bgcolor="#eeeeee"
| ASRock
| [http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939 939A785GMH/128M]
| AMD K8
| AMD® RS785/SB710
| Winbond™ W83627DHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:yellow" | [[ASRock 939A785GMH-128M|WIP...]]
| DIP8
| SPI
| ?
| ?
| —

|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=171&l4=0&model=455&modelmenu=2 A8N-E]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8N-E|OK...]]25
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK A8N-SLI]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS_A8N-SLI|OK...]]25
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?modelmenu=1&model=596&l1=3&l2=15&l3=207 A8N5X]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8N5X|OK...]]25
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&modelmenu=1 A8V-E SE]
| AMD K8
| VIA K8T890 / VT8237R
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8V-E SE|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&modelmenu=1 A8V-E Deluxe]
| AMD K8
| VIA K8T890 / VT8237R
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8V-E Deluxe|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&modelmenu=1 M2A-VM]
| AMD 690G
| ATI SB600
| ITE™ IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2(+)
| style="background:lime" | [[ASUS M2A-VM|OK...]]
| PLCC
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 M2N-E]
| AMD K8
| NVIDIA MCP55
| ITE™ IT8716F
| AMD Athlon™ 64 / FX / X2 / Phenom
| Socket AM2
| style="background:lime" | [[ASUS M2N-E|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=OqYlEDFfF6ZqZGvp M2V]
| AMD K8
| VIA K8T890CF / VT8237A
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[ASUS M2V|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=324&l4=0&model=1807&modelmenu=1 M2V-MX SE]
| AMD K8
| VIA K8M890 / VT8237S
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[ASUS M2V-MX SE|OK...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=ef0qgvMIwOUagAVl M4A785-M]
| AMD Fam10h
| AMD RS780/SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3/AM2(+)
| style="background:yellow" | [[ASUS M4A785-M|WIP...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=0KyowHKUFAQqH2DO M4A78-EM]
| AMD Fam10h
| AMD RS780/SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3/AM2(+)
| style="background:lime" | [[ASUS M4A78-EM|OK...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ MEW-AM]
| Intel® 82810
| Intel® 82801AA (ICH)
| SMSC® LPC47B272
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[ASUS MEW-AM|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| ASUS
| [http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm MEW-VM]
| Intel® 82810
| Intel® 82801AA (ICH)
| SMSC® LPC47B272
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:yellow" | WIP28
| PLCC
| ?
| style="background:lime" | Y
| style="background:red" | N
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ P2B]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P2B|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ P2B-F]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P2B-F|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ P2B-D]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| 2x Slot 1
| style="background:lime" | [[ASUS P2B-D|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ P2B-DS]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| 2x Slot 1
| style="background:lime" | [[ASUS P2B-DS|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ P2B-LS]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P2B-LS|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | ...43
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ P3B-F]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P3B-F|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| A-Trend
| [http://www.motherboard.cz/mb/atrend/atc6220.htm ATC-6220]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[A-Trend ATC-6220|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| A-Trend
| [http://active-hardware.com/english/reviews/mainboard/atc6240.htm ATC-6240]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83627HF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| ?
| —

|- bgcolor="#dddddd"
| AZZA
| [http://web.tiscali.it/acorp/?http://web.archive.org/web/20050426181911/http://web.tiscali.it/acorp/mobo_spec/azza/pt-6ibd/pt-6ibd.htm PT-6IBD]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[AZZA PT-6IBD|OK...]]
| DIP32
| Parallel
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Biostar
| [http://www.motherboard.cz/mb/biostar/M6TBA.htm M6TBA]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMSC FDC37M60x
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[Biostar M6TBA|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| Compaq
| Deskpro EN SFF P600
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC97307
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| ?
| —


|- bgcolor="#eeeeee"
| ECS
| [http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&DetailID=95&DetailName=Feature&MenuID=24&LanID=4 P6IWP-Fe]
| Intel® 82810
| Intel® 82801AA (ICH)
| ITE IT8712F
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[ECS P6IWP-Fe|OK]]
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[GIGABYTE GA-6BXC|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| —| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1430 GA-6BXE]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[GIGABYTE GA-6BXE|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/ GA-2761GXDK] (Churchill)
| AMD K8
| SiS761GX/SiS966
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2 (?)
| Socket AM2
| style="background:lime" | [[GIGABYTE GA-2761GXDK|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&ModelName=GA-M57SLI-S4 GA-M57SLI-S4]
| AMD K8
| NVIDIA MCP55
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[GIGABYTE GA-M57SLI-S4|OK...]]
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| style="background:yellow; text-align:center" | [[Gigabyte m57sli Vendor Cooperation Score|3]]
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com/products/product-page.aspx?pid=3274 GA-MA785GMT-UD2H]
| AMD Fam10h
| AMD 785G / SB710
| ITE IT8718F
| AMD Phenom™ II / Athlon™ II
| Socket AM3
| style="background:lime" | [[GIGABYTE GA-MA785GMT-UD2H|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com/products/product-page.aspx?pid=2995 GA-MA78GM-US2H]
| AMD Fam10h
| AMD 780G / SB700
| ITE IT8718F
| AMD Phenom™ / Athlon™ / Sempron™
| Socket AM2+
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| HP
| e-Vectra P2706T
| Intel 82810E
| Intel 82801AA (ICH)
| NSC PC87364
| Intel® Pentium® III / Celeron®
| PGA370
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Intel
| [http://support.gateway.com/s/MOTHERBD/INTEL/2514906/2514906nv.shtml D810E2CB]
| Intel® 82810E
| Intel® 82801BA (ICH2)
| SMSC LPC47M102
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[Intel D810E2CB|OK...]]
| PLCC
| FWH
| N
| ?
| —
|- bgcolor="#dddddd"
| Intel
| [http://www.intel.com/Products/Desktop/Motherboards/D945GCLF/D945GCLF-overview.htm D945GCLF]
| Intel® 945GC
| Intel® ICH7
| SMSC LPC47M15x
| Intel® Atom™
| Socket 441
| style="background:red" | WIP44
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Mitac
| [http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/products/tyan/6513wu/6513wu.htm 6513WU]
| Intel® 82810E
| Intel® 82801AB (ICH0)
| SMSC LPC47U332
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[Mitac 6513WU|OK...]]
| PLCC
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=332&maincat_no=1 MS-6119]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&maincat_no=1&prod_no=335 MS-6147]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| style="background:lime" | Y
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/Boards/Motherboards/MicroStar/Ms6156/MS6156.htm MS-6156]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| MSI
| [http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no=1 MS-6178]
| Intel® 82810
| Intel® 82801AB (ICH0)
| Winbond™ W83627HF
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[MSI MS-6178|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=170&maincat_no=1 MS-7135 (K8N Neo3)]
| AMD K8
| NVIDIA CK8046
| Winbond® W83627THF
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
| Socket 754
| style="background:lime" | [[MSI MS-7135|OK...]]
| PLCC
| LPC
| style="background:yellow" | ...29
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=255&maincat_no=1&cat2_no=171 MS-7260 (K9N Neo)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Sempron™ / Athlon™ 64 / X2
| Socket AM2
| style="background:lime" | [[MSI MS-7260|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:yellow" | ...39
| —

|- bgcolor="#eeeeee"
| NEC
| [http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ PowerMate 2000]
| Intel® 82810
| Intel® 82801AB (ICH0)
| SMSC® LPC47B27x
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[NEC PowerMate 2000|OK...]]
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| Shuttle
| [http://global.shuttle.com/product_detail.jsp?PI=89 SN25P]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Sempron™ / Athlon™ 64 / X2 / Opteron™ 1XX
| Socket 939
| style="background:red" | [[Shuttle SN25P|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Soyo
| Soyo SY-6BA+ III
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[Soyo SY-6BA Plus III|OK]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| Sun
| [http://www.sun.com/desktop/workstation/ultra40/index.xml Ultra 40]
| AMD K8
| NVIDIA CK8045
| SMSC® LPC47B397
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami ATX (S1846)]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87309
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/tigerk8w.html Tiger K8W (S2875)]
| AMD K8
| AMD-8111™, 8151™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8w.html Thunder K8W (S2885)]
| AMD K8
| AMD-8111™, 8131™, 8151™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8we.html Thunder K8WE (S2895)]
| AMD K8
| AMD-8131™, NVIDIA CK8045
| SMSC® LPC47B397
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Servers'''

|- bgcolor="#eeeeee"
| agámi
| [http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-6000-series Aruma/AIS6000 series]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD K8
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD Fam10h
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Arima
| [http://web.archive.org/web/20080127024444/http://www.arima.com.tw/server/Product/ViewProduct.asp?View=HDAMA HDAMA]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87360
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Dell
| [http://support.dell.com/support/edocs/systems/pe1850/en/index.htm PowerEdge 1850]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:yellow" | WIP2
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| HP
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 ProLiant DL145 G3]
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| AMD Opteron™
| Socket F
| style="background:lime" | [[HP DL145 G3|OK]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IBM
| [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-53255 eServer 325]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87366
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IBM
| [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-58655 eServer 326]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87366
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Intel
| [http://www.intel.com/support/motherboards/server/se7520jr2/ Jarrell (SE7520JR2)]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| NSC PC87427
| Intel® Xeon®
| ?
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 DK8-HTX]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[IWILL DK8-HTX|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060509143427/http://www.iwill.net/product_2.asp?p_id=42&sp=Y DK8S2]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060213163325/http://www.iwill.net/product_2.asp?p_id=28 DK8X]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| MSI
| [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx K9SD Master-S2R (MS-9185)]
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| AMD Opteron™
| Socket F
| style="background:lime" | OK12
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 K9SD Master (MS-9282)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK15
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Newisys
| [http://web.archive.org/web/20070922231423/http://www.newisys.com/core/2100e.html 2100 Server] (SUN Fire v20z)
| AMD K8
| AMD-8111™, 8131™
| NSC PC87360
| AMD Opteron™
| Socket F
| style="background:lime" | OK7
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Nokia
| [http://press.nokia.com/PR/200103/813151_5.html IP530]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ FDC37C878
| Intel® Pentium® II/III, Celeron®
| Socket 370
| style="background:lime" | [[Nokia IP530|OK...]]
| DIP32
| Parallel
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]
| AMD Fam10h
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm H8DME-2]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK41
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DAi-G]
| Intel® E7525
| Intel® E7525, ESB6300
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DHE-G]
| Intel® E7520
| Intel® E7520, ESB6300
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHE-G2.cfm X6DHE-G2]
| Intel® E7520
| Intel® 82801ER (ICH5R), ESB6300
| NSC PC87427
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG.cfm X6DHR-iG]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG2.cfm X6DHR-iG2]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigeri7501r.html Tiger i7501R (S2735)]
| Intel® E7501
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tomcatk8s.html Tomcat K8S (S2850)]
| AMD K8
| AMD-8111™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8s.html Thunder K8S (S2880)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8sr.html Thunder K8SR (S2881)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2881|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8spro.html Thunder K8S Pro (S2882)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2882|OK...]]20
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8sre.html Thunder K8SRE (S2891)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2891|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8se.html Thunder K8SE (S2892)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2892|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder n3600R (S2912)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | [[Tyan S2912|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder n3600R (S2912)]
| AMD Fam10h
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | [[Tyan S2912|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8qs.html Thunder K8QS (S4880)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8qspro.html Thunder K8QS Pro (S4882)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Laptops'''

|- bgcolor="#dddddd"
| Getac
| [http://en.getac.com/products/P470/P470_overview.html P470]
| Intel® 945
| Intel® ICH7
| SMSC® FDC37N972 + SIO10N268
| Intel® Core 2 Duo T7200
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Roda
| [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html RK886EX (Rocky III+)]
| Intel® 945
| Intel® ICH7
| SMSC® LPC47N227
| Intel® Core 2 Duo Mobile T5500
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Embedded / SBC / PC/104 / Half-size boards'''

|- bgcolor="#eeeeee"
| Advantech
| [http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8 PCM-5820]
| AMD GX1
| AMD CS5530A
| Winbond® W83977AF
| AMD Geode™ GX1
| —
| style="background:lime" | [[Advantech PCM-5820|OK...]]
| PLCC32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| AMD
| Rumba
| AMD GX9
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™GX9
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.com/english/products/datasheets/ecm855.asp smartModule855]
| Intel® 855PM
| Intel® 82801DBM (ICH4-M)
| Winbond™ W83627HF
| ?
| ?
| style="background:red" | WIP13
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG MSM586SEG]
| integrated
| integrated
| integrated
| AMD Élan™SC520
| —
| style="background:yellow" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV MSM800SEV]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK22
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| EagleLion
| 5BCM
| AMD GX1
| AMD  CS5530
| NSC PC97317
| ?
| —
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| IEI
| [http://www.icpamerica.com/products/single_board_computers/5_25_NOVA/NOVA-4899.html NOVA-4899R]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977TF
| AMD Geode™ GX1
| —
| style="background:yellow" | WIP17
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/news_content.asp?id=erbium/projectOBJ00150613 JUKI-511P]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977F
| AMD Geode™ GX1
| —
| style="background:lime" | [[IEI JUKI 511P|OK...]]27
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX IEI PCISA-LX-800-R10]
| AMD LX
| AMD Geode™ CS5536
| Winbond™ W83627EHG
| AMD Geode™ LX
| —
| style="background:lime" | [[IEI LX 800|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/product_IPC.asp?model=ROCKY-512 ROCKY-512]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977F
| AMD Geode™ GX1
| —
| style="background:lime" | [[IEI ROCKY 512|OK...]]27
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| iWave
| [http://www.iwavesystems.com/iW-RainbowG6.htm iW-RainboW-G6]
| Intel Poulsbo US15W
| Intel Poulsbo US15W
| —
| Intel Atom Z530/Z510
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/productoverview/products-in-detail/85-lipperts-cool-frontrunner.html Cool FrontRunner]
| AMD GX9
| AMD CS5535
| Winbond™ W83627HF
| AMD Geode™ GX
| —
| style="background:red" | WIP2
| PLCC
| FWH
| style="background:lime" | Y
| ?
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-hurricane-lx800.html Hurricane-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-cool-literunner-lx800.html Cool LiteRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-cool-roadrunner-lx800.html Cool RoadRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-cool-spacerunner-lx800.html Cool SpaceRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| PC Engines
| [http://pcengines.ch/alix1c.htm ALIX.1C]
| AMD Geode™ LX
| AMD Geode™ CS5536
| Winbond® W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.1C|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| style="background:lime; text-align:center" | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]

|- bgcolor="#eeeeee"
| TechNexion
| [http://www.technexion.com/index.php/embedded-mainboards/amd/tim-5690 TIM-5690]
| AMD M690E
| ATI SB600
| ITE IT8712F
| AMD Sempron
| Socket AM2(+)
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| TechNexion
| [http://www.technexion.com/index.php/tim-8690 TIM-8690]
| AMD M690E
| ATI SB600
| ITE IT8712F
| AMD Sempron™ / Athlon™ 64 / X2
| Socket AM2
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Traverse Technologies
| [http://www.traverse.com.au/productview.php?product_id=117 Geos]
| AMD LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK
| PLCC
| ?
| style="background:lime" | Y
| ?
| —

|- bgcolor="#eeeeee"
| TS31
| [http://www.embeddedarm.com/epc/ts5300-spec-h.html TS-5300]
| integrated
| integrated
| integrated
| AMD Élan™SC520
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Mini-ITX / Micro-ITX / Nano-ITX'''

|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F2|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E J7F4K1G2E]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F4K1G2E|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4K1G5D J7F4K1G5D]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F4K1G5D|OK...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Kontron
| [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]
| Intel® 945
| Intel® ICH7
| 2x Winbond® W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| mPGA478
| style="background:lime" | [[Kontron 986LCD-M mITX|OK...]]
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Kontron
| [http://us.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx.html KT690/mITX]
| AMD M690T
| ATI SB600
| Winbond™ W83627DHG
| AMD Turion64™ dual core / AMD Sempron
| Socket AM2(+)
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=1054&maincat_no=388# Fuzzy CN700]
| VIA CN700
| VIA VT8237R(P)
| Winbond™ W83627EHG
| VIA C7™
| NanoBGA2
| style="background:yellow" | [[MSI FUZZY CN700|WIP...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]
| VIA VT8601
| VIA VT8231
| Winbond™ W83627HF
| VIA C3™, VIA EDEN™
| —
| style="background:yellow" | [[EPIA|WIP...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-M|OK...]]10
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| EPIA-M700
| VIA VX800
| VIA VX800
| Winbond W83697HF/F/HG
| ?
| ?
| style="background:red" | [[VIA EPIA-M700|WIP...]]
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=202 EPIA-MII]
| VIA VT8623
| VIA VT8235, Ricoh RL5C476
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-MII|OK...]]8
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=301 EPIA-ML]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-ML|OK...]]10
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN10000EG]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-CN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN13000G]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-CN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN12000EG]
| VIA CN700
| VIA VT8237R
| Winbond™ W83627EHG
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA EPIA-EN|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN15000G]
| VIA CN700
| VIA VT8237R
| Winbond™ W83627EHG
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA EPIA-EN|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=473 EPIA-LN10000EG/EAG]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-LN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7400]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA NAB7400|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7410]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA NAB7410|WIP...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.idot.com.tw/en/products/mb-pc2500e/ pc2500e]
| VIA CN700
| VIA VT8237R
| ITE IT8716F
| VIA C7™, VIA Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA pc2500e|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.idotpc.com/TheStore/pc/viewCategories.asp?idCategory=56 EPIA-N]
| VIA CN400
| VIA VT8237R
| Winbond W83697HF
| ?
| ?
| style="background:yellow" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Set-top-boxes / Thin clients'''

|- bgcolor="#eeeeee"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE61]
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:red" | Broken40
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| ASI
| MB-5BLGP32
| AMD GX1
| AMD CS5530
| NSC PC87351
| AMD Geode™ GX1
| —
| style="background:lime" | [[ASI MB-5BLGP|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| ASI
| [http://www.hojerteknik.com/winnet.htm MB-5BLMP]33
| AMD GX1
| AMD CS5530
| NSC PC87351
| AMD Geode™ GX1
| —
| style="background:lime" | [[ASI MB-5BLMP|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| AXUS
| [http://www.keyton.co.jp/products/UAXT/TC-320.html TC320]
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[AXUS TC320|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| BCOM
| [http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_compact.htm WinNET100]34
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[BCOM WINNET100|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| BCOM
| WinNET P680
| VIA CN700
| VIA VT8237R Plus
| Winbond™ W83697HG
| Via C7™
| —
| style = "background:yellow" | [[BCOM WinNET P680|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Linutop
| [http://linutop.com/ Linutop]
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK19
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| RCA
| [http://www.settoplinux.org/index.php?title=RCA_RM4100 RM4100]
| Intel® 82830M
| Intel® 82801DB (ICH4)
| SMSC® LPC47M192
| Intel® Mobile Celeron
| Socket 479
| style="background:lime" | [[RCA RM4100|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| TeleVideo
| [http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm TC7020]
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[TeleVideo TC7020|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Thomson
| [http://www.settoplinux.org/index.php?title=Thomson_IP1000 IP1000]
| Intel® 82830M
| Intel® 82801DB (ICH4)
| SMSC® LPC47M192
| Low Voltage Intel® Pentium® III
| Socket 479
| style="background:lime" | [[Thomson IP1000|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| Wyse
| [http://www.wyse.de/products/hardware/thinclients/S50/index.asp S50]
| AMD GX2
| AMD CS5536
| —
| AMD Geode™ GX2
| —
| style="background:lime" | OK
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Devel/Eval Boards'''

|- bgcolor="#eeeeee"
| AMD
| [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800] (Salsa)
| AMD LX
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Norwich
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK21
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T] (Herring)
| AMD K8
| AMD RS690/SB600
| ITE IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| style="background:lime" | [[AMD DBM690T|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| AMD
| Mahogany
| AMD K8
| AMD RS780E/SB700
| ITE IT8718F
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| style="background:lime" | OK
| ?
| SPI
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Mahogany
| AMD Fam10h
| AMD RS780E/SB700
| ITE IT8718F
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| style="background:lime" | OK
| ?
| SPI
| ?
| ?
| —

|- bgcolor="#eeeeee"
| AMD
| Pistachio
| AMD K8
| AMD RS690/SB600
| —
| ?
| Socket AM2
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Tilapia
| AMD Fam10h
| AMD RS780/SB700
| ITE IT8718F
| ?
| Socket AM3
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Broadcom
| Blast
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| ?
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Intel
| 3100 devkit (Mt. Arvon)
| Intel® 3100
| Intel® 3100
| Intel® 3100
| Intel® Pentium® M
| Socket 479
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| EagleHeights
| Intel® 3100
| Intel® 3100
| Intel® 3100
| Intel® Pentium® M
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| EP80579 devkit (Truxton)
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| XE7501devkit
| Intel® E7501
| Intel® 82801CA (ICH3-S)
| SMSC® LPC47B272
| ?
| ?
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| NVIDIA
| l1_2pvv
| AMD K8
| NVIDIA MCP55+IO55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK14
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| VIA
| VT8454c
| VIA CX700
| integrated
| integrated
| VIA C7™
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Miscellaneous'''

|- bgcolor="#eeeeee"
| Emulation
| [http://fabrice.bellard.free.fr/qemu/ QEMU x86]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| —
| Intel® Pentium® II/III (?)
| —
| style="background:lime" | [[QEMU Build Tutorial|OK...]]
| ?
| ?
| ?
| ?
| —

|}


1 NVIDIA nForce™ Professional 2200 (CK804). 
2 Work in progress. 
3 This was an AMD64 reference board. 
4 Vendor Cooperation Score. 
5 NVIDIA nForce™ Professional 2200 and 2050 (2 × CK804). 
6 NVIDIA nForce™ 4, nForce 4 SLI, or nForce 4 4x. 
7 LSI1030 SCSI controller can not be used to boot the machine. 
8 Use the ''epia-m'' code for now. The on-board PCMCIA and CF sockets work. coreboot can boot from CF (the stock BIOS can't). [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016448.html Some problems] remain, though. 
9 The AMD GX (internally known as GX2 for some time) is actually the successor to the GX1. 
10 Use the ''epia-m'' code for now (plus [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016423.html a few hacks], e.g. disable Firewire/CF slot,
because they're not present on the board). 
12 Except for some [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016463.html possible problems with SATA2 ports], everything should work. 
13 See also http://www.linuxbios.org/pipermail/linuxbios/2006-November/017065.html. 
14 These boards ''should'' work fine, but we have no confirmed reports on the [[Mailinglist|mailing list]] so far, so we cannot tell for sure. 
15 See http://www.openbios.org/pipermail/linuxbios/2007-February/018299.html. 
17 Seems to be [http://www.linuxbios.org/pipermail/linuxbios/2006-November/016651.html partially working], specifically eth0, eth2, the PCI slot, the USB ports, and the serial console [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021226.html are working]. Other parts are not yet finished. 
19 The Linutop does not ship with coreboot, but [http://linutop.com/wiki/index.php/Developers#Upgrading_to_LinuxBIOS the code should work]. 
20 Fan-control doesn't work yet. 
21 This is ''the'' AMD Geode LX reference board and coreboot reference implementation on the AMD Geode LX, contributed and maintained by AMD engineers. 
22 The board can boot a Linux kernel currently, but there's [http://www.linuxbios.org/pipermail/linuxbios/2007-May/020770.html no VGA support, yet]. 
25 [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021280.html Works fine], only smaller issues remain to be fixed. A [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021308.html list of known issues] is available. 
27 The JUKI-511P and ROCKY-512 both use the same code and target (targets/iei/juki-511p). Thus, both [http://www.linuxbios.org/pipermail/linuxbios/2007-June/021862.html support the same features and have the same limitations]: IDE, USB, ethernet, serial, keyboard and sound work, but there are problems booting from IDE1 ([http://www.linuxbios.org/pipermail/linuxbios/2007-June/021996.html this patch] may help), and VGA video doesn't work, yet. 
28 Partially supported, almost boots a Linux kernel. [http://www.linuxbios.org/pipermail/linuxbios/2007-June/022217.html Some issues] still remain to be fixed, though. 
29 Some boards have ROM sockets, others are soldered. 
30 The irq table in CN is from VIA. You may need to run getpir to generate your own irq table. 
31 Technologic Systems. 
32 Used in the Neoware Eon 4000s thin client. 
33 Used in the IGEL WinNET III thin client. 
34 Used in the IGEL-316 thin client. 
35 ROM chip package (PLCC, DIP32, DIP8, SOIC8). 
36 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 
37 ROM chip socketed (Y/N)? 
38 Board supported by [[Flashrom]] (Y/N)? 
39 Interestingly [[flashrom]] does not work when the vendor BIOS is booted, but it does work flawlessly when the machine is booted with coreboot. 
40 Broken v4 port, try the v3 port instead. The v4 version will be fixed at some point. 
41 RAM must be matched exactly in each bank. 
43 Works. Until flashrom officially supports this board, force it with ASUS P2B-F as the mainboard target. 
44 Boots MS-DOS fine using SeaBIOS, might boot Linux. 


== Motherboards supported in coreboot v3 ==

<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 have been integrated in what now became v4.</div>

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | ROM 1
! align="left" | P 2
! align="left" | S 3
! align="left" | F 4
! align="left" | VCS5
! align="left" | v3 only 7

|- bgcolor="#eeeeee"
| Advanced Digital Logic
| [http://www.adlogic-pc104.com/products/cpu/datasheets/MSM800SEV_SEL.pdf MSM800SEV]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N

|- bgcolor="#dddddd"
| AMD
| DB800
| AMD Geode™ LX
| AMD CS5536
| ?
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| AMD
| [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T] (Herring)
| AMD K8
| AMD RS690/SB600
| ITE IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| AMD
| Norwich
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD K8
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N

|- bgcolor="#eeeeee"
| AMP
| TinyGX
| AMD Geode™ LX
| AMD CS5536
| ITE IT8716F
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y

|- bgcolor="#dddddd"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE61]
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| TSOP32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE62]
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[Artec Group DBE62|OK...]]
| TSOP32
| FWH
| style="background:red" | N
| style="background:lime" | Y
| style="background:lime; text-align:center" | [[Artec Group DBE62 Vendor Cooperation Score|4]]
| style="background:red" | Y

|- bgcolor="#eeeeee"
| Emulation
| [http://fabrice.bellard.free.fr/qemu/ QEMU x86]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| —
| Intel® Pentium® II/III (?)
| —
| style="background:lime" | OK
| —
| ?
| —
| —
| —
| style="background:lime" | N

|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&ModelName=GA-M57SLI-S4 GA-M57SLI-S4]
| AMD K8
| NVIDIA MCP55
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2
| style="background:orange" | WIP
| ...6
| ?
| style="background:red" | N
| style="background:lime" | Y
| style="background:yellow; text-align:center" | [[Gigabyte m57sli Vendor Cooperation Score|3]]
| style="background:lime" | N

|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y

|- bgcolor="#dddddd"
| Kontron
| [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]
| Intel® 945
| Intel® ICH7
| 2x Winbond® W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| mPGA478
| style="background:orange" | WIP
| PLCC
| ?
| ?
| ?
| —
| style="background:lime" | N

|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix1c.htm ALIX.1C]
| AMD Geode™ LX
| AMD Geode™ CS5536
| Winbond® W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.1C|OK...]]
| ?
| ?
| ?
| ?
| style="background:lime; text-align:center" | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]
| style="background:lime" | N
|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix2c3.htm ALIX.2C3]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.2CX|OK...]]
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y
|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix2c2.htm ALIX.2C2]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.2CX|OK...]]
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y

|- bgcolor="#dddddd"
| VIA
| EPIA-CN
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N

|}


1 ROM chip package (PLCC, DIP32, DIP8, SOIC8). 
2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 
3 ROM chip socketed (Y/N)? 
4 Board supported by [[Flashrom]] (Y/N)? 
5 Vendor Cooperation Score. 
6 There are two versions of the [[GIGABYTE GA-M57SLI-S4]], one with a soldered PLCC chip, one with a soldered SOIC8 chip. 
7 Board is only available in v3, not yet in v4? 



== Motherboards supported in coreboot v1 ==

Not all motherboards have been ported from coreboot v1 to coreboot v4, yet (check the CBv4 field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | CBv4?

|- bgcolor="#6699ff"
| colspan="9" | '''Desktops / Workstations'''

|- bgcolor="#eeeeee"
| ASUS
| A7M
| AMD AMD76x
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| ASUS
| [http://www.ciao.co.uk/ASUS_ALi_Chipset_CUA__5410161 CUA]
| Acer M1631 (ALADDiN TNT2)
| Acer M1535
| Acer M1535
| Intel® Pentium® III
| Socket 370
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| ASUS
| [http://www.dealtime.com/xPF-ASUS-ASUS-Intel-Socket7-PNP586-Motherboard TX97-LE]
| Intel® 430TX
| Intel® 82371EB (PIIX4E)
| SMC FDC37C67X
| Intel® Pentium®, Pentium® MMX, AMD K5
| Socket 7
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Bitworks
| IMS
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87351
| ?
| Slot1 1
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Chaintech
| [http://www.xbitlabs.com/articles/mainboards/display/chaintech-7kjd.html CT-7KJD]
| AMD-761™
| VIA VT8231
| VIA VT8231
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Elitegroup (ECS)
| [http://www.ecsusa.com/products/k7sem_v3.html K7SEM]
| SiS730S
| SiS730S
| SiS730S
| AMD Athlon™ / Athlon™ XP / Duron™
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Elitegroup (ECS)
| [http://www.ecsusa.com/downloads/manual_p6s.html P6STP-FL]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot1 1
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee"
| GIGABYTE
| GA-6OXE
| Intel® 815EP
| Intel® 82801
| ITE IT8712F
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Leadtek
| [http://web.archive.org/web/20000616073856/http://www.leadtek.com.tw/e6300MAX.htm WinFast 6300MAX]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Matsonic
| [http://web.archive.org/web/20000619011053/www.matsonic.com/index_2.htm MS7308E]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:lime" | OK3
| style="background:red" | No

|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m754lmr.asp M754LMR]
| Acer M1631
| Acer M1535
| Acer M1535
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m758mr.asp M758LMR(+)]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m787cl%2B.asp M787CL+]
| SiS630
| SiS630
| SiS950
| VIA C3™
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m810lmr.asp M810LMR]
| SiS670
| SiS670
| SiS950
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| M810LR
| SiS670
| SiS670
| SiS950
| AMD Athlon™ / Duron™
| Socket 462
| style="background:lime" | [[PCCHIPS M810LR|???]]
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m830lmr.asp M830L(M)R]
| SiS735
| SiS735
| SiS950
| AMD Athlon™ / Athlon™ XP / Duron™
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/860/P4DC6.cfm P4DC6]
| Intel® 82860
| Intel® 82801, 82806
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| P4DC6P
| Intel® 82860
| Intel® 82801, 82806
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Tyan
| TigerMPX
| AMD-76x™
| AMD-768™
| Winbond™ W83627HF
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| guiness
| AMD-76x™
| AMD-766™
| Winbond™ W83627HF
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tiger133.html Tiger 133 (S1834)]
| VIA VT8601
| ?
| Winbond™ W83977EF
| Intel® Pentium® II/III
| Slot 1
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami ATX (S1846)]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87309
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| style="background:lime" | Yes
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigermpx.html Tiger MPX (S2466)]
| AMD-762™
| AMD-768™
| Winbond™ W83627HF
| AMD Athlon® MP
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk7xpro.html Thunder K7X Pro (S2469)]
| AMD-762™
| AMD-768™
| Winbond™ W83627HF
| AMD Athlon® MP
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="9" | '''Servers'''

|- bgcolor="#eeeeee"
| ASUS
| [http://www.asus.de/products.aspx?l1=9&l2=39&l3=103&model=113&modelmenu=1 PU-DLS]
| Intel® E7501
| Intel® 82801CA (ICH3-S)
| Winbond™ W83627HF
| Intel® Xeon®
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Compaq
| DS10
| Alpha Tsunami
| Acer M1543
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Intel
| clearwater
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Intel
| clearwater533
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| RLX
| [http://web.archive.org/web/20040413125915/rlxtechnologies.com/index.php?se=servers&id=3 ServerBlade 800i]
| Micron 21PAD
| Acer M1535
| Acer M1535
| ?
| ?
| style="background:lime" | OK2
| style="background:red" | No

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE.cfm P4DPE]
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE-G2.cfm P4DPE-G2]
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| P4DPR
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7505/X5DAE.cfm X5DAE]
| Intel® E7505
| Intel® 82801CA (ICH3-S), 82801DB (ICH4), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DPE-G2.cfm X5DPE-G2]
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| X5DPR
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigeri7501.html Tiger i7501 (S2723)]
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="9" | '''Laptops'''

|- bgcolor="#eeeeee"
| IBM
| [http://www.thinkwiki.org/wiki/Category:T23 ThinkPad T23]
| Intel® 82830
| Intel® 82801
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Embedded / SBC / PC/104'''

|- bgcolor="#eeeeee"
| Advantech
| pcm-5823
| NSC GX1
| NSC CS5530
| SMC FDC37B72X
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Advantech
| pcm-9574
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Cocom
| voyager2
| NSC GX1
| NSC CS5530
| NSC PC97317
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| DigitalLogic
| smartcore-p3
|
|
|
|
|
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| DigitalLogic
| smartcore-p5
|
|
|
|
|
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Lanner
| [http://www.embedded-computing.com/products/search/fm/id/?10784 EM-370]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium®III / Celeron®
| Slot 370
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Lippert
| [http://web.archive.org/web/20031204180239/www.lippert-at.com/pc104plus.html Cool RoadRunner II]
| NSC GX1
| NSC CS5530
| SMC FDC37B72X
| NSC Geode GX1
| —
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Nano
| nano
| NSC GX1
| NSC SCX200
| ?
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| STMicroelectronics
| [http://mcu.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=75 STPC® Consumer-II]
| integrated
| integrated
| SMC FDC37B78X
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| STMicroelectronics
| [http://mcu.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=75 STPC® Elite]
| integrated
| integrated
| SMC FDC37B78X
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Supertek
| ST3-WT
| NSC GX1
| NSC CS5535
| NSC PC97317
| Geode
| ?
| style="background:lime" | OK ([[User:Stepan|SR]])
| style="background:red" | No

|- bgcolor="#eeeeee"
| Technoland
| [http://web.archive.org/web/20040406003346/technoland.com/tl_embsbc710.htm TL-EmbSBC 710]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83877EF
| Intel® Pentium® III / Celeron®
| Slot 1
| style="background:lime" | [[Technoland SBC 710|???]]
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="9" | '''Mini-ITX'''

|- bgcolor="#eeeeee"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]
| VIA VT8601
| VIA VT8231
| Winbond™ W83627HF
| VIA C3™ / EDEN™
| ?
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™ / EDEN™
| ?
| style="background:#eeeeee" | ?
| style="background:lime" | Yes

|- bgcolor="#6699ff"
| colspan="9" | '''Set-top-boxes / Thin clients'''

|- bgcolor="#eeeeee"
| Lex
| [http://www.lex.com.tw:8080/product/CV860A.htm CV860A]
| VIA VT8601A
| VIA VT82C686B
| VIA VT82C686B
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| RCN
| Dc1100s
| VIA VT694
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Devel/Eval Boards'''

|- bgcolor="#eeeeee"
| Motorola
| Sandpoint
| Motorola MPC107
| Winbond™ W83C553
| NSC PC97307
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:lime" | Yes

|- bgcolor="#6699ff"
| colspan="9" | '''Miscellaneous'''

|- bgcolor="#eeeeee"
| BCM
| e100
| SiS550
| SiS550
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Dell
| 350
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMC FDC37B907
| ?
| Slot 1
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| irobot
| Proto1
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMS FDC37N769
| ?
| Slot 1
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| SiS
| 540 (?)
| SiS540
| SiS540
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 550 (?)
| SiS550
| SiS550
| ?
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 635 (?)
| ?
| SiS635
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 735 (?)
| SiS735
| SiS735
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| VIA
| vt5292
| VIA VT8601
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| VIA
| vt5426
| VIA VT8601
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|}


1 Work in progress. 
2 http://www.linuxbios.org/pipermail/linuxbios/2002-October/000743.html 
3 http://www.linuxbios.org/pipermail/linuxbios/2003-September/005385.html 


__FORCETOC__

Supported Motherboards

2010-12-20T23:59:40Z

Uwe: /* Motherboards supported in coreboot v4 */ iWave iW-RainboW-G6.

{| border="0" valign="top" width="100%"
| valign="top"|
See the page [[Confirmed working svn revisions]] for a table of which revision to start testing with on your particular mainboard. Click on the Status column bellow to learn more info about the board.

'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards. For AMD Geode LX targets, '''coreboot v3''' might be better than coreboot v4 in some minor aspects, but most features should be ported to v4 by now.
* If a mainboard is not supported by coreboot v4, try [[Supported_Motherboards#Motherboards_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Motherboards#Motherboards_supported_in_coreboot_v3|coreboot v3]] for support.
* However, in general it is '''not''' recommended to use coreboot v3 — this was an experimental development tree which is gradually being merged into v4.
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.

See also [[Supported Chipsets and Devices|Supported Chipsets & Devices]].

| valign="top" align="right"|

'''Color Legend'''
{| border="1" style="font-size: smaller"
|- bgcolor="#eeeeee"
| style="background:red" | Motherboard is work in progress, unfinished, or on hold.
|-
| style="background:yellow" | Motherboard mostly works, but some issues remain.
|-
| style="background:lime" | Motherboard is fully supported.
|}

|}

== Motherboards supported in coreboot v4 ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | ROM 35
! align="left" | P 36
! align="left" | S 37
! align="left" | F 38
! align="left" | VCS4

|- bgcolor="#6699ff"
| colspan="13" | '''Desktops / Workstations'''

|- bgcolor="#dddddd"
| Abit
| [http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAME=BE6-II+V2.0&fMTYPE=Slot+1 Abit BE6-II V2.0]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| —
| —

|- bgcolor="#eeeeee"
| ASRock
| [http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939 939A785GMH/128M]
| AMD K8
| AMD® RS785/SB710
| Winbond™ W83627DHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:yellow" | [[ASRock 939A785GMH-128M|WIP...]]
| DIP8
| SPI
| ?
| ?
| —

|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=171&l4=0&model=455&modelmenu=2 A8N-E]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8N-E|OK...]]25
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK A8N-SLI]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS_A8N-SLI|OK...]]25
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?modelmenu=1&model=596&l1=3&l2=15&l3=207 A8N5X]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8N5X|OK...]]25
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&modelmenu=1 A8V-E SE]
| AMD K8
| VIA K8T890 / VT8237R
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8V-E SE|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&modelmenu=1 A8V-E Deluxe]
| AMD K8
| VIA K8T890 / VT8237R
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8V-E Deluxe|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&modelmenu=1 M2A-VM]
| AMD 690G
| ATI SB600
| ITE™ IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2(+)
| style="background:lime" | [[ASUS M2A-VM|OK...]]
| PLCC
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 M2N-E]
| AMD K8
| NVIDIA MCP55
| ITE™ IT8716F
| AMD Athlon™ 64 / FX / X2 / Phenom
| Socket AM2
| style="background:lime" | [[ASUS M2N-E|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=OqYlEDFfF6ZqZGvp M2V]
| AMD K8
| VIA K8T890CF / VT8237A
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[ASUS M2V|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=324&l4=0&model=1807&modelmenu=1 M2V-MX SE]
| AMD K8
| VIA K8M890 / VT8237S
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[ASUS M2V-MX SE|OK...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=ef0qgvMIwOUagAVl M4A785-M]
| AMD Fam10h
| AMD RS780/SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3/AM2(+)
| style="background:yellow" | [[ASUS M4A785-M|WIP...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=0KyowHKUFAQqH2DO M4A78-EM]
| AMD Fam10h
| AMD RS780/SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3/AM2(+)
| style="background:lime" | [[ASUS M4A78-EM|OK...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ MEW-AM]
| Intel® 82810
| Intel® 82801AA (ICH)
| SMSC® LPC47B272
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[ASUS MEW-AM|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| ASUS
| [http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm MEW-VM]
| Intel® 82810
| Intel® 82801AA (ICH)
| SMSC® LPC47B272
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:yellow" | WIP28
| PLCC
| ?
| style="background:lime" | Y
| style="background:red" | N
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ P2B]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P2B|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ P2B-F]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P2B-F|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ P2B-D]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| 2x Slot 1
| style="background:lime" | [[ASUS P2B-D|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ P2B-DS]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| 2x Slot 1
| style="background:lime" | [[ASUS P2B-DS|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ P2B-LS]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P2B-LS|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | ...43
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ P3B-F]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[ASUS P3B-F|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| A-Trend
| [http://www.motherboard.cz/mb/atrend/atc6220.htm ATC-6220]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[A-Trend ATC-6220|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| A-Trend
| [http://active-hardware.com/english/reviews/mainboard/atc6240.htm ATC-6240]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83627HF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| ?
| —

|- bgcolor="#dddddd"
| AZZA
| [http://web.tiscali.it/acorp/?http://web.archive.org/web/20050426181911/http://web.tiscali.it/acorp/mobo_spec/azza/pt-6ibd/pt-6ibd.htm PT-6IBD]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[AZZA PT-6IBD|OK...]]
| DIP32
| Parallel
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Biostar
| [http://www.motherboard.cz/mb/biostar/M6TBA.htm M6TBA]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMSC FDC37M60x
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[Biostar M6TBA|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| Compaq
| Deskpro EN SFF P600
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC97307
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| ?
| —


|- bgcolor="#eeeeee"
| ECS
| [http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&DetailID=95&DetailName=Feature&MenuID=24&LanID=4 P6IWP-Fe]
| Intel® 82810
| Intel® 82801AA (ICH)
| ITE IT8712F
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[ECS P6IWP-Fe|OK]]
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[GIGABYTE GA-6BXC|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| —| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1430 GA-6BXE]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[GIGABYTE GA-6BXE|OK...]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/ GA-2761GXDK] (Churchill)
| AMD K8
| SiS761GX/SiS966
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2 (?)
| Socket AM2
| style="background:lime" | [[GIGABYTE GA-2761GXDK|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&ModelName=GA-M57SLI-S4 GA-M57SLI-S4]
| AMD K8
| NVIDIA MCP55
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[GIGABYTE GA-M57SLI-S4|OK...]]
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| style="background:yellow; text-align:center" | [[Gigabyte m57sli Vendor Cooperation Score|3]]
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com/products/product-page.aspx?pid=3274 GA-MA785GMT-UD2H]
| AMD Fam10h
| AMD 785G / SB710
| ITE IT8718F
| AMD Phenom™ II / Athlon™ II
| Socket AM3
| style="background:lime" | [[GIGABYTE GA-MA785GMT-UD2H|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com/products/product-page.aspx?pid=2995 GA-MA78GM-US2H]
| AMD Fam10h
| AMD 780G / SB700
| ITE IT8718F
| AMD Phenom™ / Athlon™ / Sempron™
| Socket AM2+
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| HP
| e-Vectra P2706T
| Intel 82810E
| Intel 82801AA (ICH)
| NSC PC87364
| Intel® Pentium® III / Celeron®
| PGA370
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Intel
| [http://support.gateway.com/s/MOTHERBD/INTEL/2514906/2514906nv.shtml D810E2CB]
| Intel® 82810E
| Intel® 82801BA (ICH2)
| SMSC LPC47M102
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[Intel D810E2CB|OK...]]
| PLCC
| FWH
| N
| ?
| —
|- bgcolor="#dddddd"
| Intel
| [http://www.intel.com/Products/Desktop/Motherboards/D945GCLF/D945GCLF-overview.htm D945GCLF]
| Intel® 945GC
| Intel® ICH7
| SMSC LPC47M15x
| Intel® Atom™
| Socket 441
| style="background:red" | WIP44
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Mitac
| [http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/products/tyan/6513wu/6513wu.htm 6513WU]
| Intel® 82810E
| Intel® 82801AB (ICH0)
| SMSC LPC47U332
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[Mitac 6513WU|OK...]]
| PLCC
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=332&maincat_no=1 MS-6119]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&maincat_no=1&prod_no=335 MS-6147]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| style="background:lime" | Y
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/Boards/Motherboards/MicroStar/Ms6156/MS6156.htm MS-6156]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| MSI
| [http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no=1 MS-6178]
| Intel® 82810
| Intel® 82801AB (ICH0)
| Winbond™ W83627HF
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[MSI MS-6178|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=170&maincat_no=1 MS-7135 (K8N Neo3)]
| AMD K8
| NVIDIA CK8046
| Winbond® W83627THF
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
| Socket 754
| style="background:lime" | [[MSI MS-7135|OK...]]
| PLCC
| LPC
| style="background:yellow" | ...29
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=255&maincat_no=1&cat2_no=171 MS-7260 (K9N Neo)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Sempron™ / Athlon™ 64 / X2
| Socket AM2
| style="background:lime" | [[MSI MS-7260|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:yellow" | ...39
| —

|- bgcolor="#eeeeee"
| NEC
| [http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ PowerMate 2000]
| Intel® 82810
| Intel® 82801AB (ICH0)
| SMSC® LPC47B27x
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[NEC PowerMate 2000|OK...]]
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| Shuttle
| [http://global.shuttle.com/product_detail.jsp?PI=89 SN25P]
| AMD K8
| NVIDIA CK8046
| ITE IT8712F
| AMD Sempron™ / Athlon™ 64 / X2 / Opteron™ 1XX
| Socket 939
| style="background:red" | [[Shuttle SN25P|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Soyo
| Soyo SY-6BA+ III
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | [[Soyo SY-6BA Plus III|OK]]
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| Sun
| [http://www.sun.com/desktop/workstation/ultra40/index.xml Ultra 40]
| AMD K8
| NVIDIA CK8045
| SMSC® LPC47B397
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami ATX (S1846)]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87309
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/tigerk8w.html Tiger K8W (S2875)]
| AMD K8
| AMD-8111™, 8151™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8w.html Thunder K8W (S2885)]
| AMD K8
| AMD-8111™, 8131™, 8151™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8we.html Thunder K8WE (S2895)]
| AMD K8
| AMD-8131™, NVIDIA CK8045
| SMSC® LPC47B397
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Servers'''

|- bgcolor="#eeeeee"
| agámi
| [http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-6000-series Aruma/AIS6000 series]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD K8
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD Fam10h
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Arima
| [http://web.archive.org/web/20080127024444/http://www.arima.com.tw/server/Product/ViewProduct.asp?View=HDAMA HDAMA]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87360
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Dell
| [http://support.dell.com/support/edocs/systems/pe1850/en/index.htm PowerEdge 1850]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:yellow" | WIP2
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| HP
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 ProLiant DL145 G3]
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| AMD Opteron™
| Socket F
| style="background:lime" | [[HP DL145 G3|OK]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IBM
| [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-53255 eServer 325]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87366
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IBM
| [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-58655 eServer 326]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87366
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Intel
| [http://www.intel.com/support/motherboards/server/se7520jr2/ Jarrell (SE7520JR2)]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| NSC PC87427
| Intel® Xeon®
| ?
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 DK8-HTX]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[IWILL DK8-HTX|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060509143427/http://www.iwill.net/product_2.asp?p_id=42&sp=Y DK8S2]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060213163325/http://www.iwill.net/product_2.asp?p_id=28 DK8X]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| MSI
| [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx K9SD Master-S2R (MS-9185)]
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| AMD Opteron™
| Socket F
| style="background:lime" | OK12
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 K9SD Master (MS-9282)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK15
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Newisys
| [http://web.archive.org/web/20070922231423/http://www.newisys.com/core/2100e.html 2100 Server] (SUN Fire v20z)
| AMD K8
| AMD-8111™, 8131™
| NSC PC87360
| AMD Opteron™
| Socket F
| style="background:lime" | OK7
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Nokia
| [http://press.nokia.com/PR/200103/813151_5.html IP530]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ FDC37C878
| Intel® Pentium® II/III, Celeron®
| Socket 370
| style="background:lime" | [[Nokia IP530|OK...]]
| DIP32
| Parallel
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]
| AMD Fam10h
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm H8DME-2]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK41
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DAi-G]
| Intel® E7525
| Intel® E7525, ESB6300
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DHE-G]
| Intel® E7520
| Intel® E7520, ESB6300
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHE-G2.cfm X6DHE-G2]
| Intel® E7520
| Intel® 82801ER (ICH5R), ESB6300
| NSC PC87427
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG.cfm X6DHR-iG]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG2.cfm X6DHR-iG2]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigeri7501r.html Tiger i7501R (S2735)]
| Intel® E7501
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tomcatk8s.html Tomcat K8S (S2850)]
| AMD K8
| AMD-8111™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8s.html Thunder K8S (S2880)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8sr.html Thunder K8SR (S2881)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2881|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8spro.html Thunder K8S Pro (S2882)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2882|OK...]]20
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8sre.html Thunder K8SRE (S2891)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2891|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8se.html Thunder K8SE (S2892)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2892|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder n3600R (S2912)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | [[Tyan S2912|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder n3600R (S2912)]
| AMD Fam10h
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | [[Tyan S2912|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8qs.html Thunder K8QS (S4880)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8qspro.html Thunder K8QS Pro (S4882)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Laptops'''

|- bgcolor="#dddddd"
| Getac
| [http://en.getac.com/products/P470/P470_overview.html P470]
| Intel® 945
| Intel® ICH7
| SMSC® FDC37N972 + SIO10N268
| Intel® Core 2 Duo T7200
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Roda
| [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html RK886EX (Rocky III+)]
| Intel® 945
| Intel® ICH7
| SMSC® LPC47N227
| Intel® Core 2 Duo Mobile T5500
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Embedded / SBC / PC/104 / Half-size boards'''

|- bgcolor="#eeeeee"
| Advantech
| [http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8 PCM-5820]
| AMD GX1
| AMD CS5530A
| Winbond® W83977AF
| AMD Geode™ GX1
| —
| style="background:lime" | [[Advantech PCM-5820|OK...]]
| PLCC32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| AMD
| Rumba
| AMD GX9
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™GX9
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.com/english/products/datasheets/ecm855.asp smartModule855]
| Intel® 855PM
| Intel® 82801DBM (ICH4-M)
| Winbond™ W83627HF
| ?
| ?
| style="background:red" | WIP13
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG MSM586SEG]
| integrated
| integrated
| integrated
| AMD Élan™SC520
| —
| style="background:yellow" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV MSM800SEV]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK22
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| EagleLion
| 5BCM
| AMD GX1
| AMD  CS5530
| NSC PC97317
| ?
| —
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| IEI
| [http://www.icpamerica.com/products/single_board_computers/5_25_NOVA/NOVA-4899.html NOVA-4899R]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977TF
| AMD Geode™ GX1
| —
| style="background:yellow" | WIP17
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/news_content.asp?id=erbium/projectOBJ00150613 JUKI-511P]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977F
| AMD Geode™ GX1
| —
| style="background:lime" | [[IEI JUKI 511P|OK...]]27
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX IEI PCISA-LX-800-R10]
| AMD LX
| AMD Geode™ CS5536
| Winbond™ W83627EHG
| AMD Geode™ LX
| —
| style="background:lime" | [[IEI LX 800|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/product_IPC.asp?model=ROCKY-512 ROCKY-512]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977F
| AMD Geode™ GX1
| —
| style="background:lime" | [[IEI ROCKY 512|OK...]]27
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| iWave
| [http://www.iwavesystems.com/iW-RainbowG6.htm iW-RainboW-G6]
| Intel Poulsbo US15W
| Intel Poulsbo US15W
| —
| Intel Atom Z530/Z510
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/productoverview/products-in-detail/85-lipperts-cool-frontrunner.html Cool FrontRunner]
| AMD GX9
| AMD CS5535
| Winbond™ W83627HF
| AMD Geode™ GX
| —
| style="background:red" | WIP2
| PLCC
| FWH
| style="background:lime" | Y
| ?
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-hurricane-lx800.html Hurricane-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-cool-literunner-lx800.html Cool LiteRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-cool-roadrunner-lx800.html Cool RoadRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.de/en/lipperts-cool-spacerunner-lx800.html Cool SpaceRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| PC Engines
| [http://pcengines.ch/alix1c.htm ALIX.1C]
| AMD Geode™ LX
| AMD Geode™ CS5536
| Winbond® W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.1C|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| style="background:lime; text-align:center" | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]

|- bgcolor="#eeeeee"
| TechNexion
| [http://www.technexion.com/index.php/embedded-mainboards/amd/tim-5690 TIM-5690]
| AMD M690E
| ATI SB600
| ITE IT8712F
| AMD Sempron
| Socket AM2(+)
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| TechNexion
| [http://www.technexion.com/index.php/tim-8690 TIM-8690]
| AMD M690E
| ATI SB600
| ITE IT8712F
| AMD Sempron™ / Athlon™ 64 / X2
| Socket AM2
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Traverse Technologies
| [http://www.traverse.com.au/productview.php?product_id=117 Geos]
| AMD LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK
| PLCC
| ?
| style="background:lime" | Y
| ?
| —

|- bgcolor="#eeeeee"
| TS31
| [http://www.embeddedarm.com/epc/ts5300-spec-h.html TS-5300]
| integrated
| integrated
| integrated
| AMD Élan™SC520
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Mini-ITX / Micro-ITX / Nano-ITX'''

|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F2|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E J7F4K1G2E]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F4K1G2E|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4K1G5D J7F4K1G5D]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F4K1G5D|OK...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Kontron
| [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]
| Intel® 945
| Intel® ICH7
| 2x Winbond® W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| mPGA478
| style="background:lime" | [[Kontron 986LCD-M mITX|OK...]]
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Kontron
| [http://us.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx.html KT690/mITX]
| AMD M690T
| ATI SB600
| Winbond™ W83627DHG
| AMD Turion64™ dual core / AMD Sempron
| Socket AM2(+)
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=1054&maincat_no=388# Fuzzy CN700]
| VIA CN700
| VIA VT8237R(P)
| Winbond™ W83627EHG
| VIA C7™
| NanoBGA2
| style="background:yellow" | [[MSI FUZZY CN700|WIP...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]
| VIA VT8601
| VIA VT8231
| Winbond™ W83627HF
| VIA C3™, VIA EDEN™
| —
| style="background:yellow" | [[EPIA|WIP...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-M|OK...]]10
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| EPIA-M700
| VIA VX800
| VIA VX800
| Winbond W83697HF/F/HG
| ?
| ?
| style="background:red" | [[VIA EPIA-M700|WIP...]]
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=202 EPIA-MII]
| VIA VT8623
| VIA VT8235, Ricoh RL5C476
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-MII|OK...]]8
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=301 EPIA-ML]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-ML|OK...]]10
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN10000EG]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-CN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN13000G]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-CN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN12000EG]
| VIA CN700
| VIA VT8237R
| Winbond™ W83627EHG
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA EPIA-EN|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN15000G]
| VIA CN700
| VIA VT8237R
| Winbond™ W83627EHG
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA EPIA-EN|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=473 EPIA-LN10000EG/EAG]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-LN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7400]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA NAB7400|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7410]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA NAB7410|WIP...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.idot.com.tw/en/products/mb-pc2500e/ pc2500e]
| VIA CN700
| VIA VT8237R
| ITE IT8716F
| VIA C7™, VIA Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA pc2500e|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.idotpc.com/TheStore/pc/viewCategories.asp?idCategory=56 EPIA-N]
| VIA CN400
| VIA VT8237R
| Winbond W83697HF
| ?
| ?
| style="background:yellow" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Set-top-boxes / Thin clients'''

|- bgcolor="#eeeeee"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE61]
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:red" | Broken40
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| ASI
| MB-5BLGP32
| AMD GX1
| AMD CS5530
| NSC PC87351
| AMD Geode™ GX1
| —
| style="background:lime" | [[ASI MB-5BLGP|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| ASI
| [http://www.hojerteknik.com/winnet.htm MB-5BMLP]33
| AMD GX1
| AMD CS5530
| NSC PC87351
| AMD Geode™ GX1
| —
| style="background:lime" | [[ASI MB-5BLMP|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| AXUS
| [http://www.keyton.co.jp/products/UAXT/TC-320.html TC320]
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[AXUS TC320|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| BCOM
| [http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_compact.htm WinNET100]34
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[BCOM WINNET100|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| BCOM
| WinNET P680
| VIA CN700
| VIA VT8237R Plus
| Winbond™ W83697HG
| Via C7™
| —
| style = "background:yellow" | [[BCOM WinNET P680|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Linutop
| [http://linutop.com/ Linutop]
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK19
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| RCA
| [http://www.settoplinux.org/index.php?title=RCA_RM4100 RM4100]
| Intel® 82830M
| Intel® 82801DB (ICH4)
| SMSC® LPC47M192
| Intel® Mobile Celeron
| Socket 479
| style="background:lime" | [[RCA RM4100|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| TeleVideo
| [http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm TC7020]
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[TeleVideo TC7020|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Thomson
| [http://www.settoplinux.org/index.php?title=Thomson_IP1000 IP1000]
| Intel® 82830M
| Intel® 82801DB (ICH4)
| SMSC® LPC47M192
| Low Voltage Intel® Pentium® III
| Socket 479
| style="background:lime" | [[Thomson IP1000|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| Wyse
| [http://www.wyse.de/products/hardware/thinclients/S50/index.asp S50]
| AMD GX2
| AMD CS5536
| —
| AMD Geode™ GX2
| —
| style="background:lime" | OK
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Devel/Eval Boards'''

|- bgcolor="#eeeeee"
| AMD
| [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800] (Salsa)
| AMD LX
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Norwich
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK21
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T] (Herring)
| AMD K8
| AMD RS690/SB600
| ITE IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| style="background:lime" | [[AMD DBM690T|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| AMD
| Mahogany
| AMD K8
| AMD RS780E/SB700
| ITE IT8718F
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| style="background:lime" | OK
| ?
| SPI
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Mahogany
| AMD Fam10h
| AMD RS780E/SB700
| ITE IT8718F
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| style="background:lime" | OK
| ?
| SPI
| ?
| ?
| —

|- bgcolor="#eeeeee"
| AMD
| Pistachio
| AMD K8
| AMD RS690/SB600
| —
| ?
| Socket AM2
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Tilapia
| AMD Fam10h
| AMD RS780/SB700
| ITE IT8718F
| ?
| Socket AM3
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Broadcom
| Blast
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| ?
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Intel
| 3100 devkit (Mt. Arvon)
| Intel® 3100
| Intel® 3100
| Intel® 3100
| Intel® Pentium® M
| Socket 479
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| EagleHeights
| Intel® 3100
| Intel® 3100
| Intel® 3100
| Intel® Pentium® M
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| EP80579 devkit (Truxton)
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| XE7501devkit
| Intel® E7501
| Intel® 82801CA (ICH3-S)
| SMSC® LPC47B272
| ?
| ?
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| NVIDIA
| l1_2pvv
| AMD K8
| NVIDIA MCP55+IO55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK14
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| VIA
| VT8454c
| VIA CX700
| integrated
| integrated
| VIA C7™
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Miscellaneous'''

|- bgcolor="#eeeeee"
| Emulation
| [http://fabrice.bellard.free.fr/qemu/ QEMU x86]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| —
| Intel® Pentium® II/III (?)
| —
| style="background:lime" | [[QEMU Build Tutorial|OK...]]
| ?
| ?
| ?
| ?
| —

|}


1 NVIDIA nForce™ Professional 2200 (CK804). 
2 Work in progress. 
3 This was an AMD64 reference board. 
4 Vendor Cooperation Score. 
5 NVIDIA nForce™ Professional 2200 and 2050 (2 × CK804). 
6 NVIDIA nForce™ 4, nForce 4 SLI, or nForce 4 4x. 
7 LSI1030 SCSI controller can not be used to boot the machine. 
8 Use the ''epia-m'' code for now. The on-board PCMCIA and CF sockets work. coreboot can boot from CF (the stock BIOS can't). [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016448.html Some problems] remain, though. 
9 The AMD GX (internally known as GX2 for some time) is actually the successor to the GX1. 
10 Use the ''epia-m'' code for now (plus [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016423.html a few hacks], e.g. disable Firewire/CF slot,
because they're not present on the board). 
12 Except for some [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016463.html possible problems with SATA2 ports], everything should work. 
13 See also http://www.linuxbios.org/pipermail/linuxbios/2006-November/017065.html. 
14 These boards ''should'' work fine, but we have no confirmed reports on the [[Mailinglist|mailing list]] so far, so we cannot tell for sure. 
15 See http://www.openbios.org/pipermail/linuxbios/2007-February/018299.html. 
17 Seems to be [http://www.linuxbios.org/pipermail/linuxbios/2006-November/016651.html partially working], specifically eth0, eth2, the PCI slot, the USB ports, and the serial console [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021226.html are working]. Other parts are not yet finished. 
19 The Linutop does not ship with coreboot, but [http://linutop.com/wiki/index.php/Developers#Upgrading_to_LinuxBIOS the code should work]. 
20 Fan-control doesn't work yet. 
21 This is ''the'' AMD Geode LX reference board and coreboot reference implementation on the AMD Geode LX, contributed and maintained by AMD engineers. 
22 The board can boot a Linux kernel currently, but there's [http://www.linuxbios.org/pipermail/linuxbios/2007-May/020770.html no VGA support, yet]. 
25 [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021280.html Works fine], only smaller issues remain to be fixed. A [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021308.html list of known issues] is available. 
27 The JUKI-511P and ROCKY-512 both use the same code and target (targets/iei/juki-511p). Thus, both [http://www.linuxbios.org/pipermail/linuxbios/2007-June/021862.html support the same features and have the same limitations]: IDE, USB, ethernet, serial, keyboard and sound work, but there are problems booting from IDE1 ([http://www.linuxbios.org/pipermail/linuxbios/2007-June/021996.html this patch] may help), and VGA video doesn't work, yet. 
28 Partially supported, almost boots a Linux kernel. [http://www.linuxbios.org/pipermail/linuxbios/2007-June/022217.html Some issues] still remain to be fixed, though. 
29 Some boards have ROM sockets, others are soldered. 
30 The irq table in CN is from VIA. You may need to run getpir to generate your own irq table. 
31 Technologic Systems. 
32 Used in the Neoware Eon 4000s thin client. 
33 Used in the IGEL WinNET III thin client. 
34 Used in the IGEL-316 thin client. 
35 ROM chip package (PLCC, DIP32, DIP8, SOIC8). 
36 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 
37 ROM chip socketed (Y/N)? 
38 Board supported by [[Flashrom]] (Y/N)? 
39 Interestingly [[flashrom]] does not work when the vendor BIOS is booted, but it does work flawlessly when the machine is booted with coreboot. 
40 Broken v4 port, try the v3 port instead. The v4 version will be fixed at some point. 
41 RAM must be matched exactly in each bank. 
43 Works. Until flashrom officially supports this board, force it with ASUS P2B-F as the mainboard target. 
44 Boots MS-DOS fine using SeaBIOS, might boot Linux. 


== Motherboards supported in coreboot v3 ==

<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 have been integrated in what now became v4.</div>

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | ROM 1
! align="left" | P 2
! align="left" | S 3
! align="left" | F 4
! align="left" | VCS5
! align="left" | v3 only 7

|- bgcolor="#eeeeee"
| Advanced Digital Logic
| [http://www.adlogic-pc104.com/products/cpu/datasheets/MSM800SEV_SEL.pdf MSM800SEV]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N

|- bgcolor="#dddddd"
| AMD
| DB800
| AMD Geode™ LX
| AMD CS5536
| ?
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| AMD
| [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T] (Herring)
| AMD K8
| AMD RS690/SB600
| ITE IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| AMD
| Norwich
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD K8
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N

|- bgcolor="#eeeeee"
| AMP
| TinyGX
| AMD Geode™ LX
| AMD CS5536
| ITE IT8716F
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y

|- bgcolor="#dddddd"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE61]
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| TSOP32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —
| style="background:lime" | N
|- bgcolor="#dddddd"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE62]
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[Artec Group DBE62|OK...]]
| TSOP32
| FWH
| style="background:red" | N
| style="background:lime" | Y
| style="background:lime; text-align:center" | [[Artec Group DBE62 Vendor Cooperation Score|4]]
| style="background:red" | Y

|- bgcolor="#eeeeee"
| Emulation
| [http://fabrice.bellard.free.fr/qemu/ QEMU x86]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| —
| Intel® Pentium® II/III (?)
| —
| style="background:lime" | OK
| —
| ?
| —
| —
| —
| style="background:lime" | N

|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&ModelName=GA-M57SLI-S4 GA-M57SLI-S4]
| AMD K8
| NVIDIA MCP55
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2
| style="background:orange" | WIP
| ...6
| ?
| style="background:red" | N
| style="background:lime" | Y
| style="background:yellow; text-align:center" | [[Gigabyte m57sli Vendor Cooperation Score|3]]
| style="background:lime" | N

|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y

|- bgcolor="#dddddd"
| Kontron
| [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]
| Intel® 945
| Intel® ICH7
| 2x Winbond® W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| mPGA478
| style="background:orange" | WIP
| PLCC
| ?
| ?
| ?
| —
| style="background:lime" | N

|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix1c.htm ALIX.1C]
| AMD Geode™ LX
| AMD Geode™ CS5536
| Winbond® W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.1C|OK...]]
| ?
| ?
| ?
| ?
| style="background:lime; text-align:center" | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]
| style="background:lime" | N
|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix2c3.htm ALIX.2C3]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.2CX|OK...]]
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y
|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix2c2.htm ALIX.2C2]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.2CX|OK...]]
| ?
| ?
| ?
| ?
| —
| style="background:red" | Y

|- bgcolor="#dddddd"
| VIA
| EPIA-CN
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
| style="background:lime" | N

|}


1 ROM chip package (PLCC, DIP32, DIP8, SOIC8). 
2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 
3 ROM chip socketed (Y/N)? 
4 Board supported by [[Flashrom]] (Y/N)? 
5 Vendor Cooperation Score. 
6 There are two versions of the [[GIGABYTE GA-M57SLI-S4]], one with a soldered PLCC chip, one with a soldered SOIC8 chip. 
7 Board is only available in v3, not yet in v4? 



== Motherboards supported in coreboot v1 ==

Not all motherboards have been ported from coreboot v1 to coreboot v4, yet (check the CBv4 field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | CBv4?

|- bgcolor="#6699ff"
| colspan="9" | '''Desktops / Workstations'''

|- bgcolor="#eeeeee"
| ASUS
| A7M
| AMD AMD76x
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| ASUS
| [http://www.ciao.co.uk/ASUS_ALi_Chipset_CUA__5410161 CUA]
| Acer M1631 (ALADDiN TNT2)
| Acer M1535
| Acer M1535
| Intel® Pentium® III
| Socket 370
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| ASUS
| [http://www.dealtime.com/xPF-ASUS-ASUS-Intel-Socket7-PNP586-Motherboard TX97-LE]
| Intel® 430TX
| Intel® 82371EB (PIIX4E)
| SMC FDC37C67X
| Intel® Pentium®, Pentium® MMX, AMD K5
| Socket 7
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Bitworks
| IMS
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87351
| ?
| Slot1 1
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Chaintech
| [http://www.xbitlabs.com/articles/mainboards/display/chaintech-7kjd.html CT-7KJD]
| AMD-761™
| VIA VT8231
| VIA VT8231
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Elitegroup (ECS)
| [http://www.ecsusa.com/products/k7sem_v3.html K7SEM]
| SiS730S
| SiS730S
| SiS730S
| AMD Athlon™ / Athlon™ XP / Duron™
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Elitegroup (ECS)
| [http://www.ecsusa.com/downloads/manual_p6s.html P6STP-FL]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot1 1
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee"
| GIGABYTE
| GA-6OXE
| Intel® 815EP
| Intel® 82801
| ITE IT8712F
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Leadtek
| [http://web.archive.org/web/20000616073856/http://www.leadtek.com.tw/e6300MAX.htm WinFast 6300MAX]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Matsonic
| [http://web.archive.org/web/20000619011053/www.matsonic.com/index_2.htm MS7308E]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:lime" | OK3
| style="background:red" | No

|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m754lmr.asp M754LMR]
| Acer M1631
| Acer M1535
| Acer M1535
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m758mr.asp M758LMR(+)]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m787cl%2B.asp M787CL+]
| SiS630
| SiS630
| SiS950
| VIA C3™
| Socket 370
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m810lmr.asp M810LMR]
| SiS670
| SiS670
| SiS950
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| M810LR
| SiS670
| SiS670
| SiS950
| AMD Athlon™ / Duron™
| Socket 462
| style="background:lime" | [[PCCHIPS M810LR|???]]
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m830lmr.asp M830L(M)R]
| SiS735
| SiS735
| SiS950
| AMD Athlon™ / Athlon™ XP / Duron™
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/860/P4DC6.cfm P4DC6]
| Intel® 82860
| Intel® 82801, 82806
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| P4DC6P
| Intel® 82860
| Intel® 82801, 82806
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Tyan
| TigerMPX
| AMD-76x™
| AMD-768™
| Winbond™ W83627HF
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| guiness
| AMD-76x™
| AMD-766™
| Winbond™ W83627HF
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tiger133.html Tiger 133 (S1834)]
| VIA VT8601
| ?
| Winbond™ W83977EF
| Intel® Pentium® II/III
| Slot 1
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami ATX (S1846)]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87309
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| style="background:lime" | Yes
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigermpx.html Tiger MPX (S2466)]
| AMD-762™
| AMD-768™
| Winbond™ W83627HF
| AMD Athlon® MP
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk7xpro.html Thunder K7X Pro (S2469)]
| AMD-762™
| AMD-768™
| Winbond™ W83627HF
| AMD Athlon® MP
| Socket 462
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="9" | '''Servers'''

|- bgcolor="#eeeeee"
| ASUS
| [http://www.asus.de/products.aspx?l1=9&l2=39&l3=103&model=113&modelmenu=1 PU-DLS]
| Intel® E7501
| Intel® 82801CA (ICH3-S)
| Winbond™ W83627HF
| Intel® Xeon®
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Compaq
| DS10
| Alpha Tsunami
| Acer M1543
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Intel
| clearwater
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Intel
| clearwater533
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| RLX
| [http://web.archive.org/web/20040413125915/rlxtechnologies.com/index.php?se=servers&id=3 ServerBlade 800i]
| Micron 21PAD
| Acer M1535
| Acer M1535
| ?
| ?
| style="background:lime" | OK2
| style="background:red" | No

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE.cfm P4DPE]
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE-G2.cfm P4DPE-G2]
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| P4DPR
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7505/X5DAE.cfm X5DAE]
| Intel® E7505
| Intel® 82801CA (ICH3-S), 82801DB (ICH4), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DPE-G2.cfm X5DPE-G2]
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| X5DPR
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigeri7501.html Tiger i7501 (S2723)]
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="9" | '''Laptops'''

|- bgcolor="#eeeeee"
| IBM
| [http://www.thinkwiki.org/wiki/Category:T23 ThinkPad T23]
| Intel® 82830
| Intel® 82801
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Embedded / SBC / PC/104'''

|- bgcolor="#eeeeee"
| Advantech
| pcm-5823
| NSC GX1
| NSC CS5530
| SMC FDC37B72X
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| Advantech
| pcm-9574
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Cocom
| voyager2
| NSC GX1
| NSC CS5530
| NSC PC97317
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| DigitalLogic
| smartcore-p3
|
|
|
|
|
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| DigitalLogic
| smartcore-p5
|
|
|
|
|
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Lanner
| [http://www.embedded-computing.com/products/search/fm/id/?10784 EM-370]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium®III / Celeron®
| Slot 370
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| Lippert
| [http://web.archive.org/web/20031204180239/www.lippert-at.com/pc104plus.html Cool RoadRunner II]
| NSC GX1
| NSC CS5530
| SMC FDC37B72X
| NSC Geode GX1
| —
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Nano
| nano
| NSC GX1
| NSC SCX200
| ?
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| STMicroelectronics
| [http://mcu.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=75 STPC® Consumer-II]
| integrated
| integrated
| SMC FDC37B78X
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| STMicroelectronics
| [http://mcu.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=75 STPC® Elite]
| integrated
| integrated
| SMC FDC37B78X
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Supertek
| ST3-WT
| NSC GX1
| NSC CS5535
| NSC PC97317
| Geode
| ?
| style="background:lime" | OK ([[User:Stepan|SR]])
| style="background:red" | No

|- bgcolor="#eeeeee"
| Technoland
| [http://web.archive.org/web/20040406003346/technoland.com/tl_embsbc710.htm TL-EmbSBC 710]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83877EF
| Intel® Pentium® III / Celeron®
| Slot 1
| style="background:lime" | [[Technoland SBC 710|???]]
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="9" | '''Mini-ITX'''

|- bgcolor="#eeeeee"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]
| VIA VT8601
| VIA VT8231
| Winbond™ W83627HF
| VIA C3™ / EDEN™
| ?
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™ / EDEN™
| ?
| style="background:#eeeeee" | ?
| style="background:lime" | Yes

|- bgcolor="#6699ff"
| colspan="9" | '''Set-top-boxes / Thin clients'''

|- bgcolor="#eeeeee"
| Lex
| [http://www.lex.com.tw:8080/product/CV860A.htm CV860A]
| VIA VT8601A
| VIA VT82C686B
| VIA VT82C686B
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| RCN
| Dc1100s
| VIA VT694
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Devel/Eval Boards'''

|- bgcolor="#eeeeee"
| Motorola
| Sandpoint
| Motorola MPC107
| Winbond™ W83C553
| NSC PC97307
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:lime" | Yes

|- bgcolor="#6699ff"
| colspan="9" | '''Miscellaneous'''

|- bgcolor="#eeeeee"
| BCM
| e100
| SiS550
| SiS550
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| Dell
| 350
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMC FDC37B907
| ?
| Slot 1
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| irobot
| Proto1
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMS FDC37N769
| ?
| Slot 1
| style="background:#eeeeee" | ?
| style="background:red" | No

|- bgcolor="#dddddd"
| SiS
| 540 (?)
| SiS540
| SiS540
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 550 (?)
| SiS550
| SiS550
| ?
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 635 (?)
| ?
| SiS635
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 735 (?)
| SiS735
| SiS735
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| style="background:red" | No

|- bgcolor="#eeeeee"
| VIA
| vt5292
| VIA VT8601
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee"
| VIA
| vt5426
| VIA VT8601
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| style="background:red" | No
|}


1 Work in progress. 
2 http://www.linuxbios.org/pipermail/linuxbios/2002-October/000743.html 
3 http://www.linuxbios.org/pipermail/linuxbios/2003-September/005385.html 


__FORCETOC__

Welcome to coreboot

2010-12-20T23:54:37Z

Uwe: Intel Poulsbo/SCH/Atom & iWave iW-RainboW-G6 support

<table width="100%" valign="top"><tr valign="top"><td width="80%">

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].


With this separation of hardware initialization and later boot logic, coreboot can scale from specialized applications run directly from firmware, operating systems in flash, and custom bootloaders to implementations of firmware standards like PCBIOS and EFI without having to carry features not necessary in the target application, reducing the amount of code and flash space required.


We currently support '''[[Supported Motherboards|230]]''' different mainboards.
</div>

{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%
|-
|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = yellow|
WIDTH = 100%|
ICON = [[Benefits|More...]]|
HEADING = [[Benefits]]|
CONTENT =

* 100% Free Software (GPL), no royalties, no license fees!
* Fast boot times (3 seconds to Linux console)



* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]


}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = #d1adf6|
WIDTH = 100%|
ICON = [[Use Cases|More...]]|
HEADING = [[Use Cases]]|
CONTENT =

* Desktop PCs, servers, [[Laptop|laptops]]
* [[Clusters]]

* Embedded solutions




}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = lime|
WIDTH = 100%|
ICON = [[Payloads|More...]]|
HEADING = [[Payloads]]|
CONTENT =

* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] 
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] 
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]


}}

|}

{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_cb.png]]
|style="vertical-align:top"|
'''About''' Find out more about coreboot.<hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_devel.png]]
|style="vertical-align:top"|
'''Developers''' Get involved! Help us make coreboot better.<hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_status.png]]
|style="vertical-align:top"|
'''Status''' Find out whether your hardware is already supported.<hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_tools.png]]
|style="vertical-align:top"|
'''Related Tools''' Tools and libraries related to coreboot.<hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_101.png]]
|style="vertical-align:top"|
'''Getting Started''' Download coreboot and get started.<hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_support.png]]
|style="vertical-align:top"|
'''Support''' Learn how to contact us and find help and support.<hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]
|}

|}
</td><td width="20%">

[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]

 

'''[[News]]'''<hr />


* '''2010/12/18:''' [[News#2010.2F12.2F18_Intel_Poulsbo.2FSCH.2FAtom_and_iWave_iW-RainboW-G6_now_supported|Intel Poulsbo/SCH/Atom & iWave iW-RainboW-G6 support]]
* '''2010/12/13:''' [[News#2010.2F12.2F13_ASUS_M2N-E_now_supported|ASUS M2N-E support]]
* '''2010/12/06:''' [[News#2010.2F12.2F06_ASUS_M4A78-EM_now_supported|ASUS M4A78-EM support]]
* '''2010/11/11:''' [[News#2010.2F11.2F11_ASUS_M2V_now_supported|ASUS M2V support]]
* '''2010/09/13:''' [[News#2010.2F09.2F13_ASUS_M4A785-M_now_supported|ASUS M4A785-M support]]
* '''2010/09/10:''' [[News#2010.2F09.2F10_LiPPERT_LiteRunner-LX_and_Hurricane-LX_now_supported|LiPPERT LiteRunner-LX and Hurricane-LX support]]
* '''2010/08/17:''' [[News#2010.2F08.2F17_GIGABYTE_GA-MA785GMT-UD2H_now_supported|GIGABYTE GA-MA785GMT-UD2H support]]


'''[[Current events|Upcoming Events]]'''<hr />



* None, currently.


</td></tr></table>

__NOTOC__
__NOEDITSECTION__

News

2010-12-20T23:49:08Z

Uwe: /* 2010 */ Intel Poulsbo/SCH/Atom and iWave iW-RainboW-G6 now supported

= 2010 =

== 2010/12/18 Intel Poulsbo/SCH/Atom and iWave iW-RainboW-G6 now supported ==

coreboot now has initial support for the [http://www.iwavesystems.com/iW-RainbowG6.htm iWave iW-RainboW-G6] UMPC/MID, as well as the Intel Poulsbo/SCH/US15Wx + Atom Z5xx chipset. The code was contributed by [http://www.iwavesystems.com/ iWave] and [http://www.coresystems.de/en/ coresystems GmbH], thanks!

== 2010/12/13 ASUS M2N-E now supported ==

coreboot now supports the [[ASUS M2N-E]] board. The code was contributed by [[User:Uwe|Uwe Herman]], thanks!

== 2010/12/06 ASUS M4A78-EM now supported ==

coreboot now supports the [[ASUS M4A78-EM]] board. The code was contributed by [mailto:juhe@iki.fi Juhana Helovuo], thanks!

== 2010/11/11 ASUS M2V now supported ==

coreboot now supports the [[ASUS M2V]] board. The code was contributed by [mailto:ranma+coreboot@tdiedrich.de Tobias Diedrich], thanks!

== 2010/09/13 ASUS M4A785-M now supported ==

coreboot now supports the [[ASUS M4A785-M]] board. The code was contributed by [mailto:juhe@iki.fi Juhana Helovuo], thanks!

== 2010/09/10 LiPPERT LiteRunner-LX and Hurricane-LX now supported ==

coreboot now supports the LiPPERT [http://www.lippertembedded.de/en/lipperts-cool-literunner-lx800.html LiteRunner-LX] and [http://www.lippertembedded.de/en/lipperts-hurricane-lx800.html Hurricane-LX] boards. The code was contributed by [http://www.lippertembedded.de/ LiPPERT Embedded Computers GmbH].

== 2010/08/17 GIGABYTE GA-MA785GMT-UD2H now supported ==

coreboot now supports the [[GIGABYTE GA-MA785GMT-UD2H]] board. The code was contributed by [mailto:wangqingpei@gmail.com Wang Qing Pei], thanks!

== 2010/08/17 GIGABYTE GA-MA78GM-US2H now supported ==

coreboot now supports the [[GIGABYTE GA-MA78GM-US2H]] board. The code was contributed by [mailto:wangqingpei@gmail.com Wang Qing Pei], thanks!

== 2010/06/22 Intel D810E2CB now supported ==

coreboot now supports the [[Intel D810E2CB]] board. The code was contributed by [[User:Linux_junkie|Joseph Smith]], thanks! This is also the first Intel 82810 board to support Cache-as-RAM (CAR).

== 2010/06/09 ECS P6IWP-Fe now supported ==

coreboot now supports the [[ECS P6IWP-Fe]] board. The code was contributed by [mailto:anders@jenbo.dk Anders Jenbo], thanks!

== 2010/05/20 Traverse Technologies Geos now supported ==

coreboot now supports the [http://www.traverse.com.au/productview.php?product_id=117 Traverse Technologies Geos] ADSL2+ x86 router. The code was contributed by [mailto:nathan@traverse.com.au Nathan Williams], thanks!

== 2010/05/16 Getac P470 now supported ==

coreboot now has support for a second laptop, the [http://en.getac.com/products/P470/P470_overview.html Getac P470], based on the Intel i945 / ICH7 chipset. The code was contributed by [http://www.coresystems.de/en/ coresystems GmbH], thanks! Read the [http://www.coreboot.org/pipermail/coreboot-announce/2010-May/000007.html full announcement] for details.

== 2010/05/14 GIGABYTE GA-6BXE now supported ==

coreboot now supports the [[GIGABYTE GA-6BXE]] board. The code was contributed by [mailto:anders@jenbo.dk Anders Jenbo], thanks!

== 2010/05/08 Wyse S50 now supported ==

coreboot now supports the [[Wyse S50]] board. The code was contributed by [mailto:njacobs8@hetnet.nl Nils Jacobs], thanks!

== 2010/04/23 AMD Tilapia and DDR3 now supported ==

coreboot now [http://www.coreboot.org/pipermail/coreboot/2010-April/057631.html supports] the '''AMD Tilapia''' board (socket AM3, ASB2), including initial DDR3 support. The code was contributed by AMD, thanks a lot!

== 2010/04/19 Nokia IP530 now supported ==

The [[Nokia IP530]] is currently able to run coreboot + [[SeaBIOS]] + [[SeaBIOS#Adding_sgabios_support|sgabios]]. The code was contributed by [[User:MBertens|Marc Bertens]] and tested/committed by [[User:Uwe|Uwe Hermann]].

== 2010/04/05 ASRock 939A785GMH/128M now supported ==

coreboot now supports the [http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M ASRock 939A785GMH/128M] board. The code was contributed by [[User:Ruik|Rudolf Marek]], thanks!

== 2010/03/16 AMD Mahogany now supported ==

coreboot now has initial support for the AMD Mahogany K8 and Fam10h eval boards. The code was contributed by AMD, thanks!

== 2010/03/15 AMD RS780 and SB700 now supported ==

coreboot now has initial support for the [http://www.coreboot.org/Datasheets#AMD_RS780 AMD RS780 / SB700] chipset. The code was contributed by AMD, thanks!

== 2010/03/05 ASUS P2B-LS now supported ==

coreboot now supports the [[ASUS P2B-LS]] board. Board support and additional 440BX chipset support was written by Keith Hui, with [[User:Uwe|Uwe Hermann]] doing review/testing. This proves that despite the great age of the board in question (it was released in 1998), an active Open Source community continues to provide support over a decade later.

== 2010/01/17 Roda RK886EX (Rocky III+) now supported ==

coreboot now has support for the first laptop, the [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda RK886EX (Rocky III+)], based on the Intel i945 / ICH7 chipset. The code was contributed by [http://www.coresystems.de/en/ coresystems GmbH], thanks! Read the [http://www.coreboot.org/pipermail/coreboot-announce/2010-January/000006.html full announcement] for details.

= 2009 =

== 2009/10/21 HP e-Vectra P2706T now supported ==

coreboot now has initial support for the '''HP e-Vectra P2706T''' mainboard. The code was contributed by [[User:Uwe|Uwe Hermann]]. System information and testing by [mailto:stawel@gmail.com Pawe? Stawicki], thanks!

== 2009/10/13 MSI MS-6156 now supported ==

coreboot now has initial support for the [[MSI MS-6156]] mainboard. The code was contributed by [[User:Uwe|Uwe Hermann]].

== 2009/10/13 TechNexion TIM-5690 now supported ==

coreboot now has support for the [http://www.technexion.com/index.php/tim-5690 TechNexion TIM-5690] mainboard (AMD RS690/SB600 chipset). The code was contributed by [mailto:libra.li@technexion.com Libra Li] of TechNexion, thanks!

== 2009/10/13 Kontron KT690/mITX now supported ==

coreboot now has support for the [http://us.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx.html Kontron KT690/mITX] mainboard (AMD RS690/SB600 chipset). The code was contributed by [http://www.coresystems.de/en/ coresystems GmbH], thanks!

== 2009/09/25 coreboot on the cover of the Linux Journal ==

The [http://www.linuxjournal.com/issue/186 October 2009 Linux Journal] features the coreboot logo on the cover and contains the article [http://www.linuxjournal.com/article/10447 "Coreboot at Your Service!"] by Anton Borisov - Use coreboot to take control of your hardware.

== 2009/09/02 flashrom 0.9.1 has been released ==

[[Flashrom|flashrom 0.9.1]] has been released. See the [[Flashrom/0.9.1|release notes]] for details.

== 2009/07/15 VIA EPIA-M700 now supported ==

The One Laptop per Child, Association, Inc. has contributed initial support for the [[VIA EPIA-M700]] board (based on the VIA VX800 code submitted earlier), thanks a lot! The code is still being worked on and improved by the community.

== 2009/07/05 Mitac 6513WU now supported ==

coreboot now has initial support for the [[Mitac 6513WU]] mainboard. The code was contributed by [mailto:mgold@ncf.ca Michael Gold], thanks!

== 2009/07/01 Intel EagleHeights now supported ==

coreboot now has initial support for the '''Intel EagleHeights''' mainboard. The code was contributed by [mailto:thomas.jourdan@gmail.com Thomas Jourdan], thanks!

== 2009/07/01 VIA EPIA-N now supported ==

coreboot now has initial support for the [http://www.idotpc.com/TheStore/pc/viewCategories.asp?idCategory=56 VIA EPIA-N] mainboard. The code was contributed by [mailto:bothlyn@blueyonder.co.uk Jon Harrison], thanks!

== 2009/06/24 Soyo SY-6BA+ III now supported ==

coreboot now has initial support for the [[Soyo SY-6BA Plus III|Soyo SY-6BA+ III]] mainboard. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks [mailto:ziltro@ziltro.com Andrew Morgan] for information and testing!

== 2009/05/27 VIA VX800 now supported ==

The One Laptop per Child, Association, Inc. has contributed support for the '''VIA VX800''' chipset family to the coreboot v2 tree.

== 2009/05/04 flashrom 0.9.0 has been released ==

After nine years of development and constant improvement, we have added support for every BIOS flash ROM technology present on x86 mainboards and every flash ROM chip we ever saw in the wild.

Highlights of [[flashrom]] include:
* Parallel, LPC, FWH and SPI flash interfaces.
* 157 flash chip families and half a dozen variants of each family.
* Flash chip package agnostic. DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40 and more have all been verified to work.
* 75 different chipsets, some with multiple flash controllers.
* Special mainboard enabling code for dozens of nonstandard mainboards.
* No physical access needed, root access is sufficient.
* No bootable floppy disk, bootable CD-ROM or other media needed.
* No keyboard or monitor needed. Simply reflash remotely via SSH.
* No instant reboot needed. Reflash your ROM in a running system, verify it, be happy. The new firmware will be present next time you boot.
* Crossflashing and hotflashing is possible as long as the flash chips are electrically and logically compatible (same protocol). Great for recovery.
* Scriptability. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes.
* Speed. flashrom is much faster than vendor flash tools.
* Supports Linux, FreeBSD, DragonFly BSD, Solaris, Mac OS X. Please refer to the README for build instructions.

Thanks go to everyone who contributed to flashrom over the years and especially to Li-Ta Lo for starting this project.

The release announcement can be found at http://www.coreboot.org/pipermail/coreboot/2009-May/047636.html.

== 2009/04/22 HP ProLiant DL145 G3 now supported ==

coreboot now has support for the [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 HP ProLiant DL145 G3] mainboard. The code was contributed by [mailto:nuessle@uni-hd.de Mondrian Nuessle] (thanks!).

== 2009/04/18 ASUS P2B-D now supported ==

coreboot now has initial support for the [[ASUS P2B-D]] mainboard. The code was contributed by [[User:Uwe|Uwe Hermann]].

== 2009/04/18 VIA CX700, and VIA VT8454c mainboard now supported ==

coreboot now has support for the '''VIA CX700''' chipset, and the '''VIA VT8454c''' mainboard. The code was developed by [http://www.coresystems.de/ coresystems GmbH].

== 2009/04/06 TechNexion TIM-8690 now supported ==

coreboot now has support for the [http://www.technexion.com/index.php/tim-8690 TIM-8690] mainboard (AMD RS690/SB600 chipset). The code was contributed by [mailto:daniel@dmhome.net Daniel Toussaint], thanks!

== 2009/03/22 coreboot @ FSF LibrePlanet 2009 ==

[[User:MJones|Marc Jones]] gave a coreboot [http://marcjonesconsulting.com/FSF%20talk.pdf presentation] at the [http://www.fsf.org/ Free Software Foundation] annual meeting, [http://www.fsf.org/associate/meetings/2009 Libre Planet 2009].

== 2009/01/10 coreboot and SeaBIOS starts Windows 7 ==

[[User:Ruik|Rudolf Marek]] recorded [[Screenshots#coreboot_and_SeaBIOS_starting_Windows_7|a video of his ASUS M2V-MX SE with coreboot and SeaBIOS starting Windows 7]] on a 2GHz AMD Sempron CPU.

== 2009/01/06 Ten years of coreboot ==

Anton Borisov [http://www.h-online.com/open/The-Open-Source-BIOS-is-Ten-An-interview-with-the-coreboot-developers--/features/112353 interviewed the original developers] ([http://www.heise.de/open/Zehn-Jahre-LinuxBIOS-Coreboot--/artikel/121679 german version]) as the Open Source PC firmware celebrates '''ten years of activity'''!

= 2008 =

== 2008/12/27 coreboot at 25C3 in Berlin, Germany ==

[[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2008/Fahrplan/events/2970.en.html coreboot: Beyond The Final Frontier] at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)].
[[Screenshots#Chaos_Communication_Congress_2008_.2825C3.29:_coreboot:_Beyond_The_Final_Frontier|The video presentation is available]] and also [http://www.linux-magazin.de/news/25c3_coreboot_version_3_gibt_sich_die_ehre an article in German] about the talk.

== 2008/12/15 ASUS P2B-DS now supported ==

coreboot now has initial support for the [[ASUS P2B-DS]] mainboard. The code was contributed by [[User:Uwe|Uwe Hermann]].

== 2008/12/09 AMD Pistachio now supported ==

coreboot now has support for the '''AMD Pistachio''' evaluation board. The code was contributed by AMD, thanks!

== 2008/12/10 coreboot confirmed for SCALE 7x ==

There will be a [http://scale7x.socallinuxexpo.org/dotorg/coreboot coreboot booth] at the [http://scale7x.socallinuxexpo.org/ Southern California Linux Expo] (SCALE 7x) on '''February 20-22, 2009'''.

== 2008/12/05 NEC PowerMate 2000 now supported ==

coreboot now has initial support for the [http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ NEC PowerMate 2000] board. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks [mailto:quentin.rameau@gmail.com Quentin RAMEAU] for providing the required information and for testing.

== 2008/11/19 LiPPERT Cool RoadRunner-LX now supported ==

coreboot now has support for the [http://www.lippert-at.com/index.php?id=408 LiPPERT Cool RoadRunner-LX] mainboard. The code was contributed by [mailto:support@LiPPERTEmbedded.de Jens Rottmann] from LiPPERT Embedded Computers GmbH, thanks!

== 2008/10/30 LiPPERT Cool SpaceRunner-LX now supported ==

coreboot now has support for the [http://www.lippert-at.com/index.php?id=478 LiPPERT Cool SpaceRunner-LX] mainboard. The code was contributed by [mailto:support@LiPPERTEmbedded.de Jens Rottmann] from LiPPERT Embedded Computers GmbH, thanks!

== 2008/10/28 Intel 945, ICH7, Core Duo/Core 2 Duo, and Kontron 986LCD-M/mITX now supported ==

coreboot now has support for the '''Intel i945/ICH7 Desktop/Mobile''' chipset, the '''Core Duo/Core 2 Duo''' processor, and the [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html Kontron 986LCD-M/mITX] mainboard. The code was developed by [http://www.coresystems.de/ coresystems GmbH].

== 2008/10/27 MSI MS-6147 now supported ==

coreboot now has initial support for the '''MSI MS-6147''' mainboard. The code was contributed by [mailto:mats.andersson@gisladisker.org Mats Erik Andersson], thanks!

== 2008/10/19 coreboot confirmed for 25C3 in Berlin, Germany ==

[[User:Stuge|Peter Stuge]] will present coreboot at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)].

[[Screenshots#Chaos_Communication_Congress_2008_.2825C3.29:_coreboot:_Beyond_The_Final_Frontier|The video presentation is available]] and also [http://www.linux-magazin.de/news/25c3_coreboot_version_3_gibt_sich_die_ehre an article in German] about the talk.

== 2008/10/12 VIA pc2500e now supported ==

coreboot now has initial support for the [[VIA pc2500e]] mainboard. The code was contributed by [[User:Uwe|Uwe Hermann]].

== 2008/11/06 coreboot at ELC Europe 2008 in Ede, The Netherlands ==

[[User:Stuge|Peter Stuge]] is presenting coreboot at the [http://www.nluug.nl/events/nj08/ NLUUG Autumn Conference on Mobile Computing] and [http://www.embeddedlinuxconference.com/elc_europe08/ CE Linux Forum - Embedded Linux conference Europe 2008].

== 2008/10/26 coreboot at FSCONS 2008 in Gothenburg, Sweden ==

[[User:Stuge|Peter Stuge]] is presenting coreboot at the [http://fscons.org/ Free Society Conference and Nordic Summit 2008].

== 2008/09/24 AMD RS690 / SB600 chipset and AMD dbm690t board now supported ==

coreboot now has initial support for the '''AMD RS690 / SB600''' chipset, as well as the [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf AMD dbm690t] (Herring) board using that chipset. The code was contributed by AMD, thanks!

== 2008/09/24 Intel EP80579 (Tolapai) now supported ==

coreboot now has initial support for the '''Intel EP80579 (Tolapai)''' chipset. The code was contributed by [[User:Eswierk|Ed Swierk]], thanks!

== 2008/09/24 coreboot interview at LinuxTag 2008 is now available as podcast ==

[[User:Hailfinger|Carl-Daniel Hailfinger]] gave an [http://www.linuxpodcast.de/?id=240 interview about coreboot and flashrom] at LinuxTag 2008 in Berlin. It was broadcast live on [http://www.radiotux.de/ RadioTux] and is now available as [http://www.linuxpodcast.de/?id=240 podcast]. The interview is in German. Thanks to Sirko Kemter for organizing the interview, Thomas Steinbrecher for interviewing and Ingo Ebel for cutting it and putting it online.

== 2008/09/23 ASUS M2V-MX SE now supported ==

coreboot now has initial support for the [[ASUS M2V-MX SE]] mainboard. The code was contributed by [[User:Ruik|Rudolf Marek]], thanks!

== 2008/09/13 coreboot talk at OpenBSD Slackathon in Stockholm ==

[[User:Stuge|Peter Stuge]] presented coreboot at the [http://slackathon.se/2008/ Slackathon 2008] OpenBSD meeting.

== 2008/09/10 Jetway J7F2/J7F4 now supported ==

coreboot now has initial support for the [[Jetway J7F2|Jetway J7F2/J7F4]] mainboards. The code was contributed by [[User:Hawke|Alex Mauer]], thanks!

== 2008/09/05 VIA VT8237S now supported ==

coreboot now has initial support for the '''VIA VT8237S''' southbridge. The code was contributed by [[User:Ruik|Rudolf Marek]], thanks!

== 2008/08/04 ASI MB-5BLGP / Neoware Eon 4000s now supported ==

coreboot now has initial support for the '''ASI MB-5BLGP (Neoware Eon 4000s)''' board. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks [mailto:hanneshe@arcor.de Hannes Hegewald] for providing the required information and for testing.

== 2008/07/01 New logo announced ==

The coreboot hare is the new project logo. Check it out over on the [[Logo]] page.

== 2008/07/01 coreboot booth at OpenExpo in Zürich ==

coreboot will be exhibiting at [http://www.openexpo.ch/ OpenExpo 2008] on '''September 24-25 2008''' in '''Zürich/Winterthur'''.

We are also [[News#2008.2F04.2F19_coreboot_is_a_Hackontest_candidate|a Hackontest candidate]], the Hackontest is organized in connection with the Expo.

== 2008/06/27 A-Trend ATC-6240 now supported ==

coreboot now has initial support for the [http://active-hardware.com/english/reviews/mainboard/atc6240.htm A-Trend ATC-6240] board. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks [mailto:eagle__eye@maktoob.com shadow] for providing the required information.

== 2008/05/28 coreboot booth at LinuxTag in Berlin ==

There will be a [[LinuxTag 2008|coreboot booth at LinuxTag 2008]] on '''May 28-31 2008''' in '''Berlin'''.

== 2008/05/19 VIA EPIA-CN now supported ==

coreboot now has initial support for the [http://www.coreboot.org/VIA_EPIA-CN_Build_Tutorial VIA EPIA-CN] board. The code was contributed by [mailto:aaron.lwe@gmail.com Aaron Lwe] of VIA, with various interim patches and testing also by [mailto:corey_osgood@verizon.net Corey Osgood], [mailto:urbez@linuxupc.upc.edu Urbez Santana Roma], [[User:Bari|Bari Ari]], and [mailto:remenic@gmail.com Richard Stellingwerff], thanks a lot! The code contribution also contained various VIA CN700 improvements which should make porting further VIA C7 + CN700 + VT8237R boards easier.

== 2008/05/16 Thomson IP1000 now supported ==

coreboot now has initial support for the [http://www.settoplinux.org/index.php Thomson IP1000] board. The code was contributed by [[User:Linux junkie|Joseph Smith]]. Linux has never been able to run on this board until now.

== 2008/04/24 IEI PCISA-LX-800-R10 now supported ==

Thanks to the contributions from [[User:Nikola|Nikolay Petukhov]] we now have support for the [[IEI LX 800|IEI PCISA-LX-800-R10]] half-size mainboard in our tree.

== 2008/04/21 coreboot participating in Google Summer of Code 2008 ==

The coreboot project (with [http://www.coresystems.de coresystems GmbH] as mentoring organization) is taking part in the [http://code.google.com/soc/ Google Summer of Code™ 2008] (GSoC). This year, the project has been assigned two slots/students who will work on the following projects:

* [http://code.google.com/soc/2008/coresystems/appinfo.html?csaid=ED0729A9DB64B39B All Virtual All The Time (AVATT)]
: ''This project aims to integrate into the coreboot BIOS a payload consisting of a minimalist KVM-aware Linux kernel along with an initrd image that contains the tools needed for creating and starting guest virtual machines installed on top of it. The resulting system could host any x86(or x86-64) OS that can run over KVM (almost any major OS does), and there is a great challenge to make it as small as possible, so that it can fit in a 2MB flash image.''
* [http://code.google.com/soc/2008/coresystems/appinfo.html?csaid=5B0D5443ED6193C7 SCSI booting in coreboot]
: ''Currently coreboot can not boot from an arbitrary SCSI controller. There are two solutions for the problem: (1) Use Linux and Kexec. This requires to keep the SCSI driver in the flash chip. (2) Use x86emu/vm86/ADLO and the int13 method. This would allow to use the PCI option rom available on all modern SCSI controllers. So we obviously need a solution based on the latter. This could as well be implemented as a Linux program, as an intermediate payload, or as a shared library. At this point of time, I would like to implemente it as a daemon program. The program needs to catch the int13 interrupt vector that the SCSI option rom installs and make it available to arbitrary (firmware/payload) code trying to load something from disk.''

== 2008/04/19 coreboot is a Hackontest candidate ==

[[User:Hailfinger|Carl-Daniel Hailfinger]] has registered coreboot at [http://www.hackontest.org/ Hackontest].

: ''Hackontest is a 24 hour programming competition between teams of three open source software projects.

: The event takes place at OpenExpo on September 24/25, 2008 in Zurich, Switzerland.''

[[Image:HackontestBanner_468x60-01.jpg]]

[http://www.hackontest.org/index.php?action=Root-projectDetail(36) Click here to request features and vote for them.]

== 2008/04/19 PC Engines ALIX.2C3 now supported ==

Thanks to [[User:Ward|Ward Vandewege]] coreboot v3 now supports the PC Engines [http://pcengines.ch/alix2c3.htm ALIX.2C3] mainboard.

== 2008/04/04 Silicon Mechanics to ship servers with coreboot preinstalled ==

Chris Watson at [http://siliconmechanics.com Silicon Mechanics] says:

:''We will commit to offering coreboot preinstallation on the [http://www.siliconmechanics.com/i7045/opteron-server.php Rackform nServ A236] with a specific set of hardware and software. In the future, we may expand the program to additional platforms based on customer interest. We will include a message about coreboot support on the platform page in the next few days with instructions to contact sales for additional information.''

If you want to buy such a machine, please contact Art Mann ([mailto:artm@siliconmechanics.com artm@siliconmechanics.com]) at Silicon Mechanics.

The A236 is a nice 1U server with 4 drive bays and a dual Opteron board (Supermicro H8DMR), which [http://www.coreboot.org/Supported_Motherboards is supported in coreboot v2].

== 2008/04/03 coreboot Symposium in Denver ==

There was a coreboot symposium in Denver, April 3 – 5, 2008 held during the High Performance Computer Science Week (HPCSW) [http://www.hpcsw.org LinuxBIOS Summit].

More information is available on the [[Coreboot Symposium 2008]] page.

== 2008/03/29 TeleVideo TC7020 now supported ==

coreboot now has initial support for the [[TeleVideo TC7020]] thin client. The code was contributed by [mailto:tokyo246@gmail.com Kenji Noguchi], thanks!

== 2008/03/17 MSI MS-6119 now supported ==

coreboot now has initial support for the [http://global.msi.com.tw/index.php?func=proddesc&prod_no=332&maincat_no=1 MSI MS-6119] board. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks [mailto:mechno@gmail.com Maarten van Eeuwijk] for information and testing.

== 2008/03/17 Intel 3100 chipset and Intel devkit (Mt. Arvon) board now supported ==

coreboot now has initial support for the [http://www.intel.com/design/intarch/devkits/pm3100.htm Intel "Mt. Arvon"] development board, as well as the [http://www.intel.com/design/chipsets/embedded/3100.htm Intel 3100] chipset. The code was contributed by [[User:Eswierk|Ed Swierk]].

== 2008/03/09 RCA RM4100 now supported ==

coreboot now has initial support for the [http://www.settoplinux.org RCA RM4100] board. The code was contributed by [[User:Linux junkie|Joseph Smith]]. This also includes support for the Intel 830M (82830) northbridge.

== 2008/03/07 ASUS A8V-E Deluxe now supported ==

coreboot now has [[ASUS A8V-E Deluxe|initial support]] for the [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&modelmenu=1 ASUS A8V-E Deluxe] board. The testing so far was done by [[User:Uwe|Uwe Hermann]], re-using code written by [mailto:r.marek@assembler.cz Rudolf Marek] for the ASUS A8V-E SE (thanks!), which is very similar.

== 2008/02/20 MSI MS-7135 (K8N Neo3) now supported ==

coreboot now has initial support for the [http://global.msi.com.tw/index.php?func=proddesc&prod_no=170&maincat_no=1 MSI MS-7135 (K8N Neo3)] board. The code was contributed by [[User:Jakllsch|Jonathan A. Kollasch]].

== 2008/01/27 Abit BE6-II V2.0 now supported ==

coreboot now supports the [http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAME=BE6-II+V2.0&fMTYPE=Slot+1 Abit BE6-II V2.0] board. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks Sergei Antonov for information and testing.

== 2008/01/12 LinuxBIOS is now called coreboot ==

As Ron Minnich, the founder of the LinuxBIOS project [http://www.coreboot.org/pipermail/coreboot/2008-January/029133.html explains in his announcement] the LinuxBIOS project has now been renamed to '''coreboot'''. Read the [http://www.coreboot.org/pipermail/coreboot/2008-January/029133.html whole announcement] for more details and the reasons behind the renaming.

= 2007 =

== 2007/11/26 ASUS MEW-AM now supported ==

LinuxBIOS now [[ASUS MEW-AM|supports]] the [ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ ASUS MEW-AM] board. The code was contributed by [[User:Uwe|Uwe Hermann]].

== 2007/11/13 Advantech PCM-5820 now supported ==

LinuxBIOS now [[Advantech PCM-5820|supports]] the [http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8&BU=ACG&PD= Advantech PCM-5820] half-size board. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks to [[User:Erwan|Erwan Velu]] for help and testing.

== 2007/11/13 Lightning talk at FSCONS 2007 in Gothenburg on 2007/12/08 ==

[mailto:peter@stuge.se Peter Stuge] is presenting [http://fscons.org/node/138 a LinuxBIOS lightning talk] at [http://fscons.org/ FSCONS 2007] on December 8.

== 2007/11/03 ASUS A8V-E SE now supported ==

Thanks to the great contribution from [mailto:r.marek@assembler.cz Rudolf Marek] we now have support for the [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&modelmenu=1 ASUS A8V-E SE] mainboard.

== 2007/10/31 Various Intel 440BX boards now supported ==

We now have initial support for various Intel 440BX / 82371EB based mainboards of the Pentium II/III era, namely the ASUS P2B-F, ASUS P3B-F, A-Trend ATC-6220, AZZA PT-6IBD, Biostar M6TBA, Compaq Deskpro EN SFF P600, and GIGABYTE GA-6BXC. The code was contributed by [[User:Uwe|Uwe Hermann]]. Thanks to todthgie, idwer_, and zxy_64-2 on [[IRC]] for helping with some of the boards.

== 2007/10/30 SiS761GX/SiS966 chipset and GIGABYTE GA-2761GXDK board now supported ==

Thanks to the great contributions from Morgan Tsai of SiS we now have support for both the SiS761GX/SiS966 chipset and the GIGABYTE [http://www.rssfeedbus.com/index.php?showtopic=1515 GA-2761GXDK] mainboard, which uses that chipset.

== 2007/10/30 VIA K8T890 / VT8237R now supported ==

Thanks to the great contribution from [mailto:r.marek@assembler.cz Rudolf Marek] we now have support for the VIA K8T890 / VT8237R chipset. A mainboard which uses this chipset will soon be added.

== 2007/10/26 AXUS TC320 now supported ==

LinuxBIOS now [[AXUS TC320|supports]] the '''AXUS TC320''' (Geode GX1 based) thin client. The code was contributed by [[User:Jbe|Jürgen Beisert]].

== 2007/10/10 BCOM WinNET100 (IGEL-316) now supported ==

LinuxBIOS now [[BCOM WINNET100|supports]] the '''BCOM WinNET100''' mainboard, as found in (e.g.) the '''IGEL-316''' (Geode GX1 based) thin client. The code was contributed by [[User:Jbe|Jürgen Beisert]].

== 2007/09/22 MSI MS-7260 now supported ==

LinuxBIOS now [[MSI MS-7260|supports]] the MSI [http://global.msi.com.tw/index.php?func=proddesc&prod_no=255&maincat_no=1&cat2_no=171 MS-7260 (K9N Neo)] mainboard. The code was added by [[User:Uwe|Uwe Hermann]], but most of the hard work (K8 + MCP55 support) was done by others.

== 2007/09/13 MSI MS-6178 now supported ==

Thanks to [[User:Uwe|Uwe Hermann]] we now have preliminary support for the MSI [http://www.msi-technology.de/produkte/main_idx_view.php?Prod_id=27 MS-6178] mainboard.

== 2007/09/08 PC Engines ALIX1.C now supported ==

Thanks to [[User:Rminnich|Ron Minnich]] we now have preliminary support for the PC Engines [http://pcengines.ch/alix1c.htm ALIX1.C] mainboard.

== 2007/06/14 Intel 810 chipset and ASUS MEW-VM now supported ==

Thanks to the great contributions from [mailto:corey_osgood@verizon.net Corey Osgood] we now have preliminary support for both the Intel 810 chipset (82810 northbridge) and the ASUS MEW-VM mainboard, which uses that northbridge.

== 2007/06/13 AMD DB800 (Salsa) now supported ==

LinuxBIOS now supports the AMD [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800] (a.k.a Salsa) Geode LX reference/evaluation mainboard. The code was contributed by [mailto:marc.jones@amd.com Marc Jones] of AMD.

== 2007/06/07 IEI JUKI-511P and ROCKY-512 now supported ==

Thanks to the contributions from [mailto:nikolaypetukhov@gmail.com Nikolay Petukhov] we now have support for the IEI JUKI-511P and the IEI ROCKY-512 half-size mainboards in our tree!

== 2007/05/24 ASUS A8N-E now supported ==

Thanks to the nice work of [mailto:pdegler@rumms.uni-mannheim.de Philipp Degler] we now have support for the ASUS A8N-E mainboard in our tree!

== 2007/05/23 LinuxBIOS booth at LinuxTag in Berlin, 29/5-2/6 ==

In one corner of Messe Berlin hall 12 (booth 12-80) we will be showing a couple of different systems all using LinuxBIOS to boot. There is a boot time competition in the booth (nice T-shirts to win!) and on Saturday 2/6 the developers will be presenting a [[LinuxTag 2007 Workshop|workshop]] where visitors are walked through the steps required to make their own EPIA/-M/-MII board run LinuxBIOS!

Video of an [http://video.google.com/videoplay?docid=3820348270731247338&hl=en interview] at the LinuxBIOS booth.

== 2007/05/05 DIGITAL-LOGIC MSM800SEV now supported ==

The [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV DIGITAL-LOGIC MSM800SEV] mainboard is now supported by LinuxBIOS. The code was written by [[User:Rminnich|Ron Minnich]], based on the recent AMD Geode LX framework contributed by AMD.

== 2007/05/04 AMD Norwich support and generally improved AMD Geode LX support ==

LinuxBIOS now supports the AMD Norwich reference/evaluation mainboard. This is ''the'' AMD Geode LX reference platform, and it's now well-supported by LinuxBIOS. Additionally the AMD Geode LX code in general was heavily improved and should simplify further ports of Geode LX systems a lot. The code was written and contributed by several AMD engineers, foremost [mailto:jordan.crouse@amd.com Jordan Crouse] and [mailto:marc.jones@amd.com Marc Jones] of AMD.

== 2007/03/14 LinuxBIOS participating in Google Summer of Code 2007 ==

The LinuxBIOS project (with [http://www.coresystems.de coresystems GmbH] as mentoring organization) is taking part in the [http://code.google.com/soc/ Google Summer of Code™ 2007] (GSoC). There is a [[GSoC|list of project ideas]] for students to work on (but feel free to suggest further ideas [[Mailinglist|on the LinuxBIOS mailing list]]).

Students who are interested in working on a LinuxBIOS-related GSoC project must apply until <strike>'''March 24, 2007'''</strike> [http://groups.google.com/group/google-summer-of-code-announce/browse_thread/thread/72f227109321bba5 Monday, March 27, 2007]!

'''Update:''' LinuxBIOS ended up with [http://code.google.com/soc/coresystems/about.html seven student projects] for GSoC 2007!

== 2007/02/24 LinuxBIOS talk at FOSDEM 2007 ==

[[User:Rminnich|Ron Minnich]] gave [http://www.fosdem.org/2007/schedule/events/linuxbios a talk about LinuxBIOS] on February 24, 2007 at [http://www.fosdem.org/2007/ FOSDEM 2007].

A [http://ftp.belnet.be/mirrors/FOSDEM/2007/FOSDEM2007-LinuxBios.ogg video recording of the talk] (Ogg, 234 MB) is available.

== 2007/02/09 MSI K9ND Master Series (MS-9282) supported in LinuxBIOS ==

LinuxBIOS now supports the MSI [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 K9SD Master Series (MS-9282)] mainboards. The code was contributed by [mailto:bxshi@msik.com.cn bxshi] of MSI, based on code for the NVIDIA MCP55 by [mailto:yinghailu@gmail.com Yinghai Lu] of AMD.

= 2006 =

== 2006/11/02 MSI K9SD Master-S2R (MS-9185) supported in LinuxBIOS ==

LinuxBIOS now supports the MSI [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx K9SD Master-S2R (MS-9185)] mainboard. The code was contributed by [mailto:bxshi@msik.com.cn bxshi] of MSI.

== 2006/10/05 AMD Rev F supported in LinuxBIOS ==

The AMD dual core support code is in public tree now. It includes
* AMD Rev F AMD64 on Socket F/Socket AM2

--yhlu

== 2006/10/01 LinuxBIOS Symposium 2006 in Hamburg ==

The LinuxBIOS Symposium 2006 took place in the old warehouse complex Speicherstadt in Hamburg, Germany.
See the page [[LinuxBIOS Symposium 2006]] for more details, slides, photos, etc...

--Stefan

= 2005 =

== 2005/06/02 AMD dual core supported in LinuxBIOS ==

The AMD dual core support code is in public tree now. It includes
* AMD D0/E0 Opteron new mem mapping support
* AMD E Opteron dual core support
* AMD E Opteron mem hole support
* AMD K8 Four Ranks DIMM support --- Quad Ranks.

--yhlu

== 2005/05/11 Nvidia CK804 (NForce4) supported in LinuxBIOS ==

The Nvidia CK804 support code is in public tree now. It includes
* Nvidia CK804 support
* smbus bus number support (to handle multi sumbus and mux)
* superio smsc47 support
* Tyan S2895/S2891/S2892 support
* flash_rom Ck804 support

--yhlu

== 2005/04/22 How Many People Are Using LinuxBIOS? Would you believe 1,000,000? ==

This question comes up to us all the time. Last week, I got an amazing answer. First, let
me mention that I tell skeptical people at vendors all the time, when
asked this question: "A lot more than just the
cluster community. The real use is in the embedded world". Well, again, last week,
I found out just how real that use is.

The system in question is the STPC Consumer. Evidently, this chipset is used in
an internet terminal sold in India. It runs LinuxBIOS and Linux.

There are at least one MILLION (1,000,000) of these things in use. I realize that is not much compared to the size of some markets, but had you told me six years ago that
one million systems would be using LinuxBIOS in 2005, I don't think I would have believed you.

--Ron

== 2005/03/01 LinuxBIOS Wiki up and running ==

After a week of testing and playing around, LinuxBIOS has a brand new Wiki now.

--Stefan

== 2005/02/28 LinuxBIOS slashdotted again ==

After Richard Stallman's call for support of free BIOS LinuxBIOS was slashdotted this weekend.

GIGABYTE GA-6BXC

2010-12-20T18:37:42Z

Uwe: GA-6BXC updates.

This page describes how to use coreboot on the [http://www.gigabyte.com/products/product-page.aspx?pid=1445 GIGABYTE GA-6BXC] mainboard.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status = OK
|CPU_L2_status = WIP
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it.
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = N/A

|RAM_EDO_status = WIP
|RAM_SDRAM_status = OK
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = N/A
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = N/A
|RAM_ecc_status = WIP
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.

|IDE_status = OK
|IDE_25_status = N/A
|SATA_status = N/A
|USB_status = OK
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = N/A
|Onboard_audio_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A
|Onboard_SCSI_status = N/A

|ISA_cards_status = Untested
|AMR_cards_status = N/A
|PCI_cards_status = OK
|Mini_PCI_cards_status = N/A
|PCIX_cards_status = N/A
|AGP_cards_status = OK
|PCIE_cards_status = N/A
|PCIE_x1_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = N/A
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = WIP
|COM1_status = OK
|COM2_status = OK
|PP_status = OK
|PP_comments = Doing '''modprobe ppdev''' seems to work, everything else is untested.
|PS2_keyboard_status = WIP
|PS2_keyboard_comments = Doesn't seem to work, yet. This is being investigated.
|PS2_mouse_status = WIP
|Game_port_status = N/A
|IR_status = Untested
|Speaker_status = OK
|DiskOnChip_status = N/A

|Sensors_status = Untested
|Watchdog_status = N/A
|SMBus_status = N/A
|CAN_bus_status = N/A
|CPUfreq_status = N/A
|Powersave_status = N/A
|ACPI_status = No
|ACPI_comments = There is no ACPI implementation for this board, yet.
|Reboot_status = OK
|Poweroff_status = No
|Poweroff_comments = Needs ACPI.
|LEDs_status = Untested
|HPET_status = N/A
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = No
|WakeOnLAN_comments = NIC is powered off when the system is off.
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = OK

}}

{{PD-self}}

ASUS M2N-E

2010-12-19T12:19:49Z

Uwe:

This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].

== Status ==

{{Status|

|CPU_status = OK
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+
|CPU_L1_status = OK
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|CPU_L2_status = OK
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = Untested
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = OK
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = OK
|RAM_dualchannel_comments = Seems to work. Tested: Two 512MB DIMMs (in the DIMM_A2 and DIMM_B2 slots).
|RAM_ecc_status = Untested

|IDE_status = OK
|IDE_comments = Tested: Booting from IDE disk (CF card actually).
|IDE_25_status = N/A
|SATA_status = OK
|SATA_comments = Tested: Booting from a SATA disk in ports SATA1-SATA6 (all of them work).
|USB_status = OK
|USB_comments = Tested: USB keyboard on all 10 USB ports.
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = OK
|Onboard_audio_status = OK
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A
|Onboard_SCSI_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|Mini_PCI_cards_status = N/A
|PCIX_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Tested: PCI graphics card in all three PCI slots.
|PCIE_x1_status = OK
|PCIE_x1_comments = Tested: PCI-E x1 NIC in both PCI-E x1 slots.
|PCIE_x2_status = N/A
|PCIE_x4_status = OK
|PCIE_x4_comments = Tested: PCI-E x1 NIC (which also fits in the x4 slot).
|PCIE_x8_status = N/A
|PCIE_x16_status = OK
|PCIE_x16_comments = Tested: PCI-E x16 graphics card.
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = WIP
|Floppy_comments = Doesn't seem to work, yet.
|COM1_status = OK
|COM2_status = N/A
|PP_status = OK
|PP_comments = Tested: '''modprobe ppdev'''.
|PS2_keyboard_status = OK
|PS2_mouse_status = OK
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status = OK
|DiskOnChip_status = N/A

|Sensors_status = OK
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.
|Watchdog_status = N/A
|SMBus_status = N/A
|CAN_bus_status = N/A
|CPUfreq_status = WIP
|CPUfreq_comments = Doesn't work, yet.
|Powersave_status = N/A
|ACPI_status = No
|ACPI_comments = There's no ACPI implementation for this board, yet.
|Reboot_status = OK
|Poweroff_status = No
|Poweroff_comments = Needs ACPI support.
|LEDs_status = OK
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.
|HPET_status = WIP
|HPET_comments = Currently not enabled in coreboot, but you can enable it via the '''hpet=force''' Linux kernel cmdline argument. The '''powertop''' tool works fine.
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = WIP
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).

}}

{{PD-self}}

ASUS M2N-E

2010-12-19T00:58:48Z

Uwe: More M2N-E updates.

This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].

== Status ==

{{Status|

|CPU_status = OK
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+
|CPU_L1_status = OK
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|CPU_L2_status = OK
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = Untested
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = OK
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = OK
|RAM_dualchannel_comments = Seems to work. Tested: Two 512MB DIMMs (in the DIMM_A2 and DIMM_B2 slots).
|RAM_ecc_status = Untested

|IDE_status = OK
|IDE_comments = Tested: Booting from IDE disk (CF card actually).
|IDE_25_status = N/A
|SATA_status = OK
|SATA_comments = Tested: Booting from a SATA disk in ports SATA1-SATA6 (all of them work).
|USB_status = OK
|USB_comments = Tested: USB keyboard on all 10 USB ports.
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = OK
|Onboard_audio_status = OK
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A
|Onboard_SCSI_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|Mini_PCI_cards_status = N/A
|PCIX_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Tested: PCI graphics card in all three PCI slots.
|PCIE_x1_status = OK
|PCIE_x1_comments = Tested: PCI-E x1 NIC in both PCI-E x1 slots.
|PCIE_x2_status = N/A
|PCIE_x4_status = OK
|PCIE_x4_comments = Tested: PCI-E x1 NIC (which also fits in the x4 slot).
|PCIE_x8_status = N/A
|PCIE_x16_status = OK
|PCIE_x16_comments = Tested: PCI-E x16 graphics card.
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = Untested
|Floppy_comments =
|COM1_status = OK
|COM2_status = N/A
|PP_status = OK
|PP_comments = Tested: '''modprobe ppdev'''.
|PS2_keyboard_status = OK
|PS2_mouse_status = OK
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status = OK
|DiskOnChip_status = N/A

|Sensors_status = OK
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.
|Watchdog_status = N/A
|SMBus_status = N/A
|CAN_bus_status = N/A
|CPUfreq_status = WIP
|CPUfreq_comments = Doesn't work, yet.
|Powersave_status = N/A
|ACPI_status = No
|ACPI_comments = There's no ACPI implementation for this board, yet.
|Reboot_status = OK
|Poweroff_status = No
|Poweroff_comments = Needs ACPI support.
|LEDs_status = OK
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.
|HPET_status = WIP
|HPET_comments = Currently not enabled in coreboot, but you can enable it via the '''hpet=force''' Linux kernel cmdline argument. The '''powertop''' tool works fine.
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = WIP
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).

}}

{{PD-self}}

ASUS M2N-E

2010-12-18T23:54:12Z

Uwe: Various ASUS M2N-E status updates.

This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].

== Status ==

{{Status|

|CPU_status = OK
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+
|CPU_L1_status = OK
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|CPU_L2_status = OK
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = Untested
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = OK
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = OK
|RAM_dualchannel_comments = Seems to work. Tested: Two 512MB DIMMs (in the DIMM_A2 and DIMM_B2 slots).
|RAM_ecc_status = Untested

|IDE_status = OK
|IDE_comments = Tested: Booting from IDE disk (CF card actually).
|IDE_25_status = N/A
|SATA_status = Untested
|USB_status = OK
|USB_comments = Tested: USB keyboard on all 10 USB ports.
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = OK
|Onboard_audio_status = OK
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A
|Onboard_SCSI_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|Mini_PCI_cards_status = N/A
|PCIX_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Tested: PCI graphics card in all three PCI slots.
|PCIE_x1_status = OK
|PCIE_x1_comments = Tested: PCI-E x1 NIC.
|PCIE_x2_status = N/A
|PCIE_x4_status = OK
|PCIE_x4_comments = Tested: PCI-E x1 NIC (which also fits in x4 slots).
|PCIE_x8_status = N/A
|PCIE_x16_status = Untested
|PCIE_x16_comments =
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = Untested
|Floppy_comments =
|COM1_status = OK
|COM2_status = N/A
|PP_status = OK
|PP_comments = Tested: '''modprobe ppdev'''.
|PS2_keyboard_status = OK
|PS2_mouse_status = Untested
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status = OK
|DiskOnChip_status = N/A

|Sensors_status = OK
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.
|Watchdog_status = Untested
|Watchdog_comments =
|SMBus_status = N/A
|CAN_bus_status = N/A
|CPUfreq_status = WIP
|CPUfreq_comments = Doesn't work, yet.
|Powersave_status = N/A
|ACPI_status = No
|ACPI_comments = There's no ACPI implementation for this board, yet.
|Reboot_status = OK
|Poweroff_status = No
|Poweroff_comments = Needs ACPI support.
|LEDs_status = OK
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.
|HPET_status = Untested
|HPET_comments =
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = WIP
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).

}}

{{PD-self}}

Datasheets

2010-12-18T13:39:07Z

Uwe: /* Intel */ Intel Atom / SCH

This page lists '''publically available datasheets''' and programming guides from various vendors. It includes CPU, chipset, Super I/O, and many other datasheets.

= x86 architecture =

== AMD ==

AMD provides their [http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.1&product=5.7&contentType=Tech+Doc+Processor&ostype=&keywords=&items=20 AMD64 Architecture and Software manuals], which are a very useful reference for AMD systems, of course (but also explain lots of non-AMD-specific x86 stuff too):

* [http://support.amd.com/us/Processor_TechDocs/24592.pdf Volume 1: Application Programming]
* [http://support.amd.com/us/Processor_TechDocs/24593.pdf Volume 2: System Programming 24593]
* [http://support.amd.com/us/Processor_TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26568.pdf Volume 4: 128-Bit Media Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26569.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions]
* [http://support.amd.com/us/Processor_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions]

Other AMD documents:
* [http://support.amd.com/us/Processor_TechDocs/43724.pdf Lightweight Profiling Specification]
* [http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf AMD I/O Virtualization Technology (IOMMU) Specification]
* [http://support.amd.com/us/Processor_TechDocs/32200.pdf Open Platform Management Architecture Specification]
* [http://support.amd.com/us/Processor_TechDocs/25481.pdf CPUID Specification]
* [http://support.amd.com/us/Processor_TechDocs/41918.pdf Advanced Platform Management Link (APML) Specification]

== Intel ==

Intel provides their [http://developer.intel.com/products/processor/manuals/index.htm Intel® 64 and IA-32 Architectures Software Developer's Manuals] which are a very useful reference to the x86 architecture in general:

* [http://developer.intel.com/Assets/PDF/manual/253665.pdf Volume 1: Basic Architecture]
* [http://developer.intel.com/Assets/PDF/manual/253666.pdf Volume 2A: Instruction Set Reference, A-M]
* [http://developer.intel.com/Assets/PDF/manual/253667.pdf Volume 2B: Instruction Set Reference, N-Z]
* [http://developer.intel.com/Assets/PDF/manual/253668.pdf Volume 3A: System Programming Guide]
* [http://developer.intel.com/Assets/PDF/manual/253669.pdf Volume 3B: System Programming Guide]
* [http://www.intel.com/Assets/PDF/manual/252046.pdf Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes]

Other Intel documents:

* [http://www.intel.com/Assets/PDF/manual/318148.pdf Intel® 64 Architecture x2APIC Specification]
* [http://www.intel.com/Assets/PDF/manual/248966.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual]
* [http://www.intel.com/Assets/PDF/manual/323640.pdf Intel® Carry-Less Multiplication Instruction and its Usage for Computing the GCM Mode White Paper]
* [http://www.intel.com/Assets/PDF/manual/323641.pdf Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Set White Paper]
* [http://www.intel.com/Assets/PDF/manual/323850.pdf Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) Application Note]

= CPU =

== AMD ==

=== AMD Fam11h ===

* [http://support.amd.com/us/Processor_TechDocs/41256.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/41788.pdf Revision Guide for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/43373.pdf AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks]

Turion64:
* [http://support.amd.com/us/Processor_TechDocs/32816.pdf AMD Turion™ 64 Mobile Technology Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/41407.pdf AMD Turion™ 64 X2 Mobile Technology Dual-Core Processor Product Data Sheet]

Athlon64:
* [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]

=== AMD Fam10h ===

* [http://support.amd.com/us/Processor_TechDocs/31116.pdf BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h]
** [http://support.amd.com/us/Processor_TechDocs/41322.pdf Revision Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/40546-PUB-Optguide_3-11_5-21-09.pdf Software Optimization Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/43374.pdf AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/43375.pdf AMD Family 10h Desktop Processor Power and Thermal Data Sheet]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/40036.pdf Family 10h AMD Opteron Processor Product Data Sheet]

Phenom:
* [http://support.amd.com/us/Processor_TechDocs/44109.pdf Family 10h AMD Phenom™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/46878.pdf Family 10h AMD Phenom™ II Processor Product Data Sheet]

=== AMD K8 ===

Athlon64/Opteron:
* [http://support.amd.com/us/Processor_TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/25759.pdf Revision Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/26633_5649.pdf AMD Athlon™ and AMD Opteron™ Processors Thermal Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/40555.pdf Performance Guidelines for AMD Athlon™ and AMD Opteron™ ccNUMA Multiprocessor Systems]
* [http://support.amd.com/us/Processor_TechDocs/24707_PUB.PDF Clock Generator Specification for AMD Athlon™ and AMD Opteron™ Processors]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/23932.pdf AMD Opteron™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30417.pdf AMD Opteron™ Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/40820_PUB_AMD_Opteron_Processor_Production_Notice_rev_3_08.pdf AMD Opteron™ x52 and x54 Production Notice]
* [http://support.amd.com/us/Processor_TechDocs/30925.pdf Builders Guide for AMD Opteron™ Processor-Based Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/33340.pdf AMD Opteron™ Multiprocessor Systems Running Linux Technical Bulletin for AMD OEMs and Partners]

Family 0Fh:
* [http://support.amd.com/us/Processor_TechDocs/32559.pdf BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/33610.pdf Revision Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/31119.pdf AMD NPT Family 0Fh Processor Electrical Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/33954.pdf AMD NPT Family 0Fh Desktop Processor Power and Thermal Data Sheet]

=== Athlon64 ===

* [http://support.amd.com/us/Processor_TechDocs/24659.pdf AMD Athlon™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31783.pdf AMD Athlon™ Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/43042.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/33425.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet] (ver 3.10, 1/21/2007)
** [http://support.amd.com/us/Processor_TechDocs/42989.pdf AMD Athlon™ X2 Dual-Core Processor for Notebooks Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/30431.pdf AMD Athlon™ FX Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31366.pdf AMD Athlon™ FX-60 Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31225.pdf Mobile AMD Athlon™ Processor 3400+ Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31684.pdf Builder's Guide for AMD Athlon™ Processor-Based Desktops and Workstations]

=== Athlon (32bit) ===

* [http://support.amd.com/us/Processor_TechDocs/21016.pdf AMD Athlon™ Processor Module Data Sheet] (rev. M-0, 5/31/2000)
** [http://support.amd.com/us/Processor_TechDocs/22054.pdf AMD Athlon™ Processor Technical Brief]
* [http://support.amd.com/us/Processor_TechDocs/26237.PDF AMD Athlon™ XP Processor Model 10 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/27375.pdf AMD Athlon XP Processor Model 10 with 256K L2 Cache]
** [http://support.amd.com/us/Processor_TechDocs/27532.pdf AMD Athlon™ Processor Model 10 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/26426.PDF AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/25175.pdf AMD Athlon™ XP Processor Model 8 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/25703.pdf AMD Athlon™ Processor Model 8 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25722.pdf AMD Athlon™ MP Processor Model 8 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/24685.pdf AMD Athlon™ MP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24309.pdf AMD Athlon™ XP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24332.pdf AMD Athlon™ Processor Model 6 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25480.pdf AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/23792.pdf AMD Athlon™ Processor Model 4 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23614.pdf AMD Athlon™ Processor Model 4 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/22651.pdf AMD Athlon™ Processor Voltage Regulation Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23811.pdf AMD Athlon™ Processor Module Signal and Power-Up Requirements Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25823.pdf Builder’s Guide for 2P Capable Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/25325.pdf System Considerations for Dual AMD Athlon™ MP Processors in Tower and 1U Form Factors]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]
* [http://support.amd.com/us/Processor_TechDocs/24228.pdf Methodologies for Measuring Temperature on AMD Athlon™ and AMD Duron™ Processors]
* [http://support.amd.com/us/Processor_TechDocs/22007.pdf AMD Athlon™ Processor x86 Code Optimization Guide]

=== Sempron ===

* [http://support.amd.com/us/Processor_TechDocs/31805.pdf AMD Sempron™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31994.pdf AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31993.pdf AMD Sempron™ Processor Model 10 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31693.pdf AMD Sempron™ Processor Model 8 Data Sheet]

=== Duron ===

* [http://support.amd.com/us/Processor_TechDocs/TN13.pdf AMD Duron™ Processor Rev. A0: CPUID Reporting of L2 Cache Size]
* [http://support.amd.com/us/Processor_TechDocs/25848.PDF AMD Duron™ Processor Model 8 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/24310.pdf AMD Duron™ Processor Model 7 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24806.pdf AMD Duron™ Processor Model 7 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/23802.pdf AMD Duron™ Processor Model 3 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23865.pdf AMD Duron™ Processor Model 3 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]

=== Socket specs ===

* [http://support.amd.com/us/Processor_TechDocs/25766.pdf AMD Socket 940 Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/31412.pdf AMD Functional Data Sheet, 940 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/30353.pdf AMD Socket 940 Qualification Plan]
* [http://support.amd.com/us/Processor_TechDocs/31700.pdf Socket F (1207) Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/32800.pdf Thermal Design Guide for Socket F (1207) Processors]
* [http://support.amd.com/us/Processor_TechDocs/31875.pdf Socket AM2 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/40523.pdf Socket AM3 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31839.pdf Low-Profile Socket S1 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31410.pdf AMD Functional Data Sheet, 754 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/24850.PDF Socket 754 Design and Qualification Requirements]
* [http://support.amd.com/us/Processor_TechDocs/31411.pdf AMD Functional Data Sheet, 939-Pin Package]
* [http://support.amd.com/us/Processor_TechDocs/23986.pdf Socket A AMD Processor and Heatsink Installation Guide]

=== Misc ===

* [http://support.amd.com/us/Processor_TechDocs/20734.pdf AMD Processor Recognition Application Note]
* [http://support.amd.com/us/Processor_TechDocs/22466.pdf AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets Manual]
* [http://support.amd.com/us/Processor_TechDocs/21928.pdf 3DNow!™Technology Manual]
** [http://support.amd.com/us/Processor_TechDocs/22621.pdf 3DNow!™ Instruction Porting Guide Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23794.pdf AMD Thermal, Mechanical, and Chassis Cooling Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/30579_3_74.pdf AMD Processor Performance Evaluation Guide]
* [http://support.amd.com/us/Processor_TechDocs/32035.pdf Compiler Usage Guidelines for AMD64 Platforms Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors]
* [http://support.amd.com/us/Processor_TechDocs/26951.pdf Thermal Interface Material Comparison: Thermal Pads vs. Thermal Grease]
* [http://support.amd.com/us/Processor_TechDocs/26003.pdf Builders Guide for Desktop/Tower Systems]
* [http://support.amd.com/us/Processor_TechDocs/26698.pdf Linux Kernel Issue with Systems Using AGP Graphics]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/30887.pdf Building AMD64 Applications with the Microsoft Platform SDK]
* [http://support.amd.com/us/Processor_TechDocs/30888.pdf Creating an AMD64 Build Enviroment for DirectX-Based Applations]
* [http://support.amd.com/us/Processor_TechDocs/33609.pdf Processor Utilization with Microsoft® Windows® Media Center Edition on Systems Enabled with Cool'n'Quiet™ and AMD PowerNow™ Technologies]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/tn17.pdf Microsoft Windows® 2000 Patch for AGP Applications on AMD Athlon™ and AMD Duron™ Processors]

== Intel ==

=== Intel Pentium III ===

* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii Highlights/Overview]
* [http://ark.intel.com/ProductCollection.aspx?familyID=590&MarketSegment=DT List of Pentium III models, steppings, etc.]
* [http://www.intel.com/support/processors/pentiumiii/sb/CS-023730.htm Intel® Pentium® III Processor: Datasheets]
** [http://download.intel.com/support/processors/pentiumiii/sb/24965705.pdf Intel® Pentium® III Processor with 512-KB L2 Cache at 1.13GHz to 1.40 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24976503.pdf Intel® Pentium® III Processor Based on 0.13 Micron Process Up to 1.33 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24526408.pdf Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24445209.pdf Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/27367306.pdf Low Voltage Intel® Pentium® III Processor 512-KB] (PDF)
* [http://www.intel.com/design/intarch/specupdt/244453.htm Intel® Pentium® III Processor Specification Update] ([http://download.intel.com/design/intarch/specupdt/24445358.pdf PDF])

Mobile:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-m Highlights/Overview]
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023739.htm Mobile Intel® Pentium® III Processor - M Datasheet] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/29834006.pdf PDF])
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023740.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/24530659.pdf PDF])
* [http://www.intel.com/design/intarch/specupdt/245306.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/design/intarch/specupdt/24530663.pdf PDF])
* [http://developer.intel.com/design/mobile/datashts/245302.htm Mobile Pentium® III Processor in BGA2 and Micro-PGA2 Packages] ([http://download.intel.com/design/mobile/datashts/24530202.pdf PDF])

Embedded:
* [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii.htm Embedded Intel® Architecture Processors: Intel® Pentium® III Processors: Technical Documents]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_pga370.htm Intel® Pentium® III Processor - PGA370]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_low.htm Intel® Pentium® III Processor - Low Power]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_vol.htm Low Voltage Intel® Pentium® III Processor]

Xeon:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-xeon Highlights/Overview]

== VIA ==

=== VIA Padlock ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=281 Security Application note]
* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 PadLock Programming Guide]

= Northbridge =

== AMD ==

=== AMD RS880 ===

* [http://support.amd.com/us/Embedded_TechDocs/46143_rs880_BDG_pub_3.00.pdf AMD RS880 Family BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46141_rs880_rpr_pub_3.00.pdf AMD RS880 Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/46142_rs880_rrg_pub_3.00.pdf AMD RS880 Family Register Reference Guide] (RRG)

=== AMD RD890 ===

Not public (yet?). However, some of the information may be contained in the public docs in the RS880 section.

* AMD RD890 BIOS Developer's Guide (Publication #43606)
* AMD RD890 Register Reference Guide (Publication #43607)

=== AMD RS780 ===

* [http://support.amd.com/us/Embedded_TechDocs/43734_rs780_bdg_pub_1.01.pdf AMD 780G Family BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf AMD 780G Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/43451_rs780_rrg_pub_1.01.pdf AMD 780G Family Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/45732_rs780e_ds_pub_3.10.pdf AMD 780E Databook]
* [http://support.amd.com/us/Embedded_TechDocs/48319.pdf AMD 780 Product Errata]

Apparently there are other docs as well, not sure if they provide any additional information or if they are part of the public documents above:

* AMD RD780 Register Reference Guide
* AMD RX780 Register Reference Guide
* AMD RS780M Hybrid Graphics – System BIOS Detailed Design Document (Publication #44969)
* AMD RD790 Register Programming Requirements (Publication #42462)
* AMD RD790 Register Reference Guide (Publication #42988)
* AMD RD790 BIOS Developer's Guide (Publication #43093)

=== AMD RS690 ===

* [http://support.amd.com/us/Embedded_TechDocs/43372_rs690_rrg_3.00o.pdf AMD RS690 Register Reference Guide] (RRG)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41977_rs690_ds_3.06.pdf AMD 690G Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41978_rs690m_ds_3.06.pdf AMD M690 Databook (Notebook Solutions)]
* [http://support.amd.com/us/Embedded_TechDocs/42437_m690t_ds_3_08.pdf AMD M690T/M690E Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD690Series_LogoGuide.pdf AMD 690 Chipset Logos]

=== Misc ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD_7-Series_Chipsets_-_Guidelines.pdf AMD 7-Series Chipsets - Guidelines.pdf]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD Model S1 DBM690T, Socket S1 and M690T/SB600 Chipset Development Board]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMDCrossFire_LogoGuide.pdf AMD 480X Chipset Logos]

== Intel ==

=== Intel Atom Z5xx and SCH US15Wx ===

* [http://ark.intel.com/ProductCollection.aspx?codeName=24973 Overview of products formerly named Poulsbo]
* [http://edc.intel.com/Platforms/Atom-Z5xx/#hardware Overview: Intel® Atom™ Processor Z5xx Series and Intel® System Controller Hub US15Wx]
** [http://edc.intel.com/Link.aspx?id=1387 Datasheet: Intel® System Controller Hub (Intel® SCH)] (PDF)
** [http://edc.intel.com/Link.aspx?id=1905 Datasheet: Intel® System Controller Hub (Intel® SCH) (large form factor)] (PDF)

=== Intel NM10 Express ===

* [http://www.intel.com/Products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm Overview]
** [http://www.intel.com/Assets/PDF/datasheet/322896.pdf Intel® NM10 Express Chipset Datasheet]
** [http://www.intel.com/Assets/PDF/specupdate/322897.pdf Intel® NM10 Express Chipset Specification Update]

=== Intel 860 ===

* [http://www.intel.com/design/archives/chipsets/860/index.htm Hardware Design: Archives - Intel® 860 Chipset Family Technical Documentation]
** [http://www.intel.com/design/chipsets/datashts/290713.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Datasheet]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
*** [http://www.intel.com/design/chipsets/specupdt/290715.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Specification Update]: [http://www.intel.com/design/chipsets/specupdt/29071501.pdf PDF]
** [http://www.intel.com/design/chipsets/applnots/292269.htm Intel® 860 Chipset Thermal Considerations Application Note (AP-721)]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298252.htm Intel® Xeon® Processor and Intel® 860 Chipset Platform Design Guide]: [http://download.intel.com/design/chipsets/designex/29825204.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298302.htm Intel® 860 Chipset Memory Expansion Card (MEC) Design Guide]: [http://download.intel.com/design/chipsets/designex/29830201.pdf PDF]
** [http://www.intel.com/design/chipsets/schematics/860_crb.htm Intel 860 Chipset CRB Schematics]: [http://download.intel.com/design/chipsets/schematics/860_crb.pdf PDF]

=== Intel 82815E ===

* [http://download.intel.com/design/chipsets/datashts/29068801.pdf 82815 Chipset Family]
* [http://download.intel.com/design/chipsets/designex/29823401.pdf 82815E Chipset Platform Design Guide]
* [http://download.intel.com/design/chipsets/designex/29824906.pdf 82815E Chipset Platform Design Guide update]

=== Intel 440BX ===

* [http://download.intel.com/design/chipsets/datashts/29063301.pdf Datasheet]
* [http://download.intel.com/design/chipsets/datashts/27321903.pdf Electrical and Thermal Timing Specification]

=== Intel 440LX ===

* [http://download.intel.com/design/chipsets/datashts/29056402.pdf Datasheet]
* [http://www.intel.com/design/chipsets/specupdt/29765505.pdf Spec update]

== VIA ==

VIA has a [http://linux.via.com.tw portal] with some source code and datasheets.

=== VIA VX800 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241 VIA VX800 Programming Manual]

=== VIA CX700M/VX700 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 VIA CX700M/VX700 Programming Manual]

= Southbridge =

== AMD ==

=== AMD SB820M ===

* [http://support.amd.com/us/Embedded_TechDocs/47283_sb820m_ds_pub_2.00.pdf AMD SB820M Southbridge Databook]

=== AMD SB800 ===

Not available yet, but here are the numbers for the documents we'd like to get. I found these numbers with a creative Internet search.

* AMD SB800 Databook (Publication #44758)

=== AMD SB700/SB710/SB750 ===

* [http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf AMD SB700/710/750 BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf AMD SB700/710/750 Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/42413_sb7xx_rpr_pub_1.00.pdf AMD SB700/710/750 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/45215_sb710_ds_pub_1.25.pdf AMD SB710 Databook]
* [http://support.amd.com/us/Embedded_TechDocs/46837.pdf AMD SB700 Family Product Errata]

=== AMD SB600 ===

* [http://support.amd.com/us/Embedded_TechDocs/46157_sb600_bdg_pub.3.00.pdf AMD SB600 BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46155_sb600_rrg_pub_3.03.pdf AMD SB600 Register Reference Manual] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/46156_sb600_rpr_pub_3.02b.pdf AMD SB600 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42119_sb600_ds_3.05.pdf AMD SB600 Databook] (rev. 3.05)
* [http://support.amd.com/us/Embedded_TechDocs/42119_sb600_ds_pub_3.07.pdf AMD SB600 Databook] (rev. 3.07)

=== AMD 8111 ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/24674.pdf AMD-8111™ HyperTransport™ I/O Hub Data Sheet]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/26036.pdf AMD-8111™ HyperTransport™ I/O Hub Product Brief]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/25720.pdf AMD-8111™ HyperTransport™ I/O Hub Revision Guide]

== Intel ==

=== Intel 82801BA/BAM (ICH2) ===

* [http://developer.intel.com/design/chipsets/datashts/290687.htm Datasheet]

= Super I/O =

== ITE ==

* [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 PC Desktop/Notebook Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 Desktop Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=6 Notebook Super I/Os]

== Winbond / Nuvoton ==

* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/ISASuperIO/ ISA Super I/Os]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/LPCSuperIOforDesktopAndServer/ LPC Super I/O for Desktop & Server]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforDesktop/ Advanced Super I/O for Desktop]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforNotebook/ Advanced Super I/O for Notebook]

== Fintek ==

* [http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17&layer=0 Super Hardware Monitor + SIO]

== NSC ==

(bought by Winbond, now Nuvoton)

== ALi ==

== SMSC ==

* [http://www.smsc.com/main/catalog/ioprods.html Products / datasheets overview]
* [http://www.smsc.com/main/datasheet.html Various product datasheets]

= Other =

== ACPI ==

* http://www.acpi.info

== USB ==

== Misc ==

* [http://support.amd.com/us/Pages/techdocs.aspx AMD public documents]
** The [http://www.amd.com/us/products/embedded/develop-and-design/Pages/processor-chipset-linux-supprt.aspx AMD64 Embedded Processors and Chipset Linux Support] web page features links to supported projects (like coreboot) and links to documentation.

= Resources =

There are many datasheet archives on the web which may have other (usually older) datasheets which already disappeared from vendor websites.

Datasheets

2010-12-18T11:15:08Z

Uwe: /* Intel */ Intel NM10

This page lists '''publically available datasheets''' and programming guides from various vendors. It includes CPU, chipset, Super I/O, and many other datasheets.

= x86 architecture =

== AMD ==

AMD provides their [http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.1&product=5.7&contentType=Tech+Doc+Processor&ostype=&keywords=&items=20 AMD64 Architecture and Software manuals], which are a very useful reference for AMD systems, of course (but also explain lots of non-AMD-specific x86 stuff too):

* [http://support.amd.com/us/Processor_TechDocs/24592.pdf Volume 1: Application Programming]
* [http://support.amd.com/us/Processor_TechDocs/24593.pdf Volume 2: System Programming 24593]
* [http://support.amd.com/us/Processor_TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26568.pdf Volume 4: 128-Bit Media Instructions]
* [http://support.amd.com/us/Processor_TechDocs/26569.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions]
* [http://support.amd.com/us/Processor_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions]

Other AMD documents:
* [http://support.amd.com/us/Processor_TechDocs/43724.pdf Lightweight Profiling Specification]
* [http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf AMD I/O Virtualization Technology (IOMMU) Specification]
* [http://support.amd.com/us/Processor_TechDocs/32200.pdf Open Platform Management Architecture Specification]
* [http://support.amd.com/us/Processor_TechDocs/25481.pdf CPUID Specification]
* [http://support.amd.com/us/Processor_TechDocs/41918.pdf Advanced Platform Management Link (APML) Specification]

== Intel ==

Intel provides their [http://developer.intel.com/products/processor/manuals/index.htm Intel® 64 and IA-32 Architectures Software Developer's Manuals] which are a very useful reference to the x86 architecture in general:

* [http://developer.intel.com/Assets/PDF/manual/253665.pdf Volume 1: Basic Architecture]
* [http://developer.intel.com/Assets/PDF/manual/253666.pdf Volume 2A: Instruction Set Reference, A-M]
* [http://developer.intel.com/Assets/PDF/manual/253667.pdf Volume 2B: Instruction Set Reference, N-Z]
* [http://developer.intel.com/Assets/PDF/manual/253668.pdf Volume 3A: System Programming Guide]
* [http://developer.intel.com/Assets/PDF/manual/253669.pdf Volume 3B: System Programming Guide]
* [http://www.intel.com/Assets/PDF/manual/252046.pdf Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes]

Other Intel documents:

* [http://www.intel.com/Assets/PDF/manual/318148.pdf Intel® 64 Architecture x2APIC Specification]
* [http://www.intel.com/Assets/PDF/manual/248966.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual]
* [http://www.intel.com/Assets/PDF/manual/323640.pdf Intel® Carry-Less Multiplication Instruction and its Usage for Computing the GCM Mode White Paper]
* [http://www.intel.com/Assets/PDF/manual/323641.pdf Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Set White Paper]
* [http://www.intel.com/Assets/PDF/manual/323850.pdf Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) Application Note]

= CPU =

== AMD ==

=== AMD Fam11h ===

* [http://support.amd.com/us/Processor_TechDocs/41256.pdf BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/41788.pdf Revision Guide for AMD Family 11h Processors]
** [http://support.amd.com/us/Processor_TechDocs/43373.pdf AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks]

Turion64:
* [http://support.amd.com/us/Processor_TechDocs/32816.pdf AMD Turion™ 64 Mobile Technology Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/41407.pdf AMD Turion™ 64 X2 Mobile Technology Dual-Core Processor Product Data Sheet]

Athlon64:
* [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]

=== AMD Fam10h ===

* [http://support.amd.com/us/Processor_TechDocs/31116.pdf BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h]
** [http://support.amd.com/us/Processor_TechDocs/41322.pdf Revision Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/40546-PUB-Optguide_3-11_5-21-09.pdf Software Optimization Guide for AMD Family 10h Processors]
* [http://support.amd.com/us/Processor_TechDocs/43374.pdf AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/43375.pdf AMD Family 10h Desktop Processor Power and Thermal Data Sheet]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/40036.pdf Family 10h AMD Opteron Processor Product Data Sheet]

Phenom:
* [http://support.amd.com/us/Processor_TechDocs/44109.pdf Family 10h AMD Phenom™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/46878.pdf Family 10h AMD Phenom™ II Processor Product Data Sheet]

=== AMD K8 ===

Athlon64/Opteron:
* [http://support.amd.com/us/Processor_TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/25759.pdf Revision Guide for AMD Athlon™ and AMD Opteron™ Processors]
** [http://support.amd.com/us/Processor_TechDocs/26633_5649.pdf AMD Athlon™ and AMD Opteron™ Processors Thermal Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/40555.pdf Performance Guidelines for AMD Athlon™ and AMD Opteron™ ccNUMA Multiprocessor Systems]
* [http://support.amd.com/us/Processor_TechDocs/24707_PUB.PDF Clock Generator Specification for AMD Athlon™ and AMD Opteron™ Processors]

Opteron:
* [http://support.amd.com/us/Processor_TechDocs/23932.pdf AMD Opteron™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30417.pdf AMD Opteron™ Processor Power and Thermal Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/40820_PUB_AMD_Opteron_Processor_Production_Notice_rev_3_08.pdf AMD Opteron™ x52 and x54 Production Notice]
* [http://support.amd.com/us/Processor_TechDocs/30925.pdf Builders Guide for AMD Opteron™ Processor-Based Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/33340.pdf AMD Opteron™ Multiprocessor Systems Running Linux Technical Bulletin for AMD OEMs and Partners]

Family 0Fh:
* [http://support.amd.com/us/Processor_TechDocs/32559.pdf BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/33610.pdf Revision Guide for AMD NPT Family 0Fh Processors]
** [http://support.amd.com/us/Processor_TechDocs/31119.pdf AMD NPT Family 0Fh Processor Electrical Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/33954.pdf AMD NPT Family 0Fh Desktop Processor Power and Thermal Data Sheet]

=== Athlon64 ===

* [http://support.amd.com/us/Processor_TechDocs/24659.pdf AMD Athlon™ Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/30430.pdf AMD Athlon™ Processor Power and Thermal Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31783.pdf AMD Athlon™ Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/43042.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/33425.pdf AMD Athlon™ X2 Dual-Core Processor Product Data Sheet] (ver 3.10, 1/21/2007)
** [http://support.amd.com/us/Processor_TechDocs/42989.pdf AMD Athlon™ X2 Dual-Core Processor for Notebooks Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/30431.pdf AMD Athlon™ FX Processor Product Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/31366.pdf AMD Athlon™ FX-60 Processor Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31225.pdf Mobile AMD Athlon™ Processor 3400+ Competitive Performance Guide]
* [http://support.amd.com/us/Processor_TechDocs/31684.pdf Builder's Guide for AMD Athlon™ Processor-Based Desktops and Workstations]

=== Athlon (32bit) ===

* [http://support.amd.com/us/Processor_TechDocs/21016.pdf AMD Athlon™ Processor Module Data Sheet] (rev. M-0, 5/31/2000)
** [http://support.amd.com/us/Processor_TechDocs/22054.pdf AMD Athlon™ Processor Technical Brief]
* [http://support.amd.com/us/Processor_TechDocs/26237.PDF AMD Athlon™ XP Processor Model 10 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/27375.pdf AMD Athlon XP Processor Model 10 with 256K L2 Cache]
** [http://support.amd.com/us/Processor_TechDocs/27532.pdf AMD Athlon™ Processor Model 10 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/26426.PDF AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/25175.pdf AMD Athlon™ XP Processor Model 8 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/25703.pdf AMD Athlon™ Processor Model 8 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25722.pdf AMD Athlon™ MP Processor Model 8 Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/24685.pdf AMD Athlon™ MP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24309.pdf AMD Athlon™ XP Processor Model 6 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24332.pdf AMD Athlon™ Processor Model 6 Revision Guide]
** [http://support.amd.com/us/Processor_TechDocs/25480.pdf AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms]
* [http://support.amd.com/us/Processor_TechDocs/23792.pdf AMD Athlon™ Processor Model 4 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23614.pdf AMD Athlon™ Processor Model 4 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/22651.pdf AMD Athlon™ Processor Voltage Regulation Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23811.pdf AMD Athlon™ Processor Module Signal and Power-Up Requirements Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25823.pdf Builder’s Guide for 2P Capable Servers and Workstations]
* [http://support.amd.com/us/Processor_TechDocs/25325.pdf System Considerations for Dual AMD Athlon™ MP Processors in Tower and 1U Form Factors]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]
* [http://support.amd.com/us/Processor_TechDocs/24228.pdf Methodologies for Measuring Temperature on AMD Athlon™ and AMD Duron™ Processors]
* [http://support.amd.com/us/Processor_TechDocs/22007.pdf AMD Athlon™ Processor x86 Code Optimization Guide]

=== Sempron ===

* [http://support.amd.com/us/Processor_TechDocs/31805.pdf AMD Sempron™ Processor Product Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31994.pdf AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31993.pdf AMD Sempron™ Processor Model 10 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/31693.pdf AMD Sempron™ Processor Model 8 Data Sheet]

=== Duron ===

* [http://support.amd.com/us/Processor_TechDocs/TN13.pdf AMD Duron™ Processor Rev. A0: CPUID Reporting of L2 Cache Size]
* [http://support.amd.com/us/Processor_TechDocs/25848.PDF AMD Duron™ Processor Model 8 Data Sheet]
* [http://support.amd.com/us/Processor_TechDocs/24310.pdf AMD Duron™ Processor Model 7 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/24806.pdf AMD Duron™ Processor Model 7 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/23802.pdf AMD Duron™ Processor Model 3 Data Sheet]
** [http://support.amd.com/us/Processor_TechDocs/23865.pdf AMD Duron™ Processor Model 3 Revision Guide]
* [http://support.amd.com/us/Processor_TechDocs/24387.pdf One Page AMD Athlon™ and AMD Duron™ Processor-Based System Build Checklist]

=== Socket specs ===

* [http://support.amd.com/us/Processor_TechDocs/25766.pdf AMD Socket 940 Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/31412.pdf AMD Functional Data Sheet, 940 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/30353.pdf AMD Socket 940 Qualification Plan]
* [http://support.amd.com/us/Processor_TechDocs/31700.pdf Socket F (1207) Design Specification]
** [http://support.amd.com/us/Processor_TechDocs/32800.pdf Thermal Design Guide for Socket F (1207) Processors]
* [http://support.amd.com/us/Processor_TechDocs/31875.pdf Socket AM2 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/40523.pdf Socket AM3 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31839.pdf Low-Profile Socket S1 Design Specification]
* [http://support.amd.com/us/Processor_TechDocs/31410.pdf AMD Functional Data Sheet, 754 Pin Package]
** [http://support.amd.com/us/Processor_TechDocs/24850.PDF Socket 754 Design and Qualification Requirements]
* [http://support.amd.com/us/Processor_TechDocs/31411.pdf AMD Functional Data Sheet, 939-Pin Package]
* [http://support.amd.com/us/Processor_TechDocs/23986.pdf Socket A AMD Processor and Heatsink Installation Guide]

=== Misc ===

* [http://support.amd.com/us/Processor_TechDocs/20734.pdf AMD Processor Recognition Application Note]
* [http://support.amd.com/us/Processor_TechDocs/22466.pdf AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets Manual]
* [http://support.amd.com/us/Processor_TechDocs/21928.pdf 3DNow!™Technology Manual]
** [http://support.amd.com/us/Processor_TechDocs/22621.pdf 3DNow!™ Instruction Porting Guide Application Note]
* [http://support.amd.com/us/Processor_TechDocs/23794.pdf AMD Thermal, Mechanical, and Chassis Cooling Design Guide]
* [http://support.amd.com/us/Processor_TechDocs/30579_3_74.pdf AMD Processor Performance Evaluation Guide]
* [http://support.amd.com/us/Processor_TechDocs/32035.pdf Compiler Usage Guidelines for AMD64 Platforms Application Note]
* [http://support.amd.com/us/Processor_TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors]
* [http://support.amd.com/us/Processor_TechDocs/26951.pdf Thermal Interface Material Comparison: Thermal Pads vs. Thermal Grease]
* [http://support.amd.com/us/Processor_TechDocs/26003.pdf Builders Guide for Desktop/Tower Systems]
* [http://support.amd.com/us/Processor_TechDocs/26698.pdf Linux Kernel Issue with Systems Using AGP Graphics]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/30887.pdf Building AMD64 Applications with the Microsoft Platform SDK]
* [http://support.amd.com/us/Processor_TechDocs/30888.pdf Creating an AMD64 Build Enviroment for DirectX-Based Applations]
* [http://support.amd.com/us/Processor_TechDocs/33609.pdf Processor Utilization with Microsoft® Windows® Media Center Edition on Systems Enabled with Cool'n'Quiet™ and AMD PowerNow™ Technologies]
* [http://support.amd.com/us/Processor_TechDocs/32979.pdf Microsoft® Windows® XP and Windows® Server 2003 Processor Speed Reporting]
* [http://support.amd.com/us/Processor_TechDocs/tn17.pdf Microsoft Windows® 2000 Patch for AGP Applications on AMD Athlon™ and AMD Duron™ Processors]

== Intel ==

=== Intel Pentium III ===

* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii Highlights/Overview]
* [http://ark.intel.com/ProductCollection.aspx?familyID=590&MarketSegment=DT List of Pentium III models, steppings, etc.]
* [http://www.intel.com/support/processors/pentiumiii/sb/CS-023730.htm Intel® Pentium® III Processor: Datasheets]
** [http://download.intel.com/support/processors/pentiumiii/sb/24965705.pdf Intel® Pentium® III Processor with 512-KB L2 Cache at 1.13GHz to 1.40 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24976503.pdf Intel® Pentium® III Processor Based on 0.13 Micron Process Up to 1.33 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24526408.pdf Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/24445209.pdf Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet] (PDF)
** [http://download.intel.com/support/processors/pentiumiii/sb/27367306.pdf Low Voltage Intel® Pentium® III Processor 512-KB] (PDF)
* [http://www.intel.com/design/intarch/specupdt/244453.htm Intel® Pentium® III Processor Specification Update] ([http://download.intel.com/design/intarch/specupdt/24445358.pdf PDF])

Mobile:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-m Highlights/Overview]
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023739.htm Mobile Intel® Pentium® III Processor - M Datasheet] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/29834006.pdf PDF])
* [http://www.intel.com/support/processors/mobile/pentiumiii/sb/CS-023740.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/support/processors/mobile/pentiumiii/sb/24530659.pdf PDF])
* [http://www.intel.com/design/intarch/specupdt/245306.htm Mobile Intel® Pentium® III Processor and Mobile Intel® Pentium® III Processor-M Specification Update] ([http://download.intel.com/design/intarch/specupdt/24530663.pdf PDF])
* [http://developer.intel.com/design/mobile/datashts/245302.htm Mobile Pentium® III Processor in BGA2 and Micro-PGA2 Packages] ([http://download.intel.com/design/mobile/datashts/24530202.pdf PDF])

Embedded:
* [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii.htm Embedded Intel® Architecture Processors: Intel® Pentium® III Processors: Technical Documents]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_pga370.htm Intel® Pentium® III Processor - PGA370]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_low.htm Intel® Pentium® III Processor - Low Power]
** [http://www.intel.com/design/intarch/pentiumiii/docs_pentiumiii_vol.htm Low Voltage Intel® Pentium® III Processor]

Xeon:
* [http://www.intel.com/p/en_US/support/highlights/processors/pentiumiii-xeon Highlights/Overview]

== VIA ==

=== VIA Padlock ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=281 Security Application note]
* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 PadLock Programming Guide]

= Northbridge =

== AMD ==

=== AMD RS880 ===

* [http://support.amd.com/us/Embedded_TechDocs/46143_rs880_BDG_pub_3.00.pdf AMD RS880 Family BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46141_rs880_rpr_pub_3.00.pdf AMD RS880 Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/46142_rs880_rrg_pub_3.00.pdf AMD RS880 Family Register Reference Guide] (RRG)

=== AMD RD890 ===

Not public (yet?). However, some of the information may be contained in the public docs in the RS880 section.

* AMD RD890 BIOS Developer's Guide (Publication #43606)
* AMD RD890 Register Reference Guide (Publication #43607)

=== AMD RS780 ===

* [http://support.amd.com/us/Embedded_TechDocs/43734_rs780_bdg_pub_1.01.pdf AMD 780G Family BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf AMD 780G Family Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/43451_rs780_rrg_pub_1.01.pdf AMD 780G Family Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/45732_rs780e_ds_pub_3.10.pdf AMD 780E Databook]
* [http://support.amd.com/us/Embedded_TechDocs/48319.pdf AMD 780 Product Errata]

Apparently there are other docs as well, not sure if they provide any additional information or if they are part of the public documents above:

* AMD RD780 Register Reference Guide
* AMD RX780 Register Reference Guide
* AMD RS780M Hybrid Graphics – System BIOS Detailed Design Document (Publication #44969)
* AMD RD790 Register Programming Requirements (Publication #42462)
* AMD RD790 Register Reference Guide (Publication #42988)
* AMD RD790 BIOS Developer's Guide (Publication #43093)

=== AMD RS690 ===

* [http://support.amd.com/us/Embedded_TechDocs/43372_rs690_rrg_3.00o.pdf AMD RS690 Register Reference Guide] (RRG)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41977_rs690_ds_3.06.pdf AMD 690G Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/41978_rs690m_ds_3.06.pdf AMD M690 Databook (Notebook Solutions)]
* [http://support.amd.com/us/Embedded_TechDocs/42437_m690t_ds_3_08.pdf AMD M690T/M690E Databook]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD690Series_LogoGuide.pdf AMD 690 Chipset Logos]

=== Misc ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMD_7-Series_Chipsets_-_Guidelines.pdf AMD 7-Series Chipsets - Guidelines.pdf]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD Model S1 DBM690T, Socket S1 and M690T/SB600 Chipset Development Board]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/AMDCrossFire_LogoGuide.pdf AMD 480X Chipset Logos]

== Intel ==

=== Intel NM10 Express ===

* [http://www.intel.com/Products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm Overview]
** [http://www.intel.com/Assets/PDF/datasheet/322896.pdf Intel® NM10 Express Chipset Datasheet]
** [http://www.intel.com/Assets/PDF/specupdate/322897.pdf Intel® NM10 Express Chipset Specification Update]

=== Intel 860 ===

* [http://www.intel.com/design/archives/chipsets/860/index.htm Hardware Design: Archives - Intel® 860 Chipset Family Technical Documentation]
** [http://www.intel.com/design/chipsets/datashts/290713.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Datasheet]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
*** [http://www.intel.com/design/chipsets/specupdt/290715.htm Intel® 860 Chipset: 82860 Memory Controller Hub (MCH) Specification Update]: [http://www.intel.com/design/chipsets/specupdt/29071501.pdf PDF]
** [http://www.intel.com/design/chipsets/applnots/292269.htm Intel® 860 Chipset Thermal Considerations Application Note (AP-721)]: [http://download.intel.com/design/chipsets/datashts/29071301.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298252.htm Intel® Xeon® Processor and Intel® 860 Chipset Platform Design Guide]: [http://download.intel.com/design/chipsets/designex/29825204.pdf PDF]
** [http://www.intel.com/design/chipsets/designex/298302.htm Intel® 860 Chipset Memory Expansion Card (MEC) Design Guide]: [http://download.intel.com/design/chipsets/designex/29830201.pdf PDF]
** [http://www.intel.com/design/chipsets/schematics/860_crb.htm Intel 860 Chipset CRB Schematics]: [http://download.intel.com/design/chipsets/schematics/860_crb.pdf PDF]

=== Intel 82815E ===

* [http://download.intel.com/design/chipsets/datashts/29068801.pdf 82815 Chipset Family]
* [http://download.intel.com/design/chipsets/designex/29823401.pdf 82815E Chipset Platform Design Guide]
* [http://download.intel.com/design/chipsets/designex/29824906.pdf 82815E Chipset Platform Design Guide update]

=== Intel 440BX ===

* [http://download.intel.com/design/chipsets/datashts/29063301.pdf Datasheet]
* [http://download.intel.com/design/chipsets/datashts/27321903.pdf Electrical and Thermal Timing Specification]

=== Intel 440LX ===

* [http://download.intel.com/design/chipsets/datashts/29056402.pdf Datasheet]
* [http://www.intel.com/design/chipsets/specupdt/29765505.pdf Spec update]

== VIA ==

VIA has a [http://linux.via.com.tw portal] with some source code and datasheets.

=== VIA VX800 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241 VIA VX800 Programming Manual]

=== VIA CX700M/VX700 ===

* [http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 VIA CX700M/VX700 Programming Manual]

= Southbridge =

== AMD ==

=== AMD SB820M ===

* [http://support.amd.com/us/Embedded_TechDocs/47283_sb820m_ds_pub_2.00.pdf AMD SB820M Southbridge Databook]

=== AMD SB800 ===

Not available yet, but here are the numbers for the documents we'd like to get. I found these numbers with a creative Internet search.

* AMD SB800 Databook (Publication #44758)

=== AMD SB700/SB710/SB750 ===

* [http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf AMD SB700/710/750 BIOS Developer’s Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/43009_sb7xx_rrg_pub_1.00.pdf AMD SB700/710/750 Register Reference Guide] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/42413_sb7xx_rpr_pub_1.00.pdf AMD SB700/710/750 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/Embedded_TechDocs/45215_sb710_ds_pub_1.25.pdf AMD SB710 Databook]
* [http://support.amd.com/us/Embedded_TechDocs/46837.pdf AMD SB700 Family Product Errata]

=== AMD SB600 ===

* [http://support.amd.com/us/Embedded_TechDocs/46157_sb600_bdg_pub.3.00.pdf AMD SB600 BIOS Developer's Guide] (BDG)
* [http://support.amd.com/us/Embedded_TechDocs/46155_sb600_rrg_pub_3.03.pdf AMD SB600 Register Reference Manual] (RRG)
* [http://support.amd.com/us/Embedded_TechDocs/46156_sb600_rpr_pub_3.02b.pdf AMD SB600 Register Programming Requirements] (RPR)
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42119_sb600_ds_3.05.pdf AMD SB600 Databook] (rev. 3.05)
* [http://support.amd.com/us/Embedded_TechDocs/42119_sb600_ds_pub_3.07.pdf AMD SB600 Databook] (rev. 3.07)

=== AMD 8111 ===

* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/24674.pdf AMD-8111™ HyperTransport™ I/O Hub Data Sheet]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/26036.pdf AMD-8111™ HyperTransport™ I/O Hub Product Brief]
* [http://support.amd.com/us/ChipsetMotherboard_TechDocs/25720.pdf AMD-8111™ HyperTransport™ I/O Hub Revision Guide]

== Intel ==

=== Intel 82801BA/BAM (ICH2) ===

* [http://developer.intel.com/design/chipsets/datashts/290687.htm Datasheet]

= Super I/O =

== ITE ==

* [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 PC Desktop/Notebook Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 Desktop Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=6 Notebook Super I/Os]

== Winbond / Nuvoton ==

* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/ISASuperIO/ ISA Super I/Os]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/LPCSuperIOforDesktopAndServer/ LPC Super I/O for Desktop & Server]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforDesktop/ Advanced Super I/O for Desktop]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforNotebook/ Advanced Super I/O for Notebook]

== Fintek ==

* [http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17&layer=0 Super Hardware Monitor + SIO]

== NSC ==

(bought by Winbond, now Nuvoton)

== ALi ==

== SMSC ==

* [http://www.smsc.com/main/catalog/ioprods.html Products / datasheets overview]
* [http://www.smsc.com/main/datasheet.html Various product datasheets]

= Other =

== ACPI ==

* http://www.acpi.info

== USB ==

== Misc ==

* [http://support.amd.com/us/Pages/techdocs.aspx AMD public documents]
** The [http://www.amd.com/us/products/embedded/develop-and-design/Pages/processor-chipset-linux-supprt.aspx AMD64 Embedded Processors and Chipset Linux Support] web page features links to supported projects (like coreboot) and links to documentation.

= Resources =

There are many datasheet archives on the web which may have other (usually older) datasheets which already disappeared from vendor websites.

Flag Days

2010-12-17T20:29:42Z

Uwe:

This page collects sweeping changes on the tree that might have an impact on boards that weren't tested by the developer, or on uncommitted development. It's sorted by revision (and thus date) and provides a Changelog to anyone who needs to update older trees.

To prevent inaccuracies, changes prior to the creation of this page aren't logged. The head revision at the time of creation of this page was r5151.

== r5152: Change in PS/2 keyboard API ==

'''Applicable if:''' local changes/additions to Super I/Os.

The [http://www.coreboot.org/pipermail/coreboot/2010-February/056012.html name and function prototype of the PS/2 keyboard initialization function changed]:

-void init_pc_keyboard('''unsigned port0, unsigned port1''', struct pc_keyboard *kbd);
+void pc_keyboard_init(struct pc_keyboard *keyboard);

This dismisses the first two arguments (which had to be the constant values 0x60, 0x64 before). This should only have an impact on locally developed Super I/O code that might require to follow this change. The changes required for porting old code are usually of the form:

-init_pc_keyboard('''0x60, 0x64''', 0);
+pc_keyboard_init(0);

or

-init_pc_keyboard('''res0->base, res1->base''', &conf->keyboard);
+pc_keyboard_init(&conf->keyboard);

== r5162: Move crt0s away from user servicable parts in the build system ==

'''Applicable if:''' local changes/additions to mainboards.

The crt0s variable in the buildsystem, which collects the various parts that are combined to crt0.o, is [http://www.coreboot.org/pipermail/coreboot/2010-February/056062.html setup generically] now.

This change must be replicated with local mainboard changes/additions. It should be enough to simply '''remove all crt0s entries''' from <code>src/mainboard/$(MAINBOARDDIR)/Makefile.inc</code>.

If you want to check the behaviour:
* apply the Makefile patch (which adds the printcrt0s rule) to your tree
* run "make printcrt0s", note the result
* apply the entire patch
* run "make printcrt0s", and compare the results

== r5164: Move ldscripts away from user servicable parts in the build system ==

'''Applicable if:''' local changes/additions to mainboards

The ldscripts variable in the buildsystem, which collects the various parts of the linker script used to link coreboot, is [http://www.coreboot.org/pipermail/coreboot/2010-February/056089.html setup generically] now.

This change must be replicated with local mainboard changes/additions. It should be enough to simply '''remove all ldscripts entries''' from <code>src/mainboard/$(MAINBOARDDIR)/Makefile.inc</code>.

== r5167: Reorganize i82801 southbridge drivers ==

'''Applicable if:''' your mainboard uses the i82801xx, i82801dbm, i82801ca or i82801er driver (Intel ICH).

The drivers have been unified and split up.

* If your mainboard has an ICH0 or ICH (ie. i810 based boards) use the i82801ax driver
* If your mainboard has an ICH2 driver (ie. i815 based boards) use the i82801bx driver
* If your mainboard used the i82801ca driver before use the i82801cx driver
* If your mainboard used the i82801dbm driver before use the i82801dx driver
* If your mainboard used the i82801er driver before use the i82801ex driver

== r5168: Move generic build rules away from user servicable parts in the build system ==

'''Applicable if:''' local changes/additions to mainboards.

Various rules of object files that exist for every board, or that exist for every board with a given configuration option, are [http://www.coreboot.org/pipermail/coreboot/2010-February/056089.html moved to] <code>src/arch/i386/Makefile.inc</code>.

If your mainboard uses a custom <code>reset.c</code> file, which provides a <code>hard_reset()</code> function, you must add <code>select BOARD_HAS_HARD_RESET</code> to your board's Kconfig.

The following change only needs to be replicated with newly created local mainboards. It should be enough to '''remove the following lines''' from <code>src/mainboard/$(MAINBOARDDIR)/Makefile.inc</code>:
* initobj-y += crt0.o
* obj-y += mainboard.o
* obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
* obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
* obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o

Also, <code>include some_path/Makefile.romccboard.inc</code> must be dropped, as this file was removed. A statement to set <code>ROMCCFLAGS</code> must be kept. If your mainboard's Makefile is empty after these changes, or only contains comments, you can remove it completely.

== r5171: Move generic build rules away from user servicable parts in the build system ==

'''Applicable if:''' local changes/additions to mainboards

Various rules of object files that exist for every board, or that exist for every board with a given configuration option, are [http://www.coreboot.org/pipermail/coreboot/2010-February/056154.html moved to] <code>src/arch/i386/Makefile.inc</code>.

If your mainboard uses a custom <code>fadt.c</code> file, you must add <code>select BOARD_HAS_FADT</code> to your board's Kconfig. Better yet, the FADTs related to that chipset should be consolidated (probably in the southbridge)

If your mainboard uses a custom <code>get_bus_conf.c</code> file, you must add <code>select HAVE_BUS_CONFIG</code> to your board's Kconfig.

The following change only needs to be replicated with newly created local mainboards. It should be enough to '''remove the following lines''' from <code>src/mainboard/$(MAINBOARDDIR)/Makefile.inc</code>:
* obj-y += get_bus_conf.o
* obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
* obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
* obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o

Also, <code>include some_path/Makefile.k8_CAR.inc</code> or <code>include some_path/Makefile.k8_ck804.inc</code> must be dropped, as these files were removed. If your mainboard's Makefile is empty after these changes, or only contains comments, you can remove it completely.

== r5176: Automate SSDT pull-in ==

'''Applicable if:''' using <code>ssdtX.asl</code> files and <code>ACPI_SSDTX_NUM</code> config variable.

<code>ACPI_SSDTX_NUM</code> must be 4 or 5 (the only values found in the tree so far, but this could be extended), and means the highest number in <code>ssdtX.asl</code> in the mainboard tree (numbering starts at 2). <code>ssdt[2..X].asl</code> are automatically pulled in by the build system then. To adapt, please check that <code>ACPI_SSDTX_NUM</code> is 4 or 5, then remove the SSDT related rules in the mainboard's <code>Makefile</code>.

If <code>ACPI_SSDTX_NUM</code> should be some other value, please report to the list, so we can adapt the build system for your case.

== r5259: Remove config variables related to newconfig ==

'''Applicable if:''' local additions to mainboards (and CPUs in some cases).

Uses of <code>HAVE_FAILOVER_BOOT</code>, <code>HAVE_FALLBACK_BOOT</code>, <code>USE_FAILOVER_IMAGE</code>, <code>USE_FALLBACK_IMAGE</code> must be removed as they were dropped from the build system and might lead to wrong behaviour.

To do this, keep the code wrapped in #if statements which evaluate to true, and remove code that the preprocessor would have left out.

== r5266: Replace printk_*(...) by printk(BIOS_*, ...) ==

'''Applicable if:''' local additions.

<code>printk_*</code> calls are replaced by <code>printk(BIOS_*, ...)</code>.

To adapt, you can use something like this (thanks go to Zheng Bao for this command):

sed -i 's/printk_$[a-z]*$(/printk(BIOS_\U\1\E, /g' *.c

== r5311: unify quadcore.h and dualcore.h to multicore.h ==

'''Applicable if:''' local additions to mainboards.

#include <cpu/amd/dualcore.h>

and

#include <cpu/amd/quadcore.h>

have been replaced by

#include <cpu/amd/multicore.h>

The files were often included in <code>get_bus_conf.c</code> and <code>mptable.c</code>.

== r5313: drop LB_CKS_* from Kconfig ==

'''Applicable if:''' local additions to mainboards.

CMOS option handling does no longer keep information on where the coreboot checksums are stored twice.

<code>LB_CKS_RANGE_START</code>, <code>LB_CKS_RANGE_END</code> and <code>LB_CKS_LOC</code> should no longer be defined in Kconfig anymore. <code>build_opt_tbl</code> will do the job automatically.

In C code, all variants of <code>CONFIG_LB_CKS_*</code> are now called <code>LB_CKS_*</code> again as they're no longer config variables.

In addition, there is a new requirement for <code>cmos.layout</code> files now: There has to be a checksum description:

# -----------------------------------------------------------------
checksums

checksum 392 983 984

== r5341: arch/i386/lib/console.c dropped ==

'''Applicable if:''' local additions.

If your (<code>romstage.c</code>) code included <code>arch/i386/lib/console.c</code> until now, it should include <code>console/console.c</code> instead.

== r5511: asm.h dropped. ==

The #define <code>ASSEMBLY</code> is now passed by the Makefile for assembler files. The <code>asm.h</code> construct is no longer needed. Just drop <code>asm.h</code> includes from your code. If you use the <code>post_code()</code> macro, you can now include <code><cpu/x86/post_code.h></code>.

== r5525: devicetree.cb: APIC rename ==

'''Applicable if:''' local additions to mainboards.

In <code>devicetree.cb</code> rename "apic" to "lapic" and "apic_cluster" to "lapic_cluster".

== r5528: Remove C-includes from romstages ==

'''Applicable if:''' local additions to mainboards.

Replace any <code>console/console.c</code> #include in <code>romstage.c</code> with <code>console/console.h</code>. For CAR-boards, also remove the <code>pc80/serial.c</code> #include.

== r5538: Remove C-includes from romstage ==

'''Applicable if:''' local additions to mainboards.

Remove <code>pc80/serial.c</code> #include in <code>romstage.c</code> on ROMCC-boards, too.

== r5548: Remove C-includes from romstages ==

'''Applicable if:''' local additions to mainboards based on Fam10h.

Remove <code>northbridge/amd/amdht/ht_wrapper.c</code>, <code>northbridge/amd/amdfam10/raminit_amdmct.c</code>, <code>cpu/amd/model_10xxx/fidvid.c</code>, <code>pc80/mc146818rtc_early.c</code> from your mainboard's <code>romstage.c</code>.

== r5647: Build mptable entries for buses from device tree ==

'''Applicable if:''' Board not adapted yet.

r5647 adds a new function <code>mptable_write_buses</code>, which acts as a replacement for all <code>smp_write_bus</code> calls in boards' mptable.c. So far, only <code>kontron/986lcd-m</code> uses it, but all boards should do so in future.

Most boards do the following for the bus entries in mptable:
* Determine the highest PCI bus ID (either hardcoded or by reading out some known device).
* Register PCI buses numbered 0 to highest.
* Register ISA bus numbered highest+1.

Alternatively, some boards simply hardcode a number of calls to register each bus.

Identify that code and replace it with something like:
<code>mptable_write_buses(mc, &max_pci_bus, &isa_bus);</code>
where <code>mc</code> is the <code>struct mp_config_table *</code> used in your <code>mptable.c</code>. The variables <code>max_pci_bus</code> and <code>isa_bus</code> (sometimes called <code>bus_isa</code>) are set to the respective values by <code>mptable_write_buses</code>. If you don't need those variables in your board's <code>smp_write_config_table</code> function pass <code>NULL</code> instead.

== r5682: Drop USE_PRINTK_IN_CAR, USE_INIT ==

'''Applicable if:''' local additions to mainboards.

Drop <code>USE_PRINTK_IN_CAR</code> in your board's </code>Kconfig</code> file, if it exists. Its functionality is automatically enabled if CAR is enabled. Drop <code>USE_INIT</code>. This wasn't used, so dropping it doesn't change any behavior.

== r5745: Drop HAVE_HIGH_TABLES, HAVE_LOW_TABLES, FALLBACK_SIZE ==

'''Applicable if:''' local additions to mainboards.

These config options have no effect anymore, so simply drop them.

== r5754: Rework mainboard handling in Kconfig ==

'''Applicable if:''' local additions to mainboards.

<code>src/mainboard/*/*/Kconfig</code> got seriously reworked. Basically, list your board in the applicable <code>src/mainboard/*/Kconfig</code> file, rename the BOARD_vendor_boardname option to <code>BOARD_SPECIFIC_OPTIONS</code> (or somesuch, it's a dummy), and mark its type as "def_bool y". Then guard the entire <code>Kconfig</code> file of your mainboard with "if BOARD_vendor_boardname" .... "endif".

See other mainboards for examples.

== r5756: Rename USE_DCACHE_RAM to CACHE_AS_RAM ==

'''Applicable if:''' local additions to mainboards.

Rename <code>USE_DCACHE_RAM</code> to <code>CACHE_AS_RAM</code> in your board's <code>Kconfig</code> (if applicable).

== r5779: Use standard RAMBASE on Geode LX ==

'''Applicable if:''' new Geode LX based boards in tree.

Drop the <code>RAMBASE</code> config setting it to 0x4000, so coreboot uses the default of 1MB. Eventually, <code>RAMBASE</code> will be dropped completely.

== r5781: Drop SB600/SB700 configuration flags ==

'''Applicable if:''' new SB600/SB700 boards in tree.

Drop <code>ide0_enable</code>, <code>sata0_enable</code>, and <code>hda_viddid</code> from your board's <code>devicetree.cb</code>.

== r5787: HEADS UP: TSC based timer might fail ==

'''Applicable if:''' board uses TSC based timer, and PIT2 is unusable.

r5787 changes the default time source for calibrating the TSC based routines from I/O port accesses to PIT2, to increase boot speed. Should r5787 fail on your system, and <code>UDELAY_TSC</code> is enabled, you can try to add <code>select TSC_CALIBRATE_WITH_IO</code> to your board's <code>Kconfig</code>. If that fixes your board, please report to coreboot@coreboot.org.

== r5791+r5792: HEADS UP: Fix slow decompression on AMD Fam10 based boards ==

'''Applicable if:''' board uses Fam10.

Many users of Fam10 based boards disabled compression of the ramstage to massively improve boot time. Following r5792, this should not be necessary anymore.

== r5800: Move DIMM_SUPPORT out of the sockets ==

'''Applicable if:''' new local K8/Fam10 based board.

r5800 moves the memory type determination out of the sockets as it has been shown that a single CPU socket can be used for multiple memory types. Now, boards have to define the RAM they accept in Kconfig.

To get the older behaviour back, here's a list of sockets and what must be '''select'''ed in the boards to get the same configuration:
* socket_AM2: <code>DIMM_DDR2</code>
* socket_AM3: <code>DIMM_DDR3, DIMM_REGISTERED</code>
* socket_AM2r2: <code>DIMM_DDR2, DIMM_REGISTERED</code>
* socket_F: <code>DIMM_DDR2, DIMM_REGISTERED</code>
* socket_ASB2: <code>DIMM_DDR3, DIMM_REGISTERED</code>
* socket_F_1207: <code>DIMM_DDR2, DIMM_REGISTERED</code>

== r5803: Remove kludge for reserved resources on i945 ==

'''Applicable if:''' new local i945 based board.

Before r5803, some northbridge specific resources had to be added with a board specific handler. This is not necessary in r5803+.
Remove the call to <code>add_northbridge_resources()</code> in <code>add_mainboard_resources()</code>.
If this was the only action in <code>add_mainboard_resources()</code>, you can remove the function altogether '''and''' remove <code>HAVE_MAINBOARD_RESOURCES</code> in your board's <code>Kconfig</code>.

== r5825: New method for specifying SATA phys values on AMD SB700 ==

'''Applicable if:''' new local SB700 based board.

r5825 introduces a new API on SB700 to specify SATA phys values. The SB700 code defines some default values in <code>src/southbridge/amd/sb700/sb700_sata.c:sb700_setup_sata_phys()</code>. As this function is declared "weak", you can define your own function of the same name in your board's <code>mainboard.c</code> that writes the correct values for your board. See <code>src/mainboard/asrock/939a785gmh/mainboard.c</code> as an example.

== r5841: HEADSUP: Building romstage with global variables will fail ==

'''Applicable if:''' local changes.

Starting r5841 we let the build break if global variables are found in the romstage. As they're assigned addresses in ROM space, writing them would fail. To prevent such unobvious errors, we detect that condition and the build fails with the error message "'''Do not use global variables in romstage'''". It doesn't look if those are written to, so it might fail on code that would work (and it did).

To find the global variable, use <code>objdump -x</code> on your object files (for romstage, they're usually suffixed with <code>.initobj.o</code>) to find which has a <code>.bss</code> or <code>.data</code> section with content (more than 0 bytes). The symbol table printed by <code>objdump -x</code> also tells you what the variable is called.

== r5886: Change buildsystem to require source file names instead of object files ==

'''Applicable if:''' local changes or additions to the build system (particularily Makefile.inc).

Various build system variables are renamed, and their use has changed too:
* initobjs-y is now romstage-y
* objs-y is now ramstage-y
* driver-y keeps the name but changes meaning
* smmobj-y is now smm-y
All of these variables must be filled with ''source'' filenames, not ''object'' filenames as it used to be.
For most scenarios, it will be sufficient to change (for example) <code>initobjs-y += foo.o</code> in <code>romstage-y += foo.c</code>.

== r5891: Move configuration values from romstage.c to Kconfig ==

'''Applicable if:''' local changes or additions to i945 based boards.

Values were moved to Kconfig to have them available in all compilation units, not just <code>romstage.c</code>. In particular:
* <code>CHIPSET_I945GM</code> -> <code>CONFIG_I945GM</code>
* <code>CHIPSET_I945GC</code> -> <code>CONFIG_I945GC</code>
* <code>CHANNEL_XOR_RANDOMIZATION</code>, <code>OVERRIDE_CLOCK_DISABLE</code>, <code>MAXIMUM_SUPPORTED_FREQUENCY</code> -> <code>CONFIG_*</code>

If your changes or additions use them, you'll have to adapt your changes. If you define the old variants in a <code>romstage.c</code>, you'll have to move them to <code>Kconfig</code>. See <code>kontron/986lcd-m</code> as a model.

== r5893: Split I945 northbridge to I945GC and I945GM ==

'''Applicable if:''' local changes or additions to i945 based boards.

To simplify configuration, we now support two northbridges, i945GC and i945GM in the Kconfig system, instead of i945 with the GM or GC modifiers as separate attribute. The code is still shared as it's mostly the same.

To adapt boards, change <code>NORTHBRIDGE_INTEL_I945</code> in <code>Kconfig</code> to <code>NORTHBRIDGE_INTEL_I945GC</code> or <code>NORTHBRIDGE_INTEL_I945GM</code> as appropriate and remove the I945GC or I945GM attribute (introduced in r5891).

== r5898: Rename CACHE_AS_RAM_ADDRESS_DEBUG to CONFIG_DEBUG_CAR ==

'''Applicable if:''' local changes or additions to AMD based boards.

If you set <code>CACHE_AS_RAM_ADDRESS_DEBUG</code> in your <code>romstage.c</code> to get verbose output in CAR setup, you now have to select <code>DEBUG_CAR</code> in <code>Kconfig</code> instead.

== r5910: Move out .c includes from i945 (and some other boards) ==

'''Applicable if:''' local changes or additions to CAR boards.

Instead of including sources in <code>romstage.c</code>, they're now compiled as separate units. r5910 does this for i945 based boards and on all CAR boards for <code>src/lib/ramtest.c</code>.
To adapt, remove the corresponding includes from your <code>romstage.c</code>. You might have to include header files instead, as replacement to <code>ramtest.c</code> <code>lib.h</code> is a likely candidate.

== r5911: Move out usbdebug .c includes from CAR boards ==

'''Applicable if:''' local changes or additions to CAR boards.

If your board supports the USB debug port, you will have to remove the related source include statements (two: one for the chipset, one for the generic code) and include <code>usbdebug.h</code> instead.

== r6149/r6150: Drop duplicate prefixing from component filenames ==

'''Applicable if:''' adding any new components.

coreboot used to call its filenames <code>src/southbridge/intel/i82801gx/i82801gx_lpc.c</code>. This convention has been dropped and the component name is not supposed to be part of the file name anymore, as it is sufficiently described by the location of the file. Please drop the component prefix from filenames for all new components.

== r6161: Rename src/arch/i386 to src/arch/x86 ==

'''Applicable if:''' you have local changes in <code>src/arch/i386</code>.

If you have local changes in <code>src/arch/i386</code>, please make sure to apply them to <code>src/arch/x86</code> instead.

Supported Chipsets and Devices

2010-12-16T22:02:10Z

Uwe: /* Devices supported in coreboot v1 */

'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.
* In general it is '''not''' recommended to use coreboot v3 — this was an experimental development tree which is gradually being merged into v4.
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. However, it is definately desirable to port boards from v1 to v4 whereever possible.

See also [[Supported Motherboards]].

== Devices supported in coreboot v4 ==

{| border="0" valign="top"
| valign="top"|

'''Northbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Northbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Fam10h
| style="background:lime" | OK16
|- bgcolor="#eeeeee" valign="top"
| AMD
| K8
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| GX1
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| GX (GX2)
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| LX
| style="background: lime" | OK

|- bgcolor="#dddddd" valign="top"
| Intel®
| E7501
| style="background:#eeeeee" | ?
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7520
| style="background:#eeeeee" | ?
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7525
| style="background:#eeeeee" | ?
|- bgcolor="#dddddd" valign="top"
| Intel®
| 3100
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82443BX (440BX)
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82810
| style="background:yellow" | WIP9
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82830
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82855
| style="background:yellow" | WIP
|- bgcolor="#dddddd" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Intel®
| 945
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| SiS
| SiS761GX
| style="background:lime" | OK

|- bgcolor="#dddddd" valign="top"
| VIA
| VT8601 (PLE133)
| style="background:yellow" | WIP
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8623 (CLE266)
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| K8T890
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| K8M890
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| CN400
| ?
|- bgcolor="#dddddd" valign="top"
| VIA
| CN700
| style="background:lime" | OK14
|- bgcolor="#dddddd" valign="top"
| VIA
| CX700
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| VX800
| style="background:yellow" | WIP

|}

| valign="top"|

'''Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8111
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8131
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8132
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8151
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5530/CS5530A
| style="background:yellow" | WIP
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5535
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5536
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| RS690
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB600
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| RS780/RS785?
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB700/SB7x0
| style="background: lime " | OK

|- bgcolor="#dddddd" valign="top"
| Broadcom
| BCM21000
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Broadcom
| BCM5780
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Broadcom
| BCM5785
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| Intel®
| 6300ESB (ESB6300)
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 3100
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82371EB (PIIX4E)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801AA/AB (ICH/ICH0)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801BA/BAM (ICH2/ICH2-M)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801CA/CAM (ICH3-S/ICH3-M)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801EB/ER (ICH5/ICH5R)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801GX (ICH7)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82870
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| PXHD
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background:lime" | OK

|- bgcolor="#dddddd" valign="top"
| NVIDIA
| CK804
| style="background:lime" | OK17
|- bgcolor="#dddddd" valign="top"
| NVIDIA
| MCP55
| style="background:lime" | OK17

|- bgcolor="#eeeeee" valign="top"
| Ricoh
| RL5C476
| style="background:#eeeeee" | ?

|- bgcolor="#dddddd" valign="top"
| SiS
| SiS966(L)
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8231
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8235
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8237R
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8237A
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8237S
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT82C686
| style="background:yellow" | WIP

|}

| valign="top"|

'''Super I/Os'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| ASUS
| A8000
| style="background:lime" | OK12, 13

|- bgcolor="#dddddd" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Fintek
| F71859
| style="background:yellow" | OK19
|- bgcolor="#dddddd" valign="top"
| Fintek
| F71863F/FG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Fintek
| F71872F/FG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Fintek
| F71889
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8661F
| style="background:yellow" | OK5
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8671F
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8673F
| style="background:yellow" | OK5
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8705F
| style="background:yellow" | OK5
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8712F
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F
| style="background:yellow" | OK5

|- bgcolor="#dddddd" valign="top"
| Intel®
| 3100
| style="background:lime" | OK15
|- bgcolor="#dddddd" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background:lime" | OK15

|- bgcolor="#eeeeee" valign="top"
| NSC
| PC8374
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87309
| style="background:yellow" | OK5
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87351
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87360
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87366
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87417
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87427
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97307
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97317
| style="background:#eeeeee" | ?

|- bgcolor="#dddddd" valign="top"
| ServerEngines
| PILOT
| style="background:yellow" | OK18

|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37M70x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B80x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B78x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B72x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B81x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37M60x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47B27x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M10x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M112
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M13x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M15x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M192
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47B397
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| DME1737
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| SCH5307
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47N217
| style="background:#dddddd" | ?

|- bgcolor="#eeeeee" valign="top"
| VIA
| VT1211
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT82C686(A/B)
| style="background:yellow" | OK5

|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627DHG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627UHG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627EHG/HF/EHF/THF
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83697HF/HG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627THF/THG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83977F
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83977TF
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83977EF
| style="background:lime" | OK4
|}

| valign="top"|

'''CPUs'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Type
! align="left" | CPU
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| x86
| AMD
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| x86
| Intel®
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| x86
| VIA
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Emulated
| QEMU
| style="background:lime" | OK
|}

'''SOCs'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | SOC
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Elan SC520
| style="background: lime" | OK
|- bgcolor="#dddddd" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background: lime" | OK
|}

|}


4 The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least). 
5 Pre-RAM serial output works fine, but nothing else, yet. 
9 Works mostly, but currently there are some limitations as to which RAM DIMMs can be used. 
12 All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though. 
13 The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737. 
14 Working, but not widely tested, yet. Works with single DIMM DDR2. 
15 The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far. 
16 Barcelona B0-B3 supported. 
17 MCP55 and CK804 are supported, but no open documents are available from NVIDIA. 
18 Partially supported, but not all features implemented. 
19 Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet. 


== Devices supported in coreboot v3 ==

<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged into v4.</div>

{| border="0" valign="top"
| valign="top"|

'''Northbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Northbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Geode LX
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| Geode K8
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| Intel®
| 82443BX (440BX)
| style="background:orange" | WIP
|- bgcolor="#dddddd" valign="top"
| Intel®
| 945
| style="background:orange" | WIP

|- bgcolor="#eeeeee" valign="top"
| VIA
| CN700
| style="background:orange" | WIP

|}

| valign="top"|

'''Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD-8111
| style="background:yellow" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD-8132
| style="background:yellow" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD-8151
| style="background:yellow" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5536
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| RS690
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB600
| style="background: lime " | OK

|- bgcolor="#dddddd" valign="top"
| Intel®
| 82371EB (PIIX4E)
| style="background:orange" | WIP
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82801GX (ICH7)
| style="background:orange" | WIP

|- bgcolor="#eeeeee" valign="top"
| NVIDIA
| MCP55
| style="background:orange" | WIP1

|- bgcolor="#dddddd" valign="top"
| VIA
| VT8237R
| style="background:orange" | WIP

|}

| valign="top"|

'''Super I/Os'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| VIA
| VT1211
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627HF
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627THG
| style="background:lime" | OK

|}

| valign="top"|

'''CPUs'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Type
! align="left" | CPU
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Geode LX
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| K8
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| Generic
| i586
| style="background:orange" | WIP

|- bgcolor="#eeeeee" valign="top"
| Intel
| Core Duo / Core 2 Duo
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| VIA
| C7
| style="background:orange" | WIP

|}

|}


1 MCP55 and CK804 are supported, but no open documents are available from NVIDIA.


== Devices supported in coreboot v1 ==

Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].

{| border="0" valign="top"
| valign="top"|

'''Northbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Northbridge
! align="left" | Status
! align="left" | v4?

|- bgcolor="#eeeeee" valign="top"
| Acer
| M1631
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Alpha
| Tsunami
| style="background:#dddddd" | ?
| style="background:#dddddd" | —3
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD76x
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 430TX
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 440BX
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| Intel®
| 440GX
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82815EP
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82830
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82860
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7500
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7501
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7505
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Micron
| 21PAD
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Motorola
| MPC107
| style="background:#dddddd" | ?
| style="background:#dddddd" | —3
|- bgcolor="#eeeeee" valign="top"
| NSC/AMD
| GX1
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| VIA
| VT694
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8601
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8623
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|}

| valign="top"|

'''Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status
! align="left" | v4?

|- bgcolor="#eeeeee" valign="top"
| Acer
| M1535
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Acer
| M1543
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| AMD
| AMD766
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| AMD
| AMD768
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801CA
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801DB
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82870
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| PIIX4E
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| NSC/AMD
| CS5530
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| NSC
| SCX200
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8231
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8235
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT82C686
| style="background:#eeeeee" | ?
| style="background:yellow" | WIP2
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83C553
| style="background:#dddddd" | ?
| style="background:#dddddd" | —3
|}

| valign="top"|

'''Super I/Os'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Status
! align="left" | v4?

|- bgcolor="#eeeeee" valign="top"
| Acer
| M1535
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87309
| style="background:lime" | OK
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87351
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97307
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97317
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| SiS
| 950
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37B72X
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37B78X
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37B807
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37C669
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37C67X
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37N769
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| VIA
| VT1211
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8231
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686
| style="background:#dddddd" | ?
| style="background:yellow" | WIP2
|- bgcolor="#eeeeee" valign="top"
| Winbond™
| W83627HF
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Winbond™
| W83877TF
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Winbond™
| W83977EF
| style="background:#eeeeee" | ?
| style="background:lime" | Yes1
|}

| valign="top"|

'''North-/Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | North/South
! align="left" | Status
! align="left" | v4?

|- bgcolor="#eeeeee" valign="top"
| NSC
| SCX200
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 540
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 550
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 630
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 635
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 730
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 735
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| ST
| STPC
| style="background:#eeeeee" | ?
| style="background:red" | No
|}

'''CPUs'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Type
! align="left" | CPU
! align="left" | Status
! align="left" | v4?

|- bgcolor="#eeeeee" valign="top"
| Alpha
| EV6
| style="background:#eeeeee" | ?
| style="background:#eeeeee" | —3
|- bgcolor="#dddddd" valign="top"
| PowerPC
| ?
| style="background:#dddddd" | ?
| style="background:#dddddd" | —3
|- bgcolor="#eeeeee" valign="top"
| x86
| AMD
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| x86
| Intel®
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| x86
| VIA
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|}

|}


1 The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least). 
2 Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet. 
3 Will not be ported anytime soon, we focus on x86 in coreboot v4. 


__FORCETOC__