coreboot - User contributions [en]

ASUS F2A85-M

2013-05-22T13:19:52Z

Ward:

== Status ==

=== Notes ===

* The ASUS F2A85-M CSM is same as F2A85-M.
* get VGA from original bios using this:
Source: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html

for internal VGA:
Boot the legacy BIOS, and use http://www.coreboot.org/VGA_support chapter

extracting from your system: dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768

You will need following patch to seabios:
<code>
--- a/src/optionroms.c
+++ b/src/optionroms.c
@@ -215,7 +215,10 @@ is_pci_vga(struct pci_device *pci)
{
if (pci->class != PCI_CLASS_DISPLAY_VGA)
return 0;
- u16 cmd = pci_config_readw(pci->bdf, PCI_COMMAND);
+ u16 cmd = pci_config_readw(pci->bdf, PCI_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+
+ pci_config_writew(pci->bdf, PCI_COMMAND, cmd);
+
if (!(cmd & PCI_COMMAND_IO && cmd & PCI_COMMAND_MEMORY))
return 0;
while (pci->parent) {
</code>

Reason is unknown, I see coreboot is writing 7 to cmd, but there is actually
6... Maybe there is some magic about IO decode bit...

* Add VGA bios in the menuconfig
* If you use PS/2 de-select legacy free
* De-select running option ROMs, leave this to Seabios
* Use seabios as payload
* Hotswapping has some issues (most likely USB3, disable it in orig bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues.

=== TODOs ===
* test virtualization
* test HDMI
* update VERB tables
* test suspend

{{Status|

|CPU_status = OK
|CPU_comments =
|CPU_L1_status = OK
|CPU_L1_comments =
|CPU_L2_status = OK
|CPU_L2_comments =
|CPU_L3_status = N/A
|CPU_multiple_status = OK
|CPU_multicore_status = OK
|CPU_multicore_comments =
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = N/A
|RAM_DDR3_status = OK
|RAM_DDR3_comments = Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less!
|RAM_dualchannel_status = OK
|RAM_ecc_status = N/A
|RAM_ecc_comments =

|IDE_status = N/A
|IDE_comments =
|IDE_25_status = N/A
|IDE_CF_status = N/A
|CDROM_DVD_status = Untested
|SATA_status = OK
|SATA_comments = Tested only first top port on left in sixpack (from outside view).
|USB_status = Untested
|USB_comments =
|Onboard_VGA_status = OK
|Onboard_VGA_comments = HDMI untested
|Onboard_ethernet_status = OK
|Onboard_audio_status = Untested
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCIE_x1_status = OK
|PCIE_x2_status = N/A
|PCIE_x4_status = OK
|PCIE_x8_status = N/A
|PCIE_x16_status = OK
|PCIE_x16_comments =
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = Untested
|COM1_status = OK
|COM2_status = N/A
|PS2_keyboard_status = OK
|PS2_mouse_status = Untested
|PP_status = N/A
|PP_comments =
|Game_port_status = N/A
|IR_status = ?
|Speaker_status = ?
|DiskOnChip_status = N/A

|Sensors_status = Untested
|CAN_bus_status = N/A
|CPUfreq_status = OK
|CPUfreq_comments =
|Powersave_status = ?
|ACPI_status = OK
|ACPI_comments = ACPI power button event works, suspend untested.
|Reboot_status = OK
|Poweroff_status = OK
|LEDs_status = Unknown
|HPET_status = OK
|RNG_status = ?
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = OK

}}

== Hardware info ==

This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:

{|
|| [[Image:IMG_20130522_084444.jpg|thumb|Winbond 25Q64F]]
|}

The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]

File:IMG 20130522 084444.jpg

2013-05-22T13:10:36Z

Ward: Asus F2A85-M rom chip

Asus F2A85-M rom chip

User:Ward

2012-09-07T00:27:21Z

Ward: /* Ward Vandewege */

=== Ward Vandewege ===

I'm a (part-time) CTO for the [http://www.fsf.org Free Software Foundation]. We have a [http://www.fsf.org/campaigns/free-bios.html Campaign for a free BIOS], because a Free BIOS is essential to achieve true computing freedom.

Where possible, we only buy hardware capable of running coreboot. Currently, we are standardizing on AMD-based systems: in terms of servers we have some Tyan systems and more recently we've purchased Silicon Mechanics A236 and A266 servers. We also have a bunch of Gigabyte M57SLI-S4 based machines, a few PC Engines ALIX boards, and a couple Asus M2A-VM boards.

You can reach me at ward@gnu.org.

Fun Stuff

2011-12-06T02:26:02Z

Ward:

== Failure at scale ==

A BIOS gets confused in a very visible way:

[[File:Billboard_bios_fail.jpeg|640px]]

Photo courtesy Greg Kurtzer of LBL.

== What floor am I on? ==

An elevator in Spain:

[[File:Elevator_spain.jpeg|640px]]

Photo courtesy Gorka Guardiola

== Confused payphone ==

A payphone in trouble. Taken during the LinuxBIOS summit in Hamburg, Germany in October 2006. Bonus: two coreboot hackers visible in the reflection.

[[File:Dscn3815.jpg|640px]]

Photo by Ward Vandewege

File:Dscn3815.jpg

2011-12-06T02:23:36Z

Ward: Confused payphone in Hamburg, Germany (2006)

Confused payphone in Hamburg, Germany (2006)

GIGABYTE GA-MA785GMT-UD2H

2010-08-20T20:40:17Z

Ward:

This board exists in 4 versions: v1.0, v1.1, v1.3 and v3.3.

This documentation applies to [http://www.gigabyte.com/products/product-page.aspx?pid=3274 v1.1]. If you have a different version of the board, YMMV.

==Dual BIOS==

This board has a dual bios chip. Both chips are 8Mbit; the main bios is called M_BIOS, the backup bios B_BIOS. Gigabyte claims the backup bios can not be flashed by the user. It contains code that will overwrite M_BIOS if it determines that M_BIOS is corrupted.

The M_BIOS chip is a [http://www.mct.net/download/macronix/mx25l8005.pdf Macronix MX25L8005].

If you flash coreboot into M_BIOS and something goes wrong, you can force B_BIOS to boot and reflash M_BIOS by bridging pins 4 (GND) and 7 (#HOLD) on the M_BIOS chip, powering up the machine, and then releasing your bridge after a few seconds. The B_BIOS will take over at that point - you will hear a beep, and see the B_BIOS boot and forcibly re-flash M_BIOS.

GIGABYTE GA-MA785GMT-UD2H

2010-08-20T20:14:09Z

Ward:

This board exists in 4 versions: v1.0, v1.1, v1.3 and v3.3.

This documentation applies to [http://www.gigabyte.com/products/product-page.aspx?pid=3274 v1.1]. If you have a different version of the board, YMMV.

==Dual BIOS==

This board has a dual bios chip. Both chips are 8Mbit; the main bios is called M_BIOS, the backup bios B_BIOS. Gigabyte claims the backup bios can not be flashed by the user. It contains code that will overwrite M_BIOS if it determines that M_BIOS is corrupted.

The M_BIOS chip is a [http://www.mct.net/download/macronix/mx25l8005.pdf Macronix MX25L8005].

If you flash coreboot into M_BIOS and something goes wrong, you can force B_BIOS to boot and reflash M_BIOS by bridging pins 4 (GND) and 7 (#HOLD) on the M_BIOS chip, powering up the machine, and then releasing your bridge. The B_BIOS will take over at that point - you will hear a beep, and see the B_BIOS boot and forcibly re-flash M_BIOS.

GIGABYTE GA-MA785GMT-UD2H

2010-08-20T20:13:42Z

Ward: Created page with "This board exists in 4 versions: v1.0, v1.1, v1.3 and v3.3. This documentation applies to [http://www.gigabyte.com/products/product-page.aspx?pid=3274 v1.1]. If you have a diffe..."

This board exists in 4 versions: v1.0, v1.1, v1.3 and v3.3.

This documentation applies to [http://www.gigabyte.com/products/product-page.aspx?pid=3274 v1.1]. If you have a different version of the board, YMMV.

==GA-MA785GMT-UD2H==

==Dual BIOS==

This board has a dual bios chip. Both chips are 8Mbit; the main bios is called M_BIOS, the backup bios B_BIOS. Gigabyte claims the backup bios can not be flashed by the user. It contains code that will overwrite M_BIOS if it determines that M_BIOS is corrupted.

The M_BIOS chip is a [http://www.mct.net/download/macronix/mx25l8005.pdf Macronix MX25L8005].

If you flash coreboot into M_BIOS and something goes wrong, you can force B_BIOS to boot and reflash M_BIOS by bridging pins 4 (GND) and 7 (#HOLD) on the M_BIOS chip, powering up the machine, and then releasing your bridge. The B_BIOS will take over at that point - you will hear a beep, and see the B_BIOS boot and forcibly re-flash M_BIOS.

Development Guidelines

2010-05-21T14:33:27Z

Ward: /* Required Toolchain */

= Development Environment =

== Required Toolchain ==

* GNU development environment:
** [http://gcc.gnu.org/ GCC] (tested: 4.1.2 prerelease)
** G++
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils] (tested: 2.17.50.0.5)
* libncurses*-dev
* Python (tested: 2.4, 2.5)
* bash (tested: 3.0, 3.1)
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)
* [http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml pciutils-devel/pciutils-dev] This package is called libpci-dev in Ubuntu (Intrepid Ibex and newer) and Debian (Lenny and newer).

= Coding Guidelines =

== General Guidelines ==

* Encapsulate and isolate assembly language
* Code shall not be "commented out"
* No use of floating-point arithmetics
* No hiding of identifiers defined in outer scopes
* Typedefs are unique (device_t?)
* Functions shall have prototype declarations
* Local functions should be declared static
* No definitions in header files
* All variables are assigned before use
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')

== Comments ==

=== References ===

If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).

== Coding Style ==

* We use the [http://lxr.linux.no/source/Documentation/CodingStyle Linux kernel coding style] for coreboot.
* You can use the 'indent' tool to fix the coding style like this:
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.

= Documentation Guidelines =

== General Guidelines and Tips ==

* Documentation should be put into the wiki and/or in the code as Doxygen comments
* Avoid using different styles and looks of documentation
* Document ''what'', not ''how'' (No comments like ''// add one to i'')
* Document assumptions, stipulations etc...
* Document design and concepts!
* Not lots of documentation but good documentation
* Structured documentation
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...

== Automatic documentation ==

* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.
* To create a Doxygen comment, write
/**
* Sample comment.
*/
:or
/** Sample comment. */
* There are a few commands that describe what kind of comment you are adding:
::@param — input parameters of a function
::@return — return value of a function
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html

Full example:

/**
* Calculate the length of a string.
*
* @param str The input string.
* @return The length of the string, not including the final NUL character.
*/
static inline size_t strlen(const char *str)
{
/* ... */
}

= Testing =

Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting
patches.

== autobuild ==

Autobuild can be found at [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/abuild/abuild coreboot/util/abuild].

Please run ''abuild'' '''before''' you commit.

Autobuild is also running on every check-in to the repository and sending result mails to the coreboot [[Mailinglist|mailing list]]. The results of this build are also available at http://qa.coreboot.org/ in the ''build'' section of each revision.

== autotest ==

Each revision is also tested with an automated test system: http://qa.coreboot.org/overview.php?tested=1. If you developed coreboot for a certain mainboard or wish to help improving coreboot's quality by running the testsuite on one of your mainboards, please contact [mailto:info@coresystems.de info@coresystems.de].

= How to contribute =

== Creating Patches ==

* '''Always use a checkout of the latest svn revision of the code'''. Patches that do not apply on the latest svn revision will be rejected!
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).
* If your patch is supposed to add new files, please add them to your local repository before creating a diff. Use
svn add path/to/file
* Create your patches by executing the following command in the top-level coreboot directory:
svn diff > ~/some_descriptive_name.patch
* Open the patch in a text-editor and double-check that your changes are correct, and that the patch only contains what you think it contains.

== Testing your Patch ==

Patches can be tested against your clean local repository by using the '''patch''' command. Just copy your new patch file to the top-level directory of your clean local repository and issue this command:

patch -p0 < filename.patch

== Sign-off Procedure ==

We employ a similar sign-off procedure for coreboot
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.
Please add a note such as
Signed-off-by: Random J Developer <random@developer.example.org>
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.

Patches without a Signed-off-by cannot be committed!

You have to use your real name in the Signed-off-by line and in any copyright notices you add. Patches without an associated real name cannot be committed!

'''Developer's Certificate of Origin 1.1:'''

By making a contribution to this project, I certify that: 
(a) The contribution was created in whole or in part by me and I have
the right to submit it under the open source license indicated in the file; or 
(b) The contribution is based upon previous work that, to the best of my
knowledge, is covered under an appropriate open source license and I have the
right under that license to submit that work with modifications, whether created
in whole or in part by me, under the same open source license (unless I am
permitted to submit under a different license), as indicated in the file; or 
(c) The contribution was provided directly to me by some other person who
certified (a), (b) or (c) and I have not modified it; and 
(d) In the case of each of (a), (b), or (c), I understand and agree that
this project and the contribution are public and that a record of the contribution
(including all personal information I submit with it, including my sign-off) is
maintained indefinitely and may be redistributed consistent with this project or the
open source license indicated in the file.

Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].

== Reviews ==

* Send your patch to the [[Mailinglist|mailing list]] for review. Changes that impact a lot of code should also be documented in the [http://tracker.coreboot.org/trac/coreboot/ issue tracker].
** Start the email with a detailed description of what the patch does and why. This text will usually end up in the commit logs so don't clutter it with useless stuff which should not go into the commit message.
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch.
*** Example: ''Signed-off-by: John Doe <john@example.com>''
** Add a single line which only contains "---". Everything which comes after that line will not be included in the commit message.
* The developers on the mailing list will review and/or test your patch and send comments or suggestions. Please post updated patches to the mailing list again.
* If the patch looks ok to one or more developers, they will reply to your mail with an Acked-by: line.
** Example: ''Acked-by: John Doe <john@example.com>''
* Every non-trivial patch must get at least one Acked-by: by another developer before it can be commited.
** Exception: if you are fixing '''trivial''' things like a typo in a comment, you may specify your own name and email address in the Acked-by: field, and add the word "trivial" in the commit description (in '''addition''' to the commit description).

== Repository Commits ==

Commits to the coreboot subversion repository have to be done with a commit comment. This may be short, but descriptive:

* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:
svn diff | less
* Include the following information in the svn commit message:
** The description from the email containing the patch.
** All Signed-off-by: and Acked-by: lines your patch received.
** Reference or close bugs which are fixed by the commit, or are related to it. See [[Development Guidelines#How_to_close_Trac_issues_automatically_via_email|below]] for details.

= Bug-Tracker =

== Where is the coreboot bug tracker? ==

It is available at http://tracker.coreboot.org/. Log in with your svn username and password if you have one.

== Why do we use a bug tracker? ==

We want a standardized interface for keeping track of open issues. The [[Mailinglist|mailing list]] is fine for discussion, but long standing issues, plans, goals, milestones can not be tracked there in a sufficient manner. There is no means of quality control via the mailing list.

Therefore changes that impact a lot of code '''must''' be documented in the bug tracker. Also, please document bugs in the tracker.

== How can I close Trac issues automatically via svn commits? ==

It searches commit messages for text in the form of:
* command #1
* command #1, #2
* command #1 & #2
* command #1 and #2 

You can have more then one command in a message. The following commands
are supported. There is more then one spelling for each command, to make
this as user-friendly as possible. 
* closes, fixes
The specified issue numbers are closed with the contents of this
commit message being added to it.
* references, refs, addresses, re
The specified issue numbers are left in their current status, but
the contents of this commit message are added to their notes. 
A fairly complicated example of what you can do is with a commit message of: 
Changed blah and foo to do this or that. Fixes #10 and #12, and refs #12. 
This will close #10 and #12, and add a note to #12.

= License Issues =

* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.

== Common License Header ==

Please quote the full GPL license header text in every file, as shown below. It should contain:

* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.
** Example:
::''Copyright (C) 2006 John Doe <john@example.com>''
::''Copyright (C) 2004-2006 Company, Inc.''
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).
** Example:
::''Copyright (C) 2004-2006 Company, Inc.''
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''
* The full '''GPL header''' as shown below.

'''Complete example for *.c and *.h files:'''

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003-2005 John Doe <john@example.com>
* Copyright (C) 2005 Jane Doe <jane@example.com>
* Copyright (C) 2006 Company, Inc.
* (Written by Janet Doe <janet@example.com> for Company, Inc.)
* Copyright (C) 2007 Joe Doe <joe@example.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''

##
## This file is part of the coreboot project.
##
## Copyright (C) 2003-2005 John Doe <john@example.com>
## Copyright (C) 2005 Jane Doe <jane@example.com>
## Copyright (C) 2006 Company, Inc.
## (Written by Janet Doe <janet@example.com> for Company, Inc.)
## Copyright (C) 2007 Joe Doe <joe@example.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

Development Guidelines

2010-05-21T14:31:24Z

Ward: /* Required Toolchain */

= Development Environment =

== Required Toolchain ==

* GNU development environment:
** [http://gcc.gnu.org/ GCC] (tested: 4.1.2 prerelease)
** G++
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils] (tested: 2.17.50.0.5)
* libncurses*-dev
* Python (tested: 2.4, 2.5)
* bash (tested: 3.0, 3.1)
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)
* [http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml pciutils-devel/pciutils-dev] This package is called libpci-dev in Ubuntu (Intrepid Ibex and newer).

= Coding Guidelines =

== General Guidelines ==

* Encapsulate and isolate assembly language
* Code shall not be "commented out"
* No use of floating-point arithmetics
* No hiding of identifiers defined in outer scopes
* Typedefs are unique (device_t?)
* Functions shall have prototype declarations
* Local functions should be declared static
* No definitions in header files
* All variables are assigned before use
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')

== Comments ==

=== References ===

If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).

== Coding Style ==

* We use the [http://lxr.linux.no/source/Documentation/CodingStyle Linux kernel coding style] for coreboot.
* You can use the 'indent' tool to fix the coding style like this:
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.

= Documentation Guidelines =

== General Guidelines and Tips ==

* Documentation should be put into the wiki and/or in the code as Doxygen comments
* Avoid using different styles and looks of documentation
* Document ''what'', not ''how'' (No comments like ''// add one to i'')
* Document assumptions, stipulations etc...
* Document design and concepts!
* Not lots of documentation but good documentation
* Structured documentation
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...

== Automatic documentation ==

* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.
* To create a Doxygen comment, write
/**
* Sample comment.
*/
:or
/** Sample comment. */
* There are a few commands that describe what kind of comment you are adding:
::@param — input parameters of a function
::@return — return value of a function
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html

Full example:

/**
* Calculate the length of a string.
*
* @param str The input string.
* @return The length of the string, not including the final NUL character.
*/
static inline size_t strlen(const char *str)
{
/* ... */
}

= Testing =

Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting
patches.

== autobuild ==

Autobuild can be found at [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/abuild/abuild coreboot/util/abuild].

Please run ''abuild'' '''before''' you commit.

Autobuild is also running on every check-in to the repository and sending result mails to the coreboot [[Mailinglist|mailing list]]. The results of this build are also available at http://qa.coreboot.org/ in the ''build'' section of each revision.

== autotest ==

Each revision is also tested with an automated test system: http://qa.coreboot.org/overview.php?tested=1. If you developed coreboot for a certain mainboard or wish to help improving coreboot's quality by running the testsuite on one of your mainboards, please contact [mailto:info@coresystems.de info@coresystems.de].

= How to contribute =

== Creating Patches ==

* '''Always use a checkout of the latest svn revision of the code'''. Patches that do not apply on the latest svn revision will be rejected!
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).
* If your patch is supposed to add new files, please add them to your local repository before creating a diff. Use
svn add path/to/file
* Create your patches by executing the following command in the top-level coreboot directory:
svn diff > ~/some_descriptive_name.patch
* Open the patch in a text-editor and double-check that your changes are correct, and that the patch only contains what you think it contains.

== Testing your Patch ==

Patches can be tested against your clean local repository by using the '''patch''' command. Just copy your new patch file to the top-level directory of your clean local repository and issue this command:

patch -p0 < filename.patch

== Sign-off Procedure ==

We employ a similar sign-off procedure for coreboot
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.
Please add a note such as
Signed-off-by: Random J Developer <random@developer.example.org>
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.

Patches without a Signed-off-by cannot be committed!

You have to use your real name in the Signed-off-by line and in any copyright notices you add. Patches without an associated real name cannot be committed!

'''Developer's Certificate of Origin 1.1:'''

By making a contribution to this project, I certify that: 
(a) The contribution was created in whole or in part by me and I have
the right to submit it under the open source license indicated in the file; or 
(b) The contribution is based upon previous work that, to the best of my
knowledge, is covered under an appropriate open source license and I have the
right under that license to submit that work with modifications, whether created
in whole or in part by me, under the same open source license (unless I am
permitted to submit under a different license), as indicated in the file; or 
(c) The contribution was provided directly to me by some other person who
certified (a), (b) or (c) and I have not modified it; and 
(d) In the case of each of (a), (b), or (c), I understand and agree that
this project and the contribution are public and that a record of the contribution
(including all personal information I submit with it, including my sign-off) is
maintained indefinitely and may be redistributed consistent with this project or the
open source license indicated in the file.

Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].

== Reviews ==

* Send your patch to the [[Mailinglist|mailing list]] for review. Changes that impact a lot of code should also be documented in the [http://tracker.coreboot.org/trac/coreboot/ issue tracker].
** Start the email with a detailed description of what the patch does and why. This text will usually end up in the commit logs so don't clutter it with useless stuff which should not go into the commit message.
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch.
*** Example: ''Signed-off-by: John Doe <john@example.com>''
** Add a single line which only contains "---". Everything which comes after that line will not be included in the commit message.
* The developers on the mailing list will review and/or test your patch and send comments or suggestions. Please post updated patches to the mailing list again.
* If the patch looks ok to one or more developers, they will reply to your mail with an Acked-by: line.
** Example: ''Acked-by: John Doe <john@example.com>''
* Every non-trivial patch must get at least one Acked-by: by another developer before it can be commited.
** Exception: if you are fixing '''trivial''' things like a typo in a comment, you may specify your own name and email address in the Acked-by: field, and add the word "trivial" in the commit description (in '''addition''' to the commit description).

== Repository Commits ==

Commits to the coreboot subversion repository have to be done with a commit comment. This may be short, but descriptive:

* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:
svn diff | less
* Include the following information in the svn commit message:
** The description from the email containing the patch.
** All Signed-off-by: and Acked-by: lines your patch received.
** Reference or close bugs which are fixed by the commit, or are related to it. See [[Development Guidelines#How_to_close_Trac_issues_automatically_via_email|below]] for details.

= Bug-Tracker =

== Where is the coreboot bug tracker? ==

It is available at http://tracker.coreboot.org/. Log in with your svn username and password if you have one.

== Why do we use a bug tracker? ==

We want a standardized interface for keeping track of open issues. The [[Mailinglist|mailing list]] is fine for discussion, but long standing issues, plans, goals, milestones can not be tracked there in a sufficient manner. There is no means of quality control via the mailing list.

Therefore changes that impact a lot of code '''must''' be documented in the bug tracker. Also, please document bugs in the tracker.

== How can I close Trac issues automatically via svn commits? ==

It searches commit messages for text in the form of:
* command #1
* command #1, #2
* command #1 & #2
* command #1 and #2 

You can have more then one command in a message. The following commands
are supported. There is more then one spelling for each command, to make
this as user-friendly as possible. 
* closes, fixes
The specified issue numbers are closed with the contents of this
commit message being added to it.
* references, refs, addresses, re
The specified issue numbers are left in their current status, but
the contents of this commit message are added to their notes. 
A fairly complicated example of what you can do is with a commit message of: 
Changed blah and foo to do this or that. Fixes #10 and #12, and refs #12. 
This will close #10 and #12, and add a note to #12.

= License Issues =

* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.

== Common License Header ==

Please quote the full GPL license header text in every file, as shown below. It should contain:

* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.
** Example:
::''Copyright (C) 2006 John Doe <john@example.com>''
::''Copyright (C) 2004-2006 Company, Inc.''
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).
** Example:
::''Copyright (C) 2004-2006 Company, Inc.''
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''
* The full '''GPL header''' as shown below.

'''Complete example for *.c and *.h files:'''

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003-2005 John Doe <john@example.com>
* Copyright (C) 2005 Jane Doe <jane@example.com>
* Copyright (C) 2006 Company, Inc.
* (Written by Janet Doe <janet@example.com> for Company, Inc.)
* Copyright (C) 2007 Joe Doe <joe@example.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''

##
## This file is part of the coreboot project.
##
## Copyright (C) 2003-2005 John Doe <john@example.com>
## Copyright (C) 2005 Jane Doe <jane@example.com>
## Copyright (C) 2006 Company, Inc.
## (Written by Janet Doe <janet@example.com> for Company, Inc.)
## Copyright (C) 2007 Joe Doe <joe@example.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

FlexyICE

2010-04-17T19:23:19Z

Ward: /* Booting SPI boards */ add potential SPI testclip

[[Image:artec_dongle.jpg|thumb|right|Artec Group FlexyICE (version 1).]]

== About the FlexyICE ==

The FlexyICE (formerly known as LPC dongle) is made by [http://www.artecgroup.com/products/hardware-products/programmable-lpc-dongle.html Artec Group], based in Estonia. It costs about EUR 160 (2009-11).

The FlexyICE connects to a computer via USB. It connects to the target via an LPC header.

The FlexyICE comes with [http://opencores.org/projects.cgi/web/usb_dongle_fpga/overview free software and full schematics] (scroll all the way to the bottom for download links, or click on the CVS: browse link near the top). The host-based software is written in Python, and works just fine under GNU/Linux.

The FlexyICE has 16 MByte of onboard memory, divided in 4 banks of 4 Mbyte each. The 'mode-selection' jumpers allow selection of each bank: 00, 01, 10, 11.

The dongle also has two 16-segment LED displays that can show POST codes.

If you hold the reset button on the dongle, the second LED will show the version of the VHDL you have - currently 03, 04 or 05.

Artec Group provides [http://opencores.org/cvsweb.shtml/usb_dongle_fpga/release/EPCS_update_tool.zip a tool] to upgrade the VHDL on the dongle that can be run under GNU/Linux (it's a python program). They also provide the binary image for the v5 of the VHDL. Of course all sources are available to build that binary image, but currently proprietary software on Windows is needed to do so. You will need a byteblaster-II cable (which can be purchased at http://www.customcircuitsolutions.com/cable.html or http://fpgaguy.110mb.com/, for instance). This tool has only received limited testing, so please be careful and report any problems to the author.

== Using the FlexyICE ==
=== Drivers for Windows and Mac OS ===
The FlexyICE can be accessed using its usb-to-serial chip (FT245B(M)). For Windows and Mac OS, you need a driver for the chip, which can be found at the [http://www.ftdichip.com/Drivers/VCP.htm chip vendor's website].

=== Reading from and writing to the FlexyICE ===

If you use Ubuntu, make sure to uninstall brltty (apt-get remove brltty --purge) before you hook up the FlexyICE; otherwise it will hijack the FlexyICE and you won't be able to talk to it. Brltty is a software braille terminal.

Images are downloaded via USB. With the latest version of the VHDL (v5), it should take about 8 seconds to write a 512KByte image to the FlexyICE.

Here's a command that writes a 512KByte image to the FlexyICE

./dongle.py -v -c /dev/ttyUSB0 alix0-1.bin 3584K

The -v parameter makes the command verbose. -c /dev/ttyUSB0 means 'use device /dev/ttyS0'. Alix0-1.bin is the image that is to be written to the FlexyICE (it's a 512KByte file), and 3584K is the offset at which it should be written. Always calculate that number as 4Mbyte - size of your image.

And here's how you can read the image back:

./dongle.py -c /dev/ttyUSB0 -r 3670016 512K test2.rom

The -r parameter indicates 'read', and 3670016 is the offset at which the program should start reading (this is 3584K), for 512K bytes. You can express the offset in decimal (like in this example, in hex with a leading 0x, or in abbreviated decimal - for instance 3584K). Test2.rom is the file the image will be stored in on your computer.

If you actually wrote and read an image, you should now md5sum both files to make sure they are identical.

== Adapters and Cables ==

=== Booting an ALIX.1C ===

First of all, you'll need to make a custom cable. The ALIX.1C has a 20-pin header (J16) that can be used to hook up the FlexyICE. The pin layout is documented on page 13 and 14 in the [http://pcengines.ch/pdf/alix1c.pdf ALIX.1C manual]:

<pre>
1 LCLK0 LPC clock (33 MHz)
2 GND ground
3 LAD0 LPC data 0
4 GND ground
5 LAD1 LPC data 1
6 GND ground
7 LAD2 LPC data 2
8 GND ground
9 LAD3 LPC data 3
10 GND ground
11 LFRAME# LPC frame
12 GND ground
13 PCIRST# reset (active low)
14 NC reserved
15 ISP high to use LPC flash, low to use on-board flash, pulled low by resistor
16 VCC +5V supply
17 GND ground
18 V3 +3.3V supply
19 SERIRQ serial interrupt
20 LDRQ# LPC DMA request
</pre>

The Artec Group FlexyICE has a 10-pin LPC connector that is described [http://www.artecgroup.com/downloads/task,doc_download/gid,5/Itemid,33/ in the schematics]. This is the pin layout:

<pre>
1 RESETX
2 LAD0
3 LAD1
4 LAD2
5 LAD3
6 LFRAME#
7 R33 GND
8 PCICLK1
9 GND
10 VCC 3V in
</pre>

Peter Stuge figured out the correct wiring [http://www.coreboot.org/pipermail/coreboot/2007-December/028011.html here] and [http://www.coreboot.org/pipermail/coreboot/2007-December/028012.html here]. This is the wiring diagram:

<pre>
FlexyICE - ALIX.1C

1 - 13
2 - 3
3 - 5
4 - 7
5 - 9
6 - 11
7 - NC
8 - 1
9 - 2/4/6/8/10/12/17 (just pick one)
10 - NC
- 15 connected to 18
</pre>

In the above, pin 7 on the FlexyICE should not be connected to anything on the ALIX.1C. Pin 9 on the FlexyICE should be connected to one of 2/4/6/8/10/12/17 on the ALIX.1C, not all of those pins. Pin 15 and 18 on the ALIX.1C side need to be shorted, but not connected to anything on the FlexyICE side.

Cable length is important - your cable should not be more than a few centimeter long.

The easiest way to make such a cable is to take an old floppy or IDE-40 flat ribbon cable (don't use IDE-80, its wires are much thinner which makes things harder), cut it, and put a 10-pin header on the FlexyICE side.

If you are in the US, you can buy 10-pin headers [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=32492&productId=32492 here] (Jameco part number 32492). You might also want to get [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=73252&productId=73252 a crimping tool] (Jameco part number 73252).

This is what a finished cable looks like:

[[Image:Dscn3151_640_480.jpg||Custom ALIX.1C to FlexyICE cable]]

You can test your cable by booting the ALIX.1C, and then hooking it up to the FlexyICE (using J16 on the ALIX.1C, of course). Now reboot the ALIX.1C board; the LEDs on the FlexyICE should show post codes as the ALIX.1C shuts down and tries to boot. Unless you've prepared the FlexyICE and stored an image into it, the ALIX.1C will not boot. But if you see POST codes on the LEDs, your cable is likely to be good. If not, use a multimeter and make sure it matches the layout above. Also make sure that it is not too long.

Now make sure the FlexyICE is correctly configured:

Jump pin 1/2 on J1. Make sure JMP4 is set to position 1/2 (i.e. NOT to the pins marked as LPC). Make sure that you leave the mode select jumpers in the same position between the writing of the image into the FlexyICE and trying to boot off it.

Now write your image to the top of the memory bank you want to use (see higher). Then disconnect the FlexyICE from your computer, reconnect it, make sure that you have your cable connected to the LPC port on the FlexyICE and J16 on the ALIX.1C, and plug in power to the ALIX.1C. Also hook up a serial port to the ALIX.1C so that you see what happens during boot. If all goes well, you will see post codes on the FlexyICE LEDs as the ALIX.1C boots.

=== Booting FWH PLCC boards ===

It is also possible to boot FWH PLCC boards, if you make a special cable. For an example of such a cable, see some photos here: http://www.artecdesign.ee/~martr/dongle-fwh-plcc-cable/. TODO: we need to find a place to buy such a connector, and we need to document the pinout of the cable.

=== Booting SPI boards ===

With a VHDL change and the proper cable, it should be possible to use the FlexyICE to boot SPI-based boards. Artec is considering this as a planned feature for [http://www.opencores.org/projects.cgi/web/artec_dongle_ii_fpga/overview FlexyICE II] VHDL - when that is done, interested parties can try to backport the relevant open source VHDL parts.

An SPI adapter would also be needed. This might be a good candidate: [http://www.dediprog.com/SPI-flash-in-circuit-programming/ISP-Testclip-SO8 ISP Testclip SO8]

{{GPL}}

Welcome to coreboot

2009-11-14T00:57:55Z

Ward:

<table width="100%" valign="top"><tr valign="top"><td width="80%">

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].

We currently support '''[[Supported Motherboards|212]]''' different mainboards.

</div>

{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%
|-
|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = yellow|
WIDTH = 100%|
ICON = [[Benefits|More...]]|
HEADING = [[Benefits]]|
CONTENT =

* 100% Free Software (GPL), no royalties, no license fees!
* Fast boot times (3 seconds to Linux console)



* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]


}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = #d1adf6|
WIDTH = 100%|
ICON = [[Use Cases|More...]]|
HEADING = [[Use Cases]]|
CONTENT =

* Desktop PCs and servers
* [[Clusters]]

* Embedded solutions




}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = lime|
WIDTH = 100%|
ICON = [[Payloads|More...]]|
HEADING = [[Payloads]]|
CONTENT =

* [[FILO]] / [http://grub.enbug.org/CoreBoot GRUB2] 
* [[Linux]] / [[Booting Windows using coreboot|Windows]] / [[Booting FreeBSD using coreboot|FreeBSD]]
* [[Etherboot]]


}}

|}

{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_cb.png]]
|style="vertical-align:top"|
'''About''' Find out more about coreboot.<hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Clusters]] | [[Vendors]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_devel.png]]
|style="vertical-align:top"|
'''Developers''' Get involved! Help us make coreboot better.<hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[SerialICE]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_status.png]]
|style="vertical-align:top"|
'''Status''' Find out whether your hardware is already supported.<hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [http://qa.coreboot.org Build Status]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_tools.png]]
|style="vertical-align:top"|
'''Related Tools''' Tools and libraries related to coreboot.<hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_101.png]]
|style="vertical-align:top"|
'''Getting Started''' Download coreboot and get started.<hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[:Category:Tutorials|Board Tutorials]] | [[QEMU]] | [[AMD SimNow]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_support.png]]
|style="vertical-align:top"|
'''Support''' Learn how to contact us and find help and support.<hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot v2 Options]]
|}

|}
</td><td width="20%">

[[File:Coreboot linuxjournal.jpg|center|thumb|[[News#2009.2F09.2F25_coreboot_on_the_cover_of_the_Linux_Journal|coreboot @ Linux Journal]] ]]

 

'''[[News]]'''<hr />


* '''2009/10/21:''' [[News#2009.2F10.2F21_HP_e-Vectra_P2706T_now_supported|HP e-Vectra P2706T support]]
* '''2009/10/13:''' [[News#2009.2F10.2F13_MSI_MS-6156_now_supported|MSI MS-6156 support]]
* '''2009/10/13:''' [[News#2009.2F10.2F13_TechNexion_TIM-5690_now_supported|TechNexion TIM-5690 support]]
* '''2009/10/13:''' [[News#2009.2F10.2F13_Kontron_KT690.2FmITX_now_supported|Kontron KT690/mITX support]]
* '''2009/09/25:''' [[News#2009.2F09.2F25_coreboot_on_the_cover_of_the_Linux_Journal|coreboot @ Linux Journal]]
* '''2009/09/02:''' [[News#2009.2F09.2F02_flashrom_0.9.1_has_been_released|flashrom 0.9.1 released]]
* '''2009/07/15:''' [[News#2009.2F07.2F15_VIA_EPIA-M700_now_supported|VIA EPIA-M700 support]]


'''[[Current events|Upcoming Events]]'''<hr />



* '''2009/12/27:''' coreboot presentation at [http://events.ccc.de/congress/2009/ 26C3] in Berlin


</td></tr></table>

__NOTOC__
__NOEDITSECTION__

Products

2009-11-01T17:38:59Z

Ward: add http://corehost.us - shameless self promotion...

Here's a list of vendors and their products running coreboot/LinuxBIOS. Please [[Mailinglist|contact us]] if you wish to add your product to the following list.

== Artec Group ==

[http://www.artecgroup.com Artec Group] runs coreboot on their Geode LX based [http://www.thincan.com DBE61 ThinCan] system.

== Cluster Labs ==
[http://www.cluster-labs.com/ Cluster Labs] sells a 1.1 GHz PIII cluster node with 1 GB memory, fast ethernet, and boots coreboot.

== corehost ==

[http://corehost.us corehost] is the first hosting provider in the world to deploy hardware that runs coreboot. You can rent virtual or dedicated servers based on hardware that runs coreboot.

== coresystems GmbH ==
[http://www.coresystems.de/ coresystems GmbH] is offering coreboot based services and products. If you are a hardware/appliance vendor and want your system running coreboot, contact coresystems. As a coreboot contributor, coresystems is hosting the coreboot development repository, mailing list and web page.

== Cray ==
The Cray [http://www.cray.com/products/xd1/ Xd1] is an Opteron-based system which runs coreboot.

== CW Linux ==
[http://www.cwlinux.com CW Linux] offers pre-installed coreboot motherboards, SDK and related hardware for people want to use or develop applications on coreboot. It also provides professional services for custom coreboot-based system development.

== i-TECH Corp. ==
[http://www.i-tech.com/ i-TECH] is selling test and analysis tools with coreboot, including all its "Satellite" Fibre Channel analyzers (IFC-3016, IFC-4016, IFC-30, IFC40) and "PassPort"-based test and analysis tools.

== Linutop ==
[http://linutop.com/ Linutop] is going to ship coreboot on their diskless computers.

== Linux Labs ==
[http://www.linuxlabs.com Linux Labs] is selling [http://www.linuxlabs.com/starterclusters.html LinuxBIOS Beowulf clusters] comprised of 1U x86-based nodes with LinuxBIOS installed.

== Linux NetworX ==
[http://www.linuxnetworx.com Linux NetworX], a major contributor to the coreboot project, used to sell a variety of cluster solutions with coreboot installed. LNXI was recently bought by Cray.

== LUCIDA ==
[http://www.lucidatech.com LUCIDA] is shipping several of their thin clients, e.g. the [http://www.lucidatech.com/product/lt2610.htm LT2610] and the [http://www.lucidatech.com/product/lt3712.htm LT3712] with coreboot, according to their website.

== MikroTik ==
[http://www.routerboard.com MikroTik] is offering the [http://216.239.59.104/search?q=cache:pT2IZCrEZEsJ:www.routerboard.com/pdf/RouterBOARD200SeriesA4-3-0.pdf+routerboard+linuxbios&hl=de&ct=clnk&cd=1&gl=de Routerboard 200 series] which seems to be shipped with coreboot (devices from other Routerboard series might use coreboot, too).

== O.N.E. Technologies ==
[http://www.onelabs.com/ O.N.E. Technologies] offers coreboot on all their x86 products and offers coreboot development services.

== Silicon Mechanics ==
[http://siliconmechanics.com Silicon Mechanics] will ship their [http://www.siliconmechanics.com/i7045/opteron-server.php Rackform nServ A236] with coreboot preinstalled if requested. See [http://coreboot.org/News#2008.2F04.2F04_Silicon_Mechanics_to_ship_servers_with_coreboot_preinstalled our news item from 2008/04/04]. The [http://www.siliconmechanics.com/i9226/quad-core-opteron.php Rackform nServ A255] uses the same motherboard, and is also available with coreboot.

== VIA ==
[http://www.via.com.tw VIA] is helping the coreboot community support many new Epia's, mainboards and chipsets with several code donations and open programming guides. With key input from VIA, coreboot will soon support over 30 Mini-ITX mainboards. These mainboards are made by VIA, Jetway, Phitronics and MSI featuring the VIA C7 cpu, CN700 and VT8237 chipset. 
[http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN10000EG/CN130000G] 
[http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=473 EPIA-LN10000EG/AEG] 
[http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp pc2500] [http://www.via.com.tw/en/resources/pressroom/pressrelease.jsp?press_release_no=1729 Phitronics / VIA pc2500] 
[http://linux.via.com.tw/support/downloadFiles.action Linux VIA Portal] aims to expand cooperation with open source communities by providing drivers, chipset programming manuals and source code for select Linux distributions to technical software developers.

__NOTOC__

Supported Motherboards

2009-09-30T17:07:18Z

Ward: /* Motherboards supported in coreboot v2 */ add supermicro h8dmr (fam10) and h8dme (k8)

{| border="0" valign="top" width="100%"
| valign="top"|
See the page [[Confirmed working svn revisions]] for a table of which revision to start testing with on your particular mainboard.

Note: If a mainboard is not supported by coreboot v2, try [[Supported_Motherboards#Motherboards_supported_in_coreboot_v1|checking coreboot v1]] for support. Do '''not''' attempt to use coreboot v3 unless you are familiar with it — this is an early development version which is not ready for production use, yet.

See also [[Supported Chipsets and Devices|Supported Chipsets & Devices]].

| valign="top" align="right"|

'''Color Legend'''
{| border="1" style="font-size: smaller"
|- bgcolor="#eeeeee"
| style="background:red" | Motherboard is work in progress, unfinished, or on hold.
|-
| style="background:yellow" | Motherboard mostly works, but some issues remain.
|-
| style="background:lime" | Motherboard is fully supported.
|}

|}

== Motherboards supported in coreboot v3 ==

<div style="color: #ff0000">coreboot v3 is an alpha-stage development version of coreboot and is not meant for production use, yet!</div>

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status / Tutorial
! align="left" | ROM 1
! align="left" | P 2
! align="left" | S 3
! align="left" | F 4
! align="left" | VCS5

|- bgcolor="#eeeeee"
| Advanced Digital Logic
| [http://www.adlogic-pc104.com/products/cpu/datasheets/MSM800SEV_SEL.pdf MSM800SEV]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| AMD
| DB800
| AMD Geode™ LX
| AMD CS5536
| ?
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| AMD
| [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T] (Herring)
| AMD K8
| AMD RS690/SB600
| ITE IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| AMD
| Norwich
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD K8
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| AMP
| TinyGX
| AMD Geode™ LX
| AMD CS5536
| ITE IT8716F
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE61]
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:orange" | WIP
| TSOP32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE62]
| AMD Geode™ LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[Artec Group DBE62|OK...]]
| TSOP32
| FWH
| style="background:red" | N
| style="background:lime" | Y
| style="background:lime; text-align:center" | [[Artec Group DBE62 Vendor Cooperation Score|4]]

|- bgcolor="#eeeeee"
| Emulation
| [http://fabrice.bellard.free.fr/qemu/ QEMU x86]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| —
| Intel® Pentium® II/III (?)
| —
| style="background:lime" | OK
| —
| ?
| —
| —
| —

|- bgcolor="#dddddd"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&ModelName=GA-M57SLI-S4 GA-M57SLI-S4]
| AMD K8
| NVIDIA MCP55
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2
| style="background:orange" | WIP
| ...6
| ?
| style="background:red" | N
| style="background:lime" | Y
| style="background:yellow; text-align:center" | [[Gigabyte m57sli Vendor Cooperation Score|3]]

|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Kontron
| [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]
| Intel® 945
| Intel® ICH7
| 2x Winbond® W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| mPGA478
| style="background:orange" | WIP
| PLCC
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix1c.htm ALIX.1C]
| AMD Geode™ LX
| AMD Geode™ CS5536
| Winbond® W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.1C|OK...]]
| ?
| ?
| ?
| ?
| style="background:lime; text-align:center" | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]
|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix2c3.htm ALIX.2C3]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.2CX|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| PC Engines
| [http://pcengines.ch/alix2c2.htm ALIX.2C2]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.2CX|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| EPIA-CN
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:orange" | WIP
| ?
| ?
| ?
| ?
| —

|}


1 ROM chip package (PLCC, DIP32, DIP8, SOIC8). 
2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 
3 ROM chip socketed (Y/N)? 
4 Board supported by [[Flashrom]] (Y/N)? 
5 Vendor Cooperation Score. 
6 There are two versions of the [[GIGABYTE GA-M57SLI-S4]], one with a soldered PLCC chip, one with a soldered SOIC8 chip. 



== Motherboards supported in coreboot v2 ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status / Tutorial
! align="left" | ROM 35
! align="left" | P 36
! align="left" | S 37
! align="left" | F 38
! align="left" | VCS4

|- bgcolor="#6699ff"
| colspan="13" | '''Desktops / Workstations'''

|- bgcolor="#eeeeee"
| Abit
| [http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAME=BE6-II+V2.0&fMTYPE=Slot+1 Abit BE6-II V2.0]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| ?
| ?
| ?
| —
| —

|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=171&l4=0&model=455&modelmenu=2 A8N-E]
| AMD K8
| NVIDIA CK8041
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8N-E|OK...]]25
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK A8N-SLI]
| AMD K8
| NVIDIA CK8041
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS_A8N-SLI|OK...]]25
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?modelmenu=1&model=596&l1=3&l2=15&l3=207 A8N5X]
| AMD K8
| NVIDIA CK8041
| ITE IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8N5X|OK...]]25
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&modelmenu=1 A8V-E SE]
| AMD K8
| VIA K8T890 / VT8237R
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8V-E SE|OK...]]
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=376&modelmenu=1 A8V-E Deluxe]
| AMD K8
| VIA K8T890 / VT8237R
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| style="background:lime" | [[ASUS A8V-E Deluxe|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&modelmenu=1 M2A-VM]
| AMD 690G
| ATI SB600
| ITE™ IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2(+)
| style="background:lime" | [[ASUS M2A-VM|OK...]]
| PLCC
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=324&l4=0&model=1807&modelmenu=1 M2V-MX SE]
| AMD K8
| VIA K8M890 / VT8237S
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[ASUS M2V-MX SE|OK...]]
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ MEW-AM]
| Intel® 82810
| Intel® 82801AA (ICH)
| SMSC® LPC47B272
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[ASUS MEW-AM|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:red" | N
| —
|- bgcolor="#dddddd"
| ASUS
| [http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm MEW-VM]
| Intel® 82810
| Intel® 82801AA (ICH)
| SMSC® LPC47B272
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:yellow" | WIP28
| PLCC
| ?
| style="background:lime" | Y
| style="background:red" | N
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ P2B]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | [[ASUS P2B|WIP...]]
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ P2B-F]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | [[ASUS P2B-F|WIP...]]
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ P2B-D]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| 2x Slot 1
| style="background:yellow" | [[ASUS P2B-D|WIP...]]
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ P2B-DS]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| 2x Slot 1
| style="background:yellow" | [[ASUS P2B-DS|WIP...]]
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| ASUS
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ P3B-F]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | [[ASUS P3B-F|WIP...]]
| DIP32
| ?
| style="background:lime" | Y
| style="background:red" | N
| —

|- bgcolor="#eeeeee"
| A-Trend
| [http://www.motherboard.cz/mb/atrend/atc6220.htm ATC-6220]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| A-Trend
| [http://active-hardware.com/english/reviews/mainboard/atc6240.htm ATC-6240]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83627HF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| DIP32
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| AZZA
| [http://web.tiscali.it/acorp/?http://web.archive.org/web/20050426181911/http://web.tiscali.it/acorp/mobo_spec/azza/pt-6ibd/pt-6ibd.htm PT-6IBD]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | [[AZZA PT-6IBD|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Biostar
| [http://www.motherboard.cz/mb/biostar/M6TBA.htm M6TBA]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMSC FDC37M60x
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | [[Biostar M6TBA|WIP...]]
| DIP32
| ?
| style="background:lime" | Y
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| Compaq
| Deskpro EN SFF P600
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC97307
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| GIGABYTE
| [http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/ GA-2761GXDK] (Churchill)
| AMD K8
| SiS761GX/SiS966
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2 (?)
| Socket AM2
| style="background:lime" | [[GIGABYTE GA-2761GXDK|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2287&ModelName=GA-M57SLI-S4 GA-M57SLI-S4]
| AMD K8
| NVIDIA MCP55
| ITE IT8716F
| AMD Sempron™ / Athlon™ 64 / FX / X2
| Socket AM2
| style="background:lime" | [[GIGABYTE GA-M57SLI-S4|OK...]]
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| style="background:yellow; text-align:center" | [[Gigabyte m57sli Vendor Cooperation Score|3]]

|- bgcolor="#dddddd"
| Mitac
| [http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/products/tyan/6513wu/6513wu.htm 6513WU]
| Intel® 82810E
| Intel® 82801AB (ICH0)
| SMSC LPC47U332
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[Mitac 6513WU|OK...]]
| PLCC
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=332&maincat_no=1 MS-6119]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&maincat_no=1&prod_no=335 MS-6147]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://www.msi-technology.de/index.php?func=proddesc&prod_no=343&maincat_no=1 MS-6178]
| Intel® 82810
| Intel® 82801AB (ICH0)
| Winbond™ W83627HF
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[MSI MS-6178|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=170&maincat_no=1 MS-7135 (K8N Neo3)]
| AMD K8
| NVIDIA CK804
| Winbond® W83627THF
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
| Socket 754
| style="background:yellow" | [[MSI MS-7135|WIP...]]29
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=255&maincat_no=1&cat2_no=171 MS-7260 (K9N Neo)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Sempron™ / Athlon™ 64 / X2
| Socket AM2
| style="background:lime" | [[MSI MS-7260|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:yellow" | ...39
| —

|- bgcolor="#eeeeee"
| NEC
| [http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ PowerMate 2000]
| Intel® 82810
| Intel® 82801AB (ICH0)
| SMSC® LPC47B27x
| Intel® Pentium® III / Celeron®
| Socket 370
| style="background:lime" | [[NEC PowerMate 2000|OK...]]
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| Shuttle
| [http://global.shuttle.com/product_detail.jsp?PI=89 SN25P]
| AMD K8
| NVIDIA CK8041
| ITE IT8712F
| AMD Sempron™ / Athlon™ 64 / X2 / Opteron™ 1XX
| Socket 939
| style="background:red" | [[Shuttle SN25P|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Soyo
| [[Soyo SY-6BA Plus III|Soyo SY-6BA+ III]]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| Sun
| [http://www.sun.com/desktop/workstation/ultra40/index.xml Ultra 40]
| AMD K8
| NVIDIA CK8041
| SMSC® LPC47B397
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami ATX (S1846)]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87309
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:yellow" | WIP
| DIP32
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/tigerk8w.html Tiger K8W (S2875)]
| AMD K8
| AMD-8111™, 8151™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8w.html Thunder K8W (S2885)]
| AMD K8
| AMD-8111™, 8131™, 8151™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8we.html Thunder K8WE (S2895)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| SMSC® LPC47B397
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Servers'''

|- bgcolor="#eeeeee"
| agámi
| [http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-6000-series Aruma/AIS6000 series]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD K8
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| AMD
| Serengeti Cheetah
| AMD Fam10h
| AMD-8111™, 8151™, 8132™
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Arima
| [http://web.archive.org/web/20080127024444/http://www.arima.com.tw/server/Product/ViewProduct.asp?View=HDAMA HDAMA]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87360
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Dell
| S1850
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| ?
| ?
| style="background:red" | WIP2
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| HP
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 ProLiant DL145 G3]
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| AMD Opteron™
| Socket F
| style="background:lime" | [[HP DL145 G3|OK]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| IBM
| [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-53255 eServer 325]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87366
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IBM
| [http://www-307.ibm.com/pc/support/site.wss/document.do?sitestyle=ibm&lndocid=MIGR-58655 eServer 326]
| AMD K8
| AMD-8111™, 8131™
| NSC PC87366
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Intel
| [http://www.intel.com/support/motherboards/server/se7520jr2/ Jarrell (SE7520JR2)]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| NSC PC87427
| Intel® Xeon®
| ?
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 DK8-HTX]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[IWILL DK8-HTX|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060509143427/http://www.iwill.net/product_2.asp?p_id=42&sp=Y DK8S2]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| IWILL
| [http://web.archive.org/web/20060213163325/http://www.iwill.net/product_2.asp?p_id=28 DK8X]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| MSI
| [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx K9SD Master-S2R (MS-9185)]
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| AMD Opteron™
| Socket F
| style="background:lime" | OK12
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| MSI
| [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 K9SD Master (MS-9282)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK15
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Newisys
| [http://web.archive.org/web/20070922231423/http://www.newisys.com/core/2100e.html 2100 Server] (SUN Fire v20z)
| AMD K8
| AMD-8111™, 8131™
| NSC PC87360
| AMD Opteron™
| Socket F
| style="background:lime" | OK7
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| NVIDIA
| l1_2pvv
| AMD K8
| NVIDIA MCP55+IO55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK14
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm H8DMR-i2]
| AMD Fam10h
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm H8DME-2]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| style="background:lime" | OK41
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DAi-G]
| Intel® E7525
| Intel® E7525, ESB6300
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7525/X6DAi-G.cfm X6DHE-G]
| Intel® E7520
| Intel® E7520, ESB6300
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHE-G2.cfm X6DHE-G2]
| Intel® E7520
| Intel® 82801ER (ICH5R), ESB6300
| NSC PC87427
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG.cfm X6DHR-iG]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon800/E7520/X6DHR-iG2.cfm X6DHR-iG2]
| Intel® E7520
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigeri7501r.html Tiger i7501R (S2735)]
| Intel® E7501
| Intel® 82801ER (ICH5R)
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tomcatk8s.html Tomcat K8S (S2850)]
| AMD K8
| AMD-8111™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8s.html Thunder K8S (S2880)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8sr.html Thunder K8SR (S2881)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2881|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8spro.html Thunder K8S Pro (S2882)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2882|OK...]]20
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8sre.html Thunder K8SRE (S2891)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2891|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8se.html Thunder K8SE (S2892)]
| AMD K8
| AMD-8131™, NVIDIA CK8041
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | [[Tyan S2892|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder n3600R (S2912)]
| AMD K8
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | [[Tyan S2912|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Thunder n3600R (S2912)]
| AMD Fam10h
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| style="background:lime" | [[Tyan S2912|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8qs.html Thunder K8QS (S4880)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk8qspro.html Thunder K8QS Pro (S4882)]
| AMD K8
| AMD-8111™, 8131™
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Laptops'''

|- bgcolor="#eeeeee"
| OLPC
| btest
| AMD GX9
| AMD CS5536
| —
| AMD Geode™ GX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| OLPC
| rev_a
| AMD GX9
| AMD CS5536
| —
| AMD Geode™ GX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Embedded / SBC / PC/104 / Half-size boards'''

|- bgcolor="#eeeeee"
| Advantech
| [http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8 PCM-5820]
| AMD GX1
| AMD CS5530A
| Winbond® W83977AF
| AMD Geode™ GX1
| —
| style="background:lime" | [[Advantech PCM-5820|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| AMD
| Rumba
| AMD GX9
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™GX9
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.com/english/products/datasheets/ecm855.asp smartModule855]
| Intel® 855PM
| Intel® 82801DBM (ICH4-M)
| Winbond™ W83627HF
| ?
| ?
| style="background:red" | WIP13
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM586SEG MSM586SEG]
| integrated
| integrated
| integrated
| AMD Élan™SC520
| —
| style="background:yellow" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| DIGITAL-LOGIC
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV MSM800SEV]
| AMD Geode™ LX
| AMD Geode™ CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK22
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| EagleLion
| 5BCM
| AMD GX1
| AMD  CS5530
| NSC PC97317
| ?
| —
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Embedded Planet
| [http://www.embeddedplanet.com/products/ep405pc.asp EP405PC]
| IBM PPC 405GP
| Winbond® W83C553F-G
| ?
| AMCC PPC405GP(r)
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| IEI
| [http://www.icpamerica.com/products/single_board_computers/5_25_NOVA/NOVA-4899.html NOVA-4899R]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977TF
| AMD Geode™ GX1
| —
| style="background:yellow" | WIP17
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/news_content.asp?id=erbium/projectOBJ00150613 JUKI-511P]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977F
| AMD Geode™ GX1
| —
| style="background:lime" | [[IEI JUKI 511P|OK...]]27
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX IEI PCISA-LX-800-R10]
| AMD LX
| AMD Geode™ CS5536
| Winbond™ W83627EHG
| AMD Geode™ LX
| —
| style="background:lime" | [[IEI LX 800|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| IEI
| [http://www.ieiworld.com/en/product_IPC.asp?model=ROCKY-512 ROCKY-512]
| AMD GX1
| AMD Geode™ CS5530A
| Winbond™ W83977F
| AMD Geode™ GX1
| —
| style="background:lime" | [[IEI ROCKY 512|OK...]]27
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.com/cool-frontrunner.html Cool Frontrunner]
| AMD GX9
| AMD CS5535
| Winbond™ W83627HF
| AMD Geode™ GX
| —
| style="background:red" | WIP2
| PLCC
| FWH
| style="background:lime" | Y
| ?
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.com/cool-spacerunner-lx800.html Cool SpaceRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| SOIC8
| SPI
| style="background:red" | N
| ?
| —
|- bgcolor="#eeeeee"
| LiPPERT
| [http://www.lippertembedded.com/cool-roadrunner-lx800.html Cool RoadRunner-LX]
| AMD Geode™ LX
| AMD Geode™ CS5536
| ITE IT8712F
| AMD Geode™ LX
| —
| style="background:lime" | OK
| PLCC
| FWH
| style="background:lime" | Y
| ?
| —

|- bgcolor="#dddddd"
| PC Engines
| [http://pcengines.ch/alix1c.htm ALIX.1C]
| AMD Geode™ LX
| AMD Geode™ CS5536
| Winbond® W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | [[PC Engines ALIX.1C|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| style="background:lime; text-align:center" | [[PC Engines ALIX.1C Vendor Cooperation Score|4]]

|- bgcolor="#eeeeee"
| TS31
| [http://www.embeddedarm.com/epc/ts5300-spec-h.html TS-5300]
| integrated
| integrated
| integrated
| AMD Élan™SC520
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Total Impact
| [http://www.beowulf.org/archive/2001-January/001857.html briQ]
| IBM CPC710-100+
| Winbond® W83C553
| ?
| PowerPC 750 (G3) / 7400 (G4)
| ?
| style="background:#dddddd" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Mini-ITX / Micro-ITX / Nano-ITX'''

|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 J7F2]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F2|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E J7F4K1G2E]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F4K1G2E|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Jetway
| [http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4K1G5D J7F4K1G5D]
| VIA CN700
| VIA VT8237R(P)
| Fintek F71805F
| VIA C7™
| NanoBGA2
| style="background:lime" | [[Jetway J7F4K1G5D|OK...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Kontron
| [http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/986lcdmmitx.html 986LCD-M/mITX]
| Intel® 945
| Intel® ICH7
| 2x Winbond® W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| mPGA478
| style="background:lime" | [[Kontron 986LCD-M mITX|OK...]]
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| MSI
| [http://global.msi.com.tw/index.php?func=proddesc&prod_no=1054&maincat_no=388# Fuzzy CN700]
| VIA CN700
| VIA VT8237R(P)
| Winbond™ W83627EHG
| VIA C7™
| NanoBGA2
| style="background:yellow" | [[MSI FUZZY CN700|WIP...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]
| VIA VT8601
| VIA VT8231
| Winbond™ W83627HF
| VIA C3™, VIA EDEN™
| —
| style="background:yellow" | [[EPIA|WIP...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-M|OK...]]10
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| EPIA-M700
| VIA VX800
| VIA VX800
| Winbond W83697HF/F/HG
| ?
| ?
| style="background:red" | [[VIA EPIA-M700|WIP...]]
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=202 EPIA-MII]
| VIA VT8623
| VIA VT8235, Ricoh RL5C476
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-MII|OK...]]8
| ?
| ?
| ?
| style="background:lime" | Y
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=301 EPIA-ML]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™, VIA EDEN™
| Socket 370
| style="background:lime" | [[VIA EPIA-ML|OK...]]10
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN10000EG]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-CN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN13000G]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-CN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN12000EG]
| VIA CN700
| VIA VT8237R
| Winbond™ W83627EHG
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA EPIA-EN|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399 EPIA-EN15000G]
| VIA CN700
| VIA VT8237R
| Winbond™ W83627EHG
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA EPIA-EN|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=473 EPIA-LN10000EG/EAG]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA EPIA-LN|OK...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7400]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA NAB7400|WIP...]]30
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=590 NAB7410]
| VIA CN700
| VIA VT8237R
| VIA VT1211
| VIA C7™, VIA  Esther C5J™
| NanoBGA2
| style="background:yellow" | [[VIA NAB7410|WIP...]]30
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.idot.com.tw/en/products/mb-pc2500e/ pc2500e]
| VIA CN700
| VIA VT8237R
| ITE IT8716F
| VIA C7™, VIA Esther C5J™
| NanoBGA2
| style="background:lime" | [[VIA pc2500e|OK...]]
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| VIA
| [http://www.idotpc.com/TheStore/pc/viewCategories.asp?idCategory=56 EPIA-N]
| VIA CN400
| VIA VT8237R
| Winbond W83697HF
| ?
| ?
| style="background:yellow" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Set-top-boxes / Thin clients'''

|- bgcolor="#eeeeee"
| Artec Group
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 DBE61]
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:red" | Broken40
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| ASI
| MB-5BLGP32
| AMD GX1
| AMD CS5530
| NSC PC87351
| AMD Geode™ GX1
| —
| style="background:lime" | [[ASI MB-5BLGP|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#dddddd"
| ASI
| [http://www.hojerteknik.com/winnet.htm MB-5BMLP]33
| AMD GX1
| AMD CS5530
| NSC PC87351
| AMD Geode™ GX1
| —
| style="background:lime" | [[ASI MB-5BLMP|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| AXUS
| [http://www.keyton.co.jp/products/UAXT/TC-320.html TC320]
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[AXUS TC320|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| BCOM
| [http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_compact.htm WinNET100]34
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[BCOM WINNET100|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#dddddd"
| BCOM
| WinNET P680
| VIA CN700
| VIA VT8237R Plus
| Winbond™ W83697HG
| Via C7™
| —
| style = "background:yellow" | [[BCOM WinNET P680|WIP...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Linutop
| [http://linutop.com/ Linutop]
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK19
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| RCA
| [http://www.settoplinux.org/index.php?title=RCA_RM4100 RM4100]
| Intel® 82830M
| Intel® 82801DB (ICH4)
| SMSC® LPC47M192
| Intel® Mobile Celeron
| Socket 479
| style="background:lime" | [[RCA RM4100|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#eeeeee"
| TeleVideo
| [http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm TC7020]
| AMD GX1
| AMD CS5530A
| NSC PC97317
| AMD Geode™ GX1
| —
| style="background:lime" | [[TeleVideo TC7020|OK...]]
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Thomson
| [http://www.settoplinux.org/index.php?title=Thomson_IP1000 IP1000]
| Intel® 82830M
| Intel® 82801DB (ICH4)
| SMSC® LPC47M192
| Low Voltage Intel® Pentium® III
| Socket 479
| style="background:lime" | [[Thomson IP1000|OK...]]
| ?
| ?
| ?
| style="background:lime" | Y
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Devel/Eval Boards'''

|- bgcolor="#eeeeee"
| AMD
| [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800] (Salsa)
| AMD LX
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Norwich
| AMD LX
| AMD CS5536
| —
| AMD Geode™ LX
| —
| style="background:lime" | OK21
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| [http://www.amd.com/us-en/assets/content_type/DownloadableAssets/42655A_S1DBM680T_PB.pdf dbM690T] (Herring)
| AMD K8
| AMD RS690/SB600
| ITE IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| style="background:lime" | [[AMD DBM690T|OK...]]
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| AMD
| Pistachio
| AMD K8
| AMD RS690/SB600
| —
| ?
| Socket AM2
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Broadcom
| Blast
| AMD K8
| Broadcom BCM5785/5780
| NSC PC87417
| ?
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| Intel
| 3100 devkit (Mt. Arvon)
| Intel® 3100
| Intel® 3100
| Intel® 3100
| Intel® Pentium® M
| Socket 479
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| EagleHeights
| Intel® 3100
| Intel® 3100
| Intel® 3100
| Intel® Pentium® M
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| EP80579 devkit (Truxton)
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| Intel® EP80579
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —
|- bgcolor="#eeeeee"
| Intel
| XE7501devkit
| Intel® E7501
| Intel® 82801CA (ICH3-S)
| SMSC® LPC47B272
| ?
| ?
| style="background:#eeeeee" | ?
| ?
| ?
| ?
| ?
| —

|- bgcolor="#dddddd"
| Motorola
| [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=SANDPOINTX3&nodeId=01M964472741978 Sandpoint X3]
| MPC107
| Winbond™ W83C553
| NSC PC97307
| MPC74xx
| ?
| style="background:lime" | OK6
| ?
| ?
| ?
| ?
| —

|- bgcolor="#eeeeee"
| VIA
| VT8454c
| VIA CX700
| integrated
| integrated
| VIA C7™
| ?
| style="background:lime" | OK
| ?
| ?
| ?
| ?
| —

|- bgcolor="#6699ff"
| colspan="13" | '''Miscellaneous'''

|- bgcolor="#eeeeee"
| Emulation
| [http://fabrice.bellard.free.fr/qemu/ QEMU x86]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| —
| Intel® Pentium® II/III (?)
| —
| style="background:lime" | [[QEMU Build Tutorial|OK...]]
| ?
| ?
| ?
| ?
| —

|}


1 NVIDIA nForce™ Professional 2200 (CK804). 
2 Work in progress. 
3 This was an AMD64 reference board. 
4 Vendor Cooperation Score. 
6 Only the Altimus X3 MPC7410 PMC is tested. Some PCI ethernet cards work. 
7 LSI1030 SCSI controller can not be used to boot the machine. 
8 Use the ''epia-m'' code for now. The on-board PCMCIA and CF sockets work. coreboot can boot from CF (the stock BIOS can't). [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016448.html Some problems] remain, though. 
9 The AMD GX (internally known as GX2 for some time) is actually the successor to the GX1. 
10 Use the ''epia-m'' code for now (plus [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016423.html a few hacks], e.g. disable Firewire/CF slot,
because they're not present on the board). 
12 Except for some [http://www.linuxbios.org/pipermail/linuxbios/2006-October/016463.html possible problems with SATA2 ports], everything should work. 
13 See also http://www.linuxbios.org/pipermail/linuxbios/2006-November/017065.html. 
14 These boards ''should'' work fine, but we have no confirmed reports on the [[Mailinglist|mailing list]] so far, so we cannot tell for sure. 
15 See http://www.openbios.org/pipermail/linuxbios/2007-February/018299.html. 
17 Seems to be [http://www.linuxbios.org/pipermail/linuxbios/2006-November/016651.html partially working], specifically eth0, eth2, the PCI slot, the USB ports, and the serial console [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021226.html are working]. Other parts are not yet finished. 
19 The Linutop does not ship with coreboot, but [http://linutop.com/wiki/index.php/Developers#Upgrading_to_LinuxBIOS the code should work]. 
20 Fan-control doesn't work yet. 
21 This is ''the'' AMD Geode LX reference board and coreboot reference implementation on the AMD Geode LX, contributed and maintained by AMD engineers. 
22 The board can boot a Linux kernel currently, but there's [http://www.linuxbios.org/pipermail/linuxbios/2007-May/020770.html no VGA support, yet]. 
25 [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021280.html Works fine], only smaller issues remain to be fixed. A [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021308.html list of known issues] is available. 
27 The JUKI-511P and ROCKY-512 both use the same code and target (targets/iei/juki-511p). Thus, both [http://www.linuxbios.org/pipermail/linuxbios/2007-June/021862.html support the same features and have the same limitations]: IDE, USB, ethernet, serial, keyboard and sound work, but there are problems booting from IDE1 ([http://www.linuxbios.org/pipermail/linuxbios/2007-June/021996.html this patch] may help), and VGA video doesn't work, yet. 
28 Partially supported, almost boots a Linux kernel. [http://www.linuxbios.org/pipermail/linuxbios/2007-June/022217.html Some issues] still remain to be fixed, though. 
29 See also http://www.coreboot.org/pipermail/coreboot/2008-February/031102.html. 
30 The irq table in CN is from VIA. You may need to run getpir to generate your own irq table. 
31 Technologic Systems. 
32 Used in the Neoware Eon 4000s thin client. 
33 Used in the IGEL WinNET III thin client. 
34 Used in the IGEL-316 thin client. 
35 ROM chip package (PLCC, DIP32, DIP8, SOIC8). 
36 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 
37 ROM chip socketed (Y/N)? 
38 Board supported by [[Flashrom]] (Y/N)? 
39 Interestingly [[flashrom]] does not work when the vendor BIOS is booted, but it does work flawlessly when the machine is booted with coreboot. 
40 Broken v2 port, try the v3 port instead. 
41 Ram must be matched exactly in each back 


== Motherboards supported in coreboot v1 ==

Not all motherboards have been ported from coreboot v1 to coreboot v2, yet (check the CBv2 field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Mainboard
! align="left" | Northbridge
! align="left" | Southbridge
! align="left" | Super I/O
! align="left" | CPU
! align="left" | Socket
! align="left" | Status
! align="left" | Tutorial
! align="left" | CBv2?

|- bgcolor="#6699ff"
| colspan="10" | '''Desktops / Workstations'''

|- bgcolor="#eeeeee"
| ASUS
| A7M
| AMD AMD76x
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| ASUS
| [http://www.ciao.co.uk/ASUS_ALi_Chipset_CUA__5410161 CUA]
| Acer M1631 (ALADDiN TNT2)
| Acer M1535
| Acer M1535
| Intel® Pentium® III
| Socket 370
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| ASUS
| [http://www.dealtime.com/xPF-ASUS-ASUS-Intel-Socket7-PNP586-Motherboard TX97-LE]
| Intel® 430TX
| Intel® 82371EB (PIIX4E)
| SMC FDC37C67X
| Intel® Pentium®, Pentium® MMX, AMD K5
| Socket 7
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Bitworks
| IMS
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87351
| ?
| Slot1 1
| style="background:#dddddd" | ?
| —
| style="background:yellow" | WIP1

|- bgcolor="#eeeeee"
| Chaintech
| [http://www.xbitlabs.com/articles/mainboards/display/chaintech-7kjd.html CT-7KJD]
| AMD-761™
| VIA VT8231
| VIA VT8231
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Elitegroup (ECS)
| [http://www.ecsusa.com/products/k7sem_v3.html K7SEM]
| SiS730S
| SiS730S
| SiS730S
| AMD Athlon™ / Athlon™ XP / Duron™
| Socket 462
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| Elitegroup (ECS)
| [http://www.ecsusa.com/downloads/manual_p6s.html P6STP-FL]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| GIGABYTE
| [http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductID=1445 GA-6BXC]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| ITE IT8671F
| Intel® Pentium® II/III, Celeron®
| Slot1 1
| style="background:#eeeeee" | ?
| —
| style="background:lime" | Yes
|- bgcolor="#eeeeee"
| GIGABYTE
| GA-6OXE
| Intel® 815EP
| Intel® 82801
| ITE IT8712F
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Leadtek
| [http://web.archive.org/web/20000616073856/http://www.leadtek.com.tw/e6300MAX.htm WinFast 6300MAX]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| Matsonic
| [http://web.archive.org/web/20000619011053/www.matsonic.com/index_2.htm MS7308E]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:lime" | OK3
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m754lmr.asp M754LMR]
| Acer M1631
| Acer M1535
| Acer M1535
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m758mr.asp M758LMR(+)]
| SiS630
| SiS630
| SiS950
| Intel® Pentium®III, Celeron®
| Socket 370
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m787cl%2B.asp M787CL+]
| SiS630
| SiS630
| SiS950
| VIA C3™
| Socket 370
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m810lmr.asp M810LMR]
| SiS670
| SiS670
| SiS950
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| M810LR
| SiS670
| SiS670
| SiS950
| AMD Athlon™ / Duron™
| Socket 462
| style="background:#dddddd" | ?
| [[PCCHIPS M810LR|Tutorial]]
| style="background:red" | No
|- bgcolor="#dddddd"
| PCCHIPS
| [http://www.pcchipsusa.com/prod-m830lmr.asp M830L(M)R]
| SiS735
| SiS735
| SiS950
| AMD Athlon™ / Athlon™ XP / Duron™
| Socket 462
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/860/P4DC6.cfm P4DC6]
| Intel® 82860
| Intel® 82801, 82806
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| P4DC6P
| Intel® 82860
| Intel® 82801, 82806
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Tyan
| TigerMPX
| AMD-76x™
| AMD-768™
| Winbond™ W83627HF
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| guiness
| AMD-76x™
| AMD-766™
| Winbond™ W83627HF
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tiger133.html Tiger 133 (S1834)]
| VIA VT8601
| ?
| Winbond™ W83977EF
| Intel® Pentium® II/III
| Slot 1
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tsunamiatx.html Tsunami ATX (S1846)]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| NSC PC87309
| Intel® Pentium® II/III, Celeron®
| Slot 1
| style="background:lime" | OK
| —
| style="background:lime" | Yes
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigermpx.html Tiger MPX (S2466)]
| AMD-762™
| AMD-768™
| Winbond™ W83627HF
| AMD Athlon® MP
| Socket 462
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/thunderk7xpro.html Thunder K7X Pro (S2469)]
| AMD-762™
| AMD-768™
| Winbond™ W83627HF
| AMD Athlon® MP
| Socket 462
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Servers'''

|- bgcolor="#eeeeee"
| ASUS
| [http://www.asus.de/products.aspx?l1=9&l2=39&l3=103&model=113&modelmenu=1 PU-DLS]
| Intel® E7501
| Intel® 82801CA (ICH3-S)
| Winbond™ W83627HF
| Intel® Xeon®
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Compaq
| DS10
| Alpha Tsunami
| Acer M1543
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| Intel
| clearwater
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Intel
| clearwater533
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| RLX
| [http://web.archive.org/web/20040413125915/rlxtechnologies.com/index.php?se=servers&id=3 ServerBlade 800i]
| Micron 21PAD
| Acer M1535
| Acer M1535
| ?
| ?
| style="background:lime" | OK2
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE.cfm P4DPE]
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7500/P4DPE-G2.cfm P4DPE-G2]
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| P4DPR
| Intel® E7500
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7505/X5DAE.cfm X5DAE]
| Intel® E7505
| Intel® 82801CA (ICH3-S), 82801DB (ICH4), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| [http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DPE-G2.cfm X5DPE-G2]
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Supermicro
| X5DPR
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Tyan
| [http://www.tyan.com/archive/products/html/tigeri7501.html Tiger i7501 (S2723)]
| Intel® E7501
| Intel® 82801CA (ICH3-S), 82870
| Winbond™ W83627HF
| Intel® Xeon®
| Socket 604
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Laptops'''

|- bgcolor="#eeeeee"
| IBM
| [http://www.thinkwiki.org/wiki/Category:T23 ThinkPad T23]
| Intel® 82830
| Intel® 82801
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Embedded / SBC / PC/104'''

|- bgcolor="#eeeeee"
| Advantech
| pcm-5823
| NSC GX1
| NSC CS5530
| SMC FDC37B72X
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| Advantech
| pcm-9574
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Cocom
| voyager2
| NSC GX1
| NSC CS5530
| NSC PC97317
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| DigitalLogic
| smartcore-p3
|
|
|
|
|
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| DigitalLogic
| smartcore-p5
|
|
|
|
|
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Lanner
| [http://www.embedded-computing.com/products/search/fm/id/?10784 EM-370]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83977EF
| Intel® Pentium®III / Celeron®
| Slot 370
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| Lippert
| [http://web.archive.org/web/20031204180239/www.lippert-at.com/pc104plus.html Cool RoadRunner II]
| NSC GX1
| NSC CS5530
| SMC FDC37B72X
| NSC Geode GX1
| —
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Nano
| nano
| NSC GX1
| NSC SCX200
| ?
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| STMicroelectronics
| [http://mcu.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=75 STPC® Consumer-II]
| integrated
| integrated
| SMC FDC37B78X
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| STMicroelectronics
| [http://mcu.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=75 STPC® Elite]
| integrated
| integrated
| SMC FDC37B78X
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Supertek
| ST3-WT
| NSC GX1
| NSC CS5535
| NSC PC97317
| Geode
| ?
| style="background:lime" | OK ([[User:Stepan|SR]])
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| Technoland
| [http://web.archive.org/web/20040406003346/technoland.com/tl_embsbc710.htm TL-EmbSBC 710]
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| Winbond™ W83877EF
| Intel® Pentium® III / Celeron®
| Slot 1
| style="background:#eeeeee" | ?
| [[Technoland SBC 710|Tutorial]]
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Mini-ITX'''

|- bgcolor="#eeeeee"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21 EPIA]
| VIA VT8601
| VIA VT8231
| Winbond™ W83627HF
| VIA C3™ / EDEN™
| ?
| style="background:#eeeeee" | ?
| —
| style="background:lime" | Yes
|- bgcolor="#eeeeee"
| VIA
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81 EPIA-M]
| VIA VT8623
| VIA VT8235
| VIA VT1211
| VIA C3™ / EDEN™
| ?
| style="background:#eeeeee" | ?
| —
| style="background:lime" | Yes

|- bgcolor="#6699ff"
| colspan="10" | '''Set-top-boxes / Thin clients'''

|- bgcolor="#eeeeee"
| Lex
| [http://www.lex.com.tw:8080/product/CV860A.htm CV860A]
| VIA VT8601A
| VIA VT82C686B
| VIA VT82C686B
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| RCN
| Dc1100s
| VIA VT694
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#6699ff"
| colspan="10" | '''Devel/Eval Boards'''

|- bgcolor="#eeeeee"
| Motorola
| Sandpoint
| Motorola MPC107
| Winbond™ W83C553
| NSC PC97307
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:lime" | Yes

|- bgcolor="#6699ff"
| colspan="10" | '''Miscellaneous'''

|- bgcolor="#eeeeee"
| BCM
| e100
| SiS550
| SiS550
| ?
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| Dell
| 350
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMC FDC37B907
| ?
| Slot 1
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| irobot
| Proto1
| Intel® 440BX
| Intel® 82371EB (PIIX4E)
| SMS FDC37N769
| ?
| Slot 1
| style="background:#eeeeee" | ?
| —
| style="background:red" | No

|- bgcolor="#dddddd"
| SiS
| 540 (?)
| SiS540
| SiS540
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 550 (?)
| SiS550
| SiS550
| ?
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 635 (?)
| ?
| SiS635
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No
|- bgcolor="#dddddd"
| SiS
| 735 (?)
| SiS735
| SiS735
| SiS950
| ?
| ?
| style="background:#dddddd" | ?
| —
| style="background:red" | No

|- bgcolor="#eeeeee"
| VIA
| vt5292
| VIA VT8601
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|- bgcolor="#eeeeee"
| VIA
| vt5426
| VIA VT8601
| VIA VT82C686
| VIA VT82C686
| ?
| ?
| style="background:#eeeeee" | ?
| —
| style="background:red" | No
|}


1 Work in progress. 
2 http://www.linuxbios.org/pipermail/linuxbios/2002-October/000743.html 
3 http://www.linuxbios.org/pipermail/linuxbios/2003-September/005385.html 


__FORCETOC__

Datasheets

2009-08-08T10:11:05Z

Ward: /* Northbridge */ add links to AMD RS780 chipset docs

This page lists '''publically available datasheets''' and programming guides from various vendors. It includes CPU, chipset, Super I/O, and many other datasheets.

= CPU =

== AMD K8 ==

* AMD K8 BKDG (BIOS and kernel developer's guide) [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF revision E] and [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf revision F]

== AMD Fam10 ==

* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF AMD Fam10 BKDG] (BIOS and kernel developer's guide)

== VIA Padlock ==

* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=281 Security Application note]
* [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 PadLock Programming Guide]

= Northbridge =

== AMD RS690 ==

* [http://developer.amd.com/gpu_assets/43372_rs690_rrg_3.00o.pdf AMD RS690 RRG] (Register Reference Guide)
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41977_rs690_ds_3.06.pdf AMD RS690 Databook]
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41978_rs690m_ds_3.06.pdf AMD RS690M Databook]
* [http://support.amd.com/us/Embedded_TechDocs/42437_m690t_ds_3_08.pdf AMD M690T/E Databook]

== AMD RS780 ==

* [http://developer.amd.com/Assets/43291_rs780_rpr_pub_1.00.pdf AMD RS780 Register Programming Requirements]
* [http://developer.amd.com/Assets/43451_rs780_rrg_pub_1.00.pdf AMD RS780 ASIC Family Register Reference Guide]
* [http://developer.amd.com/Assets/43734_rs780_bdg_pub_1.00.pdf AMD RS780 ASIC Family BIOS Developer’s Guide]
* [http://developer.amd.com/assets/45732_rs780e_ds_pub_1.20.pdf AMD RS780E Databook]

== VIA CX700M/VX700 ==

* [http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 VIA CX700M/VX700 Programming Manual]

== VIA VX800 ==

* [http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241 VIA VX800 Programming Manual]

= Southbridge =

== AMD SB600 ==

* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf AMD SB600 RRG] (Register Reference Guide)
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46156_sb600_rpr_pub_3.02b.pdf AMD SB600 RPR] (Register Programming Requirements)
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46157_sb600_bdg_pub300.pdf AMD SB600 BDG] (BIOS Developer's Guide)
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/42119_sb600_ds_3.05.pdf AMD SB600 Databook]

== AMD SB700/SB710/SB750 ==

* [http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf AMD SB700/710/750 Register Reference Guide]
* [http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf AMD SB700/710/750 BIOS Developer’s Guide]
* [http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf AMD SB700/710/750 Register Programming Requirements]
* [http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf AMD SB710 Databook]

= Super I/O =

== ITE ==

* [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 PC Desktop/Notebook Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=5 Desktop Super I/Os]
** [http://www.ite.com.tw/EN/products_kind.aspx?CategoryID=3&ID=6 Notebook Super I/Os]

== Winbond / Nuvoton ==

* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/ISASuperIO/ ISA Super I/Os]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/LPCSuperIOforDesktopAndServer/ LPC Super I/O for Desktop & Server]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforDesktop/ Advanced Super I/O for Desktop]
* [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/SuperIO/AdvancedSuperIOforNotebook/ Advanced Super I/O for Notebook]

== Fintek ==

* [http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17&layer=0 Super Hardware Monitor + SIO]

== NSC ==

(bought by Winbond, now Nuvoton)

== ALi ==

== SMSC ==

* [http://www.smsc.com/main/catalog/ioprods.html Products / datasheets overview]
* [http://www.smsc.com/main/datasheet.html Various product datasheets]

= Other =

* [http://www.amd.com/us-en/Processors/TechnicalResources/1,,30_182_739,00.html AMD public documents]
** The [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_15872,00.html AMD64 Embedded Processors and Chipset Linux Support] web page features links to supported projects (like coreboot) and links to documentation.

= Resources =

There are many datasheet archives on the web which may have other (usually older) datasheets which already disappeared from vendor websites.

Supported Chipsets and Devices

2009-07-20T14:11:23Z

Ward: /* Devices supported in coreboot v2 */ add missing br

Note: If a device is not supported by coreboot v2, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] for support. Do '''not''' attempt to use coreboot v3 — this is an early development version which is not ready for production use, yet.

See also [[Supported Motherboards]].

== Devices supported in coreboot v3 ==

<div style="color: #ff0000">coreboot v3 is an alpha-stage development version of coreboot and is not meant for production use, yet!</div>

{| border="0" valign="top"
| valign="top"|

'''Northbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Northbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Geode LX
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| Geode K8
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| Intel®
| 82443BX (440BX)
| style="background:orange" | WIP
|- bgcolor="#dddddd" valign="top"
| Intel®
| 945
| style="background:orange" | WIP

|- bgcolor="#eeeeee" valign="top"
| VIA
| CN700
| style="background:orange" | WIP

|}

| valign="top"|

'''Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD-8111
| style="background:yellow" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD-8132
| style="background:yellow" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD-8151
| style="background:yellow" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5536
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| RS690
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB600
| style="background: lime " | OK

|- bgcolor="#dddddd" valign="top"
| Intel®
| 82371EB (PIIX4E)
| style="background:orange" | WIP
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82801GX (ICH7)
| style="background:orange" | WIP

|- bgcolor="#eeeeee" valign="top"
| NVIDIA
| MCP55
| style="background:orange" | WIP1

|- bgcolor="#dddddd" valign="top"
| VIA
| VT8237R
| style="background:orange" | WIP

|}

| valign="top"|

'''Super I/Os'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| VIA
| VT1211
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627HF
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627THG
| style="background:lime" | OK

|}

| valign="top"|

'''CPUs'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Type
! align="left" | CPU
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Geode LX
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| K8
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| Generic
| i586
| style="background:orange" | WIP

|- bgcolor="#eeeeee" valign="top"
| Intel
| Core Duo / Core 2 Duo
| style="background:orange" | WIP

|- bgcolor="#dddddd" valign="top"
| VIA
| C7
| style="background:orange" | WIP

|}

|}


1 MCP55 and CK804 are supported, but no open documents are available from NVIDIA.


== Devices supported in coreboot v2 ==

{| border="0" valign="top"
| valign="top"|

'''Northbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Northbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Fam10
| style="background:lime" | OK16
|- bgcolor="#eeeeee" valign="top"
| AMD
| K8
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| GX1
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| GX (GX2)
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| LX
| style="background: lime" | OK

|- bgcolor="#dddddd" valign="top"
| IBM
| CPC710
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| IBM
| CPC925
| style="background:#dddddd" | ?

|- bgcolor="#eeeeee" valign="top"
| Intel®
| E7501
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| E7520
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| E7525
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82810
| style="background:yellow" | WIP9
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82830
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82443BX ([http://developer.intel.com/design/chipsets/440bx/ 440BX])
| style="background:yellow" | WIP11
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82855PM
| style="background:red" | WIP2
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 3100
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 945
| style="background:lime" | OK

|- bgcolor="#dddddd" valign="top"
| Motorola
| MPC107
| style="background:#dddddd" | ?

|- bgcolor="#eeeeee" valign="top"
| SiS
| SiS761GX
| style="background:lime" | OK

|- bgcolor="#dddddd" valign="top"
| VIA
| VT8601 (PLE133)
| style="background:yellow" | WIP
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8623 (CLE266)
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| K8T890
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| K8M890
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| CN700
| style="background:lime" | OK14
|- bgcolor="#dddddd" valign="top"
| VIA
| CX700
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| VIA
| VX800
| style="background:yellow" | WIP

|}

| valign="top"|

'''Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8111
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8131
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8132
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD8151
| style="background: lime" | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5530/CS5530A
| style="background:yellow" | WIP
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5535
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| AMD
| CS5536
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| RS690
| style="background: lime " | OK
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB600
| style="background: lime " | OK

|- bgcolor="#dddddd" valign="top"
| Broadcom
| BCM5780
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Broadcom
| BCM5785
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| Intel®
| 6300ESB (ESB6300)
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82371EB (PIIX4E)
| style="background:yellow" | WIP6
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801AA/AB (ICH/ICH0)
| style="background:lime" | OK10
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801BA/BAM (ICH2/ICH2-M)
| style="background:lime" | OK10
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801CA/CAM (ICH3-S/ICH3-M)
| style="background:lime" | OK10
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)
| style="background:lime" | OK10
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801EB/ER (ICH5/ICH5R)
| style="background:lime" | OK10
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82870
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| PXHD
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 3100
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background:lime" | OK

|- bgcolor="#dddddd" valign="top"
| NVIDIA
| CK804
| style="background:lime" | OK17
|- bgcolor="#dddddd" valign="top"
| NVIDIA
| MCP55
| style="background:lime" | OK17

|- bgcolor="#eeeeee" valign="top"
| Ricoh
| RL5C476
| style="background:#eeeeee" | ?

|- bgcolor="#dddddd" valign="top"
| SiS
| SiS966(L)
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8231
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8235
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8237R
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8237A
| style="background:red" | WIP
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8237S
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT82C686
| style="background:lime" | OK

|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83C553
| style="background:#dddddd" | ?

|}

| valign="top"|

'''Super I/Os'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| ASUS
| A8000
| style="background:lime" | 12, 13

|- bgcolor="#dddddd" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | OK

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8661F
| style="background:yellow" | OK 1
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8671F
| style="background:yellow" | OK 1
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8673F
| style="background:yellow" | OK 1
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8705F
| style="background:yellow" | OK 1
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8712F
| style="background:lime" | OK 8
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F
| style="background:yellow" | OK 1

|- bgcolor="#dddddd" valign="top"
| Intel®
| 3100
| style="background:lime" | OK 15
|- bgcolor="#dddddd" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background:lime" | OK 15

|- bgcolor="#eeeeee" valign="top"
| NSC
| PC8374
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87309
| style="background:yellow" | OK 5
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87351
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87360
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87366
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87417
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87427
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97307
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97317
| style="background:#eeeeee" | ?

|- bgcolor="#dddddd" valign="top"
| ServerEngines
| PILOT
| style="background:yellow" | OK18

|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37M70x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B80x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B78x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B72x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37B81x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| FDC37M60x
| style="background:lime" | OK3,12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47B27x
| style="background:lime" | OK7,12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M10x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M112
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M13x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M15x
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47M192
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47B397
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| DME1737
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| SCH5307
| style="background:lime" | OK12
|- bgcolor="#dddddd" valign="top"
| SMSC®
| LPC47N217
| style="background:#dddddd" | ?

|- bgcolor="#eeeeee" valign="top"
| VIA
| VT1211
| style="background:#eeeeee" | ?
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT82C686(A/B)
| style="background:yellow" | OK5

|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627DHG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627UHG
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627EHG/HF/EHF/THF
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83697HF/HG
| ?
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627THF
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83627THG
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83977F
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83977TF
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83977EF
| style="background:lime" | OK4
|}

| valign="top"|

'''CPUs'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Type
! align="left" | CPU
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| x86
| AMD
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| x86
| Intel®
| style="background:lime" | OK
|- bgcolor="#eeeeee" valign="top"
| x86
| VIA
| style="background:lime" | OK
|- bgcolor="#dddddd" valign="top"
| PowerPC
| MPC74xx
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| PowerPC
| PPC4xx
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| PowerPC
| PPC7xx
| style="background:#dddddd" | ?
|- bgcolor="#dddddd" valign="top"
| PowerPC
| PPC970
| style="background:#dddddd" | ?
|- bgcolor="#eeeeee" valign="top"
| Emulated
| QEMU
| style="background:lime" | OK
|}

'''SOCs'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | SOC
! align="left" | Status

|- bgcolor="#eeeeee" valign="top"
| AMD
| Elan SC520
| style="background: lime" | OK
|- bgcolor="#dddddd" valign="top"
| Intel®
| EP80579 (Tolapai)
| style="background: lime" | OK
|}

|}


1 Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested. 
2 Work in progress. 
3 Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602). 
4 The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least). 
5 Pre-RAM serial output works fine, but nothing else, yet. 
6 IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list. 
7 Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested. 
8 [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work. 
9 Works mostly, but currently there are some limitations as to which RAM DIMMs can be used. 
10 These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore. 
11 Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish. 
12 All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though. 
13 The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737. 
14 Working, but not widely tested, yet. Works with single DIMM DDR2. 
15 The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far. 
16 Barcelona B0-B3 supported. 
17 MCP55 and CK804 are supported, but no open documents are available from NVIDIA. 
18 Partially supported, but not all features implemented.


== Devices supported in coreboot v1 ==

Not all devices have been ported from coreboot v1 to coreboot v2, yet (check "v2?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].

{| border="0" valign="top"
| valign="top"|

'''Northbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Northbridge
! align="left" | Status
! align="left" | v2?

|- bgcolor="#eeeeee" valign="top"
| Acer
| M1631
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Alpha
| Tsunami
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| AMD
| AMD76x
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 430TX
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 440BX
| style="background:#dddddd" | ?
| style="background:yellow" | Yes3
|- bgcolor="#dddddd" valign="top"
| Intel®
| 440GX
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82815EP
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82830
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| 82860
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7500
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7501
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| Intel®
| E7505
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Micron
| 21PAD
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Motorola
| MPC107
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC/AMD
| GX1
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| VIA
| VT694
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8601
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8623
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|}

| valign="top"|

'''Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status
! align="left" | v2?

|- bgcolor="#eeeeee" valign="top"
| Acer
| M1535
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Acer
| M1543
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| AMD
| AMD766
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| AMD
| AMD768
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801CA
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82801DB
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| 82870
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Intel®
| PIIX4E
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| NSC/AMD
| CS5530
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| NSC
| SCX200
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8231
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT8235
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| VIA
| VT82C686
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| Winbond™
| W83C553
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|}

| valign="top"|

'''Super I/Os'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Status
! align="left" | v2?

|- bgcolor="#eeeeee" valign="top"
| Acer
| M1535
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87309
| style="background:lime" | OK
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC87351
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97307
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| NSC
| PC97317
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| SiS
| 950
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37B72X
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37B78X
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37B807
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37C669
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37C67X
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| SMC
| FDC37N769
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| VIA
| VT1211
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#dddddd" valign="top"
| VIA
| VT8231
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686
| style="background:#dddddd" | ?
| style="background:yellow" | Yes2
|- bgcolor="#eeeeee" valign="top"
| Winbond™
| W83627HF
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| Winbond™
| W83877TF
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| Winbond™
| W83977EF
| style="background:#eeeeee" | ?
| style="background:lime" | Yes1
|}

| valign="top"|

'''North-/Southbridges'''

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | North/South
! align="left" | Status
! align="left" | v2?

|- bgcolor="#eeeeee" valign="top"
| NSC
| SCX200
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 540
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 550
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 630
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 635
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 730
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| SiS
| 735
| style="background:#dddddd" | ?
| style="background:red" | No
|- bgcolor="#eeeeee" valign="top"
| ST
| STPC
| style="background:#eeeeee" | ?
| style="background:red" | No
|}

'''CPUs'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Type
! align="left" | CPU
! align="left" | Status
! align="left" | v2?

|- bgcolor="#eeeeee" valign="top"
| Alpha
| EV6
| style="background:#eeeeee" | ?
| style="background:red" | No
|- bgcolor="#dddddd" valign="top"
| PowerPC
| ?
| style="background:#dddddd" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| x86
| AMD
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| x86
| Intel®
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|- bgcolor="#eeeeee" valign="top"
| x86
| VIA
| style="background:#eeeeee" | ?
| style="background:lime" | Yes
|}

|}


1 The W83977EF works fine with the W83977TF code in coreboot v2 (the pre-RAM serial part at least). 
2 Pre-RAM serial output works in coreboot v2, but the rest is not supported, yet. 
3 Work in progress. 


__FORCETOC__

SeaBIOS

2009-04-25T23:49:37Z

Ward: /* coreboot */

'''SeaBIOS''' (previously known as '''LegacyBIOS''') is an open-source legacy BIOS implementation, which can also be used as coreboot [[Payloads|payload]].

= Use cases =

Any software requiring 16-bit BIOS services benefits from SeaBIOS.

== Windows XP ==

Windows XP has been booted on real hardware with coreboot and SeaBIOS. Some patches are required.

== Windows Vista ==

Windows Vista (64/32 bit) has been booted on real hardware with coreboot and SeaBIOS. Some patches are required.

== Windows 7 Beta ==

Windows 7 Beta (?? bit) has been booted on real hardware with coreboot and SeaBIOS. Some patches are required.

== GRUB ==

GRUB works with coreboot and SeaBIOS on real hardware and boots Linux just fine.

= Building =

== SeaBIOS ==

You can download the latest version of SeaBIOS through a git repository:

<source lang="bash">
$ git clone git://git.linuxtogo.org/home/kevin/seabios.git seabios
$ cd seabios
</source>

Alternatively, the released versions of SeaBIOS can be found at http://linuxtogo.org/~kevin/SeaBIOS/. There's also a [http://git.linuxtogo.org/?p=kevin/seabios.git;a=summary gitweb] facility to browse the latest source code online.

Edit '''src/config.h''' and set the following values:

<source lang="C">
#define CONFIG_COREBOOT 1
#define CONFIG_DEBUG_SERIAL 1
#define CONFIG_OPTIONROMS_DEPLOYED 0
#define CONFIG_COREBOOT_FLASH 1
#define CONFIG_VGAHOOKS 1
</source>

Then:

<source lang="bash">
$ make
</source>

The final SeaBIOS payload file is '''out/bios.bin.elf''', which can be used with coreboot v2 or v3.

== coreboot ==

For best results, use coreboot-v2 and edit the target Config.lb with the following:

option CONFIG_CBFS=1
option HAVE_HIGH_TABLES=1
...
romimage "fallback"
...
payload /path/to/seabios/out/bios.bin.elf
end

Unfortunately, many boards don't have HAVE_HIGH_TABLES support yet. If the build fails complaining about this option, one can edit the src/mainboard/<vendor>/<board>/Options.lb file and add a "uses HAVE_HIGH_TABLES" line. Then one can edit src/arch/i386/boot/tables.c and change the lines:

<source lang="C">
uint64_t high_tables_base = 0;
uint64_t high_tables_size;
</source>

to:

<source lang="C">
uint64_t high_tables_base = ( <memorysize> )*1024*1024 - (64*1024);
uint64_t high_tables_size = 64*1024;
</source>

where <memorysize> is the amount of memory (in MiB) available on the target machine, but not more than 3072. So, if you have more than 3GiB of ram installed, put 3072. Otherwise, put the number of MiB of ram installed in your machine.

Alternatively, one can add proper support for HAVE_HIGH_TABLES.

Once the above is done, the final image will be in '''coreboot.rom'''.

= SeaBIOS and CBFS =

SeaBIOS can read the coreboot flash filesystem and extract option roms and payloads.

== Adding a VGA option rom ==

Once a '''coreboot.rom''' file has been prepared, one can add option roms to it. It is frequently necessary to add a vga option rom for built-in VGA adapters so that they are properly initialized.

The first step is to find the vendor and device id of the VGA adapter. This information can be found from '''lspci''':

<source lang="bash">
$ lspci -vnn
...
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP [1106:3344] (rev 01) (prog-if 00 [VGA controller])
</source>

In the above example, the VGA vendor/deviceid is "1106:3344". [[VGA_support#How_to_retrieve_a_good_video_bios|Obtain the vga rom]] (eg, vgabios.bin) and add it to the rom with:

<source lang="bash">
$ ./cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom 0
$ ./cbfstool coreboot.rom print
</source>

After the above is done, one can write the coreboot.rom file to flash. SeaBIOS will extract the vga rom and run it during boot.

== Adding gpxe support ==

A [[http://www.etherboot.org/ gpxe]] option rom can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option rom]]. The first step is to find the ethernet vendor/device id. For example:

<source lang="bash">
$ lspci -vnn
...
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet [10ec:8167] (rev 10)
</source>

Then one can build a gpxe option rom. For example:

<source lang="bash">
$ cd gpxe/src/
$ make bin/10ec8167.rom
</source>

And add it to the coreboot image. For example:

<source lang="bash">
$ ./cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom 0
$ ./cbfstool coreboot.rom print
</source>

In addition to gpxe, other option roms can be added in the same manor.

== Adding payloads ==

Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the "img/" directory. For example:

<source lang="bash">
$ ./cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload
$ ./cbfstool coreboot.rom print
</source>

During boot, one can press the F12 key to get a boot menu. SeaBIOS will show all files in the "img/" directory, and one can instruct SeaBIOS to run them.

Note, SeaBIOS currently only supports uncompressed payloads.

FlexyICE

2009-04-11T00:58:25Z

Ward:

[[Image:artec_dongle.jpg|thumb|right|Artecgroup programmable LPC dongle.]]

== About the dongle ==

The dongle is for sale by [http://www.artecgroup.com/products/hardware-products/programmable-lpc-dongle.html Artecgroup], based in Estonia. It costs about EUR 150 (2007-12).

The dongle connects to a computer via USB. It connects to the target via an LPC header.

The dongle comes with [http://opencores.org/projects.cgi/web/usb_dongle_fpga/overview free software and full schematics] (scroll all the way to the bottom for download links, or click on the CVS: browse link near the top). The host-based software is written in Python, and works just fine under GNU/Linux.

The dongle has 16 MByte of onboard memory, divided in 4 banks of 4 Mbyte each. The 'mode-selection' jumpers allow selection of each bank: 00, 01, 10, 11.

The dongle also has two 16-segment LED displays that can show POST codes.

If you hold the reset button on the dongle, the second LED will show the version of the VHDL you have - currently 03, 04 or 05.

Artecgroup provides [http://opencores.org/cvsweb.shtml/usb_dongle_fpga/release/EPCS_update_tool.zip a tool] to upgrade the VHDL on the dongle that can be run under GNU/Linux (it's a python program). They also provide the binary image for the v5 of the VHDL. Of course all sources are available to build that binary image, but currently proprietary software on Windows is needed to do so. You will need a byteblaster-II cable (which can be purchased at http://www.customcircuitsolutions.com/cable.html or http://fpgaguy.110mb.com/, for instance). This tool has only received limited testing, so please be careful and report any problems to the author.

== Using the dongle ==
=== Drivers for Windows and Mac OS ===
The dongle can be accessed using its usb-to-serial chip (FT245B(M)). For Windows and Mac OS, you need a driver for the chip, which can be found at the [http://www.ftdichip.com/Drivers/VCP.htm chip vendor's website].

=== Reading from and writing to the dongle ===

If you use Ubuntu, make sure to uninstall brltty (apt-get remove brltty --purge) before you hook up the dongle; otherwise it will hijack the dongle and you won't be able to talk to it. Brltty is a software braille terminal.

Images are downloaded via USB. With the latest version of the VHDL (v5), it should take about 8 seconds to write a 512KByte image to the dongle.

Here's a command that writes a 512KByte image to the dongle

./dongle.py -v -c /dev/ttyUSB0 alix0-1.bin 3584K

The -v parameter makes the command verbose. -c /dev/ttyUSB0 means 'use device /dev/ttyS0'. Alix0-1.bin is the image that is to be written to the dongle (it's a 512KByte file), and 3584K is the offset at which it should be written. Always calculate that number as 4Mbyte - size of your image.

And here's how you can read the image back:

./dongle.py -c /dev/ttyUSB0 -r 3670016 512K test2.rom

The -r parameter indicates 'read', and 3670016 is the offset at which the program should start reading (this is 3584K), for 512K bytes. You can express the offset in decimal (like in this example, in hex with a leading 0x, or in abbreviated decimal - for instance 3584K). Test2.rom is the file the image will be stored in on your computer.

If you actually wrote and read an image, you should now md5sum both files to make sure they are identical.

=== Booting an ALIX.1C ===

First of all, you'll need to make a custom cable. The ALIX.1C has a 20-pin header (J16) that can be used to hook up the dongle. The pin layout is documented on page 13 and 14 in the [http://pcengines.ch/pdf/alix1c.pdf ALIX.1C manual]:

<pre>
1 LCLK0 LPC clock (33 MHz)
2 GND ground
3 LAD0 LPC data 0
4 GND ground
5 LAD1 LPC data 1
6 GND ground
7 LAD2 LPC data 2
8 GND ground
9 LAD3 LPC data 3
10 GND ground
11 LFRAME# LPC frame
12 GND ground
13 PCIRST# reset (active low)
14 NC reserved
15 ISP high to use LPC flash, low to use on-board flash, pulled low by resistor
16 VCC +5V supply
17 GND ground
18 V3 +3.3V supply
19 SERIRQ serial interrupt
20 LDRQ# LPC DMA request
</pre>

The Artecgroup LPC dongle has a 10-pin LPC dongle that is described [http://www.artecgroup.com/downloads/task,doc_download/gid,5/Itemid,33/ in the schematics]. This is the pin layout:

<pre>
1 RESETX
2 LAD0
3 LAD1
4 LAD2
5 LAD3
6 LFRAME#
7 R33 GND
8 PCICLK1
9 GND
10 VCC 3V in
</pre>

Peter Stuge figured out the correct wiring [http://www.coreboot.org/pipermail/coreboot/2007-December/028011.html here] and [http://www.coreboot.org/pipermail/coreboot/2007-December/028012.html here]. This is the wiring diagram:

<pre>
Dongle - ALIX.1C

1 - 13
2 - 3
3 - 5
4 - 7
5 - 9
6 - 11
7 - NC
8 - 1
9 - 2/4/6/8/10/12/17 (just pick one)
10 - NC
- 15 connected to 18
</pre>

In the above, pin 7 on the dongle should not be connected to anything on the ALIX.1C. Pin 9 on the dongle should be connected to one of 2/4/6/8/10/12/17 on the ALIX.1C, not all of those pins. Pin 15 and 18 on the ALIX.1C side need to be shorted, but not connected to anything on the dongle side.

Cable length is important - your cable should not be more than a few centimeter long.

The easiest way to make such a cable is to take an old floppy or IDE-40 flat ribbon cable (don't use IDE-80, its wires are much thinner which makes things harder), cut it, and put a 10-pin header on the dongle side.

If you are in the US, you can buy 10-pin headers [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=32492&productId=32492 here] (Jameco part number 32492). You might also want to get [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=73252&productId=73252 a crimping tool] (Jameco part number 73252).

This is what a finished cable looks like:

[[Image:Dscn3151_640_480.jpg||Custom ALIX.1C to Artecgroup LPC dongle cable]]

You can test your cable by booting the ALIX.1C, and then hooking it up to the dongle (using J16 on the ALIX.1C, of course). Now reboot the ALIX.1C board; the LEDs on the dongle should show post codes as the ALIX.1C shuts down and tries to boot. Unless you've prepared the dongle and stored an image into it, the ALIX.1C will not boot. But if you see POST codes on the LEDs, your cable is likely to be good. If not, use a multimeter and make sure it matches the layout above. Also make sure that it is not too long.

Now make sure the dongle is correctly configured:

Jump pin 1/2 on J1. Make sure JMP4 is set to position 1/2 (i.e. NOT to the pins marked as LPC). Make sure that you leave the mode select jumpers in the same position between the writing of the image into the dongle and trying to boot off it.

Now write your image to the top of the memory bank you want to use (see higher). Then disconnect the dongle from your computer, reconnect it, make sure that you have your cable connected to the LPC port on the dongle and J16 on the ALIX.1C, and plug in power to the ALIX.1C. Also hook up a serial port to the ALIX.1C so that you see what happens during boot. If all goes well, you will see post codes on the dongle LEDs as the ALIX.1C boots.

=== Booting FWH PLCC boards ===

It is also possible to boot FWH PLCC boards, if you make a special cable. For an example of such a cable, see some photos here: http://www.artecdesign.ee/~martr/dongle-fwh-plcc-cable/. TODO: we need to find a place to buy such a connector, and we need to document the pinout of the cable.

=== Booting SPI boards ===

With a VHDL change and the proper cable, it should be possible to use the dongle to boot SPI-based boards. Artec is considering this as a planned feature for [http://www.opencores.org/projects.cgi/web/artec_dongle_ii_fpga/overview Artec Dongle II] VHDL - when that is done, interested parties can try to backport the relevant open source VHDL parts.

{{GPL}}

File:Plcc-legs-cut-off-on-two-sides.jpg

2009-03-31T15:44:04Z

Ward: moved File:Plcc-pins-cut-off-on-two-sides.jpg to File:Plcc-legs-cut-off-on-two-sides.jpg

PLCC chip - legs cut off on two sides.

Author: [[User:Ward|Ward Vandewege]]

{{PD-self}}

Soldering a socket on your board

2009-03-31T13:16:51Z

Ward: /* Cutting the chip */ add some pictures

Mainboards where the BIOS chip is soldered onto the board (i.e., not in a socket) are usually problematic for coreboot developers and especially coreboot users, as one incorrectly flashed image will render the board unusable.

Here's a simple procedure how you can desolder/remove the chip from such a board, and '''solder on a PLCC socket''' instead (so that you can swap chips as often as you like later on).

Important: This will definitely void the warranty of your board! Also, we take no responsibility for any damage you inflict on your board or other stuff. Use at your own risk!

That said, we believe this procedure requires only relatively '''low-cost equipment''' which is widely available, and '''can also be performed by people without much soldering experience'''. You do '''not''' have to be a hardware/soldering guru to do any of this, with a little practice everyone can learn to perform the procedure.

== Video ==

[[User:Uwe|Uwe Hermann]] created a video showing most of the steps in this HOWTO. You can get it from:

* [http://www.archive.org/details/CorebootHackingHowToSolderAPlccSocketOnYourBoard archive.org]: [http://www.archive.org/download/CorebootHackingHowToSolderAPlccSocketOnYourBoard/coreboot_hacking_how_to_solder_a_plcc_socket_on_your_board_small.ogv Ogg Theora, small] (32 MB), [http://www.archive.org/download/CorebootHackingHowToSolderAPlccSocketOnYourBoard/coreboot_hacking_how_to_solder_a_plcc_socket_on_your_board.ogv Ogg Theora] (154 MB)
* [http://www.youtube.com/watch?v=30x4oxyczH4 Youtube]: Direct download via "'''youtube-dl -t 'http://www.youtube.com/watch?v=30x4oxyczH4''''" (FLV, 13 MB)
* [http://blip.tv/file/1933817 blip.tv]: [http://blip.tv/file/get/UweHermann-CorebootHackingHowToSolderAPLCCSocketOnYourBoard919.flv FLV, small] (20 MB)

The video is licensed under the '''Creative Commons Attribution-ShareAlike 3.0''' license.

<gallery>
File:Desoldering video 1.jpg
File:Desoldering video 3.jpg
File:Desoldering video 2.jpg
File:Soldering the socket.jpg
File:Desoldering video 4.jpg
File:Desoldering the chip.jpg
File:Place plcc socket.jpg
File:Test the socket.jpg
</gallery>

== Requirements ==

* A board with soldered-on PLCC chip (a similar procedure will likely work for DIP32 or DIP8 chips).
* A soldering iron, solder, and soldering wick.
** Optional: No Clean Flux ("Flussmitteldispenser" in German) for easier soldering.
* A PLCC socket (SMD type).
* A [http://www.aoyue.de/en/Aoyue_852_hot_air_rework_repair_system_smd_esd_safe.htm desoldering station] / heat gun (or a [http://hmcelectronics.com/cgi-bin/scripts/query.cgi?query=+%09+TR20M cutter]).
** Optional: [http://aoyue.de/en/Aoyue_939_Vacuum_pickup_smd_rework.htm Vacuum suction pen] for holding/dragging the chip
* Tweezers.
* Wire cutter.

<gallery>
File:Soldered plcc rom chip.jpg|Soldered PLCC chip
File:Soldering iron.jpg|Soldering iron
File:Solder.jpg|Solder
File:Desoldering wick.jpg|Desoldering wick
File:Plcc socket.jpg|PLCC socket, front
File:Plcc socket back side.jpg|PLCC socket, back
File:Desoldering station.jpg|Cheap desoldering station
File:Desoldering station accessories.jpg|Desoldering accessories
File:Tweezers.jpg|Tweezers
File:Pliers1.jpg|Wire cutter
File:Flussmitteldispenser.jpg|No Clean Flux
</gallery>

The desoldering station used here is an [http://www.aoyue.de/en/Aoyue_852_hot_air_rework_repair_system_smd_esd_safe.htm Aoyue 852 SMD Rework Station], which is available relatively cheaply (ca. 70.- Euros). There are even cheapers ones available, e.g. on eBay.

== Preparation ==

* Take a picture of the board and ROM chip. You might need that later in order to add the socket in the correct orientation. The ROM chips all have a marking where the top is (and the same is true for most boards), but on '''some''' boards there is no such marking. So write down the orientation of the chip (or take a picture).
* Prepare the PLCC socket, by cutting away the plastic middle part using the wire cutter (for easier soldering later):

<gallery>
File:Pliers1.jpg|Wire cutter and PLCC socket
File:Cutting the plastic from the plcc socket.jpg|Cut the middle part
File:Pliers2.jpg|Socket and removed plastic
File:Plcc socket back side without plastic.jpg|Prepared socket, back side
</gallery>

== Desolder or cut away the ROM chip ==

The next step is to remove the soldered ROM chip. There are multiple ways to do that.

=== Desoldering the chip using a desoldering station ===

If you have access to a desoldering station use that for desoldering the chip. Use a temperature of ca. 350-370°C. Higher temperatures might speed up the process a bit, but will also increase the risk of damaging the chip or surrounding parts. At 370°C the process takes less than 20 seconds.

* Advantages:
** Quick and painless method.
** The ROM chip will usually survive, if you're careful and don't supply too much heat.
* Disadvantages:
** You have to spend some money on a desoldering station (less than 70,- Euros).
** The surrounding chips, resistors, etc. might get too hot if you're not careful (usually doesn't happen, though).

<gallery>
File:Soldered plcc rom chip.jpg|Soldered PLCC chip
File:Desoldering station temperature.jpg|Desoldering temperature
File:Holding dragging the chip with tweezers.jpg|Hold the chip with tweezers
File:Desoldering the chip.jpg|Desoldering the chip
File:Pads after desoldering.jpg|PCB pads after desoldering
File:Rom chip desoldered front.jpg|Desoldered chip, front
File:Rom chip after desoldering.jpg|Desoldered chip, back
</gallery>

=== Desoldering the chip using a heat gun and aluminum foil ===

You can also use a piece of aluminum foil and a house hold heat gun for desoldering the chip. Most heat guns have a high and low setting, you will only need the low setting. The whole process only takes a few minutes. Blow the heat at an angle to the side of the chip at the solder joints going around the chip in a circle (never directly on top).

* Advantages:
** Fairly quick and painless as long as you don't burn yourself.
** The ROM chip will usually survive, if you're careful and don't supply too much heat.
* Disadvantages:
** You have to be very careful not to pull on the chip. You could lift a solder pad causing a whole other issue.
** The foil can get pretty hot!

<gallery>
File:Foil-hgun1.jpg|Aluminum foil folded in half (double protection).
File:Foil-hgun2.jpg|Bend the foil over the chip for cut out lines.
File:Foil-hgun3.jpg|Cut out a chip-sized rectangle.
File:Foil-hgun4.jpg|Foil with chip cut out.
File:Foil-hgun5.jpg|Place the foil over the chip.
File:Foil-hgun6.jpg|Close up of foil over chip.
File:Foil-hgun7.jpg|Blow the heat at an angle to the chip's side.
File:Foil-hgun8.jpg|Soon the chip will fall off. Use tweezers to remove.
File:Foil-hgun9.jpg|Foil and chip removed.
File:Foil-hgun10.jpg|Foil and chip.
File:Foil-hgun11.jpg|Clean the pads, solder on the socket.
</gallery>

=== Cutting the chip ===

Alternatively, you can just cut away the chip with a proper cutter (e.g. the [http://hmcelectronics.com/cgi-bin/scripts/query.cgi?query=+%09+TR20M Hakko CHP Ergonomic Micro Cutter]). Make sure to cut as close to the packaging as possible, so as to minimize strain on the paths on the motherboard while the chip is being cut off.

* Advantages:
** No desoldering station required.
** Surrounding chips, capacitors, etc. are not at risk from a heat gun.
* Disadvantages:
** Cutting the chip is a bit tedious.
** The chip is rendered unusable in the process (so make sure you have a backup before cutting it).

<gallery>
File:Plcc-pins-cut-off-on-two-sides.jpg|Legs cut off on two sides.
File:Plcc-only-legs-remain.jpg|Chip removed. Only the legs remain.
File:Plcc-no-legs.jpg|The PLCC chip with the legs cut off.
</gallery>

== Clean the pads on the board ==

The next step is to clean the PCB pads, i.e., remove the remains of solder from the pads. Use desoldering wick for that.

<gallery>
File:Pads after desoldering.jpg|Pads before cleaning
File:Pads cleaning.jpg|Cleaning with desoldering wick
File:Pads after cleaning.jpg|Cleaned pads
</gallery>

== Solder the socket onto the board ==

Now solder the PLCC socket onto the pads. This procedure is best performed manually with a soldering iron (in theory you could try to use a desoldering station / heat gut, but the results are probably not too good, and you might melt the plastic socket). Optionally, if you have some No Clean Flux handy, apply some of it on the pads. This will make the soldering process a bit easier.

We suggest to start by aligning the socket onto the pads with tweezers or with your fingers. Solder two pins in opposite corners of the socket first, in order to fixate the socket. Then solder all the other pins, one after the other. If you apply too much solder and two or more pins get connected accidentally, use the soldering wick to fix that.

<gallery>
File:Prepare two pads.jpg|Put solder on a pad
File:Prepare two pads2.jpg|Put solder on another pad
File:Fixating the socket on the pads.jpg|Aligning, tweezers
File:Place plcc socket.jpg|Aligning, fingers
File:Soldering the socket.jpg|Soldering the socket
File:Plcc socket soldered.jpg|Soldered-on socket
File:Test the socket.jpg|Testing the socket
File:Socket with chip.jpg|Socket with chip
</gallery>

== Tips ==
To keep your ROM chip from pushing in too far and possibly touching the wrong solder joint, you can use a small piece of single sided adhesive felt or thin foam. Cut out a small rectangle just big enough to fit into the opening of your PLCC Socket and stick it in the bottom of the socket against the PCB. Another tip is to place a small drop of super glue on each corner of the outside of the PLCC Socket. This helps your newly installed socket from lifting (causing damage to the solder pads) when you remove the ROM chip, which is a good idea if you are swapping out your ROM chip frequently.

== Results ==

Congratulations. You have now successfully replaced a soldered-on PLCC ROM chip on your board with a PLCC socket. You can now swap out the ROM chip as often as you want to or need to. In almost all cases, the board '''and''' the ROM chip will survive this procedure if you are careful.

== Further resources ==

* [http://ward.vandewege.net/blog/2009/03/howto-replace-a-plcc-chip-with-a-socket-ghetto-style/ HOWO: replace a PLCC chip with a socket "ghetto style"] (tutorial for doing this without desoldering station by cutting the chip)
* [http://hermann-uwe.de/blog/coreboot-hacking-how-to-solder-a-plcc-socket-on-your-board Coreboot hacking: How to solder a PLCC socket on your board] (blog post)

{{PD-self}}

File:Plcc-no-legs.jpg

2009-03-31T13:11:44Z

Ward: PLCC chip with the legs cut off. Note how I cut as close to the chip packaging as possible. Author: Ward Vandewege {{PD-self}}

PLCC chip with the legs cut off. Note how I cut as close to the chip packaging as possible.

Author: [[User:Ward|Ward Vandewege]]

{{PD-self}}

File:Plcc-only-legs-remain.jpg

2009-03-31T12:56:29Z

Ward: The PLCC chip was removed from the motherboard, only the legs remain. Author: Ward Vandewege {{PD-self}}

The PLCC chip was removed from the motherboard, only the legs remain.

Author: [[User:Ward|Ward Vandewege]]

{{PD-self}}

File:Plcc-legs-cut-off-on-two-sides.jpg

2009-03-31T12:52:38Z

Ward:

PLCC chip - legs cut off on two sides.

Author: [[User:Ward|Ward Vandewege]]

{{PD-self}}

File:Plcc-legs-cut-off-on-two-sides.jpg

2009-03-31T12:51:44Z

Ward:

Soldering a socket on your board

2009-03-27T03:10:45Z

Ward: typo

Memtest86

2009-03-18T21:30:39Z

Ward:

[[Image:Qemu memtest.png|thumb|right|The [[Memtest86]] payload.]]

'''[http://www.memtest86.com/ Memtest86]''' is a program which checks your RAM modules.

It can be run from within GRUB, but also as a coreboot payload (i.e. included in your ROM chip).

== Building ==

=== Memtest86 ===

mkdir foo
cd foo
wget http://www.memtest86.com/memtest86-3.5.tar.gz
tar xfvz memtest86-3.5.tar.gz
cd memtest86-3.5
(Optional: edit '''config.h''' and set '''#define SERIAL_CONSOLE_DEFAULT 1''' for serial support)
make

The file '''memtest''' is your final payload which you can use with coreboot (v2 or v3), either on real hardware or in a QEMU image.

=== coreboot ===

Finally, you have to build coreboot (v3 in this example) with Memtest86 as payload:

cd ..
svn co svn://coreboot.org/repository/coreboot-v3 '''-r656'''
cp memtest86-3.4/memtest coreboot-v3/payload.elf
cd coreboot-v3
make menuconfig

Now enter the '''Payload''' menu and select '''Payload type''' and then '''An ELF executable payload file'''. Now exit the menu, save your settings, and build coreboot:

make

The file '''build/coreboot.rom''' (or '''build/bios.bin''') is your final coreboot v3 image, which also contains the payload.

== Running Memtest86 in QEMU ==

For running the coreboot+Memtest86 image in QEMU, you need a patched version of '''vgabios-cirrus.bin''' in your '''build''' directory first:

cd build
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Vgabios-cirrus.zip
cd ..

You can now run coreboot and Memtest86 in QEMU:

qemu -L build -hda /dev/zero -serial stdio

== Ready-made QEMU image ==

Please follow [http://www.coreboot.org/QEMU#coreboot_v3_.2B_Memtest86 these instructions] if you want to try out coreboot and Memtest86 in [[QEMU]].

{{PD-self}}

GSoC

2009-03-16T00:45:15Z

Ward: /* USB Option ROM for SeaBIOS */

= Google Summer of Code 2009 =

http://code.google.com/images/2009socwithlogo.gif

Welcome to the [http://code.google.com/soc/ Google Summer of Code(tm)] page of the [[Welcome to coreboot|coreboot project]].

= Your own Projects =

We have come up with some ideas for cool Summer of Code projects here. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases.

But of course your application does not need to be based on any of the ideas listed below. The opposite: Maybe you have a great idea that we just didn't think of yet. Please let us know!

Feel free to contact us at the email address below, and don't hesitate to suggest whatever you have in mind.

= Possible ideas =

== Infrastructure for automatic code checking ==

We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
* Use LLVM's static code checking facilities, report regressions.
* Work on code coverage support for coreboot code (dump data into ram, or via serial. Provide tools to fetch it). Analyse that data.

=== Links ===
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker]
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]

=== Mentors ===
* [[User:PatrickGeorgi|Patrick Georgi]]
* [[User:MJones|Marc Jones]]
* [[User:Stepan|Stefan Reinauer]]

== VGA BIOS for Geode LX ==

This project's goal is to write a VGA BIOS (PCI option rom) for AMD Geode LX systems (such as the Linutop, Thincan or XO). There exists a [http://savannah.nongnu.org/projects/vgabios free VGA BIOS] but it knows nothing about real hardware. If you really want to kick the iron, this project could be enhanced to contain a complete infrastructure for including hardware initialization code for many different graphics cards.

=== Links ===
* [http://savannah.nongnu.org/projects/vgabios free VGA BIOS]

=== Mentors ===
* [[User:Ward|Ward Vandewege]]
* [[User:Stepan|Stefan Reinauer]]
* [[User:MJones|Marc Jones]]

== USB Option ROM for SeaBIOS ==

SeaBIOS is our latest and greatest way to boot all kinds of different operating systems. It is a coreboot payload that implements 16bit BIOS interrupts as they are needed by nearly all boot loaders today. In the last year, SeaBIOS learned how to cope with coreboot ACPI, and how to boot off SCSI drives. One major feature that we're desperately lacking is USB stick/disk/cdrom booting from SeaBIOS.
USB support for SeaBIOS should be implemented as a PCI option rom, using the [[libpayload]] USB stack. The USB stack currently supports UHCI controllers. Part of this project could also be to add OHCI and EHCI support to the USB stack in libpayload (not a requirement for participation, but would sure be nice!)

=== Links ===
* [[SeaBIOS]]
* [[libpayload]]

=== Mentors ===

* [[User:MJones|Marc Jones]]
* [[User:PatrickGeorgi|Patrick Georgi]]
* [[User:Stepan|Stefan Reinauer]]

== TianoCore on coreboot ==

[http://www.tianocore.org/ Tiano Core] is Intel's EFI implementation. Unlike coreboot, it is not a firmware, but rather a bootloader. Last year we started porting TianoCore to run on coreboot, but there are many things left to do. Improve Tiano Core running as a coreboot payloads, or change coreboot so it can load Tiano Core as a payloads.

This project requires no hardware skills, but especially in case of TianoCore might require knowledge of Windows compilers (VC2005?)

=== Links ===
* [http://www.tianocore.org/ Tiano Core]

=== Mentors ===
* [[User:Rminnich|Ron Minnich]]
* [[User:Stepan|Stefan Reinauer]]
* [[User:MJones|Marc Jones]]

= Previous Summer of Code projects =

We successfully participated in Google's Summer of Code in 2007 and 2008. See our [[Previous GSoC Projects|list of previous GSoC projects]].

= Why work for coreboot =

Why would you like to work for coreboot?

* coreboot offers you the opportunity to work with modern technology "right on the iron".
* Your application will be available to users worldwide and promoted along with all other coreboot projects.
* We are a very passionate team - so you will interact directly with the project initiators and project leaders.
* We have a large, helpful community. Over 100 experts in hardware and firmware lurk on our mailing list, many of them waiting to help you.

= Summer of Code Application =

Please complete the standard [http://code.google.com/soc/ Google SoC 2008 application]. Additionally, please provide information on the following:

# Who are you? What are you studying?
# Why are you the right person for this task?
# Do you have any other commitments that we should know about?
# List your C, Assembler and hardware experience.
# List your history with open source projects.
# What is your preferred method of contact? (Phone, email, Skype, etc)

Feel free to keep your application short. A 15 page essay is no better than a 2 page summary. If you wish to write 15 pages, you are of course welcome to do so, and we will gladly put your paper up on the web page. But it is not required for the application.

== How to apply ==

The Drupal project has a great page on [http://drupal.org/node/59037 How to write an SOC application].

Please also read Google's [http://code.google.com/p/google-summer-of-code/wiki/AdviceforStudents Advice for Students].

== Some Caveats ==

* Google Summer-of-Code projects are a full (day-) time job. This means we expect roughly 30-40 hours per week on your project, during the three months of coding. Obviously we have flexibility, but if your schedule (exams, courses) does not give you this amount of spare time, then maybe you should not apply.
* Getting paid by Google requires that you meet certain milestones. First, you must be in good standing with the community before the official start of the program. We suggest you post some design emails to the mailing list, and get feedback on them, both before applying, and during the "community bonding period" between acceptance and official start. Also, you must have made progress and committed significant code before the mid-term point.
* We are thinking of requiring accepted students to have a blog, where you will write about your project on a regular basis. This is so that the community at large can be involved and help you. SoC is not a private contract between your mentor and you.

== Time Frame ==

'''DEADLINE FOR STUDENT APPLICATIONS:''' Students who are interested in working on a coreboot-related GSoC project must apply between '''March 23, 2009''' and '''April 3, 2009'''! If you want to apply, please get in contact with us right away!

= Contact =

If you are interested in becoming a GSoC student, please contact [mailto:stepan@coresystems.de Stefan Reinauer].

There is also an IRC channel on irc.freenode.net: #coreboot

User:Ward

2009-03-16T00:44:00Z

Ward: /* Ward Vandewege */

=== Ward Vandewege ===

I'm a (part-time) sysadmin for the [http://www.fsf.org Free Software Foundation]. We have a [http://www.fsf.org/campaigns/free-bios.html Campaign for a free BIOS], because a Free BIOS is essential to achieve true computing freedom.

Where possible, we only buy hardware capable of running coreboot. Currently, we are standardizing on AMD-based systems: in terms of servers we have some Tyan systems and more recently we've purchased Silicon Mechanics A236 and A266 servers. We also have a bunch of Gigabyte M57SLI-S4 based machines, a few PC Engines ALIX boards, and a couple Asus M2A-VM boards.

You can reach me at ward@gnu.org.

Libpayload

2009-03-16T00:08:45Z

Ward: FILO uses libpayload

'''libpayload''' is a small BSD-licensed static library (a lightweight implementation of common and useful functions) intended to be used as a basis for coreboot payloads.

The benefits of linking a coreboot payload against libpayload are:

* Payloads do not have to implement and maintain low-level code for I/O, common functions, etc.
* Payloads can be recompiled and deployed for CPU architectures supported by coreboot in the future.
* The libpayload functions can be tested and scrutinized outside payload development.
* Payloads themselves may be partly host-tested, e.g. against an emulation libpayload.

''Just give us a main() and a pocket full of dreams and we'll do the rest.''

== Features ==

* Provides a [[Libpayload#Libc_Coverage|subset of libc functions]] (e.g. malloc, printf, strcmp, etc).
* Provides an optional tiny (n)curses implementation.
* Provides various small drivers for
** keyboard
** PC speaker
** NVRAM/CMOS access
** serial console
** VGA
** Geode framebuffer
* Reads and parses the coreboot table.http://qa.coreboot.org/docs/libpayload/

== Design ==
* [[Payload API|Discussion of the API for passing parameters to the payload]]

== Payloads using libpayload ==

* [[FILO]] is a bootloader which loads boot images from a local filesystem, without help from legacy BIOS services.
* [[coreinfo]] is a small payload which can display system information such as PCI info, an NVRAM dump, or the coreboot v3 printk buffer.
* [[GRUB invaders]] has been ported successfully to libpayload (patch pending).
* [[tint]] (a console tetris clone) has been successfully ported to libpayload.
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=scripts/kconfig/lxdialog;hb=HEAD lxdialog] from the Linux '''kconfig''' utility has been ported to be usable when linked with libpayload (patch pending).

== Downloading and building libpayload ==

$ svn co svn://coreboot.org/repos/trunk/payloads/libpayload
$ cd libpayload
$ make menuconfig
$ make

== Documentation ==

See the autogenerated documentation for libpayload [http://qa.coreboot.org/docs/libpayload/ here].

== Libc coverage ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Status
! align="left" | Function/Macro/Variable

|- bgcolor="#6699ff"
| colspan=2 | '''assert.h'''
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:red" | no
| assert()

|- bgcolor="#6699ff"
| colspan=2 | '''ctype.h'''
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isalnum(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isalpha(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int iscntrl(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isdigit(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isgraph(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int islower(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isprint(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int ispunct(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isspace(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isupper(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isxdigit(int character)

|- bgcolor="#6699ff"
| colspan=2 | '''errno.h'''
|-
| style="background:red" | no
| <code>errno</code> (global)

|- bgcolor="#6699ff"
| colspan=2 | '''float.h'''

|- bgcolor="#6699ff"
| colspan=2 | '''limits.h'''

|- bgcolor="#6699ff"
| colspan=2 | '''locale.h'''
|-
| style="background:red" | no
| <code>char *setlocale(int category, const char *locale)</code>
|-
| style="background:red" | no
| <code>struct lconv *localeconv(void)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''math.h'''
|-
| style="background:red" | no
| <code>double exp(double x)</code>
|-
| style="background:red" | no
| <code>double log(double x)</code>
|-
| style="background:red" | no
| <code>double log10(double x)</code>
|-
| style="background:red" | no
| <code>double pow(double x, double y)</code>
|-
| style="background:red" | no
| <code>double sqrt(double x)</code>
|-
| style="background:red" | no
| <code>double ceil(double x)</code>
|-
| style="background:red" | no
| <code>double floor(double x)</code>
|-
| style="background:red" | no
| <code>double fabs(double x)</code>
|-
| style="background:red" | no
| <code>double ldexp(double x, int n)</code>
|-
| style="background:red" | no
| <code>double frexp(double x, int* exp)</code>
|-
| style="background:red" | no
| <code>double modf(double x, double* ip)</code>
|-
| style="background:red" | no
| <code>double fmod(double x, double y)</code>
|-
| style="background:red" | no
| <code>double sin(double x)</code>
|-
| style="background:red" | no
| <code>double cos(double x)</code>
|-
| style="background:red" | no
| <code>double tan(double x)</code>
|-
| style="background:red" | no
| <code>double asin(double x)</code>
|-
| style="background:red" | no
| <code>double acos(double x)</code>
|-
| style="background:red" | no
| <code>double atan(double x)</code>
|-
| style="background:red" | no
| <code>double atan2(double y, double x)</code>
|-
| style="background:red" | no
| <code>double sinh(double x)</code>
|-
| style="background:red" | no
| <code>double cosh(double x)</code>
|-
| style="background:red" | no
| <code>double tanh(double x)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''setjmp.h'''
|-
| style="background:red" | no
| <code>int setjmp(jmp_buf env)</code>
|-
| style="background:red" | no
| <code>void longjmp(jmp_buf env, int val)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''signal.h'''
|-
| style="background:red" | no
| <code>void (*signal(int sig, void (*handler)(int)))(int)</code>
|-
| style="background:red" | no
| <code>int raise(int sig)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''stdarg.h'''
|-
| style="background:red" | no
| <code>void va_start(va_list ap, lastarg)</code>
|-
| style="background:red" | no
| <code>type va_arg(va_list ap, type)</code>
|-
| style="background:red" | no
| <code>void va_end(va_list ap)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''stddef.h'''

|- colspan=2
| TODO

|- bgcolor="#6699ff"
| colspan=2 | '''stdio.h'''
|-
| style="background:red" | no
| <code>FILE* fopen(const char* filename, const char* mode)</code>
|-
| style="background:red" | no
| <code>FILE* freopen(const char* filename, const char* mode, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fflush(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fclose(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int remove(const char* filename)</code>
|-
| style="background:red" | no
| <code>int rename(const char* oldname, const char* newname)</code>
|-
| style="background:red" | no
| <code>FILE* tmpfile()</code>
|-
| style="background:red" | no
| <code>char* tmpnam(char s[L_tmpnam])</code>
|-
| style="background:red" | no
| <code>int setvbuf(FILE* stream, char* buf, int mode, size_t size)</code>
|-
| style="background:red" | no
| <code>void setbuf(FILE* stream, char* buf)</code>
|-
| style="background:red" | no
| <code>int fprintf(FILE* stream, const char* format, ...)</code>
|-
| style="background:lime" | yes
| <code>int printf(const char* format, ...)</code>
|-
| style="background:lime" | yes
| <code>int sprintf(char* s, const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int vfprintf(FILE* stream, const char* format, va_list arg)</code>
|-
| style="background:lime" | yes
| <code>int vprintf(const char* format, va_list arg)</code>
|-
| style="background:lime" | yes
| <code>int vsprintf(char* s, const char* format, va_list arg)</code>
|-
| style="background:red" | no
| <code>int fscanf(FILE* stream, const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int scanf(const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int sscanf(char* s, const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int fgetc(FILE* stream)</code>
|-
| style="background:red" | no
| <code>char* fgets(char* s, int n, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fputc(int c, FILE* stream)</code>
|-
| style="background:red" | no
| <code>char* fputs(const char* s, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int getc(FILE* stream)</code>
|-
| style="background:lime" | yes
| <code>int getchar(void)</code>
|-
| style="background:red" | no
| <code>char* gets(char* s)</code>
|-
| style="background:red" | no
| <code>int putc(int c, FILE* stream)</code>
|-
| style="background:lime" | yes
| <code>int putchar(int c)</code>
|-
| style="background:lime" | yes
| <code>int puts(const char* s)</code>
|-
| style="background:red" | no
| <code>int ungetc(int c, FILE* stream)</code>
|-
| style="background:red" | no
| <code>size_t fread(void* ptr, size_t size, size_t nobj, FILE* stream)</code>
|-
| style="background:red" | no
| <code>size_t fwrite(const void* ptr, size_t size, size_t nobj, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fseek(FILE* stream, long offset, int origin)</code>
|-
| style="background:red" | no
| <code>long ftell(FILE* stream)</code>
|-
| style="background:red" | no
| <code>void rewind(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fgetpos(FILE* stream, fpos_t* ptr)</code>
|-
| style="background:red" | no
| <code>int fsetpos(FILE* stream, const fpos_t* ptr)</code>
|-
| style="background:red" | no
| <code>void clearerr(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int feof(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int ferror(FILE* stream)</code>
|-
| style="background:red" | no
| <code>void perror(const char* s)</code>

|}

| valign="top"|

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Status
! align="left" | Function/Macro/Variable

|- bgcolor="#6699ff"
| colspan=2 | '''stdlib.h'''
|-
| style="background:lime" | yes
| <code>int abs(int n)</code>
|-
| style="background:lime" | yes
| <code>long labs(long n)</code>
|-
| style="background:lime" | yes
| <code>long long llabs(long long n)</code>
|-
| style="background:red" | no
| <code>div_t div(int num, int denom)</code>
|-
| style="background:red" | no
| <code>ldiv_t ldiv(long num, long denom)</code>
|-
| style="background:red" | no
| <code>double atof(const char* s)</code>
|-
| style="background:red" | no
| <code>int atoi(const char* s)</code>
|-
| style="background:red" | no
| <code>long atol(const char* s)</code>
|-
| style="background:red" | no
| <code>double strtod(const char* s, char** endp)</code>
|-
| style="background:red" | no
| <code>long strtol(const char* s, char** endp, int base)</code>
|-
| style="background:red" | no
| <code>unsigned long strtoul(const char* s, char** endp, int base)</code>
|-
| style="background:lime" | yes
| <code>void* calloc(size_t nobj, size_t size)</code>
|-
| style="background:lime" | yes
| <code>void* malloc(size_t size)</code>
|-
| style="background:lime" | yes
| <code>void* realloc(void* p, size_t size)</code>
|-
| style="background:lime" | yes
| <code>void free(void* p)</code>
|-
| style="background:lime" | yes
| <code>void abort()</code>
|-
| style="background:red" | no
| <code>void exit(int status)</code>
|-
| style="background:red" | no
| <code>int atexit(void (*fcm)(void))</code>
|-
| style="background:red" | no
| <code>int system(const char* s)</code>
|-
| style="background:red" | no
| <code>char* getenv(const char* name)</code>
|-
| style="background:red" | no
| <code>void* bsearch(const void* key, const void* base, size_t n, size_t size, int (*cmp)(const void* keyval, const void* datum))</code>
|-
| style="background:red" | no
| <code>void qsort(void* base, size_t n, size_t size, int (*cmp)(const void*, const void*))</code>
|-
| style="background:lime" | yes
| <code>int rand(void)</code>
|-
| style="background:lime" | yes
| <code>void srand(unsigned int seed)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''string.h'''
|-
| style="background:lime" | yes
| <code>char* strcpy(char* s, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strncpy(char* s, const char* ct, size_t n)</code>
|-
| style="background:red" | no
| <code>char* strcat(char* s, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strncat(char* s, const char* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>int strcmp(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>int strncmp(const char* cs, const char* ct, size_t n)</code>
|-
| style="background:red" | no
| <code>int strcoll(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strchr(const char* cs, int c)</code>
|-
| style="background:red" | no
| <code>char* strrchr(const char* cs, int c)</code>
|-
| style="background:red" | no
| <code>size_t strspn(const char* cs, const char* ct)</code>
|-
| style="background:red" | no
| <code>size_t strcspn(const char* cs, const char* ct)</code>
|-
| style="background:red" | no
| <code>char* strpbrk(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strstr(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>size_t strlen(const char* cs)</code>
|-
| style="background:red" | no
| <code>char* strerror(int n)</code>
|-
| style="background:red" | no
| <code>char* strtok(char* s, const char* t)</code>
|-
| style="background:red" | no
| <code>size_t strxfrm(char* s, const char* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>void* memcpy(void* s, const void* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>void* memmove(void* s, const void* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>int memcmp(const void* cs, const void* ct, size_t n)</code>
|-
| style="background:red" | no
| <code>void* memchr(const void* cs, int c, size_t n)</code>
|-
| style="background:lime" | yes
| <code>void* memset(void* s, int c, size_t n)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''time.h'''
|-
| style="background:red" | no
| <code>clock_t clock(void)</code>
|-
| style="background:red" | no
| <code>time_t time(time_t* tp)</code>
|-
| style="background:red" | no
| <code>double difftime(time_t time2, time_t time1)</code>
|-
| style="background:red" | no
| <code>time_t mktime(struct tm* tp)</code>
|-
| style="background:red" | no
| <code>char* asctime(const struct tm* tp)</code>
|-
| style="background:red" | no
| <code>char* ctime(const time_t* tp)</code>
|-
| style="background:red" | no
| <code>struct tm* gmtime(const time_t* tp)</code>
|-
| style="background:red" | no
| <code>struct tm* localtime(const time_t* tp)</code>
|-
| style="background:red" | no
| <code>size_t strftime(char* s, size_t smax, const char* fmt, const struct tm* tp)</code>

|}
|}

== Usage example ==

Here's an example of a very simple payload (hello.c) and how to build it:

<pre>
#include <libpayload.h>

int main(void)
{
printf("Hello, world!\n");
halt();
return 0;
}
</pre>

Building the payload:

lpgcc -o hello.elf hello.c

{{PD-self}}

Welcome to coreboot

2009-03-01T22:16:14Z

Ward: small rephrasing

<table width="100%" valign="top"><tr valign="top"><td width="80%">

<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;">
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].

We currently support ca. '''[[Supported Motherboards|200]]''' different mainboards (v3: [[Supported Motherboards#Motherboards_supported_in_coreboot_v3|16]], v2: [[Supported Motherboards#Motherboards_supported_in_coreboot_v2|120]], v1: [[Supported Motherboards#Motherboards_supported_in_coreboot_v1|64]], some duplicates included).

<div style="font-size:1.8em">10!</div>
Anton Borisov [http://www.h-online.com/open/The-Open-Source-BIOS-is-Ten-An-interview-with-the-coreboot-developers--/features/112353 interviewed the original developers] ([http://www.heise.de/open/Zehn-Jahre-LinuxBIOS-Coreboot--/artikel/121679 german version]) as the Open Source PC firmware celebrates '''ten years of activity'''!
</div>

{| cellspacing=0 cellpadding=3 border=0 margin=0 padding=0 align="top" width=100%
|-
|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = yellow|
WIDTH = 100%|
ICON = [[Benefits|More...]]|
HEADING = [[Benefits]]|
CONTENT =

* 100% Free Software (GPL), no royalties, no license fees!
* Fast boot times (3 seconds to Linux console)
* Avoids the need for a slow/buggy/proprietary BIOS

* Written in C, contains virtually no assembly code
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|devices]], and [[payloads]]


}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = #d1adf6|
WIDTH = 100%|
ICON = [[Use Cases|More...]]|
HEADING = [[Use Cases]]|
CONTENT =

* Desktop PCs, servers, clusters, thin clients
* [[Clusters]], high-performance computing

* Embedded solutions, STBs/HTPC, appliances, terminals

* No-moving-parts solutions (ROM chip as "disk")
* Non-standard scenarios (e.g. FPGA in Opteron socket)

}}

|style="vertical-align:top"|

{{Box|
BORDER = #8898bf|
BACKGROUND = lime|
WIDTH = 100%|
ICON = [[Payloads|More...]]|
HEADING = [[Payloads]]|
CONTENT =

* [[FILO]] / [http://grub.enbug.org/CoreBoot GRUB2] / [[OpenFirmware]] / [[OpenBIOS]]
* [[Linux]] / [[Booting Windows using coreboot|Windows]] / [[Booting FreeBSD using coreboot|FreeBSD]] / [[Coreboot and NetBSD|NetBSD]] / [http://openbsd.org/ OpenBSD]
* [[SeaBIOS]] / [[Memtest86]]
* [[Etherboot]] / [[GPXE]]
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]

}}

|}

{| cellspacing=5 cellpadding=5 border=0 valign="top" width=100%
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_lb.png]]
|style="vertical-align:top"|
'''About''' Find out more about coreboot.<hr />[[News]] | [[Press]] | [[Logo]] | [[Current events|Events]] | [[History]] | [[Screenshots|Screenshots & Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Clusters]] | [[Vendors]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_devel.png]]
|style="vertical-align:top"|
'''Developers''' Get involved! Help us make coreboot better.<hr />[[Development Guidelines]] | [[Developer Manual]] | [[Coreboot v3]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[JTAG/BSDL Guide|JTAG]] | [[EHCI Debug Port]] | [[Distributed and Automated Testsystem|Testsystem]] | [[GSoC]] | [[Ideas]] | [[Laptop]] | [[Desktops]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_status.png]]
|style="vertical-align:top"|
'''Status''' Find out whether your hardware is already supported.<hr />[[Supported Motherboards]] | [[Supported Chipsets and Devices|Supported Chipsets & Devices]] | [http://qa.coreboot.org Build Status] | [[Flashrom#Supported_devices|Flashrom support]] | [[Superiotool#Supported_devices|Superiotool support]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_tools.png]]
|style="vertical-align:top"|
'''Related Tools''' Tools and libraries related to coreboot.<hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]]
|}

|-
| width=50% style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_101.png]]
|style="vertical-align:top"|
'''Getting Started''' Download coreboot and get started.<hr />[[Download coreboot|Downloads]] | [[Documentation]] | [[:Category:Tutorials|Build Tutorials]] | [[Payloads]] | [[QEMU]] | [[AMD SimNow]] | [[Confirmed working svn revisions|Confirmed Working SVN Revisions]] | [[Misc]]
|}

|style="vertical-align:top"|

{|
|style="vertical-align:top"|
[[Image:chip_support.png]]
|style="vertical-align:top"|
'''Support''' Learn how to contact us and find help and support.<hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|corebootv2 Options]]
|}

|}
</td><td width="20%">

[[Image:Kontron 986lcd m mitx with power supply.jpg|center|thumb|[[Kontron 986LCD-M mITX]] ]]

 

'''[[News]]'''<hr />


* '''2009/01/10:''' [[News#2009.2F01.2F10_coreboot_and_SeaBIOS_starts_Windows_7|Windows 7 boots]]
* '''2008/12/15:''' [[News#2008.2F12.2F15_ASUS_P2B-DS_now_supported|ASUS P2B-DS support]]
* '''2008/12/09:''' [[News#2008.2F12.2F09_AMD_Pistachio_now_supported|AMD Pistachio support]]
* '''2008/12/05:''' [[News#2008.2F12.2F05_NEC_PowerMate_2000_now_supported|NEC PowerMate 2000 support]]
* '''2008/11/19:''' [[News#2008.2F11.2F19_LiPPERT_Cool_RoadRunner-LX_now_supported|LiPPERT Cool RoadRunner LX support]]
* '''2008/10/30:''' [[News#2008.2F10.2F30_LiPPERT_Cool_SpaceRunner-LX_now_supported|LiPPERT Cool SpaceRunner LX support]]
* '''2008/10/28:''' [[News#2008.2F10.2F28_Intel_945.2C_ICH7.2C_Core_Duo.2FCore_2_Duo.2C_and_Kontron_986LCD-M.2FmITX_now_supported|Intel i945/ICH7, Core Duo, Kontron 986LCD-M support]]


'''[[Current events|Upcoming Events]]'''<hr />


* '''2009/03/03-05:''' [[User:Stepan|Stefan]], [[User:Stuge|Peter]] and [[User:Ruik|Rudolf]] are visiting [http://www.embedded-world.de/ embedded world 2009 in Nürnberg]


'''Contact'''<hr />

* [[Mailinglist|Mailing list]]: [mailto:coreboot@coreboot.org coreboot@coreboot.org]
* [[IRC]]: '''#coreboot''' (on [http://www.freenode.net/ irc.freenode.net])

</td></tr></table>
__NOTOC__
__NOEDITSECTION__

VGA support

2009-02-26T17:10:09Z

Ward: /* How to retrieve a good video bios */

== VGA initialization in coreboot v2 ==

=== General ===

You need to enable two CONFIG options in your Mainboard Option.lb

<source lang="bash">
# VGA Console
option CONFIG_CONSOLE_VGA=1
option CONFIG_PCI_ROM_RUN=1
</source>

'''CONFIG_PCI_ROM_RUN''' will use the embedded x86 emulator to run the BIOS image in the expansion ROM of a PCI device.
'''CONFIG_CONSOLE_VGA''' will redirect console messages to the VGA screen once VGA card is initialized.

For add-on (PCI/PCIe/PCI-X/AGP) VGA cards, you don't have to do anything else besides these two CONFIG options.
If your mainboard has an on-board VGA chip and you insert another VGA add-on card, the add-on
VGA card will be used instead of the on-board VGA chip.

=== On-board Video Devices ===

If you want to use the onboard VGA chip, you have to add the following options in addition to the CONFIG options described above.

==== Mainboard Configuration ====
'''Note:''' This step is not necessary for the VIA CN700 chipset.

1. In the mainboard's Config.lb (./src/mainboard/<mfg>/<board>/Config.lb) You need to specify the device number for your on-board VGA and the address that the video bios will show up at in the system.

<source lang = bash>
device pci 9.0 on # PCI
chip drivers/pci/onboard
device pci 9.0 on end
register "rom_address" = "0xfff80000" #512k image
#register "rom_address" = "0xfff00000" #1M image
end
end
</source>

Replace the 9.0 with the dev.fn of your vga device. You can find this number by doing a 'lspci' from the board booted under linux.
Please make sure the device number is correct. Otherwise the config code can not compute the proper ROM address.

===== How to compute the "rom_address" value =====

ROM (called 'flash' a lot) chips are located directly below 4Gbyte (0xffffffff) boundary.

So you need to calculate the address by subtracting the
flash chip size (and adding the offset within the image)

In coreboot the offset within the image is 0, because its the first
thing in the coreboot image.

So you need to compute the address in the systems memory space where the start of the video bios will show up.

To do this you take the 4Gb of address and subtract the size of your coreboot image.
0x100000000 - (ROM size in Kb * 1024)

You can do this in bash by:

<source lang="bash">
biossize=256
printf "0x%x\n" $(( 0x100000000 - ($biossize*1024) ))
</source>

Addresses for popular chip sizes:
256K 0xfffc0000
512k 0xfff80000
1024k 0xfff00000

==== Target Configuration ====

2. You still need to modify your target 'Config.lb' to reserve space for the additional video bios. Reduce the size of your coreboot image by the size of the video bios. You will prepend the video bios to the coreboot image in step 3.

in the normal section

<source lang="bash">
romimage "normal"
# 48K for SCSI FW or ATI ROM
option ROM_SIZE = 475136
</source>

or if you only have a "fallback" boot then use the "fallback" section instead.

In the above example the bios chip is 512Kb part. The video bios is 48Kb. So (512*1024)-(48*1024) = 475136.

'''Note:''' The Via CN700 chipset also requires legacy BIOS support. This can be found or at http://bochs.sourceforge.net/ or in the Debian package bochsbios, filename /usr/share/bochs/BIOS-bochs-legacy. You'll need to leave an additional 64k of space for the Bochs BIOS.

==== Creating an Image ====

3. Finally, prepend your video bios to the coreboot.rom

<source lang="bash">
cat videobios.bin coreboot.rom > final_coreboot.rom
</source>

where ''videobios.bin'' is the name of your video bios image.
You need to make sure the final_coreboot.rom size is the size of your ROM chip. Normally 256kb, 512kb, or 1024Kb.

See below for instructions on how to retrieve the video BIOS from your factory ROM.

'''For Via CN700:'''
<source lang="bash">
cat videobios.bin bochsbios.bin coreboot.rom > final_coreboot.rom
</source>

== VGA initialization in coreboot v3 ==

In coreboot v3 you have to set your PCI option ROM execution method under the '''Device''' menu. The default is x86emu. To get a smaller (and slightly more insecure) version, you can switch to vm86. If you don't want option rom execution, set it to Disabled.

=== On-board devices ===

To add option roms for on-board video cards to your coreboot image, you can just add the image using lar:

<source lang="bash">
lar -C lzma -a coreboot.rom vgabios.rom:pciXXXX,YYYY.rom
</source>

In the above example, vgabios.rom is the name of your option rom on disk. XXXX is the PCI vendor ID of your on-board video adapter and YYYY is its PCI device ID.

== How to retrieve a good video bios ==

=== RECOMMENDED: Extracting from your vendor bios image ===

The recommended method is to take your mainboard vendor's BIOS image and extract the VGA BIOS using a tool called awardeco/amideco/phnxdeco. These tools are available in Debian/Ubuntu. If your vendor bios is award, you would use awardeco, if it's AMI amideco, and if it's Phoenix phnxdeco.

This is the most reliable way:
* You are guaranteed to get an image that fits to your onboard VGA
* Even if your VGA BIOS uses self-modifying code you get a correct image
With this method, you may need to pad the image to a certain size, e.g. 64k. This is necessary at least for VIA CN700 chipsets where the factory VGA bios is smaller.

=== Downloading ===

There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])

=== Extracting from the system ===

However you should be able to retrieve your own video bios as well with linux.
* Boot up a machine with a commercial bios (not coreboot) with the video card you wish to work under coreboot.
* You can see where and how much your card's bios is using by doing a
<source lang="bash">cat /proc/iomem | grep 'Video ROM'</source>
* From the command line enter: <source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's bios is cached at 0xc0000, and is 64K long.
 <source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source>
This works for many of the VIA Epia boards. 
Alternatively you can automatically generate it using this nice script from Peter Stuge: 
<source lang="bash">
$ cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \
$ dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])
</source>
* You now have a video bios image

VGA support

2009-02-26T17:09:08Z

Ward: /* Extracting from your vendor bios image */

== VGA initialization in coreboot v2 ==

=== General ===

You need to enable two CONFIG options in your Mainboard Option.lb

<source lang="bash">
# VGA Console
option CONFIG_CONSOLE_VGA=1
option CONFIG_PCI_ROM_RUN=1
</source>

'''CONFIG_PCI_ROM_RUN''' will use the embedded x86 emulator to run the BIOS image in the expansion ROM of a PCI device.
'''CONFIG_CONSOLE_VGA''' will redirect console messages to the VGA screen once VGA card is initialized.

For add-on (PCI/PCIe/PCI-X/AGP) VGA cards, you don't have to do anything else besides these two CONFIG options.
If your mainboard has an on-board VGA chip and you insert another VGA add-on card, the add-on
VGA card will be used instead of the on-board VGA chip.

=== On-board Video Devices ===

If you want to use the onboard VGA chip, you have to add the following options in addition to the CONFIG options described above.

==== Mainboard Configuration ====
'''Note:''' This step is not necessary for the VIA CN700 chipset.

1. In the mainboard's Config.lb (./src/mainboard/<mfg>/<board>/Config.lb) You need to specify the device number for your on-board VGA and the address that the video bios will show up at in the system.

<source lang = bash>
device pci 9.0 on # PCI
chip drivers/pci/onboard
device pci 9.0 on end
register "rom_address" = "0xfff80000" #512k image
#register "rom_address" = "0xfff00000" #1M image
end
end
</source>

Replace the 9.0 with the dev.fn of your vga device. You can find this number by doing a 'lspci' from the board booted under linux.
Please make sure the device number is correct. Otherwise the config code can not compute the proper ROM address.

===== How to compute the "rom_address" value =====

ROM (called 'flash' a lot) chips are located directly below 4Gbyte (0xffffffff) boundary.

So you need to calculate the address by subtracting the
flash chip size (and adding the offset within the image)

In coreboot the offset within the image is 0, because its the first
thing in the coreboot image.

So you need to compute the address in the systems memory space where the start of the video bios will show up.

To do this you take the 4Gb of address and subtract the size of your coreboot image.
0x100000000 - (ROM size in Kb * 1024)

You can do this in bash by:

<source lang="bash">
biossize=256
printf "0x%x\n" $(( 0x100000000 - ($biossize*1024) ))
</source>

Addresses for popular chip sizes:
256K 0xfffc0000
512k 0xfff80000
1024k 0xfff00000

==== Target Configuration ====

2. You still need to modify your target 'Config.lb' to reserve space for the additional video bios. Reduce the size of your coreboot image by the size of the video bios. You will prepend the video bios to the coreboot image in step 3.

in the normal section

<source lang="bash">
romimage "normal"
# 48K for SCSI FW or ATI ROM
option ROM_SIZE = 475136
</source>

or if you only have a "fallback" boot then use the "fallback" section instead.

In the above example the bios chip is 512Kb part. The video bios is 48Kb. So (512*1024)-(48*1024) = 475136.

'''Note:''' The Via CN700 chipset also requires legacy BIOS support. This can be found or at http://bochs.sourceforge.net/ or in the Debian package bochsbios, filename /usr/share/bochs/BIOS-bochs-legacy. You'll need to leave an additional 64k of space for the Bochs BIOS.

==== Creating an Image ====

3. Finally, prepend your video bios to the coreboot.rom

<source lang="bash">
cat videobios.bin coreboot.rom > final_coreboot.rom
</source>

where ''videobios.bin'' is the name of your video bios image.
You need to make sure the final_coreboot.rom size is the size of your ROM chip. Normally 256kb, 512kb, or 1024Kb.

See below for instructions on how to retrieve the video BIOS from your factory ROM.

'''For Via CN700:'''
<source lang="bash">
cat videobios.bin bochsbios.bin coreboot.rom > final_coreboot.rom
</source>

== VGA initialization in coreboot v3 ==

In coreboot v3 you have to set your PCI option ROM execution method under the '''Device''' menu. The default is x86emu. To get a smaller (and slightly more insecure) version, you can switch to vm86. If you don't want option rom execution, set it to Disabled.

=== On-board devices ===

To add option roms for on-board video cards to your coreboot image, you can just add the image using lar:

<source lang="bash">
lar -C lzma -a coreboot.rom vgabios.rom:pciXXXX,YYYY.rom
</source>

In the above example, vgabios.rom is the name of your option rom on disk. XXXX is the PCI vendor ID of your on-board video adapter and YYYY is its PCI device ID.

== How to retrieve a good video bios ==

=== Extracting from your vendor bios image ===

The recommended method is to take your mainboard vendor's BIOS image and extract the VGA BIOS using a tool called awardeco/amideco/phnxdeco. These tools are available in Debian/Ubuntu. If your vendor bios is award, you would use awardeco, if it's AMI amideco, and if it's Phoenix phnxdeco.

This is the most reliable way:
* You are guaranteed to get an image that fits to your onboard VGA
* Even if your VGA BIOS uses self-modifying code you get a correct image
With this method, you may need to pad the image to a certain size, e.g. 64k. This is necessary at least for VIA CN700 chipsets where the factory VGA bios is smaller.

=== Downloading ===

There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])

=== Extracting from the system ===

However you should be able to retrieve your own video bios as well with linux.
* Boot up a machine with a commercial bios (not coreboot) with the video card you wish to work under coreboot.
* You can see where and how much your card's bios is using by doing a
<source lang="bash">cat /proc/iomem | grep 'Video ROM'</source>
* From the command line enter: <source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's bios is cached at 0xc0000, and is 64K long.
 <source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source>
This works for many of the VIA Epia boards. 
Alternatively you can automatically generate it using this nice script from Peter Stuge: 
<source lang="bash">
$ cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \
$ dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])
</source>
* You now have a video bios image

ASUS M2A-VM

2009-02-20T21:34:14Z

Ward:

This page describes how to use coreboot on the '''[http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&modelmenu=1 ASUS M2A-VM]''' mainboard.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status = OK
|CPU_L2_status = OK
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = Untested
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = WIP
|RAM_DDR2_comments = Works with 2 GB. Broken with 4 GB.
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = WIP
|RAM_dualchannel_comments = Does not work with 2x2 GB unmatched DIMMS in a dualchannel setup (expected). Patches have been sent to the list to partially fix this.
|RAM_ecc_status = Untested

|IDE_status = OK
|IDE_CF_status = Untested
|IDE_25_status = N/A
|CDROM_DVD_status = OK
|SATA_status = OK
|SATA_comments = Not working: SATA multicount transfers (detected as unsupported by Linux)
|USB_status = OK
|Onboard_SCSI_status = N/A
|Onboard_VGA_status = OK
|Onboard_VGA_comments = VESA framebuffer console does not work if you select x86emu because the VESA call interface is not available. A normal X server works fine even with 3D (radeonhd driver).
|Onboard_ethernet_status = OK
|Onboard_audio_status = WIP
|Onboard_audio_comments = Stereo output (onboard jack) in HD Audio mode works. Onboard jack for microphone input seems not to work due to an unknown reason. Coreboot says it can't find . Linux kernel complains "hda_codec: Unknown model for ALC883, trying auto-probe from BIOS..."
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Only one slot was tested.
|Mini_PCI_cards_status = N/A
|PCIE_x1_status = Untested
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = Untested
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = Untested
|COM1_status = OK
|COM2_status = N/A
|PP_status = Untested
|PS2_keyboard_status = OK
|PS2_mouse_status = Untested
|Game_port_status = Untested
|IR_status = N/A
|Speaker_status = Untested
|DiskOnChip_status = N/A

|Sensors_status = WIP
|Watchdog_status = Untested
|CAN_bus_status = N/A
|CPUfreq_status = OK
|Powersave_status = N/A
|ACPI_status = WIP
|ACPI_comments = power button works, software poweroff works, suspend is untested
|Reboot_status = OK
|Poweroff_status = OK
|LEDs_status = N/A
|HPET_status = Untested
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = WIP
|Flashrom_comments = [http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html Reported as working with the proprietary BIOS.]

}}

== Flashrom ==

You need [http://www.coreboot.org/pipermail/coreboot/2009-February/044573.html this patch] for flashrom as of 2009/02.

== Bootlog ==

The bootlog [http://www.coreboot.org/pipermail/coreboot/2008-December/043728.html is available].

== Lspci ==

=== Proprietary bios ===

<pre>
00:00.0 Host bridge: ATI Technologies Inc RS690 Host Bridge
00:01.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx)
00:07.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 3)
00:12.0 SATA controller: ATI Technologies Inc SB600 Non-Raid-5 SATA
00:13.0 USB Controller: ATI Technologies Inc SB600 USB (OHCI0)
00:13.1 USB Controller: ATI Technologies Inc SB600 USB (OHCI1)
00:13.2 USB Controller: ATI Technologies Inc SB600 USB (OHCI2)
00:13.3 USB Controller: ATI Technologies Inc SB600 USB (OHCI3)
00:13.4 USB Controller: ATI Technologies Inc SB600 USB (OHCI4)
00:13.5 USB Controller: ATI Technologies Inc SB600 USB Controller (EHCI)
00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 13)
00:14.1 IDE interface: ATI Technologies Inc SB600 IDE
00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA)
00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge
00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control
01:05.0 VGA compatible controller: ATI Technologies Inc RS690 [Radeon X1200 Series]
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
</pre>

<pre>
# lspci -vvvvvvvnx
00:00.0 0600: 1002:7910
Subsystem: 1043:826d
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
Latency: 64
00: 02 10 10 79 06 00 20 22 00 00 00 06 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 6d 82
30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00

00:01.0 0604: 1002:7912 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 99
Bus: primary=00, secondary=01, subordinate=01, sec-latency=68
I/O behind bridge: 0000d000-0000dfff
Memory behind bridge: fdc00000-fddfffff
Prefetchable memory behind bridge: 00000000fa000000-00000000fbffffff
Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [b0] Subsystem: 1002:7912
Kernel modules: shpchp
00: 02 10 12 79 07 00 30 02 00 00 04 06 00 63 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 44 d1 d1 20 02
20: c0 fd d0 fd 01 fa f1 fb 00 00 00 00 00 00 00 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00

00:07.0 0604: 1002:7917 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: fdb00000-fdbfffff
Prefetchable memory behind bridge: 00000000fdf00000-00000000fdffffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v1) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag+ RBE+ FLReset-
DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us
ClockPM- Suprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+
Address: fee0300c Data: 4149
Capabilities: [b0] Subsystem: 1043:826d
Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100] Virtual Channel <?>
Kernel driver in use: pcieport-driver
Kernel modules: shpchp
00: 02 10 17 79 07 04 10 00 00 00 04 06 08 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 e1 e1 00 00
20: b0 fd b0 fd f1 fd f1 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00

00:12.0 0106: 1002:4380 (prog-if 01 [AHCI 1.0])
Subsystem: 1043:8231
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Interrupt: pin A routed to IRQ 22
Region 0: I/O ports at ff00 [size=8]
Region 1: I/O ports at fe00 [size=4]
Region 2: I/O ports at fd00 [size=8]
Region 3: I/O ports at fc00 [size=4]
Region 4: I/O ports at fb00 [size=16]
Region 5: Memory at fe02f000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [60] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] SATA HBA <?>
Kernel driver in use: ahci
Kernel modules: ahci
00: 02 10 80 43 07 00 30 02 00 01 06 01 00 40 00 00
10: 01 ff 00 00 01 fe 00 00 01 fd 00 00 01 fc 00 00
20: 01 fb 00 00 00 f0 02 fe 00 00 00 00 43 10 31 82
30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 00 00

00:13.0 0c03: 1002:4387 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 16
Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 87 43 07 00 a0 02 00 10 03 0c 08 40 80 00
10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00

00:13.1 0c03: 1002:4388 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin B routed to IRQ 17
Region 0: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 88 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 d0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:13.2 0c03: 1002:4389 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin C routed to IRQ 18
Region 0: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 89 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 c0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 03 00 00

00:13.3 0c03: 1002:438a (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin B routed to IRQ 17
Region 0: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 8a 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 b0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:13.4 0c03: 1002:438b (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin C routed to IRQ 18
Region 0: Memory at fe02a000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 8b 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 a0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 03 00 00

00:13.5 0c03: 1002:4386 (prog-if 20 [EHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 64 bytes
Interrupt: pin D routed to IRQ 19
Region 0: Memory at fe029000 (32-bit, non-prefetchable) [size=256]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Bridge: PM- B3+
Capabilities: [e4] Debug port: BAR=1 offset=00e0
Kernel driver in use: ehci_hcd
Kernel modules: ehci-hcd
00: 02 10 86 43 17 00 b0 02 00 20 03 0c 10 40 00 00
10: 00 90 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 04 00 00

00:14.0 0c05: 1002:4385 (rev 13)
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop+ ParErr+ Stepping+ SERR+ FastB2B+ DisINTx+
Status: Cap+ 66MHz+ UDF+ FastB2B+ ParErr+ DEVSEL=?? >TAbort+ <TAbort+ <MAbort+ >SERR+ <PERR+ INTx+
Latency: 0
Region 0: I/O ports at 0b00 [size=16]
Capabilities: [b0] HyperTransport: MSI Mapping Enable- Fixed+
Kernel driver in use: piix4_smbus
Kernel modules: i2c-piix4
00: 02 10 85 43 ff ff ff ff 13 00 05 0c 00 00 80 00
10: 01 0b 00 00 ff ff ff ff 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 00 00 00

00:14.1 0101: 1002:438c (prog-if 8a [Master SecP PriP])
Subsystem: 1043:81ef
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Interrupt: pin A routed to IRQ 16
Region 0: I/O ports at 01f0 [size=8]
Region 1: I/O ports at 03f4 [size=1]
Region 2: I/O ports at 0170 [size=8]
Region 3: I/O ports at 0374 [size=1]
Region 4: I/O ports at f900 [size=16]
Capabilities: [70] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable-
Address: 00000000 Data: 0000
Kernel driver in use: ATIIXP_IDE
Kernel modules: ata_generic, ide-pci-generic, atiixp
00: 02 10 8c 43 05 00 30 02 00 8a 01 01 00 40 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 01 f9 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 70 00 00 00 00 00 00 00 ff 01 00 00

00:14.2 0403: 1002:4383
Subsystem: 1043:8249
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin ? routed to IRQ 16
Region 0: Memory at fe020000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
Address: 0000000000000000 Data: 0000
Kernel driver in use: HDA Intel
Kernel modules: snd-hda-intel
00: 02 10 83 43 06 00 10 04 00 00 03 04 08 40 00 00
10: 04 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 49 82
30: 00 00 00 00 50 00 00 00 00 00 00 00 03 00 00 00

00:14.3 0601: 1002:438d
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
00: 02 10 8d 43 0f 00 20 02 00 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:14.4 0604: 1002:4384 (prog-if 01 [Subtractive decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Bus: primary=00, secondary=03, subordinate=03, sec-latency=64
I/O behind bridge: 0000c000-0000cfff
Memory behind bridge: fcc00000-fd7fffff
Prefetchable memory behind bridge: fde00000-fdefffff
Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
00: 02 10 84 43 27 00 a0 02 00 01 04 06 00 40 81 00
10: 00 00 00 00 00 00 00 00 00 03 03 40 c0 c0 80 22
20: c0 fc 70 fd e0 fd e0 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.0 0600: 1022:1100
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Capabilities: [80] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit
Revision ID: 1.02
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00

00:18.1 0600: 1022:1101
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.2 0600: 1022:1102
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.3 0600: 1022:1103
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Capabilities: [f0] Secure device <?>
Kernel driver in use: k8temp
Kernel modules: k8temp
00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00

01:05.0 0300: 1002:791e (prog-if 00 [VGA controller])
Subsystem: 1043:826d
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 7
Region 0: Memory at fa000000 (64-bit, prefetchable) [size=32M]
Region 2: Memory at fddf0000 (64-bit, non-prefetchable) [size=64K]
Region 4: I/O ports at de00 [size=256]
Region 5: Memory at fdc00000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
Address: 0000000000000000 Data: 0000
00: 02 10 1e 79 07 00 10 00 00 00 00 03 08 40 00 00
10: 0c 00 00 fa 00 00 00 00 04 00 df fd 00 00 00 00
20: 01 de 00 00 00 00 c0 fd 00 00 00 00 43 10 6d 82
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00

02:00.0 0200: 10ec:8168 (rev 01)
Subsystem: 1043:81aa
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 1278
Region 0: I/O ports at ee00 [size=256]
Region 2: Memory at fdbff000 (64-bit, non-prefetchable) [size=4K]
Expansion ROM at fdbc0000 [disabled] [size=128K]
Capabilities: [40] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] Vital Product Data <?>
Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+
Address: 00000000fee0300c Data: 4159
Capabilities: [60] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
ExtTag+ AttnBtn+ AttnInd+ PwrInd+ RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Suprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [84] Vendor Specific Information <?>
Capabilities: [100] Advanced Error Reporting <?>
Capabilities: [12c] Virtual Channel <?>
Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-00-1a
Capabilities: [154] Power Budgeting <?>
Kernel driver in use: r8169
Kernel modules: r8169
00: ec 10 68 81 07 04 10 00 01 00 00 02 10 00 00 00
10: 01 ee 00 00 00 00 00 00 04 f0 bf fd 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 aa 81
30: 00 00 bc fd 40 00 00 00 00 00 00 00 05 01 00 00
</pre>

{{PD-self}}

ASUS M2A-VM

2009-02-20T19:07:41Z

Ward:

This page describes how to use coreboot on the '''[http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&modelmenu=1 ASUS M2A-VM]''' mainboard.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status = OK
|CPU_L2_status = OK
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = Untested
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = WIP
|RAM_DDR2_comments = Works with 2 GB. Broken with 4 GB.
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = WIP
|RAM_dualchannel_comments = Does not work with 2x2 GB unmatched DIMMS in a dualchannel setup (expected). Patches have been sent to the list to partially fix this.
|RAM_ecc_status = Untested

|IDE_status = OK
|IDE_CF_status = Untested
|IDE_25_status = N/A
|CDROM_DVD_status = OK
|SATA_status = OK
|SATA_comments = Not working: SATA multicount transfers (detected as unsupported by Linux)
|USB_status = OK
|Onboard_SCSI_status = N/A
|Onboard_VGA_status = OK
|Onboard_VGA_comments = VESA framebuffer console does not work if you select x86emu because the VESA call interface is not available. A normal X server works fine even with 3D (radeonhd driver).
|Onboard_ethernet_status = OK
|Onboard_audio_status = WIP
|Onboard_audio_comments = Stereo output (onboard jack) in HD Audio mode works. Onboard jack for microphone input seems not to work due to an unknown reason. Coreboot says it can't find . Linux kernel complains "hda_codec: Unknown model for ALC883, trying auto-probe from BIOS..."
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Only one slot was tested.
|Mini_PCI_cards_status = N/A
|PCIE_x1_status = Untested
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = Untested
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = Untested
|COM1_status = OK
|COM2_status = N/A
|PP_status = Untested
|PS2_keyboard_status = OK
|PS2_mouse_status = Untested
|Game_port_status = Untested
|IR_status = N/A
|Speaker_status = Untested
|DiskOnChip_status = N/A

|Sensors_status = WIP
|Watchdog_status = Untested
|CAN_bus_status = N/A
|CPUfreq_status = OK
|Powersave_status = N/A
|ACPI_status = WIP
|ACPI_comments = power button works, software poweroff works, suspend is untested
|Reboot_status = OK
|Poweroff_status = OK
|LEDs_status = N/A
|HPET_status = Untested
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = WIP
|Flashrom_comments = [http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html Reported as working with the proprietary BIOS.]

}}

== Bootlog ==

The bootlog [http://www.coreboot.org/pipermail/coreboot/2008-December/043728.html is available].

== Lspci ==

=== Proprietary bios ===

<pre>
00:00.0 Host bridge: ATI Technologies Inc RS690 Host Bridge
00:01.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx)
00:07.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 3)
00:12.0 SATA controller: ATI Technologies Inc SB600 Non-Raid-5 SATA
00:13.0 USB Controller: ATI Technologies Inc SB600 USB (OHCI0)
00:13.1 USB Controller: ATI Technologies Inc SB600 USB (OHCI1)
00:13.2 USB Controller: ATI Technologies Inc SB600 USB (OHCI2)
00:13.3 USB Controller: ATI Technologies Inc SB600 USB (OHCI3)
00:13.4 USB Controller: ATI Technologies Inc SB600 USB (OHCI4)
00:13.5 USB Controller: ATI Technologies Inc SB600 USB Controller (EHCI)
00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 13)
00:14.1 IDE interface: ATI Technologies Inc SB600 IDE
00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA)
00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge
00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control
01:05.0 VGA compatible controller: ATI Technologies Inc RS690 [Radeon X1200 Series]
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
</pre>

<pre>
# lspci -vvvvvvvnx
00:00.0 0600: 1002:7910
Subsystem: 1043:826d
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
Latency: 64
00: 02 10 10 79 06 00 20 22 00 00 00 06 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 6d 82
30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00

00:01.0 0604: 1002:7912 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 99
Bus: primary=00, secondary=01, subordinate=01, sec-latency=68
I/O behind bridge: 0000d000-0000dfff
Memory behind bridge: fdc00000-fddfffff
Prefetchable memory behind bridge: 00000000fa000000-00000000fbffffff
Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [b0] Subsystem: 1002:7912
Kernel modules: shpchp
00: 02 10 12 79 07 00 30 02 00 00 04 06 00 63 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 44 d1 d1 20 02
20: c0 fd d0 fd 01 fa f1 fb 00 00 00 00 00 00 00 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00

00:07.0 0604: 1002:7917 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: fdb00000-fdbfffff
Prefetchable memory behind bridge: 00000000fdf00000-00000000fdffffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v1) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag+ RBE+ FLReset-
DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us
ClockPM- Suprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+
Address: fee0300c Data: 4149
Capabilities: [b0] Subsystem: 1043:826d
Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100] Virtual Channel <?>
Kernel driver in use: pcieport-driver
Kernel modules: shpchp
00: 02 10 17 79 07 04 10 00 00 00 04 06 08 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 e1 e1 00 00
20: b0 fd b0 fd f1 fd f1 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00

00:12.0 0106: 1002:4380 (prog-if 01 [AHCI 1.0])
Subsystem: 1043:8231
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Interrupt: pin A routed to IRQ 22
Region 0: I/O ports at ff00 [size=8]
Region 1: I/O ports at fe00 [size=4]
Region 2: I/O ports at fd00 [size=8]
Region 3: I/O ports at fc00 [size=4]
Region 4: I/O ports at fb00 [size=16]
Region 5: Memory at fe02f000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [60] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] SATA HBA <?>
Kernel driver in use: ahci
Kernel modules: ahci
00: 02 10 80 43 07 00 30 02 00 01 06 01 00 40 00 00
10: 01 ff 00 00 01 fe 00 00 01 fd 00 00 01 fc 00 00
20: 01 fb 00 00 00 f0 02 fe 00 00 00 00 43 10 31 82
30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 00 00

00:13.0 0c03: 1002:4387 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 16
Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 87 43 07 00 a0 02 00 10 03 0c 08 40 80 00
10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00

00:13.1 0c03: 1002:4388 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin B routed to IRQ 17
Region 0: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 88 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 d0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:13.2 0c03: 1002:4389 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin C routed to IRQ 18
Region 0: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 89 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 c0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 03 00 00

00:13.3 0c03: 1002:438a (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin B routed to IRQ 17
Region 0: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 8a 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 b0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:13.4 0c03: 1002:438b (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin C routed to IRQ 18
Region 0: Memory at fe02a000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 8b 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 a0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 03 00 00

00:13.5 0c03: 1002:4386 (prog-if 20 [EHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 64 bytes
Interrupt: pin D routed to IRQ 19
Region 0: Memory at fe029000 (32-bit, non-prefetchable) [size=256]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Bridge: PM- B3+
Capabilities: [e4] Debug port: BAR=1 offset=00e0
Kernel driver in use: ehci_hcd
Kernel modules: ehci-hcd
00: 02 10 86 43 17 00 b0 02 00 20 03 0c 10 40 00 00
10: 00 90 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 04 00 00

00:14.0 0c05: 1002:4385 (rev 13)
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop+ ParErr+ Stepping+ SERR+ FastB2B+ DisINTx+
Status: Cap+ 66MHz+ UDF+ FastB2B+ ParErr+ DEVSEL=?? >TAbort+ <TAbort+ <MAbort+ >SERR+ <PERR+ INTx+
Latency: 0
Region 0: I/O ports at 0b00 [size=16]
Capabilities: [b0] HyperTransport: MSI Mapping Enable- Fixed+
Kernel driver in use: piix4_smbus
Kernel modules: i2c-piix4
00: 02 10 85 43 ff ff ff ff 13 00 05 0c 00 00 80 00
10: 01 0b 00 00 ff ff ff ff 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 00 00 00

00:14.1 0101: 1002:438c (prog-if 8a [Master SecP PriP])
Subsystem: 1043:81ef
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Interrupt: pin A routed to IRQ 16
Region 0: I/O ports at 01f0 [size=8]
Region 1: I/O ports at 03f4 [size=1]
Region 2: I/O ports at 0170 [size=8]
Region 3: I/O ports at 0374 [size=1]
Region 4: I/O ports at f900 [size=16]
Capabilities: [70] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable-
Address: 00000000 Data: 0000
Kernel driver in use: ATIIXP_IDE
Kernel modules: ata_generic, ide-pci-generic, atiixp
00: 02 10 8c 43 05 00 30 02 00 8a 01 01 00 40 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 01 f9 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 70 00 00 00 00 00 00 00 ff 01 00 00

00:14.2 0403: 1002:4383
Subsystem: 1043:8249
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin ? routed to IRQ 16
Region 0: Memory at fe020000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
Address: 0000000000000000 Data: 0000
Kernel driver in use: HDA Intel
Kernel modules: snd-hda-intel
00: 02 10 83 43 06 00 10 04 00 00 03 04 08 40 00 00
10: 04 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 49 82
30: 00 00 00 00 50 00 00 00 00 00 00 00 03 00 00 00

00:14.3 0601: 1002:438d
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
00: 02 10 8d 43 0f 00 20 02 00 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:14.4 0604: 1002:4384 (prog-if 01 [Subtractive decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Bus: primary=00, secondary=03, subordinate=03, sec-latency=64
I/O behind bridge: 0000c000-0000cfff
Memory behind bridge: fcc00000-fd7fffff
Prefetchable memory behind bridge: fde00000-fdefffff
Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
00: 02 10 84 43 27 00 a0 02 00 01 04 06 00 40 81 00
10: 00 00 00 00 00 00 00 00 00 03 03 40 c0 c0 80 22
20: c0 fc 70 fd e0 fd e0 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.0 0600: 1022:1100
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Capabilities: [80] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit
Revision ID: 1.02
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00

00:18.1 0600: 1022:1101
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.2 0600: 1022:1102
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.3 0600: 1022:1103
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Capabilities: [f0] Secure device <?>
Kernel driver in use: k8temp
Kernel modules: k8temp
00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00

01:05.0 0300: 1002:791e (prog-if 00 [VGA controller])
Subsystem: 1043:826d
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 7
Region 0: Memory at fa000000 (64-bit, prefetchable) [size=32M]
Region 2: Memory at fddf0000 (64-bit, non-prefetchable) [size=64K]
Region 4: I/O ports at de00 [size=256]
Region 5: Memory at fdc00000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
Address: 0000000000000000 Data: 0000
00: 02 10 1e 79 07 00 10 00 00 00 00 03 08 40 00 00
10: 0c 00 00 fa 00 00 00 00 04 00 df fd 00 00 00 00
20: 01 de 00 00 00 00 c0 fd 00 00 00 00 43 10 6d 82
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00

02:00.0 0200: 10ec:8168 (rev 01)
Subsystem: 1043:81aa
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 1278
Region 0: I/O ports at ee00 [size=256]
Region 2: Memory at fdbff000 (64-bit, non-prefetchable) [size=4K]
Expansion ROM at fdbc0000 [disabled] [size=128K]
Capabilities: [40] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] Vital Product Data <?>
Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+
Address: 00000000fee0300c Data: 4159
Capabilities: [60] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
ExtTag+ AttnBtn+ AttnInd+ PwrInd+ RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Suprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [84] Vendor Specific Information <?>
Capabilities: [100] Advanced Error Reporting <?>
Capabilities: [12c] Virtual Channel <?>
Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-00-1a
Capabilities: [154] Power Budgeting <?>
Kernel driver in use: r8169
Kernel modules: r8169
00: ec 10 68 81 07 04 10 00 01 00 00 02 10 00 00 00
10: 01 ee 00 00 00 00 00 00 04 f0 bf fd 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 aa 81
30: 00 00 bc fd 40 00 00 00 00 00 00 00 05 01 00 00
</pre>

{{PD-self}}

ASUS M2A-VM

2009-02-20T18:50:10Z

Ward: /* Lspci */ lspci -vvvvvvvnx

This page describes how to use coreboot on the '''[http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&modelmenu=1 ASUS M2A-VM]''' mainboard.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status = OK
|CPU_L2_status = OK
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = Untested
|CPU_virt_status = Untested

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = WIP
|RAM_DDR2_comments = Works with 2 GB. Broken with 4 GB.
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = WIP
|RAM_dualchannel_comments = Does not work with 2x2 GB unmatched DIMMS in a dualchannel setup (expected). Patches have been sent to the list to partially fix this.
|RAM_ecc_status = Untested

|IDE_status = OK
|IDE_CF_status = Untested
|IDE_25_status = N/A
|CDROM_DVD_status = OK
|SATA_status = OK
|SATA_comments = Not working: SATA multicount transfers (detected as unsupported by Linux)
|USB_status = OK
|Onboard_SCSI_status = N/A
|Onboard_VGA_status = OK
|Onboard_VGA_comments = VESA framebuffer console does not work if you select x86emu because the VESA call interface is not available. A normal X server works fine even with 3D (radeonhd driver).
|Onboard_ethernet_status = OK
|Onboard_audio_status = WIP
|Onboard_audio_comments = Stereo output (onboard jack) in HD Audio mode works. Onboard jack for microphone input seems not to work due to an unknown reason. Coreboot says it can't find . Linux kernel complains "hda_codec: Unknown model for ALC883, trying auto-probe from BIOS..."
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = N/A
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = OK
|PCI_cards_comments = Only one slot was tested.
|Mini_PCI_cards_status = N/A
|PCIE_x1_status = Untested
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = Untested
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = Untested
|COM1_status = OK
|COM2_status = N/A
|PP_status = Untested
|PS2_keyboard_status = OK
|PS2_mouse_status = Untested
|Game_port_status = Untested
|IR_status = N/A
|Speaker_status = Untested
|DiskOnChip_status = N/A

|Sensors_status = WIP
|Watchdog_status = Untested
|CAN_bus_status = N/A
|CPUfreq_status = OK
|Powersave_status = N/A
|ACPI_status = WIP
|ACPI_comments = power button works, software poweroff works, suspend is untested
|Reboot_status = OK
|Poweroff_status = OK
|LEDs_status = N/A
|HPET_status = Untested
|RNG_status = N/A
|WakeOnModem_status = Untested
|WakeOnLAN_status = Untested
|WakeOnKeyboard_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = WIP
|Flashrom_comments = [http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html Reported as working with the proprietary BIOS.]

}}

== Bootlog ==

The bootlog [http://www.coreboot.org/pipermail/coreboot/2008-December/043728.html is available].

{{PD-self}}

== Lspci ==

=== Proprietary bios ===

<pre>
00:00.0 Host bridge: ATI Technologies Inc RS690 Host Bridge
00:01.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx)
00:07.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 3)
00:12.0 SATA controller: ATI Technologies Inc SB600 Non-Raid-5 SATA
00:13.0 USB Controller: ATI Technologies Inc SB600 USB (OHCI0)
00:13.1 USB Controller: ATI Technologies Inc SB600 USB (OHCI1)
00:13.2 USB Controller: ATI Technologies Inc SB600 USB (OHCI2)
00:13.3 USB Controller: ATI Technologies Inc SB600 USB (OHCI3)
00:13.4 USB Controller: ATI Technologies Inc SB600 USB (OHCI4)
00:13.5 USB Controller: ATI Technologies Inc SB600 USB Controller (EHCI)
00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 13)
00:14.1 IDE interface: ATI Technologies Inc SB600 IDE
00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA)
00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge
00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control
01:05.0 VGA compatible controller: ATI Technologies Inc RS690 [Radeon X1200 Series]
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
</pre>

<pre>
# lspci -vvvvvvvnx
00:00.0 0600: 1002:7910
Subsystem: 1043:826d
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
Latency: 64
00: 02 10 10 79 06 00 20 22 00 00 00 06 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 6d 82
30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00

00:01.0 0604: 1002:7912 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 99
Bus: primary=00, secondary=01, subordinate=01, sec-latency=68
I/O behind bridge: 0000d000-0000dfff
Memory behind bridge: fdc00000-fddfffff
Prefetchable memory behind bridge: 00000000fa000000-00000000fbffffff
Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [b0] Subsystem: 1002:7912
Kernel modules: shpchp
00: 02 10 12 79 07 00 30 02 00 00 04 06 00 63 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 44 d1 d1 20 02
20: c0 fd d0 fd 01 fa f1 fb 00 00 00 00 00 00 00 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00

00:07.0 0604: 1002:7917 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: fdb00000-fdbfffff
Prefetchable memory behind bridge: 00000000fdf00000-00000000fdffffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v1) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag+ RBE+ FLReset-
DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us
ClockPM- Suprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+
Address: fee0300c Data: 4149
Capabilities: [b0] Subsystem: 1043:826d
Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100] Virtual Channel <?>
Kernel driver in use: pcieport-driver
Kernel modules: shpchp
00: 02 10 17 79 07 04 10 00 00 00 04 06 08 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 e1 e1 00 00
20: b0 fd b0 fd f1 fd f1 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00

00:12.0 0106: 1002:4380 (prog-if 01 [AHCI 1.0])
Subsystem: 1043:8231
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Interrupt: pin A routed to IRQ 22
Region 0: I/O ports at ff00 [size=8]
Region 1: I/O ports at fe00 [size=4]
Region 2: I/O ports at fd00 [size=8]
Region 3: I/O ports at fc00 [size=4]
Region 4: I/O ports at fb00 [size=16]
Region 5: Memory at fe02f000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [60] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] SATA HBA <?>
Kernel driver in use: ahci
Kernel modules: ahci
00: 02 10 80 43 07 00 30 02 00 01 06 01 00 40 00 00
10: 01 ff 00 00 01 fe 00 00 01 fd 00 00 01 fc 00 00
20: 01 fb 00 00 00 f0 02 fe 00 00 00 00 43 10 31 82
30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 00 00

00:13.0 0c03: 1002:4387 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 16
Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 87 43 07 00 a0 02 00 10 03 0c 08 40 80 00
10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00

00:13.1 0c03: 1002:4388 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin B routed to IRQ 17
Region 0: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 88 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 d0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:13.2 0c03: 1002:4389 (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin C routed to IRQ 18
Region 0: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 89 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 c0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 03 00 00

00:13.3 0c03: 1002:438a (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin B routed to IRQ 17
Region 0: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 8a 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 b0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:13.4 0c03: 1002:438b (prog-if 10 [OHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin C routed to IRQ 18
Region 0: Memory at fe02a000 (32-bit, non-prefetchable) [size=4K]
Kernel driver in use: ohci_hcd
Kernel modules: ohci-hcd
00: 02 10 8b 43 07 00 a0 02 00 10 03 0c 08 40 00 00
10: 00 a0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 03 00 00

00:13.5 0c03: 1002:4386 (prog-if 20 [EHCI])
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 64 bytes
Interrupt: pin D routed to IRQ 19
Region 0: Memory at fe029000 (32-bit, non-prefetchable) [size=256]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Bridge: PM- B3+
Capabilities: [e4] Debug port: BAR=1 offset=00e0
Kernel driver in use: ehci_hcd
Kernel modules: ehci-hcd
00: 02 10 86 43 17 00 b0 02 00 20 03 0c 10 40 00 00
10: 00 90 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 04 00 00

00:14.0 0c05: 1002:4385 (rev 13)
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop+ ParErr+ Stepping+ SERR+ FastB2B+ DisINTx+
Status: Cap+ 66MHz+ UDF+ FastB2B+ ParErr+ DEVSEL=?? >TAbort+ <TAbort+ <MAbort+ >SERR+ <PERR+ INTx+
Latency: 0
Region 0: I/O ports at 0b00 [size=16]
Capabilities: [b0] HyperTransport: MSI Mapping Enable- Fixed+
Kernel driver in use: piix4_smbus
Kernel modules: i2c-piix4
00: 02 10 85 43 ff ff ff ff 13 00 05 0c 00 00 80 00
10: 01 0b 00 00 ff ff ff ff 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 00 00 00

00:14.1 0101: 1002:438c (prog-if 8a [Master SecP PriP])
Subsystem: 1043:81ef
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Interrupt: pin A routed to IRQ 16
Region 0: I/O ports at 01f0 [size=8]
Region 1: I/O ports at 03f4 [size=1]
Region 2: I/O ports at 0170 [size=8]
Region 3: I/O ports at 0374 [size=1]
Region 4: I/O ports at f900 [size=16]
Capabilities: [70] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable-
Address: 00000000 Data: 0000
Kernel driver in use: ATIIXP_IDE
Kernel modules: ata_generic, ide-pci-generic, atiixp
00: 02 10 8c 43 05 00 30 02 00 8a 01 01 00 40 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 01 f9 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 70 00 00 00 00 00 00 00 ff 01 00 00

00:14.2 0403: 1002:4383
Subsystem: 1043:8249
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin ? routed to IRQ 16
Region 0: Memory at fe020000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
Address: 0000000000000000 Data: 0000
Kernel driver in use: HDA Intel
Kernel modules: snd-hda-intel
00: 02 10 83 43 06 00 10 04 00 00 03 04 08 40 00 00
10: 04 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 49 82
30: 00 00 00 00 50 00 00 00 00 00 00 00 03 00 00 00

00:14.3 0601: 1002:438d
Subsystem: 1043:81ef
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
00: 02 10 8d 43 0f 00 20 02 00 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 ef 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:14.4 0604: 1002:4384 (prog-if 01 [Subtractive decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64
Bus: primary=00, secondary=03, subordinate=03, sec-latency=64
I/O behind bridge: 0000c000-0000cfff
Memory behind bridge: fcc00000-fd7fffff
Prefetchable memory behind bridge: fde00000-fdefffff
Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
00: 02 10 84 43 27 00 a0 02 00 01 04 06 00 40 81 00
10: 00 00 00 00 00 00 00 00 00 03 03 40 c0 c0 80 22
20: c0 fc 70 fd e0 fd e0 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.0 0600: 1022:1100
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Capabilities: [80] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit
Revision ID: 1.02
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00

00:18.1 0600: 1022:1101
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.2 0600: 1022:1102
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.3 0600: 1022:1103
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Capabilities: [f0] Secure device <?>
Kernel driver in use: k8temp
Kernel modules: k8temp
00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00

01:05.0 0300: 1002:791e (prog-if 00 [VGA controller])
Subsystem: 1043:826d
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 64, Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 7
Region 0: Memory at fa000000 (64-bit, prefetchable) [size=32M]
Region 2: Memory at fddf0000 (64-bit, non-prefetchable) [size=64K]
Region 4: I/O ports at de00 [size=256]
Region 5: Memory at fdc00000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable-
Address: 0000000000000000 Data: 0000
00: 02 10 1e 79 07 00 10 00 00 00 00 03 08 40 00 00
10: 0c 00 00 fa 00 00 00 00 04 00 df fd 00 00 00 00
20: 01 de 00 00 00 00 c0 fd 00 00 00 00 43 10 6d 82
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00

02:00.0 0200: 10ec:8168 (rev 01)
Subsystem: 1043:81aa
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 1278
Region 0: I/O ports at ee00 [size=256]
Region 2: Memory at fdbff000 (64-bit, non-prefetchable) [size=4K]
Expansion ROM at fdbc0000 [disabled] [size=128K]
Capabilities: [40] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] Vital Product Data <?>
Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+
Address: 00000000fee0300c Data: 4159
Capabilities: [60] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
ExtTag+ AttnBtn+ AttnInd+ PwrInd+ RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Suprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [84] Vendor Specific Information <?>
Capabilities: [100] Advanced Error Reporting <?>
Capabilities: [12c] Virtual Channel <?>
Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-00-1a
Capabilities: [154] Power Budgeting <?>
Kernel driver in use: r8169
Kernel modules: r8169
00: ec 10 68 81 07 04 10 00 01 00 00 02 10 00 00 00
10: 01 ee 00 00 00 00 00 00 04 f0 bf fd 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 aa 81
30: 00 00 bc fd 40 00 00 00 00 00 00 00 05 01 00 00
</pre>

ASUS M2A-VM

2009-02-20T18:48:30Z

Ward: add lspci (proprietary bios)

IRC

2009-02-04T21:15:49Z

Ward:

Some of the coreboot developers and users hang out in the '''#coreboot''' channel on [http://www.freenode.net/ irc.freenode.net] (to which the '''#openbios''' channel is forwarded as well).

Here you have the chance to talk to people being involved or interested in this project. Most of the discussion is tech talk. Questions on coreboot, OpenBIOS, firmware and related topics are welcome.

Most people are in CET timezone, so don't give up when this channel seems very quiet for some time.

Glossary

2009-02-04T21:11:19Z

Ward: /* PLCC */

== A ==

=== ACPI ===
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
* http://www.acpi.info/
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)

=== AGP ===
'''Advanced Graphics Port'''
* http://en.wikipedia.org/wiki/AGP

=== AGP Aperture ===
The memory range that is set aside for AGP access.
* http://en.wikipedia.org/wiki/AGP

=== AHCI ===
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
* http://en.wikipedia.org/wiki/AHCI
* http://www.intel.com/technology/serialata/ahci.htm

=== APIC ===
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
* http://osdev.berlios.de/pic.html

== B ==

=== BAR ===
Base Address Register (on PCI device).

=== BIOS ===
Basic Input/Output System.

== C ==

=== CAR ===
Cache as RAM.

=== CMOS ===
Complementary metal oxyde semiconductor.

=== CPU ===
Central processing unit (e.g. an Athlon64)

== D ==

=== DCR ===
Decode Control Register.

=== DID ===
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.

=== DMA ===
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
* http://en.wikipedia.org/wiki/Direct_memory_access

=== DSDT ===
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also. Implementation of ACPI needs to be done in a "cleanroom" development process to avoid legal issues.
* http://acpi.sourceforge.net/dsdt/index.php

== E ==

=== EEPROM ===
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).

=== EHCI ===
Enhanced Host Controller Interface (USB host controller).

== F ==

=== Flashing ===
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.

=== Framebuffer ===
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.
A framebuffer is either:
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
* On-screen, meaning that the framebuffer is directly coupled to the visible display

* http://en.wikipedia.org/wiki/Framebuffer

== G ==

=== GART ===
Graphics Address Relocation Table.
* http://www.linuxelectrons.com/article.php/20031021142247752

=== GATT ===
Graphics Aperture Translation Table.
* http://www.linuxelectrons.com/article.php/20031021142247752

=== GPIO ===
General Purpose Input/Output.
* http://en.wikipedia.org/wiki/GPIO

=== GSoC ===
[[GSoC|Google Summer of Code]].

== H ==

=== Hypertransport ===
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
* http://en.wikipedia.org/wiki/Hypertransport
* http://www.hypertransport.org
* http://www.hotchips.org/archives/hc14/3_Tue/28_AMD_Hammer_MP_HC_v8.pdf

== I ==

=== I2C ===
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.
* http://www.esacademy.com/faq/i2c/index.htm

=== IDSEL/AD ===
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
* http://www.techfest.com/hardware/bus/pci.htm
* http://www.fpga4fun.com/PCI4.html

=== IRQ ===
Interrupt ReQuest (Handler).

== J ==

=== JTAG ===
Debugging and test 4-wire interface named after an organization which defined it.

== L ==

=== LAR ===
is the Linuxbios ARchiver, now called Lightweight [[LAR_Design|ARchiver]]. It is a small utility that we use to create and change coreboot images and their modules.

=== LPC ===
'''Low Pin Count''', an interface aimed at replacing the ISA bus.
* http://www.intel.com/design/chipsets/industry/lpc.htm

=== LRU ===
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
* http://computer.laborlawtalk.com/Least%20Recently%20Used

== M ==

=== Memory Training ===

'''Memory training''' is a very complex technlogical area. We are accumulating references to it as we find them.

* A [http://www.freshpatents.com/Training-of-signal-transfer-channels-between-memory-controller-and-memory-device-dt20080515ptan20080112255.php patent for GDDR4]
* Key to understanding training is the concept of an [http://en.wikipedia.org/wiki/Eye_diagram eye diagram]

It is amazing, but there is very little out there.

=== MII ===
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.
* http://en.wikipedia.org/wiki/MII

=== MMIO ===
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
* http://en.wikipedia.org/wiki/MMIO

=== MPTable ===
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
* http://www.uruk.org/mps/
* http://www.intel.com/design/pentium/datashts/242016.htm

=== MTRR ===
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
* http://en.wikipedia.org/wiki/MTRR

== O ==

=== OHCI ===
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).
* http://en.wikipedia.org/wiki/Ohci
* http://developer.intel.com/technology/1394/download/ohci_11.htm

== P ==

=== PAM ===
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.

=== PAT ===
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
* http://www.intel.com/design/pentium4/manuals/index_new.htm
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10

=== PAT ===
Performance Acceleration Technology.
* http://www.intel.com/design/chipsets/pat.htm

=== PCI ===
Peripheral Component Interconnect.
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect

=== PCI Configuration Space ===
* http://en.wikipedia.org/wiki/PCI_Configuration_Space
* http://www.techfest.com/hardware/bus/pci.htm

=== PCI Express / PCIe ===
* http://en.wikipedia.org/wiki/Pci_express

=== PHY ===
'''PHY layer device'''. A device that provides low level access to the physical layer.
* http://en.wikipedia.org/wiki/PHY
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer

=== PIC ===
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm

=== PIO ===
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
* http://en.wikipedia.org/wiki/Programmed_input/output

=== PIR ===
Programmable Interrupt Routing?

=== PIRQ ===
PCI IRQ routing table,
* http://www.microsoft.com/whdc/archive/pciirq.mspx
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view

=== PLCC ===
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
* http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier
* http://www.webopedia.com/TERM/P/PLCC.html

=== PLL ===
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.
* http://en.wikipedia.org/wiki/PLL

=== POST ===
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.
* http://en.wikipedia.org/wiki/Power-on_self_test

== R ==

=== RDMA ===
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access

=== RCS ===
Revision control systems.

== S ==

=== SB ===
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...

=== SBA ===
SideBand Addressing.
* http://www.linuxelectrons.com/article.php/20031021142247752

=== Shadow RAM ===
RAM which content is copied from ROM residing at the same address for speedup purposes.

=== SIO ===
Serial Input/Output.
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search

=== SMBus ===
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.
* http://www.smbus.org/
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus

=== SMM ===
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.

=== SMRAM ===
System Management Random Access Memory.

=== SOIC ===
'''Small-Outline Integrated Circuit'''.
* http://en.wikipedia.org/wiki/Small-outline_integrated_circuit

=== SPD ===
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.
* http://www.simmtester.com/page/news/showpubnews.asp?num=101

=== SPI ===
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

=== SuperIO ===
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html

== T ==

=== TLB ===
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.
* http://www.linuxelectrons.com/article.php/20031021142247752
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1

== U ==

=== UC ===
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.

=== UC ===
'''UnCacheable'''. Memory type setting in MTRR/PAT.
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

=== UHCI ===
'''Universal Host Controller Interface'''. USB standard.
* http://en.wikipedia.org/wiki/UHCI
* http://developer.intel.com/technology/usb/uhci11d.htm

== V ==

=== VGAcon ===
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm

=== VID ===
'''Vendor ID''', a way of identifying the hardware manufacturer.
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx
* http://pciids.sourceforge.net/
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.

=== VMEBus ===
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.
* http://en.wikipedia.org/wiki/VMEbus

== W ==

=== WB ===
Write-Back. Memory type setting in MTRR/PAT.

=== WC ===
Write-Combining. Memory type setting in MTRR/PAT.

=== WP ===
Write Protected. Memory type setting in MTRR/PAT.

=== WT ===
Write-Through. Memory type setting in MTRR/PAT.
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

Glossary

2009-02-04T21:08:01Z

Ward: /* S */ add entry for SOIC

== A ==

=== ACPI ===
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
* http://www.acpi.info/
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
* http://kernelslacker.livejournal.com/88243.html acpitool to generate a C source (see mailing list also)

=== AGP ===
'''Advanced Graphics Port'''
* http://en.wikipedia.org/wiki/AGP

=== AGP Aperture ===
The memory range that is set aside for AGP access.
* http://en.wikipedia.org/wiki/AGP

=== AHCI ===
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
* http://en.wikipedia.org/wiki/AHCI
* http://www.intel.com/technology/serialata/ahci.htm

=== APIC ===
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
* http://osdev.berlios.de/pic.html

== B ==

=== BAR ===
Base Address Register (on PCI device).

=== BIOS ===
Basic Input/Output System.

== C ==

=== CAR ===
Cache as RAM.

=== CMOS ===
Complementary metal oxyde semiconductor.

=== CPU ===
Central processing unit (e.g. an Athlon64)

== D ==

=== DCR ===
Decode Control Register.

=== DID ===
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.

=== DMA ===
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
* http://en.wikipedia.org/wiki/Direct_memory_access

=== DSDT ===
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also. Implementation of ACPI needs to be done in a "cleanroom" development process to avoid legal issues.
* http://acpi.sourceforge.net/dsdt/index.php

== E ==

=== EEPROM ===
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).

=== EHCI ===
Enhanced Host Controller Interface (USB host controller).

== F ==

=== Flashing ===
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.

=== Framebuffer ===
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.
A framebuffer is either:
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
* On-screen, meaning that the framebuffer is directly coupled to the visible display

* http://en.wikipedia.org/wiki/Framebuffer

== G ==

=== GART ===
Graphics Address Relocation Table.
* http://www.linuxelectrons.com/article.php/20031021142247752

=== GATT ===
Graphics Aperture Translation Table.
* http://www.linuxelectrons.com/article.php/20031021142247752

=== GPIO ===
General Purpose Input/Output.
* http://en.wikipedia.org/wiki/GPIO

=== GSoC ===
[[GSoC|Google Summer of Code]].

== H ==

=== Hypertransport ===
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
* http://en.wikipedia.org/wiki/Hypertransport
* http://www.hypertransport.org
* http://www.hotchips.org/archives/hc14/3_Tue/28_AMD_Hammer_MP_HC_v8.pdf

== I ==

=== I2C ===
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.
* http://www.esacademy.com/faq/i2c/index.htm

=== IDSEL/AD ===
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
* http://www.techfest.com/hardware/bus/pci.htm
* http://www.fpga4fun.com/PCI4.html

=== IRQ ===
Interrupt ReQuest (Handler).

== J ==

=== JTAG ===
Debugging and test 4-wire interface named after an organization which defined it.

== L ==

=== LAR ===
is the Linuxbios ARchiver, now called Lightweight [[LAR_Design|ARchiver]]. It is a small utility that we use to create and change coreboot images and their modules.

=== LPC ===
'''Low Pin Count''', an interface aimed at replacing the ISA bus.
* http://www.intel.com/design/chipsets/industry/lpc.htm

=== LRU ===
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
* http://computer.laborlawtalk.com/Least%20Recently%20Used

== M ==

=== Memory Training ===

'''Memory training''' is a very complex technlogical area. We are accumulating references to it as we find them.

* A [http://www.freshpatents.com/Training-of-signal-transfer-channels-between-memory-controller-and-memory-device-dt20080515ptan20080112255.php patent for GDDR4]
* Key to understanding training is the concept of an [http://en.wikipedia.org/wiki/Eye_diagram eye diagram]

It is amazing, but there is very little out there.

=== MII ===
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.
* http://en.wikipedia.org/wiki/MII

=== MMIO ===
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
* http://en.wikipedia.org/wiki/MMIO

=== MPTable ===
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
* http://www.uruk.org/mps/
* http://www.intel.com/design/pentium/datashts/242016.htm

=== MTRR ===
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
* http://en.wikipedia.org/wiki/MTRR

== O ==

=== OHCI ===
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).
* http://en.wikipedia.org/wiki/Ohci
* http://developer.intel.com/technology/1394/download/ohci_11.htm

== P ==

=== PAM ===
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.

=== PAT ===
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
* http://www.intel.com/design/pentium4/manuals/index_new.htm
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10

=== PAT ===
Performance Acceleration Technology.
* http://www.intel.com/design/chipsets/pat.htm

=== PCI ===
Peripheral Component Interconnect.
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect

=== PCI Configuration Space ===
* http://en.wikipedia.org/wiki/PCI_Configuration_Space
* http://www.techfest.com/hardware/bus/pci.htm

=== PCI Express / PCIe ===
* http://en.wikipedia.org/wiki/Pci_express

=== PHY ===
'''PHY layer device'''. A device that provides low level access to the physical layer.
* http://en.wikipedia.org/wiki/PHY
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer

=== PIC ===
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm

=== PIO ===
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
* http://en.wikipedia.org/wiki/Programmed_input/output

=== PIR ===
Programmable Interrupt Routing?

=== PIRQ ===
PCI IRQ routing table,
* http://www.microsoft.com/whdc/archive/pciirq.mspx
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view

=== PLCC ===
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
* http://www.webopedia.com/TERM/P/PLCC.html

=== PLL ===
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.
* http://en.wikipedia.org/wiki/PLL

=== POST ===
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.
* http://en.wikipedia.org/wiki/Power-on_self_test

== R ==

=== RDMA ===
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access

=== RCS ===
Revision control systems.

== S ==

=== SB ===
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...

=== SBA ===
SideBand Addressing.
* http://www.linuxelectrons.com/article.php/20031021142247752

=== Shadow RAM ===
RAM which content is copied from ROM residing at the same address for speedup purposes.

=== SIO ===
Serial Input/Output.
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search

=== SMBus ===
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.
* http://www.smbus.org/
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus

=== SMM ===
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.

=== SMRAM ===
System Management Random Access Memory.

=== SOIC ===
'''Small-Outline Integrated Circuit'''.
* http://en.wikipedia.org/wiki/Small-outline_integrated_circuit

=== SPD ===
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.
* http://www.simmtester.com/page/news/showpubnews.asp?num=101

=== SPI ===
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

=== SuperIO ===
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html

== T ==

=== TLB ===
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.
* http://www.linuxelectrons.com/article.php/20031021142247752
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1

== U ==

=== UC ===
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.

=== UC ===
'''UnCacheable'''. Memory type setting in MTRR/PAT.
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

=== UHCI ===
'''Universal Host Controller Interface'''. USB standard.
* http://en.wikipedia.org/wiki/UHCI
* http://developer.intel.com/technology/usb/uhci11d.htm

== V ==

=== VGAcon ===
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm

=== VID ===
'''Vendor ID''', a way of identifying the hardware manufacturer.
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx
* http://pciids.sourceforge.net/
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.

=== VMEBus ===
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.
* http://en.wikipedia.org/wiki/VMEbus

== W ==

=== WB ===
Write-Back. Memory type setting in MTRR/PAT.

=== WC ===
Write-Combining. Memory type setting in MTRR/PAT.

=== WP ===
Write Protected. Memory type setting in MTRR/PAT.

=== WT ===
Write-Through. Memory type setting in MTRR/PAT.
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

PC Engines ALIX.2CX

2009-01-27T16:45:00Z

Ward:

This page is work in progress.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status =
|CPU_L2_status =
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = N/A

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = OK
|RAM_DDR2_status = N/A
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = N/A
|RAM_ecc_status = N/A

|IDE_status =
|IDE_25_status =
|IDE_CF_status =
|CDROM_DVD_status =
|SATA_status = N/A
|USB_status = OK
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = OK
|Onboard_audio_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = OK
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status =
|PCIE_x1_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = N/A
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = N/A
|COM1_status = OK
|COM2_status = N/A
|PP_status = N/A
|PS2_keyboard_status = N/A
|PS2_mouse_status = N/A
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status = N/A
|DiskOnChip_status = N/A

|Sensors_status =
|Watchdog_status =
|CAN_bus_status = N/A
|CPUfreq_status =
|Powersave_status =
|ACPI_status = No
|Reboot_status = OK
|Poweroff_status =
|LEDs_status =
|HPET_status =
|RNG_status =
|WakeOnModem_status = N/A
|WakeOnLAN_status =
|WakeOnKeyboard_status = N/A
|WakeOnMouse_status = N/A
|Smartcard_status = N/A
|Flashrom_status = OK

}}

== Notes ==

Quick build:

Coreboot works on the Alix.2c3 and its successor Alix.2d3. The easiest way to build coreboot for these boards is to use [[Buildrom]]. Enable the 'Experimental features', choose coreboot version v3, and then select the Alix.2c3 target (this also works for the Alix.2d3).

Manual build:

Alternatively, you can build coreboot manually. Currently this board is only supported in coreboot v3.

This board still needs a binary blob from AMD called VSA.

For coreboot-v3 build as alix2c3. Then add the VSA. You can download the VSA blob from [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here]. You need to uncompress it. It should be 57504 Bytes in Size and MD5 should be 0f4fd87b3eef78bd90b56a39646f5845.

Copy that file into the root of you build system and execute the following command after coreboot is built and before you flash it.

<pre>
build/util/lar/lar -C lzma -a build/bios.bin ./amd_vsa_lx_1.01.bin:blob/vsa
</pre>

If you want to use coreboot v2 on this alix board, you'll need to port coreboot to it. See [http://www.coreboot.org/AMD_Geode_Porting_Guide the Geode Porting Guide].
{{GPL}}

PC Engines ALIX.2CX

2009-01-27T16:44:24Z

Ward: update some status fields

This page is work in progress.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status =
|CPU_L2_status =
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = N/A

|RAM_EDO_status = N/A
|RAM_SDRAM_status = N/A
|RAM_SODIMM_status = N/A
|RAM_DDR_status = OK
|RAM_DDR2_status = N/A
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = N/A
|RAM_ecc_status = N/A

|IDE_status =
|IDE_25_status =
|IDE_CF_status =
|CDROM_DVD_status =
|SATA_status = N/A
|USB_status = OK
|Onboard_VGA_status = N/A
|Onboard_ethernet_status = OK
|Onboard_audio_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status = OK
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status =
|PCIE_x1_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = N/A
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = N/A
|COM1_status = OK
|COM2_status = N/A
|PP_status = N/A
|PS2_keyboard_status = N/A
|PS2_mouse_status = N/A
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status = N/A
|DiskOnChip_status = N/A

|Sensors_status =
|Watchdog_status =
|CAN_bus_status = N/A
|CPUfreq_status =
|Powersave_status =
|ACPI_status = No
|Reboot_status = OK
|Poweroff_status =
|LEDs_status =
|HPET_status =
|RNG_status =
|WakeOnModem_status = N/A
|WakeOnLAN_status =
|WakeOnKeyboard_status = N/A
|WakeOnMouse_status = N/A
|Smartcard_status = N/A
|Flashrom_status = Yes

}}

== Notes ==

Quick build:

Coreboot works on the Alix.2c3 and its successor Alix.2d3. The easiest way to build coreboot for these boards is to use [[Buildrom]]. Enable the 'Experimental features', choose coreboot version v3, and then select the Alix.2c3 target (this also works for the Alix.2d3).

Manual build:

Alternatively, you can build coreboot manually. Currently this board is only supported in coreboot v3.

This board still needs a binary blob from AMD called VSA.

For coreboot-v3 build as alix2c3. Then add the VSA. You can download the VSA blob from [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here]. You need to uncompress it. It should be 57504 Bytes in Size and MD5 should be 0f4fd87b3eef78bd90b56a39646f5845.

Copy that file into the root of you build system and execute the following command after coreboot is built and before you flash it.

<pre>
build/util/lar/lar -C lzma -a build/bios.bin ./amd_vsa_lx_1.01.bin:blob/vsa
</pre>

If you want to use coreboot v2 on this alix board, you'll need to port coreboot to it. See [http://www.coreboot.org/AMD_Geode_Porting_Guide the Geode Porting Guide].
{{GPL}}

PC Engines ALIX.2CX

2009-01-27T16:40:39Z

Ward: /* Notes */ typo

This page is work in progress.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status =
|CPU_L2_status =
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = N/A

|RAM_EDO_status = N/A
|RAM_SDRAM_status =
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = N/A
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = N/A
|RAM_ecc_status = N/A

|IDE_status =
|IDE_25_status =
|IDE_CF_status =
|CDROM_DVD_status =
|SATA_status = N/A
|USB_status = OK
|Onboard_VGA_status = N/A
|Onboard_ethernet_status =
|Onboard_audio_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status =
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status =
|PCIE_x1_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = N/A
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = N/A
|COM1_status = Yes
|COM2_status = N/A
|PP_status = N/A
|PS2_keyboard_status = N/A
|PS2_mouse_status = N/A
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status =
|DiskOnChip_status =

|Sensors_status =
|Watchdog_status =
|CAN_bus_status = N/A
|CPUfreq_status =
|Powersave_status =
|ACPI_status = No
|Reboot_status =
|Poweroff_status =
|LEDs_status =
|HPET_status =
|RNG_status =
|WakeOnModem_status = N/A
|WakeOnLAN_status =
|WakeOnKeyboard_status = N/A
|WakeOnMouse_status = N/A
|Smartcard_status = N/A
|Flashrom_status = Yes

}}

== Notes ==

Quick build:

Coreboot works on the Alix.2c3 and its successor Alix.2d3. The easiest way to build coreboot for these boards is to use [[Buildrom]]. Enable the 'Experimental features', choose coreboot version v3, and then select the Alix.2c3 target (this also works for the Alix.2d3).

Manual build:

Alternatively, you can build coreboot manually. Currently this board is only supported in coreboot v3.

This board still needs a binary blob from AMD called VSA.

For coreboot-v3 build as alix2c3. Then add the VSA. You can download the VSA blob from [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here]. You need to uncompress it. It should be 57504 Bytes in Size and MD5 should be 0f4fd87b3eef78bd90b56a39646f5845.

Copy that file into the root of you build system and execute the following command after coreboot is built and before you flash it.

<pre>
build/util/lar/lar -C lzma -a build/bios.bin ./amd_vsa_lx_1.01.bin:blob/vsa
</pre>

If you want to use coreboot v2 on this alix board, you'll need to port coreboot to it. See [http://www.coreboot.org/AMD_Geode_Porting_Guide the Geode Porting Guide].
{{GPL}}

PC Engines ALIX.2CX

2009-01-27T16:40:18Z

Ward: /* Notes */ some more detail on building this board.

This page is work in progress.

== Status ==

{{Status|

|CPU_status = OK
|CPU_L1_status =
|CPU_L2_status =
|CPU_L3_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = N/A

|RAM_EDO_status = N/A
|RAM_SDRAM_status =
|RAM_SODIMM_status = N/A
|RAM_DDR_status = N/A
|RAM_DDR2_status = N/A
|RAM_DDR3_status = N/A
|RAM_dualchannel_status = N/A
|RAM_ecc_status = N/A

|IDE_status =
|IDE_25_status =
|IDE_CF_status =
|CDROM_DVD_status =
|SATA_status = N/A
|USB_status = OK
|Onboard_VGA_status = N/A
|Onboard_ethernet_status =
|Onboard_audio_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Smartcard_status = N/A
|Onboard_CF_status =
|Onboard_PCMCIA_status = N/A

|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status =
|PCIE_x1_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x8_status = N/A
|PCIE_x16_status = N/A
|PCIE_x32_status = N/A
|HTX_status = N/A

|Floppy_status = N/A
|COM1_status = Yes
|COM2_status = N/A
|PP_status = N/A
|PS2_keyboard_status = N/A
|PS2_mouse_status = N/A
|Game_port_status = N/A
|IR_status = N/A
|Speaker_status =
|DiskOnChip_status =

|Sensors_status =
|Watchdog_status =
|CAN_bus_status = N/A
|CPUfreq_status =
|Powersave_status =
|ACPI_status = No
|Reboot_status =
|Poweroff_status =
|LEDs_status =
|HPET_status =
|RNG_status =
|WakeOnModem_status = N/A
|WakeOnLAN_status =
|WakeOnKeyboard_status = N/A
|WakeOnMouse_status = N/A
|Smartcard_status = N/A
|Flashrom_status = Yes

}}

== Notes ==

Quick build:

Coreboot works on the Alix.2c3 and its successor Alix.2d3. The easiest way to build coreboot for these boards is to use [[Buildrom]]. Enable the 'Experimental features', choose coreboot version v3, and then select the Alix.2c3 target (this also works for the Alix.2d3).

Manual build:

Alternatively, you can build coreboot manually. Currently this board is only supported in coreboot v3.

This board still needs a binary blob from AMD called VSA.

For coreboot-v3 build as alix2c3. Then add the VSA. You can download the VSA blob from [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here]. You need to uncompress it. It should be 57504 Bytes in Size and MD5 should be 0f4fd87b3eef78bd90b56a39646f5845.

Copy that file into the root of you build system and execute the following command after coreboot is build and before you flash it.

<pre>
build/util/lar/lar -C lzma -a build/bios.bin ./amd_vsa_lx_1.01.bin:blob/vsa
</pre>

If you want to use coreboot v2 on this alix board, you'll need to port coreboot to it. See [http://www.coreboot.org/AMD_Geode_Porting_Guide the Geode Porting Guide].
{{GPL}}

Press

2009-01-08T01:21:45Z

Ward: add new heise article by Anton Borisov

== 2009 ==
* January 06, 2009: [http://www.heise-online.co.uk/open/The-Open-Source-BIOS-is-Ten-An-interview-with-the-coreboot-developers--/features/112353/0: The Open Source BIOS is Ten]

== 2008 ==

* October 06, 2008: [http://www.heise.de/newsticker/Freie-Software-Was-dringend-noetig-ist--/meldung/116976 Heise: Freie Software: Was dringend nötig ist] (German)
* October 06, 2008: [http://meneame.net/story/fsf-anuncia-proyectos-software-libre-considera-alta-prioridad menéame: La FSF anuncia los proyectos de software libre que considera de alta prioridad] (Spanish)
* August 28, 2008: [http://www.linux.com/feature/145946 Linux.com: Behind the doors of the Free Software Foundation]
* February 26, 2008: [http://www.oszine.de/node/8546 OSZine: LinuxBIOS heißt jetzt Coreboot] (German) ([http://translate.google.com/translate?u=http%3A%2F%2Fwww.oszine.de%2Fnode%2F8546&langpair=de%7Cen&hl=en&ie=UTF-8 EN])
* February 25, 2008: [http://www.golem.de/0802/57919.html Golem: Aus LinuxBIOS wird Coreboot] (German)
* February 25, 2008: [http://www.pro-linux.de/news/2008/12373.html Pro-Linux: LinuxBIOS wird zu Coreboot] (German)
* February 07, 2008: [http://softlibre.barrapunto.com/article.pl?sid=08/02/07/1357250 Barrapunto: LinuxBIOS cambia de nombre a coreboot] (Spanish) ([http://translate.google.com/translate?u=http%3A%2F%2Fsoftlibre.barrapunto.com%2Farticle.pl%3Fsid%3D08%2F02%2F07%2F1357250&langpair=es%7Cen&hl=en&ie=UTF-8 EN])
* January 24, 2008: [http://www.heise.de/newsticker/meldung/102381 OSMB: Open Source Business Award in Nürnberg überreicht] (German)

== 2007 ==

* October 23, 2007: [http://digg.com/linux_unix/LinuxBIOS_Brings_Clones_One_Step_Closer_to_Freedom Digg: LinuxBIOS Brings Clones One Step Closer to Freedom]
* October 23, 2007: [http://www.enterprisenetworkingplanet.com/nethub/article.php/3706881 Enterprise Networking Planet: LinuxBIOS Brings Clones One Step Closer to Freedom]
* October 10, 2007: [http://linux.slashdot.org/article.pl?sid=07/10/10/1555202 Slashdot: Get Speed-Booting with an Open BIOS]
* October 08, 2007: [http://www.lockergnome.com/nexus/knitter/2007/10/08/boot-linux-faster-with-an-open-bios Techblog: Boot Linux Faster With An Open BIOS]
* March 09, 2007: [http://hardware.slashdot.org/article.pl?sid=07/03/09/146215 Slashdot: LinuxBIOS Gets GUI]
* March 09, 2007: [http://www.golem.de/0703/50979.html Golem: LinuxBIOS mit X-Server] (German) ([http://translate.google.com/translate?u=http%3A%2F%2Fwww.golem.de%2F0703%2F50979.html&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN])
* March 08, 2007: [http://www.genbeta.com/2007/03/08-linuxbios-arranca-tu-ordenador-en-6-segundos Genbeta: LinuxBIOS, arranca tu ordenador en 6 segundos] (Spanish) [[http://66.249.93.104/translate_c?hl=en&ie=UTF-8&oe=UTF-8&langpair=es%7Cen&u=http://www.genbeta.com/2007/03/08-linuxbios-arranca-tu-ordenador-en-6-segundos&prev=/language_tools EN]]
* March 08, 2007: [http://meneame.net/story/linuxbios-servidor-x11-flash-rom-permite-iniciar-pc-6-segundos menéame: LinuxBIOS con un servidor X11 en una Flash ROM permite iniciar una PC en 6 segundos] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fmeneame.net%2Fstory%2Flinuxbios-servidor-x11-flash-rom-permite-iniciar-pc-6-segundos&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* March 08, 2007: [http://digg.com/linux_unix/LinuxBIOS_with_X11_server_completely_in_Flash_ROM Digg.com: LinuxBIOS with X11 server, completely in Flash ROM]
* March 02, 2007: [http://www.heise.de/newsticker/meldung/86142/ Heise: Steiniger Weg zum LinuxBIOS] (German) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2F86142%2F&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 25, 2007: [http://digg.com/linux_unix/World_s_First_Motherboard_Using_LinuxBIOS_Released Digg.com: World's First Motherboard Using LinuxBIOS Released]
* February 25, 2007: [http://www.vivalinux.com.ar/hard/gigabyte-open-motherboard.html Viva Linux: Primer motherboard soportado por LinuxBIOS] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.vivalinux.com.ar%2Fhard%2Fgigabyte-open-motherboard.html&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 25, 2007: [http://www.neowin.net/index.php?act=view&id=38368 Neowin.net: World’s First Mainboard with Open-Source BIOS]
* February 24, 2007: [http://www.ixbt.com/news/hard/index.shtml?07/84/10 iXBT: Gigabyte M57SLI-S4: ?????? ?????????? ????????? ????? ? ?????????? LinuxBIOS] (?)
* February 23, 2007: [http://www.pcinpact.com/actu/news/34884-linuxbios-bios-open-source-gigabyte.htm PC INpact: LinuxBIOS: premier BIOS open source pour le grand public] (French) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.pcinpact.com%2Factu%2Fnews%2F34884-linuxbios-bios-open-source-gigabyte.htm&langpair=fr%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 22, 2007: [http://www.heise.de/newsticker/meldung/85705 Heise: LinuxBIOS für Mainstream-Mainboard mit Sockel-AM2] (German) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2F85705&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 22, 2007: [http://www.golem.de/0702/50694.html Golem: LinuxBIOS unterstützt Gigabyte-Mainboard] (German) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.golem.de%2F0702%2F50694.html&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 22, 2007: [http://br-linux.org/linux/gigabyte-vai-oferecer-uma-placa-mae-com-linuxbios BR-Linux.org: Gigabyte vai oferecer uma placa mãe com LinuxBios] (?)
* February 23, 2007: [http://www.xbitlabs.com/news/mainboards/display/20070223145912.html X-bit labs: Linux Supporters Celebrate World’s First Mainboard with Open-Source BIOS]
* February 22, 2007: [http://permalink.gmane.org/gmane.linux.kernel/496453 LKML: First desktop motherboard supported by LinuxBIOS: GIGABYTE M57SLI-S4]
* February 19, 2007: [http://www.dellideastorm.com/article/show/62549/LinuxBIOS_instead_of_proprietary_BIOS Dell Idea Storm: LinuxBIOS] ([http://www.dellideastorm.com/article/show/63081/Use_LinuxBIOS_on_Dell_PCs__Workstations Alternative page])
* February 10, 2007: [http://www.linux.org.ru/view-message.jsp?msgid=1781619 Linux.org.ru Forum: Interview with Ronald G. Minnich] (Russian) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.linux.org.ru%2Fview-message.jsp%3Fmsgid%3D1781619&langpair=ru%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 09, 2007: [http://news.linux.com/article.pl?sid=07/02/09/2134214&tid=96 Linux.com: LinuxBIOS creator talks about OLPC and EFI]
* February 09, 2007: [http://kriptopolis.org/el-creador-de-linuxbios-desconfia-de-efi Kriptopolis: El creador de LinuxBIOS desconfía de EFI] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fkriptopolis.org%2Fel-creador-de-linuxbios-desconfia-de-efi&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 08, 2007: [http://www.osnews.com/story.php?news_id=17213 OSNews: LinuxBIOS Creator: EFI is a Security Threat]
* February 06, 2007: [http://fosdem.org/2007/interview/ronald+g+minnich FOSDEM Interview: Ronald G Minnich]
* January 29, 2007: [http://meneame.net/story/primera-placa-base-sobremesa-soportada-linuxbios menéame: Primera placa base de sobremesa soportada por LinuxBIOS] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fmeneame.net%2Fstory%2Fprimera-placa-base-sobremesa-soportada-linuxbios%23comment-10&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]

== 2006 ==

* December 25, 2006: [http://www.madpenguin.org/cms/?m=show&id=7694 Mad Penguin: LinuxBIOS: The Forgotten Hero]
* December 18, 2006: [http://meneame.net/story/linuxbios-casi-listo menéame: LinuxBIOS, casi listo] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fmeneame.net%2Fstory%2Flinuxbios-casi-listo&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* December 18, 2006: [http://www.vivalinux.com.ar/hard/linuxbios-casi-listo.html VivaLinux: LinuxBIOS listo para entregar su primer fruto] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.vivalinux.com.ar%2Fhard%2Flinuxbios-casi-listo.html&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* December 16, 2006: [http://www.diariored.com/blog/001571.php Diarored: El proyecto LinuxBIOS listo para entregar su primer fruto] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.diariored.com%2Fblog%2F001571.php&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* December 14, 2006: [http://www.symlink.ch/articles/06/12/14/1319250.shtml Symlink: Status des LinuxBIOS] (German)
* December 08, 2006: [http://www.freerepublic.com/focus/f-chat/1750705/posts Free Republic: LinuxBIOS ready to go mainstream]
* December 08, 2006: [http://www.tecchannel.de/news/themen/entwicklung/457312/index.html tecCHANNEL: LinuxBIOS scheint fertig zu sein] (German)
* December 07, 2006: [http://osnews.com/comment.php?news_id=16663&limit=no&threshold=-1 OSNews: LinuxBIOS Ready to Go Mainstream]
* December 07, 2006: [http://pcburn.com/article.php?sid=1967 PCBurn: LinuxBIOS: Coming Along Nicely]
* December 07, 2006: [http://technocrat.net/d/2006/12/7/11935 Technocrat.net: LinuxBIOS - getting closer]
* December 07, 2006: [http://www.linux.com/article.pl?sid=06/11/30/199208 Linux.com: LinuxBIOS ready to go mainstream]
* November 19, 2006: [http://www.linux.org.ru/view-message.jsp?msgid=1661374 Linux.org.ru Forum: Google Linux BIOS] (Russian) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.linux.org.ru%2Fview-message.jsp%3Fmsgid%3D1661374&langpair=ru%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* November 17, 2006: [http://linuxhelp.blogspot.com/2006/11/linuxbios-truly-gpled-free-software.html LinuxBIOS - A truly GPLed Free Software BIOS]
* November 15, 2006: [http://hardware.slashdot.org/hardware/06/11/15/1423223.shtml Slashdot: Google Sponsors the LinuxBIOS project]
* November 14, 2006: [http://google-code-updates.blogspot.com/2006/11/google-sponsors-linuxbios-project.html Google Code Updates: Google Sponsors the LinuxBIOS project]
* November 14, 2006: [http://www.heise.de/newsticker/meldung/81005 Heise: Google unterstützt LinuxBIOS-Projekt] (German)
* November 14, 2006: [http://www.golem.de/0611/48929.html Golem: Google unterstützt freies BIOS] (German)
* September 21, 2006: [http://www.pro-linux.de/news/2006/10247.html Pro-Linux: LinuxBIOS-Symposium dieses Jahr in Hamburg] (German)
* September 5, 2006: [http://www.linuxdevices.com/news/NS2401026948.html LinuxDevices.com: Boot Linux faster with an open BIOS]
* August 31, 2006: [http://www-128.ibm.com/developerworks/linux/library/l-bios.html?ca=dgr-lnxw09OpenBIOS IBM developerWorks: Open BIOSes for Linux]
* August 14, 2006: [http://lwn.net/Articles/195341/ LWN: LinuxBIOS Symposium in Europe this year!] (LWN)
* February xx, 2006: [http://www.linuxbios.org/images/c/c0/LX2%40FSF_4a.pdf SAMAG: FSF is moving towards LinuxBIOS deployment] (Russian article by Anton Borisov)

== 2005 ==

* September 28, 2005: [http://www.linuxjournal.com/article/8177 The Ultimate Linux Lunchbox]
* July 19, 2005: [http://www.linuxjournal.com/article/8310 Porting LinuxBIOS to the AMD SC520: A Follow-up Report]
* June 30, 2005: [http://www.linuxjournal.com/article/8120 Porting LinuxBIOS to the AMD SC520]
* February 28, 2005: [http://www.pro-linux.de/news/2005/7867.html FSF startet Kampagne für ein freies BIOS] (German)
* February 28, 2005: [http://linux.slashdot.org/article.pl?sid=05/02/28/1126226 Stallman Calls For Action on Free BIOS]
* February 28, 2005: [http://news.com.com/2100-7344_3-5593241.html Foundation wants more of the PC to be free]
* February 26, 2005: [http://www.fsf.org/news/freebios.html Stallman calls for action on Free BIOS]

== 2004 ==

* October 26, 2004: [http://www.linuxjournal.com/article/7857 Reducing OS Boot Times for In-Car Computer Applications, Part III] (has some LinuxBIOS-related content)
* April 29, 2004: [http://izcity.com/data/system/article399.htm Izcity.com: LinuxBIOS: a computer with Linux in the heart] (Russian) [[http://translate.google.com/translate?u=http%3A%2F%2Fizcity.com%2Fdata%2Fsystem%2Farticle399.htm&langpair=ru%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* March 24, 2004: [http://developers.slashdot.org/article.pl?sid=04/03/24/2327229 In-Depth Look At LinuxBIOS]
* February 1, 2004: [http://www.linuxjournal.com/article/7170 LinuxBIOS at Four]

== 2003 ==

* December 10, 2003: [http://developers.slashdot.org/article.pl?sid=03/12/10/1434210 LinuxBIOS Project Usenix Paper]
* December 8, 2003: [http://www.theinquirer.net/default.aspx?article=13087 Stackable Open Source BIOS could cut proprietary stuff dead]
* July, 2003: [http://www.heise.de/ix/artikel/2003/07/048/ Linux-BIOS: Von der Idee zur Technik] (German)
* June, 2003: [http://www.linux-magazin.de/Artikel/ausgabe/2003/06/093_linuxbios/linuxbios.html Linux Magazin: Linux auf dem Motherboard] (German)

== 2002 ==

* November 26, 2002: [http://www.heise.de/newsticker/meldung/32643 LinuxBIOS bootet (Windows-)PCs] (German)
* November 25, 2002: [http://developers.slashdot.org/article.pl?sid=02/11/25/0331220 LinuxBIOS Boots Linux, OpenBSD, Windows]
* November 24, 2002: [http://zgp.org/linux-elitists/Pine.LNX.4.33.0211242330350.11414-100000@hydrogen.leitl.org.html ANNOUNCE: LinuxBIOS booting Windows 2000 (free software BIOS)]
* October 8, 2002: [http://science.slashdot.org/article.pl?sid=02/10/08/0324241 LinuxBIOS/BProc-based Supercomputer for LANL] from [http://slashdot.org/ Slashdot]
* September 30, 2002: [http://www.gridtoday.com/02/0930/100480.html Linux NetworX Announces LinuxBIOS Availability]
* September 23, 2002: [http://www.lanl.gov/worldview/news/releases/archive/02-106.shtml Linux Networx to build Linux supercomputer for Los Alamos] from LANL news
* September 23, 2002: [http://www.lnxi.com/news/lanl_info.php Los Alamos National Laboratory Selects Linux NetworX to Build 10 teraFLOP Linux Supercomputer] from Linux Networx

== 2001 ==

* December 15, 2001: [http://slashdot.org/article.pl?sid=01/12/15/050212 LinuxBIOS Gains Steam] from [http://slashdot.org/ Slashdot]
* December 1, 2001: [http://www.linuxjournal.com/article.php?sid=4888 Kernel Korner: About LinuxBIOS] by Eric Biederman in [http://www.linuxjournal.com/ Linux Journal]
* October 18, 2001: [http://lwn.net/2001/1018/devel.php3 Developer section] from [http://lwn.net/ LWN.net]
* October 15, 2001: [http://www.abqjournal.com/paperboy/ia/biz/478127biz10-15-01.htm LANL Builds Clever Software Tool and Gives It Away], by [http://www.inkstain.net/fleck/ John Fleck] in the [http://www.abqjournal.com/ Albuquerque Journal]
* August 3, 2001: David Hendricks at LANL's CCS division 2001 [http://www.lanl.gov/orgs/pa/News/080201.html#anchor5 student poster session]
* March 3, 2001: [http://slashdot.org/article.pl?sid=01/03/03/2313255 Booting Linux in Three Seconds] from [http://slashdot.org/ Slashdot]

== 2000 ==

* October 17, 2000: LANL's News Bulletin [http://www.lanl.gov/orgs/pa/News/101700.html#anchor5 article]
* October 12, 2000: SiS [http://alllinuxdevices.com/news_story.php3?ltsn=2000-10-12-006-03-PL-PR PR: SiS Accomplishes the First-Ever x86 Platform for LinuxBIOS] ([http://alllinuxdevices.com allLinux devices])
* June 15, 2000: [http://www.linuxdevices.com/links/LK8294110575.html The Linux BIOS Project]
* June 14, 2000: [http://linux.slashdot.org/article.pl?sid=00/06/14/2110209 Linux BIOS] from [http://slashdot.org/ Slashdot]

__NOTOC__
--[[User:Ward|Ward]] 01:21, 8 January 2009 (UTC)

Tyan S2881

2008-10-10T20:41:08Z

Ward: /* Building coreboot */

===Before you begin===

Do yourself a favor, and get a BiosSavior before you begin. There are different models, make sure you order the one you need. It depends on the size and type of the ROM chip on your board. Our S2881 board has a 4Mbit PLCC chip. This is the list of BiosSavior vendors:

http://www.ioss.com.tw/web/English/WheretoBuy.html

While coreboot replaces the functions of the proprietary bios, it does NOT replace the VGA bios. If you want VGA on your coreboot'd machine (not strictly necessary for servers), you will need to extract the VGA bios and concatenate it with the coreboot image, before burning it to your ROM. See below for details.

This wiki page is maintained by Ward Vandewege (ward at gnu dot org).

===Hardware===

The S2881 comes with a 4Mbit BIOS chip, which does not suffice to put a Linux kernel in ROM. However, it's sufficient to have a fully functional coreboot with FILO payload, as described below.

It turns out that you can also use an 8Mbit BIOS chip on the S2881. For instance, flashrom supports flashing the SST 49LF080A on the S2881 without problems. Having a 8Mbit chip allows putting a Linux kernel into the BIOS, as described in [http://www.linuxbios.org/Tyan_S2892_Build_Tutorial the S2892 the OLPC way] build tutorial.

===Payload===

coreboot requires a [[Payloads|Payload]] to boot an operating system.

If you want to boot from the network, you will need to use [http://www.etherboot.org Etherboot].

If you want to boot from an IDE drive, SATA drive, USB stick or CDROM, you can use [[FILO]].

===Building the payload===

In order to boot from a SATA disk, we use FILO.

Once you've downloaded FILO, you will need to put a file 'Config' in its root tree. An example can be found in the distribution, called 'defconfig'.

You can configure FILO to load Grub. Here's my Config, which does that:

# Use grub instead of autoboot?
USE_GRUB = 1
# Grub menu.lst path
MENULST_FILE = "hda1:/grub/menu.lst"
# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
IDE_DISK = 1
# Add a short delay when polling status registers
# (required on some broken SATA controllers)
IDE_DISK_POLL_DELAY = 1
# Driver for USB Storage
USB_DISK = 1
# VGA text console
VGA_CONSOLE = 1
PC_KEYBOARD = 1
# Enable the serial console
SERIAL_CONSOLE = 1
# Serial console; real external serial port
SERIAL_IOBASE = 0x3f8
SERIAL_SPEED = 115200
# Filesystems
FSYS_EXT2FS = 1
FSYS_ISO9660 = 1
# Support for boot disk image in bootable CD-ROM (El Torito)
ELTORITO = 1
# PCI support
SUPPORT_PCI = 1
# Enable this to scan PCI busses above bus 0
# AMD64 based boards do need this.
PCI_BRUTE_SCAN = 1
# Loader for standard Linux kernel image, a.k.a. /vmlinuz
LINUX_LOADER = 1

In order to get serial output from Grub, you will also need to add something like this to your menu.list:

# serial port 0
serial --unit=0 --speed=115200
terminal --timeout=15 serial console

Now execute 'make', which will generate a filo.elf file that will be your payload. You will need to refer to this file to build coreboot as explained below, because it gets included in the coreboot ROM image.

===Building coreboot ===

Download coreboot ([[Download coreboot]]). You need subversion revision 2251 or higher. Note that revisions 2288 through 2295 are known bad, do not use those.

If you want VGA support, a few changes are required in the coreboot source tree. Edit this file:

src/mainboard/tyan/s2881/Options.lb

You'll need to enable the following two lines:

#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1

Now - if you are going to be using a rom chip larger than 512K, you will need to also make a change in

src/mainboard/tyan/s2881/Config.lb

Assuming you are using a 1MB chip, modify the onboard vga device info from this

chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end

to this

chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000"
end

This tells coreboot where to find the VGA rom. Depending on the size of the rom chip you use, it will be at a different address (which is calculated from the top of the rom chip, and we prepend the vga rom to the coreboot image!).

Whether you want VGA or not, build a tyan/s2881 tree.

cd targets
./buildtarget tyan/s2881

Modify tyan/s2881/Config.lb; change payload setting to point to your filo.elf file 

If you don't need VGA, you will need to modify tyan/s2881/Config.lb. Comment out the line:

option ROM_SIZE = 475136

If you do need VGA, modify the ROM_SIZE line to the following, because our VGA bios is only 36KB, not 48K:

option ROM_SIZE = 487424

Make you are using GCC 3.4 (not GCC 4.0), or your image will be too large, and then:

cd tyan/s2881/s2881
make

===VGA bios===

Skip this section if you don't need VGA support in your coreboot.

The s2881 VGA bios is 36K long. The last 4KB are not available in RAM after boot (with the proprietary BIOS), however, so we can NOT use this method to extract the VGA BIOS:

While booted with your proprietary BIOS, you can see where your vga bios starts
and how much space it takes by issuing
<code>cat /proc/iomem | grep "Video ROM"</code>
Then get a copy of your vga bios.
<code>dd if=/dev/mem of=vgabios.bin bs=1k count=32 skip=768</code>
Our vga bios is 32K. Verify that the image is correct - it should start with 55 AA,
and contain strings that indicate it's your VGA bios. You should be able to clearly
make out 'ATI RAGE' etc.

So this does not work - the last 4K is missing. Thankfully, Anton Borisov has some tools that can extract the VGA BIOS - and other option ROMs, in fact - from the BIOS images that Tyan offers on its website.

You can download the tool for AMI here:

http://www.kaos.ru/biosgfx/download/AmiDeco_0.31e.src.tar.gz

Then download the latest Bios for the s2881 from the TYAN website:

http://www.tyan.com/support_download_bios.aspx?model=S.S2881

Once you have the image, you can display its contents like this:

./amideco 2881v206.rom -l

That should show output like:

-=AmiBIOSDeco, version 0.31e (Linux)=-
FileLength : 80000 (524288 bytes)
FileName : 2881v206.rom
AMIBIOS information:
Version : 0800
Packed Data : 56C90 (355472 bytes)
Start : DF83C
Packed Offset : 5F83C
Offset : 80000
Released : 14 June 2005
DirName : 2881v206.---
+------------------------------------------------------------------------------+
| Class.Instance (Name) Packed ---> Expanded Compression Offset |
+------------------------------------------------------------------------------+
08 01 ( Interface) 00798 ( 01944) => 00798 ( 01944) 5F83Ch
04 02 ( Setup Client) 03F40 ( 16192) => 069A2 ( 27042) + 5B8E8h
0C 03 ( ROM-ID) 00008 ( 00008) => 00008 ( 00008) 5B8CCh
0E 04 ( OEM Logo) 00B4D ( 02893) => 4B436 (308278) + 5AD68h
1A 05 ( Small Logo) 00532 ( 01330) => 026A2 ( 09890) + 5A820h
18 06 (ADM (Display MGR)) 01741 ( 05953) => 04019 ( 16409) + 590C8h
19 07 ( ADM Font) 0059C ( 01436) => 01304 ( 04868) + 58B18h
1B 08 ( SLAB) 25016 (151574) => 4CAA8 (314024) + 33AECh
21 09 ( Multilanguage) 03B90 ( 15248) => 0844A ( 33866) + 2FF48h
20 10 ( PCI AddOn ROM) 05B84 ( 23428) => 09000 ( 36864) + 2A3B0h
20 11 ( PCI AddOn ROM) 06343 ( 25411) => 0C800 ( 51200) + 24058h
20 12 ( PCI AddOn ROM) 0D5EA ( 54762) => 0E000 ( 57344) + 16A58h
20 13 ( PCI AddOn ROM) 05678 ( 22136) => 09000 ( 36864) + 113CCh
11 14 ( P6 Microcode) 2062004 (33955844) => 00039 ( 00057) + 0EBA4h
2E 15 ( User ROM) 047B3 ( 18355) => 07800 ( 30720) + 0A3DCh
06 16 ( DMI Data) 003CD ( 00973) => 00A1A ( 02586) + 09FF8h
2F 17 ( User-Defined ;)) 00C1D ( 03101) => 02595 ( 09621) + 093C4h
80 18 ( User-Defined ;)) 00038 ( 00056) => 00038 ( 00056) 09378h
Total Sections : 18

Now extract all these parts:

./amideco 2881v206.rom -x

That will create a number of new files:

-rw-r--r-- 1 ward ward 27042 2006-07-07 16:29 amibody.04
-rw-r--r-- 1 ward ward 1944 2006-07-07 16:29 amibody.08
-rw-r--r-- 1 ward ward 8 2006-07-07 16:29 amibody.0c
-rw-r--r-- 1 ward ward 308278 2006-07-07 16:29 amibody.0e
-rw-r--r-- 1 ward ward 0 2006-07-07 16:29 amibody.11
-rw-r--r-- 1 ward ward 16409 2006-07-07 16:29 amibody.18
-rw-r--r-- 1 ward ward 4868 2006-07-07 16:29 amibody.19
-rw-r--r-- 1 ward ward 9890 2006-07-07 16:29 amibody.1a
-rw-r--r-- 1 ward ward 314024 2006-07-07 16:29 amibody.1b
-rw-r--r-- 1 ward ward 33866 2006-07-07 16:29 amibody.21
-rw-r--r-- 1 ward ward 36864 2006-07-07 16:29 amipci_00.20
-rw-r--r-- 1 ward ward 51200 2006-07-07 16:29 amipci_01.20
-rw-r--r-- 1 ward ward 57344 2006-07-07 16:29 amipci_02.20
-rw-r--r-- 1 ward ward 36864 2006-07-07 16:29 amipci_03.20

We know that our VGA BIOS is 36K long. Only 2 files fit the bill: amipci_00.20 and amipci_03.20. If you run 'strings' on both files, you'll see that the former is the VGA BIOS, and the latter is the Option ROM for the Broadcom network card.

So, now that we have the proper VGA bios image (36K long), we need to concatenate the VGA bios with the coreboot image

<code>cat amipci_00.20 coreboot.rom > final_coreboot.rom</code>

===Burning the bios===

Make sure your Biossavior is set to the 'RD1' position (not to 'ORG'!), so that you can always revert to the original bios.

On the target machine:

cd coreboot-v2/util/flashrom
./flashrom -v -w path/to/your/coreboot.rom

If you want VGA support, make sure you burn the final_coreboot.rom image!

===Booting coreboot===

You now need to 'halt' the machine. A soft reset won't work the first time you boot from the proprietary BIOS into coreboot.

Since we set up serial output in the coreboot configuration files above, you will want to hook up a serial console (or a copy of minicom or the like) to see what the box is doing while starting up. Keep your eyes on the screen after hitting the power button - coreboot will be up and running way before you expect it!

If you have problems, don't despair. Power down the box, switch the biossavior to 'ORG' and boot in the proprietary BIOS. Just don't forget to switch the biossavior back to the 'RD1' position before flashing the BIOS!

See what went wrong, and subscribe and post to the friendly and helpful [http://wiki.linuxbios.org/index.php/Mailinglist mailing list] if you can't figure it out by yourself.

===Hardware monitoring===

The s2881 has 2 HWM chips, each driving a number of fans and temperature sensors. As of SVN revision 2674, the main HWM chip that drives most of the fans (ADT7463) is configured to be in automatic (hardware) fan control mode, based on the temperature sensors connected to it. These are the specific HWM settings:

* fans under automatic hardware control
* fans blow by default at 25% speed
* if any of the sensors goes above 55C (Tmin), the fans start blowing harder to compensate
* if any of the sensors reach 70C (THERM limit), the fans start blowing at full speed

These settings should lead to longer fan life, reduced power consumption, and better protection against accidental fan speed misconfiguration from software. And the machine is a lot less loud under light load.

The original Tyan BIOS had these settings:

* fans under manual (software) control
* fans blow by default at 100% speed
* automatic mode Tmin set to 90C
* automatic mode THERM limit set to 100C

The coreboot settings should be more ideal for real world deployment, and are a lot safer.

{{GPL}}

[[Category:Tutorials]]

Tyan S2881

2008-10-10T20:39:49Z

Ward: /* Building coreboot */

===Before you begin===

Do yourself a favor, and get a BiosSavior before you begin. There are different models, make sure you order the one you need. It depends on the size and type of the ROM chip on your board. Our S2881 board has a 4Mbit PLCC chip. This is the list of BiosSavior vendors:

http://www.ioss.com.tw/web/English/WheretoBuy.html

While coreboot replaces the functions of the proprietary bios, it does NOT replace the VGA bios. If you want VGA on your coreboot'd machine (not strictly necessary for servers), you will need to extract the VGA bios and concatenate it with the coreboot image, before burning it to your ROM. See below for details.

This wiki page is maintained by Ward Vandewege (ward at gnu dot org).

===Hardware===

The S2881 comes with a 4Mbit BIOS chip, which does not suffice to put a Linux kernel in ROM. However, it's sufficient to have a fully functional coreboot with FILO payload, as described below.

It turns out that you can also use an 8Mbit BIOS chip on the S2881. For instance, flashrom supports flashing the SST 49LF080A on the S2881 without problems. Having a 8Mbit chip allows putting a Linux kernel into the BIOS, as described in [http://www.linuxbios.org/Tyan_S2892_Build_Tutorial the S2892 the OLPC way] build tutorial.

===Payload===

coreboot requires a [[Payloads|Payload]] to boot an operating system.

If you want to boot from the network, you will need to use [http://www.etherboot.org Etherboot].

If you want to boot from an IDE drive, SATA drive, USB stick or CDROM, you can use [[FILO]].

===Building the payload===

In order to boot from a SATA disk, we use FILO.

Once you've downloaded FILO, you will need to put a file 'Config' in its root tree. An example can be found in the distribution, called 'defconfig'.

You can configure FILO to load Grub. Here's my Config, which does that:

# Use grub instead of autoboot?
USE_GRUB = 1
# Grub menu.lst path
MENULST_FILE = "hda1:/grub/menu.lst"
# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
IDE_DISK = 1
# Add a short delay when polling status registers
# (required on some broken SATA controllers)
IDE_DISK_POLL_DELAY = 1
# Driver for USB Storage
USB_DISK = 1
# VGA text console
VGA_CONSOLE = 1
PC_KEYBOARD = 1
# Enable the serial console
SERIAL_CONSOLE = 1
# Serial console; real external serial port
SERIAL_IOBASE = 0x3f8
SERIAL_SPEED = 115200
# Filesystems
FSYS_EXT2FS = 1
FSYS_ISO9660 = 1
# Support for boot disk image in bootable CD-ROM (El Torito)
ELTORITO = 1
# PCI support
SUPPORT_PCI = 1
# Enable this to scan PCI busses above bus 0
# AMD64 based boards do need this.
PCI_BRUTE_SCAN = 1
# Loader for standard Linux kernel image, a.k.a. /vmlinuz
LINUX_LOADER = 1

In order to get serial output from Grub, you will also need to add something like this to your menu.list:

# serial port 0
serial --unit=0 --speed=115200
terminal --timeout=15 serial console

Now execute 'make', which will generate a filo.elf file that will be your payload. You will need to refer to this file to build coreboot as explained below, because it gets included in the coreboot ROM image.

===Building coreboot ===

Download coreboot ([[Download coreboot]]). You need subversion revision 2251 or higher. Note that revisions 2288 through 2295 are known bad, do not use those.

If you want VGA support, a few changes are required in the coreboot source tree. Edit this file:

src/mainboard/tyan/s2881/Options.lb

You'll need to enable the following two lines:

#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1

Now - if you are going to be using a rom chip larger than 512K, you will need to also make a change in

src/mainboard/tyan/s2881/Config.lb

Assuming you are using a 1MB chip, modify the onboard vga device info from this

chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end

to this

chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000"
end

Whether you want VGA or not, build a tyan/s2881 tree.

cd targets
./buildtarget tyan/s2881

Modify tyan/s2881/Config.lb; change payload setting to point to your filo.elf file 

If you don't need VGA, you will need to modify tyan/s2881/Config.lb. Comment out the line:

option ROM_SIZE = 475136

If you do need VGA, modify the ROM_SIZE line to the following, because our VGA bios is only 36KB, not 48K:

option ROM_SIZE = 487424

Make you are using GCC 3.4 (not GCC 4.0), or your image will be too large, and then:

cd tyan/s2881/s2881
make

===VGA bios===

Skip this section if you don't need VGA support in your coreboot.

The s2881 VGA bios is 36K long. The last 4KB are not available in RAM after boot (with the proprietary BIOS), however, so we can NOT use this method to extract the VGA BIOS:

While booted with your proprietary BIOS, you can see where your vga bios starts
and how much space it takes by issuing
<code>cat /proc/iomem | grep "Video ROM"</code>
Then get a copy of your vga bios.
<code>dd if=/dev/mem of=vgabios.bin bs=1k count=32 skip=768</code>
Our vga bios is 32K. Verify that the image is correct - it should start with 55 AA,
and contain strings that indicate it's your VGA bios. You should be able to clearly
make out 'ATI RAGE' etc.

So this does not work - the last 4K is missing. Thankfully, Anton Borisov has some tools that can extract the VGA BIOS - and other option ROMs, in fact - from the BIOS images that Tyan offers on its website.

You can download the tool for AMI here:

http://www.kaos.ru/biosgfx/download/AmiDeco_0.31e.src.tar.gz

Then download the latest Bios for the s2881 from the TYAN website:

http://www.tyan.com/support_download_bios.aspx?model=S.S2881

Once you have the image, you can display its contents like this:

./amideco 2881v206.rom -l

That should show output like:

-=AmiBIOSDeco, version 0.31e (Linux)=-
FileLength : 80000 (524288 bytes)
FileName : 2881v206.rom
AMIBIOS information:
Version : 0800
Packed Data : 56C90 (355472 bytes)
Start : DF83C
Packed Offset : 5F83C
Offset : 80000
Released : 14 June 2005
DirName : 2881v206.---
+------------------------------------------------------------------------------+
| Class.Instance (Name) Packed ---> Expanded Compression Offset |
+------------------------------------------------------------------------------+
08 01 ( Interface) 00798 ( 01944) => 00798 ( 01944) 5F83Ch
04 02 ( Setup Client) 03F40 ( 16192) => 069A2 ( 27042) + 5B8E8h
0C 03 ( ROM-ID) 00008 ( 00008) => 00008 ( 00008) 5B8CCh
0E 04 ( OEM Logo) 00B4D ( 02893) => 4B436 (308278) + 5AD68h
1A 05 ( Small Logo) 00532 ( 01330) => 026A2 ( 09890) + 5A820h
18 06 (ADM (Display MGR)) 01741 ( 05953) => 04019 ( 16409) + 590C8h
19 07 ( ADM Font) 0059C ( 01436) => 01304 ( 04868) + 58B18h
1B 08 ( SLAB) 25016 (151574) => 4CAA8 (314024) + 33AECh
21 09 ( Multilanguage) 03B90 ( 15248) => 0844A ( 33866) + 2FF48h
20 10 ( PCI AddOn ROM) 05B84 ( 23428) => 09000 ( 36864) + 2A3B0h
20 11 ( PCI AddOn ROM) 06343 ( 25411) => 0C800 ( 51200) + 24058h
20 12 ( PCI AddOn ROM) 0D5EA ( 54762) => 0E000 ( 57344) + 16A58h
20 13 ( PCI AddOn ROM) 05678 ( 22136) => 09000 ( 36864) + 113CCh
11 14 ( P6 Microcode) 2062004 (33955844) => 00039 ( 00057) + 0EBA4h
2E 15 ( User ROM) 047B3 ( 18355) => 07800 ( 30720) + 0A3DCh
06 16 ( DMI Data) 003CD ( 00973) => 00A1A ( 02586) + 09FF8h
2F 17 ( User-Defined ;)) 00C1D ( 03101) => 02595 ( 09621) + 093C4h
80 18 ( User-Defined ;)) 00038 ( 00056) => 00038 ( 00056) 09378h
Total Sections : 18

Now extract all these parts:

./amideco 2881v206.rom -x

That will create a number of new files:

-rw-r--r-- 1 ward ward 27042 2006-07-07 16:29 amibody.04
-rw-r--r-- 1 ward ward 1944 2006-07-07 16:29 amibody.08
-rw-r--r-- 1 ward ward 8 2006-07-07 16:29 amibody.0c
-rw-r--r-- 1 ward ward 308278 2006-07-07 16:29 amibody.0e
-rw-r--r-- 1 ward ward 0 2006-07-07 16:29 amibody.11
-rw-r--r-- 1 ward ward 16409 2006-07-07 16:29 amibody.18
-rw-r--r-- 1 ward ward 4868 2006-07-07 16:29 amibody.19
-rw-r--r-- 1 ward ward 9890 2006-07-07 16:29 amibody.1a
-rw-r--r-- 1 ward ward 314024 2006-07-07 16:29 amibody.1b
-rw-r--r-- 1 ward ward 33866 2006-07-07 16:29 amibody.21
-rw-r--r-- 1 ward ward 36864 2006-07-07 16:29 amipci_00.20
-rw-r--r-- 1 ward ward 51200 2006-07-07 16:29 amipci_01.20
-rw-r--r-- 1 ward ward 57344 2006-07-07 16:29 amipci_02.20
-rw-r--r-- 1 ward ward 36864 2006-07-07 16:29 amipci_03.20

We know that our VGA BIOS is 36K long. Only 2 files fit the bill: amipci_00.20 and amipci_03.20. If you run 'strings' on both files, you'll see that the former is the VGA BIOS, and the latter is the Option ROM for the Broadcom network card.

So, now that we have the proper VGA bios image (36K long), we need to concatenate the VGA bios with the coreboot image

<code>cat amipci_00.20 coreboot.rom > final_coreboot.rom</code>

===Burning the bios===

Make sure your Biossavior is set to the 'RD1' position (not to 'ORG'!), so that you can always revert to the original bios.

On the target machine:

cd coreboot-v2/util/flashrom
./flashrom -v -w path/to/your/coreboot.rom

If you want VGA support, make sure you burn the final_coreboot.rom image!

===Booting coreboot===

You now need to 'halt' the machine. A soft reset won't work the first time you boot from the proprietary BIOS into coreboot.

Since we set up serial output in the coreboot configuration files above, you will want to hook up a serial console (or a copy of minicom or the like) to see what the box is doing while starting up. Keep your eyes on the screen after hitting the power button - coreboot will be up and running way before you expect it!

If you have problems, don't despair. Power down the box, switch the biossavior to 'ORG' and boot in the proprietary BIOS. Just don't forget to switch the biossavior back to the 'RD1' position before flashing the BIOS!

See what went wrong, and subscribe and post to the friendly and helpful [http://wiki.linuxbios.org/index.php/Mailinglist mailing list] if you can't figure it out by yourself.

===Hardware monitoring===

The s2881 has 2 HWM chips, each driving a number of fans and temperature sensors. As of SVN revision 2674, the main HWM chip that drives most of the fans (ADT7463) is configured to be in automatic (hardware) fan control mode, based on the temperature sensors connected to it. These are the specific HWM settings:

* fans under automatic hardware control
* fans blow by default at 25% speed
* if any of the sensors goes above 55C (Tmin), the fans start blowing harder to compensate
* if any of the sensors reach 70C (THERM limit), the fans start blowing at full speed

These settings should lead to longer fan life, reduced power consumption, and better protection against accidental fan speed misconfiguration from software. And the machine is a lot less loud under light load.

The original Tyan BIOS had these settings:

* fans under manual (software) control
* fans blow by default at 100% speed
* automatic mode Tmin set to 90C
* automatic mode THERM limit set to 100C

The coreboot settings should be more ideal for real world deployment, and are a lot safer.

{{GPL}}

[[Category:Tutorials]]

Gigabyte m57sli Vendor Cooperation Score

2008-10-06T16:48:45Z

Ward: /* Availability */

== Availability ==

[http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2539 Gigabyte M57SLI] has gone out of production as of September 2008. As of early October 2008, it's no longer available from [http://www.newegg.com/Product/Product.aspx?Item=N82E16813128014 one major distributor], but may still be available [http://www.google.com/products?q=m57sli&btnG=Search+Products&hl=en from other sources].

== Vendor Cooperation Score ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Points
! align="left" | Max
! align="left" | Rating

|- bgcolor="#eeeeee"
| '''[[#Documentation]]'''
| style="background:lime" | 49
| 80
| [[Image:four-hares.png]]

|- bgcolor="#eeeeee"
| '''[[#Hackability]]'''
| style="background:yellow" | 1
| 24
| [[Image:one-hare.png]]

|- bgcolor="#eeeeee"
| '''[[#Example and support code]]'''
| style="background:yellow" | 0
| 10
| [[Image:zero-hares.png]]

|- bgcolor="#eeeeee"
| '''Total'''
| style="background:lime" | 50
| 114
| [[Image:three-hares.png]]
|}

== Documentation ==

Score: 49/80

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Availability
! align="left" | Points

|- bgcolor="#6699ff"
| colspan="3" | '''CPU (AMD Athlon 64 X2/AMD Athlon 64 FX/AMD Athlon 64)'''

|- bgcolor="#eeeeee"
| '''Datasheet / register set'''
| Freely available [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/44109.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33425.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30431.pdf]
| style="background:lime" | 10

|- bgcolor="#dddddd"
| '''BIOS programming guide'''
| Freely available [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF]
| style="background:lime" | 10

|- bgcolor="#eeeeee"
| '''Errata'''
| Freely available [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41788.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf]
| style="background:lime" | 10

|- bgcolor="#6699ff"
| colspan="3" | '''Chipset (Nvidia nForce 570-SLI)'''

|- bgcolor="#eeeeee"
| '''Datasheet / register set'''
| NDA allowing GPL'd code
| style="background:yellow" | 3

|- bgcolor="#dddddd"
| '''BIOS programming guide'''
| NDA allowing GPL'd code
| style="background:yellow" | 3

|- bgcolor="#eeeeee"
| '''Errata'''
| NDA allowing GPL'd code
| style="background:yellow" | 3

|- bgcolor="#6699ff"
| colspan="3" | '''Super I/O (ITE IT8716)'''

|- bgcolor="#eeeeee"
| '''Datasheet / register set'''
| Freely available [http://www.ite.com.tw/product_info/file/pc/IT8716F_V0.3.zip]
| style="background:lime" | 10

|- bgcolor="#6699ff"
| colspan="3" | '''Mainboard'''

|- bgcolor="#eeeeee"
| '''Schematics'''
| Documentation is not available or the NDA does not allow release of code.
| style="background:yellow" | 0

|}

== Hackability ==

Score: 1/24. Soldering required to recover from a bad flash.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Status
! align="left" | Points

|- bgcolor="#eeeeee"
| '''Rom chip'''
| Soldered with space on the board for a secondary rom chip (pads unpopulated).
| style="background:yellow" | 1

|- bgcolor="#dddddd"
| '''LPC header'''
| No
| style="background:yellow" | 0

|- bgcolor="#eeeeee"
| '''JTAG header'''
| No
| style="background:yellow" | 0

|}

== Example and support code ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Status
! align="left" | Points

|- bgcolor="#eeeeee"
| '''Example and support code'''
| Code is not available or the NDA does now allow release of code.
| style="background:yellow" | 0
|}

== Background on our rating system ==

See the [http://www.coreboot.org/Rating_System Rating System] page for more information.

Gigabyte m57sli Vendor Cooperation Score

2008-10-06T16:42:04Z

Ward: /* Availability */

== Availability ==

[http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2539 Gigabyte M57SLI] has gone out of production as of September 2008. As of early October 2008, it's no longer available from [http://www.newegg.com/Product/Product.aspx?Item=N82E16813128014 one major distributor], but may still be available from others.

== Vendor Cooperation Score ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Points
! align="left" | Max
! align="left" | Rating

|- bgcolor="#eeeeee"
| '''[[#Documentation]]'''
| style="background:lime" | 49
| 80
| [[Image:four-hares.png]]

|- bgcolor="#eeeeee"
| '''[[#Hackability]]'''
| style="background:yellow" | 1
| 24
| [[Image:one-hare.png]]

|- bgcolor="#eeeeee"
| '''[[#Example and support code]]'''
| style="background:yellow" | 0
| 10
| [[Image:zero-hares.png]]

|- bgcolor="#eeeeee"
| '''Total'''
| style="background:lime" | 50
| 114
| [[Image:three-hares.png]]
|}

== Documentation ==

Score: 49/80

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Availability
! align="left" | Points

|- bgcolor="#6699ff"
| colspan="3" | '''CPU (AMD Athlon 64 X2/AMD Athlon 64 FX/AMD Athlon 64)'''

|- bgcolor="#eeeeee"
| '''Datasheet / register set'''
| Freely available [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/44109.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33425.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30431.pdf]
| style="background:lime" | 10

|- bgcolor="#dddddd"
| '''BIOS programming guide'''
| Freely available [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF]
| style="background:lime" | 10

|- bgcolor="#eeeeee"
| '''Errata'''
| Freely available [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41788.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf] [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf]
| style="background:lime" | 10

|- bgcolor="#6699ff"
| colspan="3" | '''Chipset (Nvidia nForce 570-SLI)'''

|- bgcolor="#eeeeee"
| '''Datasheet / register set'''
| NDA allowing GPL'd code
| style="background:yellow" | 3

|- bgcolor="#dddddd"
| '''BIOS programming guide'''
| NDA allowing GPL'd code
| style="background:yellow" | 3

|- bgcolor="#eeeeee"
| '''Errata'''
| NDA allowing GPL'd code
| style="background:yellow" | 3

|- bgcolor="#6699ff"
| colspan="3" | '''Super I/O (ITE IT8716)'''

|- bgcolor="#eeeeee"
| '''Datasheet / register set'''
| Freely available [http://www.ite.com.tw/product_info/file/pc/IT8716F_V0.3.zip]
| style="background:lime" | 10

|- bgcolor="#6699ff"
| colspan="3" | '''Mainboard'''

|- bgcolor="#eeeeee"
| '''Schematics'''
| Documentation is not available or the NDA does not allow release of code.
| style="background:yellow" | 0

|}

== Hackability ==

Score: 1/24. Soldering required to recover from a bad flash.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Status
! align="left" | Points

|- bgcolor="#eeeeee"
| '''Rom chip'''
| Soldered with space on the board for a secondary rom chip (pads unpopulated).
| style="background:yellow" | 1

|- bgcolor="#dddddd"
| '''LPC header'''
| No
| style="background:yellow" | 0

|- bgcolor="#eeeeee"
| '''JTAG header'''
| No
| style="background:yellow" | 0

|}

== Example and support code ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Item
! align="left" | Status
! align="left" | Points

|- bgcolor="#eeeeee"
| '''Example and support code'''
| Code is not available or the NDA does now allow release of code.
| style="background:yellow" | 0
|}

== Background on our rating system ==

See the [http://www.coreboot.org/Rating_System Rating System] page for more information.

Products

2008-09-25T18:00:58Z

Ward: /* Silicon Mechanics */

Here's a list of vendors and their products running coreboot/LinuxBIOS. Please [[Mailinglist|contact us]] if you wish to add your product to the following list.

== Artec Group ==

[http://www.artecgroup.com Artec Group] runs coreboot on their Geode LX based [http://www.thincan.com DBE61 ThinCan] system.

== Cluster Labs ==
[http://www.cluster-labs.com/ Cluster Labs] sells a 1.1 GHz PIII cluster node with 1 GB memory, fast ethernet, and boots coreboot.

== coresystems GmbH ==
[http://www.coresystems.de/ coresystems GmbH] is offering coreboot based services and products. If you are a hardware/appliance vendor and want your system running coreboot, contact coresystems. As a coreboot contributor, coresystems is hosting the coreboot development repository, mailing list and web page.

== Cray ==
The Cray [http://www.cray.com/products/xd1/ Xd1] is an Opteron-based system which runs coreboot.

== CW Linux ==
[http://www.cwlinux.com CW Linux] offers pre-installed coreboot motherboards, SDK and related hardware for people want to use or develop applications on coreboot. It also provides professional services for custom coreboot-based system development.

== i-TECH Corp. ==
[http://www.i-tech.com/ i-TECH] is selling test and analysis tools with coreboot, including all its "Satellite" Fibre Channel analyzers (IFC-3016, IFC-4016, IFC-30, IFC40) and "PassPort"-based test and analysis tools.

== Linutop ==
[http://linutop.com/ Linutop] is going to ship coreboot on their diskless computers.

== Linux Labs ==
[http://www.linuxlabs.com Linux Labs] is selling [http://www.linuxlabs.com/starterclusters.html LinuxBIOS Beowulf clusters] comprised of 1U x86-based nodes with LinuxBIOS installed.

== Linux NetworX ==
[http://www.linuxnetworx.com Linux NetworX], a major contributor to the coreboot project, used to sell a variety of cluster solutions with coreboot installed. LNXI was recently bought by Cray.

== LUCIDA ==
[http://www.lucidatech.com LUCIDA] is shipping several of their thin clients, e.g. the [http://www.lucidatech.com/product/lt2610.htm LT2610] and the [http://www.lucidatech.com/product/lt3712.htm LT3712] with coreboot, according to their website.

== MikroTik ==
[http://www.routerboard.com MikroTik] is offering the [http://216.239.59.104/search?q=cache:pT2IZCrEZEsJ:www.routerboard.com/pdf/RouterBOARD200SeriesA4-3-0.pdf+routerboard+linuxbios&hl=de&ct=clnk&cd=1&gl=de Routerboard 200 series] which seems to be shipped with coreboot (devices from other Routerboard series might use coreboot, too).

== O.N.E. Technologies ==
[http://www.onelabs.com/ O.N.E. Technologies] offers coreboot on all their x86 products and offers coreboot development services.

== Silicon Mechanics ==
[http://siliconmechanics.com Silicon Mechanics] will ship their [http://www.siliconmechanics.com/i7045/opteron-server.php Rackform nServ A236] with coreboot preinstalled if requested. See [http://coreboot.org/News#2008.2F04.2F04_Silicon_Mechanics_to_ship_servers_with_coreboot_preinstalled our news item from 2008/04/04]. The [http://www.siliconmechanics.com/i9226/quad-core-opteron.php Rackform nServ A255] uses the same motherboard, and is also available with coreboot.

== VIA ==
[http://www.via.com.tw VIA] is helping the coreboot community support many new Epia's, mainboards and chipsets with several code donations and open programming guides. With key input from VIA, coreboot will soon support over 30 Mini-ITX mainboards. These mainboards are made by VIA, Jetway, Phitronics and MSI featuring the VIA C7 cpu, CN700 and VT8237 chipset. 
[http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 EPIA-CN10000EG/CN130000G] 
[http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=473 EPIA-LN10000EG/AEG] 
[http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp pc2500] [http://www.via.com.tw/en/resources/pressroom/pressrelease.jsp?press_release_no=1729 Phitronics / VIA pc2500] 
[http://linux.via.com.tw/support/downloadFiles.action Linux VIA Portal] aims to expand cooperation with open source communities by providing drivers, chipset programming manuals and source code for select Linux distributions to technical software developers.

__NOTOC__

FILO

2008-09-11T17:16:34Z

Ward: /* Download FILO */

[[Image:Qemu filo.png|thumb|right|FILO trying to load menu.lst.]]
[[Image:Qemu filo prompt.png|thumb|right|FILO prompt.]]

'''FILO''' is a bootloader which loads boot images from a local filesystem,
without help from legacy BIOS services.

Expected usage is to flash it into the BIOS ROM together with coreboot.

== Download FILO ==

Download the latest version of FILO from Subversion with

$ svn co svn://coreboot.org/filo/trunk/filo

Or download the filo 0.5 release at

$ svn co svn://coreboot.org/filo/branches/filo-0.5

You can also browse the source code online at
http://tracker.coreboot.org/trac/filo/browser/trunk

== Features ==

* Supported boot devices: IDE hard disk, SATA hard disk, CD-ROM, and system memory (ROM)
* Supported filesystems: ext2, fat, jfs, minix, reiserfs, xfs, and iso9660
* Supported image formats: ELF and [b]zImage (a.k.a. /vmlinuz)
* Supports boot disk image of El Torito bootable CD-ROM. "hdc1" means the boot disk image of the CD-ROM at hdc.
* Supports loading image from raw device with user-specified offset
* Console on VGA + keyboard, serial port, or both
* Line editing with ^H, ^W and ^U keys to type arbitrary filename to boot
* Full support for the ELF Boot Proposal (where is it btw, Eric)
* Auxiliary tool to compute checksum of ELF boot images
* Full 32-bit code, no BIOS calls
* uses [[libpayload]]

== Requirements ==

Only the x86 (x64) architecture is currently supported. Some efforts have
been made to get FILO running on PPC. Contact the [[Mailinglist|coreboot mailinglist]]
for more information.

x64/AMD 64 machines work fine when compiling FILO in 32-bit mode.
(coreboot uses 32-bit mode and Linux kernel does the transition to 64-bit mode)

Recent version of GNU toolchain is required to build.

We have tested with Debian/woody (gcc 2.95.4, binutils 2.12.90.0.1,
make 3.79.1), Debian/sid (gcc 3.3.2, binutils 2.14.90.0.6,
make 3.80) and different versions of SUSE Linux from 9.0 to 10.3.

On AMD64 for Debian install the gcc-multilib package.

== Preparation ==

You need to compile libpayload (included via svn:externals in FILO)

$ cd libpayload
$ make defconfig
$ make

== Configuration ==

Configure FILO using the Kconfig interface:

$ make menuconfig

== Installation ==
Then running make again will build filo.elf, the ELF boot image of FILO.
$ make

Use build/filo.elf as your payload of coreboot, or a boot image for
[[Etherboot]].

== Credits ==

* This software was originally developed by SONE Takeshi <ts1@tsn.or.jp>
* It has been significantly enhanced and is now maintained by [mailto:stepan@coresystems.de Stefan Reinauer].
* It uses libpayload from Uwe Hermann and Jordan Crouse

== Troubleshooting ==

If you experience trouble compiling or using FILO, please report with a build log or detailed error description to the [[Mailinglist|coreboot mailing list]].

== Notes ==

=== CD-ROM Booting ===

To boot a CD-ROM or DVD you only need to specify the drive '''without a partition number'''. For example to boot to the primary drive on the secondary IDE channel you would use '''hdc''' and not '''hdc1''' in FILO.

=== Grub-like Interface ===
If you are using FILO with '''CONFIG_USE_GRUB''', and want to boot to your Linux install disk you have to do a mixture of GRUB and FILO commands.

Like GRUB you have to append a kernel (and parameters), then an initrd, and give a boot command.
Like FILO you have to give absolute paths.

Example to boot to a GeeXboX install CD-ROM:
filo> kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom installator
Press <ENTER>
filo> initrd hdc:/GEEXBOX/boot/initrd.gz
Press <ENTER>
filo> boot
Press <ENTER>

Your system will now boot right into the Linux install.

=== NVRAM Parsing ===

FILO parses the following NVRAM variables:

* 'boot_default' is parsed by the command '''nvram-default''' to obtain the default boot entry for the boot menu. It can be used as an alternative to the '''default''' command which reads the default entry as a parameter.

Press

2008-09-02T03:09:05Z

Ward:

== 2008 ==

* August 28, 2008: [http://www.linux.com/feature/145946 Linux.com: Behind the doors of the Free Software Foundation]
* February 26, 2008: [http://www.oszine.de/node/8546 OSZine: LinuxBIOS heißt jetzt Coreboot] (German) ([http://translate.google.com/translate?u=http%3A%2F%2Fwww.oszine.de%2Fnode%2F8546&langpair=de%7Cen&hl=en&ie=UTF-8 EN])
* February 25, 2008: [http://www.golem.de/0802/57919.html Golem: Aus LinuxBIOS wird Coreboot] (German)
* February 25, 2008: [http://www.pro-linux.de/news/2008/12373.html Pro-Linux: LinuxBIOS wird zu Coreboot] (German)
* February 07, 2008: [http://softlibre.barrapunto.com/article.pl?sid=08/02/07/1357250 Barrapunto: LinuxBIOS cambia de nombre a coreboot] (Spanish) ([http://translate.google.com/translate?u=http%3A%2F%2Fsoftlibre.barrapunto.com%2Farticle.pl%3Fsid%3D08%2F02%2F07%2F1357250&langpair=es%7Cen&hl=en&ie=UTF-8 EN])
* January 24, 2008: [http://www.heise.de/newsticker/meldung/102381 OSMB: Open Source Business Award in Nürnberg überreicht] (German)

== 2007 ==

* October 23, 2007: [http://digg.com/linux_unix/LinuxBIOS_Brings_Clones_One_Step_Closer_to_Freedom Digg: LinuxBIOS Brings Clones One Step Closer to Freedom]
* October 23, 2007: [http://www.enterprisenetworkingplanet.com/nethub/article.php/3706881 Enterprise Networking Planet: LinuxBIOS Brings Clones One Step Closer to Freedom]
* October 10, 2007: [http://linux.slashdot.org/article.pl?sid=07/10/10/1555202 Slashdot: Get Speed-Booting with an Open BIOS]
* October 08, 2007: [http://www.lockergnome.com/nexus/knitter/2007/10/08/boot-linux-faster-with-an-open-bios Techblog: Boot Linux Faster With An Open BIOS]
* March 09, 2007: [http://hardware.slashdot.org/article.pl?sid=07/03/09/146215 Slashdot: LinuxBIOS Gets GUI]
* March 09, 2007: [http://www.golem.de/0703/50979.html Golem: LinuxBIOS mit X-Server] (German) ([http://translate.google.com/translate?u=http%3A%2F%2Fwww.golem.de%2F0703%2F50979.html&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN])
* March 08, 2007: [http://www.genbeta.com/2007/03/08-linuxbios-arranca-tu-ordenador-en-6-segundos Genbeta: LinuxBIOS, arranca tu ordenador en 6 segundos] (Spanish) [[http://66.249.93.104/translate_c?hl=en&ie=UTF-8&oe=UTF-8&langpair=es%7Cen&u=http://www.genbeta.com/2007/03/08-linuxbios-arranca-tu-ordenador-en-6-segundos&prev=/language_tools EN]]
* March 08, 2007: [http://meneame.net/story/linuxbios-servidor-x11-flash-rom-permite-iniciar-pc-6-segundos menéame: LinuxBIOS con un servidor X11 en una Flash ROM permite iniciar una PC en 6 segundos] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fmeneame.net%2Fstory%2Flinuxbios-servidor-x11-flash-rom-permite-iniciar-pc-6-segundos&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* March 08, 2007: [http://digg.com/linux_unix/LinuxBIOS_with_X11_server_completely_in_Flash_ROM Digg.com: LinuxBIOS with X11 server, completely in Flash ROM]
* March 02, 2007: [http://www.heise.de/newsticker/meldung/86142/ Heise: Steiniger Weg zum LinuxBIOS] (German) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2F86142%2F&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 25, 2007: [http://digg.com/linux_unix/World_s_First_Motherboard_Using_LinuxBIOS_Released Digg.com: World's First Motherboard Using LinuxBIOS Released]
* February 25, 2007: [http://www.vivalinux.com.ar/hard/gigabyte-open-motherboard.html Viva Linux: Primer motherboard soportado por LinuxBIOS] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.vivalinux.com.ar%2Fhard%2Fgigabyte-open-motherboard.html&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 25, 2007: [http://www.neowin.net/index.php?act=view&id=38368 Neowin.net: World’s First Mainboard with Open-Source BIOS]
* February 24, 2007: [http://www.ixbt.com/news/hard/index.shtml?07/84/10 iXBT: Gigabyte M57SLI-S4: ?????? ?????????? ????????? ????? ? ?????????? LinuxBIOS] (?)
* February 23, 2007: [http://www.pcinpact.com/actu/news/34884-linuxbios-bios-open-source-gigabyte.htm PC INpact: LinuxBIOS: premier BIOS open source pour le grand public] (French) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.pcinpact.com%2Factu%2Fnews%2F34884-linuxbios-bios-open-source-gigabyte.htm&langpair=fr%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 22, 2007: [http://www.heise.de/newsticker/meldung/85705 Heise: LinuxBIOS für Mainstream-Mainboard mit Sockel-AM2] (German) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2F85705&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 22, 2007: [http://www.golem.de/0702/50694.html Golem: LinuxBIOS unterstützt Gigabyte-Mainboard] (German) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.golem.de%2F0702%2F50694.html&langpair=de%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 22, 2007: [http://br-linux.org/linux/gigabyte-vai-oferecer-uma-placa-mae-com-linuxbios BR-Linux.org: Gigabyte vai oferecer uma placa mãe com LinuxBios] (?)
* February 23, 2007: [http://www.xbitlabs.com/news/mainboards/display/20070223145912.html X-bit labs: Linux Supporters Celebrate World’s First Mainboard with Open-Source BIOS]
* February 22, 2007: [http://permalink.gmane.org/gmane.linux.kernel/496453 LKML: First desktop motherboard supported by LinuxBIOS: GIGABYTE M57SLI-S4]
* February 19, 2007: [http://www.dellideastorm.com/article/show/62549/LinuxBIOS_instead_of_proprietary_BIOS Dell Idea Storm: LinuxBIOS] ([http://www.dellideastorm.com/article/show/63081/Use_LinuxBIOS_on_Dell_PCs__Workstations Alternative page])
* February 10, 2007: [http://www.linux.org.ru/view-message.jsp?msgid=1781619 Linux.org.ru Forum: Interview with Ronald G. Minnich] (Russian) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.linux.org.ru%2Fview-message.jsp%3Fmsgid%3D1781619&langpair=ru%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 09, 2007: [http://news.linux.com/article.pl?sid=07/02/09/2134214&tid=96 Linux.com: LinuxBIOS creator talks about OLPC and EFI]
* February 09, 2007: [http://kriptopolis.org/el-creador-de-linuxbios-desconfia-de-efi Kriptopolis: El creador de LinuxBIOS desconfía de EFI] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fkriptopolis.org%2Fel-creador-de-linuxbios-desconfia-de-efi&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* February 08, 2007: [http://www.osnews.com/story.php?news_id=17213 OSNews: LinuxBIOS Creator: EFI is a Security Threat]
* February 06, 2007: [http://fosdem.org/2007/interview/ronald+g+minnich FOSDEM Interview: Ronald G Minnich]
* January 29, 2007: [http://meneame.net/story/primera-placa-base-sobremesa-soportada-linuxbios menéame: Primera placa base de sobremesa soportada por LinuxBIOS] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fmeneame.net%2Fstory%2Fprimera-placa-base-sobremesa-soportada-linuxbios%23comment-10&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]

== 2006 ==

* December 25, 2006: [http://www.madpenguin.org/cms/?m=show&id=7694 Mad Penguin: LinuxBIOS: The Forgotten Hero]
* December 18, 2006: [http://meneame.net/story/linuxbios-casi-listo menéame: LinuxBIOS, casi listo] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fmeneame.net%2Fstory%2Flinuxbios-casi-listo&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* December 18, 2006: [http://www.vivalinux.com.ar/hard/linuxbios-casi-listo.html VivaLinux: LinuxBIOS listo para entregar su primer fruto] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.vivalinux.com.ar%2Fhard%2Flinuxbios-casi-listo.html&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* December 16, 2006: [http://www.diariored.com/blog/001571.php Diarored: El proyecto LinuxBIOS listo para entregar su primer fruto] (Spanish) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.diariored.com%2Fblog%2F001571.php&langpair=es%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* December 14, 2006: [http://www.symlink.ch/articles/06/12/14/1319250.shtml Symlink: Status des LinuxBIOS] (German)
* December 08, 2006: [http://www.freerepublic.com/focus/f-chat/1750705/posts Free Republic: LinuxBIOS ready to go mainstream]
* December 08, 2006: [http://www.tecchannel.de/news/themen/entwicklung/457312/index.html tecCHANNEL: LinuxBIOS scheint fertig zu sein] (German)
* December 07, 2006: [http://osnews.com/comment.php?news_id=16663&limit=no&threshold=-1 OSNews: LinuxBIOS Ready to Go Mainstream]
* December 07, 2006: [http://pcburn.com/article.php?sid=1967 PCBurn: LinuxBIOS: Coming Along Nicely]
* December 07, 2006: [http://technocrat.net/d/2006/12/7/11935 Technocrat.net: LinuxBIOS - getting closer]
* December 07, 2006: [http://www.linux.com/article.pl?sid=06/11/30/199208 Linux.com: LinuxBIOS ready to go mainstream]
* November 19, 2006: [http://www.linux.org.ru/view-message.jsp?msgid=1661374 Linux.org.ru Forum: Google Linux BIOS] (Russian) [[http://translate.google.com/translate?u=http%3A%2F%2Fwww.linux.org.ru%2Fview-message.jsp%3Fmsgid%3D1661374&langpair=ru%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* November 17, 2006: [http://linuxhelp.blogspot.com/2006/11/linuxbios-truly-gpled-free-software.html LinuxBIOS - A truly GPLed Free Software BIOS]
* November 15, 2006: [http://hardware.slashdot.org/hardware/06/11/15/1423223.shtml Slashdot: Google Sponsors the LinuxBIOS project]
* November 14, 2006: [http://google-code-updates.blogspot.com/2006/11/google-sponsors-linuxbios-project.html Google Code Updates: Google Sponsors the LinuxBIOS project]
* November 14, 2006: [http://www.heise.de/newsticker/meldung/81005 Heise: Google unterstützt LinuxBIOS-Projekt] (German)
* November 14, 2006: [http://www.golem.de/0611/48929.html Golem: Google unterstützt freies BIOS] (German)
* September 21, 2006: [http://www.pro-linux.de/news/2006/10247.html Pro-Linux: LinuxBIOS-Symposium dieses Jahr in Hamburg] (German)
* September 5, 2006: [http://www.linuxdevices.com/news/NS2401026948.html LinuxDevices.com: Boot Linux faster with an open BIOS]
* August 31, 2006: [http://www-128.ibm.com/developerworks/linux/library/l-bios.html?ca=dgr-lnxw09OpenBIOS IBM developerWorks: Open BIOSes for Linux]
* August 14, 2006: [http://lwn.net/Articles/195341/ LWN: LinuxBIOS Symposium in Europe this year!] (LWN)
* February xx, 2006: [http://www.linuxbios.org/images/c/c0/LX2%40FSF_4a.pdf SAMAG: FSF is moving towards LinuxBIOS deployment] (Russian article by Anton Borisov)

== 2005 ==

* September 28, 2005: [http://www.linuxjournal.com/article/8177 The Ultimate Linux Lunchbox]
* July 19, 2005: [http://www.linuxjournal.com/article/8310 Porting LinuxBIOS to the AMD SC520: A Follow-up Report]
* June 30, 2005: [http://www.linuxjournal.com/article/8120 Porting LinuxBIOS to the AMD SC520]
* February 28, 2005: [http://www.pro-linux.de/news/2005/7867.html FSF startet Kampagne für ein freies BIOS] (German)
* February 28, 2005: [http://linux.slashdot.org/article.pl?sid=05/02/28/1126226 Stallman Calls For Action on Free BIOS]
* February 28, 2005: [http://news.com.com/2100-7344_3-5593241.html Foundation wants more of the PC to be free]
* February 26, 2005: [http://www.fsf.org/news/freebios.html Stallman calls for action on Free BIOS]

== 2004 ==

* October 26, 2004: [http://www.linuxjournal.com/article/7857 Reducing OS Boot Times for In-Car Computer Applications, Part III] (has some LinuxBIOS-related content)
* April 29, 2004: [http://izcity.com/data/system/article399.htm Izcity.com: LinuxBIOS: a computer with Linux in the heart] (Russian) [[http://translate.google.com/translate?u=http%3A%2F%2Fizcity.com%2Fdata%2Fsystem%2Farticle399.htm&langpair=ru%7Cen&hl=en&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools EN]]
* March 24, 2004: [http://developers.slashdot.org/article.pl?sid=04/03/24/2327229 In-Depth Look At LinuxBIOS]
* February 1, 2004: [http://www.linuxjournal.com/article/7170 LinuxBIOS at Four]

== 2003 ==

* December 10, 2003: [http://developers.slashdot.org/article.pl?sid=03/12/10/1434210 LinuxBIOS Project Usenix Paper]
* December 8, 2003: [http://www.theinquirer.net/default.aspx?article=13087 Stackable Open Source BIOS could cut proprietary stuff dead]
* July, 2003: [http://www.heise.de/ix/artikel/2003/07/048/ Linux-BIOS: Von der Idee zur Technik] (German)
* June, 2003: [http://www.linux-magazin.de/Artikel/ausgabe/2003/06/093_linuxbios/linuxbios.html Linux Magazin: Linux auf dem Motherboard] (German)

== 2002 ==

* November 26, 2002: [http://www.heise.de/newsticker/meldung/32643 LinuxBIOS bootet (Windows-)PCs] (German)
* November 25, 2002: [http://developers.slashdot.org/article.pl?sid=02/11/25/0331220 LinuxBIOS Boots Linux, OpenBSD, Windows]
* November 24, 2002: [http://zgp.org/linux-elitists/Pine.LNX.4.33.0211242330350.11414-100000@hydrogen.leitl.org.html ANNOUNCE: LinuxBIOS booting Windows 2000 (free software BIOS)]
* October 8, 2002: [http://science.slashdot.org/article.pl?sid=02/10/08/0324241 LinuxBIOS/BProc-based Supercomputer for LANL] from [http://slashdot.org/ Slashdot]
* September 30, 2002: [http://www.gridtoday.com/02/0930/100480.html Linux NetworX Announces LinuxBIOS Availability]
* September 23, 2002: [http://www.lanl.gov/worldview/news/releases/archive/02-106.shtml Linux Networx to build Linux supercomputer for Los Alamos] from LANL news
* September 23, 2002: [http://www.lnxi.com/news/lanl_info.php Los Alamos National Laboratory Selects Linux NetworX to Build 10 teraFLOP Linux Supercomputer] from Linux Networx

== 2001 ==

* December 15, 2001: [http://slashdot.org/article.pl?sid=01/12/15/050212 LinuxBIOS Gains Steam] from [http://slashdot.org/ Slashdot]
* December 1, 2001: [http://www.linuxjournal.com/article.php?sid=4888 Kernel Korner: About LinuxBIOS] by Eric Biederman in [http://www.linuxjournal.com/ Linux Journal]
* October 18, 2001: [http://lwn.net/2001/1018/devel.php3 Developer section] from [http://lwn.net/ LWN.net]
* October 15, 2001: [http://www.abqjournal.com/paperboy/ia/biz/478127biz10-15-01.htm LANL Builds Clever Software Tool and Gives It Away], by [http://www.inkstain.net/fleck/ John Fleck] in the [http://www.abqjournal.com/ Albuquerque Journal]
* August 3, 2001: David Hendricks at LANL's CCS division 2001 [http://www.lanl.gov/orgs/pa/News/080201.html#anchor5 student poster session]
* March 3, 2001: [http://slashdot.org/article.pl?sid=01/03/03/2313255 Booting Linux in Three Seconds] from [http://slashdot.org/ Slashdot]

== 2000 ==

* October 17, 2000: LANL's News Bulletin [http://www.lanl.gov/orgs/pa/News/101700.html#anchor5 article]
* October 12, 2000: SiS [http://alllinuxdevices.com/news_story.php3?ltsn=2000-10-12-006-03-PL-PR PR: SiS Accomplishes the First-Ever x86 Platform for LinuxBIOS] ([http://alllinuxdevices.com allLinux devices])
* June 15, 2000: [http://www.linuxdevices.com/links/LK8294110575.html The Linux BIOS Project]
* June 14, 2000: [http://linux.slashdot.org/article.pl?sid=00/06/14/2110209 Linux BIOS] from [http://slashdot.org/ Slashdot]

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