coreboot - User contributions [en]

Where to start

2013-05-08T05:02:49Z

XVilka: bolding text

Unfortunately we don't have much documentation to provide a nice learning curve. You can get help on [[IRC]] or the [[Mailinglist]], and if you're so inclined, we'd '''really really''' love contributions in the area of How Tos and documentation.

That said, we have a couple of lists of possible tasks:

* [[Project_Ideas]] contains projects that should be useful for [[GSoC]]-type timeframes, ie. 3 months or so. It also contains lists of project members that are interested in each project, so they volunteer to mentor newcomers (probably outside GSoC, too)
* [[Infrastructure_Projects]] are mostly cleanup projects. That sounds boring, but some of them might be a good entry point to various subsystems of coreboot, since you're exposed to a whole lot of code, while working on a relatively constrained task.
* Finally, we keep some TODOs on [https://trello.com/board/todos/4fc49d2461ea68c009decc4b Trello]. While this is mostly a personal collective notepad of a couple of developers, feel free to claim items there.

For all of them: We're a generally friendly community (though you might encounter a grumpy developer sometimes - we're just human, too), and like to help people who want to get started.

Bios extract

2013-04-10T08:58:52Z

XVilka: Undo revision 11747 by Idwer (talk)

'''bios_extract''' is a GPL tool for extracting individual modules from proprietary BIOS/UEFI images.

This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.
It is very useful for extracting PCI Expansion ROMs from onboard devices, like IGP graphics, raid controllers, nic boot roms, etc, for inclusion in a coreboot image.

== Installation ==

'''Manual installation'''

$ git clone http://review.coreboot.org/p/bios_extract
$ cd bios_extract
$ make
$ sudo make install

You can view sources via gitweb - http://review.coreboot.org/gitweb?p=bios_extract.git

== Development guidelines ==

We use the same [[Development Guidelines#Coding_style|coding style as coreboot]] (which is basically the Linux kernel coding style).

Coreboot Options

2013-01-12T13:44:21Z

XVilka: Updated

This is an automatically generated list of '''coreboot compile-time options''' (using coreboot/util/optionlist utility).

Last update: 2013/01/12 17:40:48. (runknown)
{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Option
! align="left" | Source
! align="left" | Format
! align="left" | Short Description
! align="left" | Description
|- bgcolor="#6699dd"
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
| EXPERT || toplevel || bool || Expert mode ||
This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are
doing! You have been warned!

||
|- bgcolor="#eeeeee"
| LOCALVERSION || toplevel || string || Local version string ||
Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler to use ||
This option allows you to select the compiler used for building
coreboot.

||
|- bgcolor="#eeeeee"
| COMPILER_GCC || toplevel || bool || GCC ||
Use the GNU Compiler Collection (GCC) to build coreboot.

For details see http://gcc.gnu.org.

||
|- bgcolor="#eeeeee"
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang ||
Use LLVM/clang to build coreboot.

For details see http://clang.llvm.org.

||
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static code analysis ||
Changes the build process to use scan-build (a utility for
running the clang static code analyzer from the command line).

Requires the scan-build utility in your system $PATH.

For details see http://clang-analyzer.llvm.org/scan-build.html.

||
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory for the scan-build report(s) ||
Directory where the scan-build reports should be stored in. The
reports are stored in subdirectories of the form 'yyyy-mm-dd-*'
in the specified directory.

If this setting is left empty, the coreboot top-level directory
will be used to store the report subdirectories.

||
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||
Enables the use of ccache for faster builds.

Requires the ccache utility in your system $PATH.

For details see https://ccache.samba.org.

||
|- bgcolor="#eeeeee"
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||
Enable this option if you are working on the sconfig device tree
parser and made changes to sconfig.l and sconfig.y.

Otherwise, say N.

||
|- bgcolor="#eeeeee"
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard-coded values.

||
|- bgcolor="#eeeeee"
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow link (i.e. SPI).

||
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||
Include the .config file that was used to compile coreboot
in the (CBFS) ROM image. This is useful if you want to know which
options were used to build a specific coreboot.rom image.

Saying Y here will increase the image size by 2-3kB.

You can use the following command to easily list the options:

grep -a CONFIG_ coreboot.rom

Alternatively, you can also use cbfstool to print the image
contents (including the raw 'config' item we're looking for).

Example:

$ cbfstool coreboot.rom print
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
offset 0x0
Alignment: 64 bytes

Name Offset Type Size
cmos_layout.bin 0x0 cmos layout 1159
fallback/romstage 0x4c0 stage 339756
fallback/coreboot_ram 0x53440 stage 186664
fallback/payload 0x80dc0 payload 51526
config 0x8d740 raw 3324
(empty) 0x8e480 null 3610440

||
|- bgcolor="#eeeeee"
| EARLY_CBMEM_INIT || toplevel || bool || Initialize CBMEM while in ROM stage ||
Make coreboot initialize the cbmem structures while running in ROM
stage. This could be useful when the ROM stage wants to communicate
some, for instance, execution timestamps.

||
|- bgcolor="#eeeeee"
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
Make coreboot create a table of timer-ID/timer-value pairs to
allow measuring time spent at different phases of the boot process.

||
|- bgcolor="#eeeeee"
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
This draws in the blobs repository, which contains binary files that
might be required for some chipsets or boards.
This flag ensures that a "Free" option remains available for users.

||
|- bgcolor="#eeeeee"
| REQUIRES_BLOB || toplevel || bool || ||
This option can be configured by boards that require the blobs
repository for the default configuration. It will make the build
fail if USE_BLOBS is disabled. Users that still desire to do a
coreboot build for such a board can override this manually, but
this option serves as warning that it might fail.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Mainboard || || || ||
|- bgcolor="#eeeeee"
| SPL_TEXT_BASE || mainboard/google/snow || hex || ||
Location of SPL. Default location is within iRAM region.

||
|- bgcolor="#eeeeee"
| SPL_MAX_SIZE || mainboard/google/snow || hex || ||
Max size of SPL. Let's say 32KB for now...

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_UART0 || mainboard/google/snow || bool || UART0 ||
Serial console on UART0

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_UART1 || mainboard/google/snow || bool || UART1 ||
Serial console on UART1

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_UART2 || mainboard/google/snow || bool || UART2 ||
Serial console on UART2

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_UART3 || mainboard/google/snow || bool || UART3 ||
Serial console on UART3

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_UART_ADDRESS || mainboard/google/snow || hex || ||
Map the UART names to the respective MMIO address.

||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||
The following X60 series ThinkPad machines have been verified to
work correctly:

ThinkPad X60s (Model 1702, 1703)
ThinkPad X60 (Model 1709)

||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||
The following T60 series ThinkPad machines have been verified to
work correctly:

Thinkpad T60p (Model 2007)

||
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
Look on the bottom side for a number like 406-0001-30. The last 2
digits state the PCB revision (3.0 in this example). For 2.0 or older
boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to
power on automatically. You may enable the button only after this
jumper has been removed. New revision boards are not restricted
in this way, and always have the power button enabled.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
If selected, the on-board SSD will act as IDE Slave instead of Master.

||
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8scm || hex || ||
though UARTs are on the NUVOTON BMC, port 0x164E
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

||
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8qgi || hex || ||
though UARTs are on the NUVOTON BMC, port 0x164E
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

||
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/tyan/s8226 || hex || ||
though UARTs are on the NUVOTON BMC, port 0x164E
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

||
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||
Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file
of the matching size.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||
Choose this option if you have a 64 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
Choose this option if you have a 128 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
Choose this option if you have a 256 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
Choose this option if you have a 512 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
Choose this option if you have a 1024 KB (1 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
Choose this option if you have a 2048 KB (2 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
Choose this option if you have a 4096 KB (4 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
Choose this option if you have a 8192 KB (8 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
Choose this option if you have a 16384 KB (16 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
The selected mainboard can optionally have the power button tied
to ground with a jumper so that the button appears to be
constantly depressed. If this option is enabled and the jumper is
installed then the board will turn on, but turn off again after a
short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an
actual power button. Select N if you have the jumper installed.

||
|- bgcolor="#eeeeee"
| MAINBOARD_SERIAL_NUMBER || mainboard || string || Serial number ||
Define the used serial number which will be used by SMBIOS tables.

||
|- bgcolor="#eeeeee"
| MAINBOARD_VERSION || mainboard || string || Version number ||
Define the used version number which will be used by SMBIOS tables.
||

|- bgcolor="#6699dd"
! align="left" | Menu: Architecture (x86) || || || ||
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Architecture (armv7) || || || ||
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/armv7 || bool || Update existing coreboot.rom image ||
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Chipset || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
|- bgcolor="#eeeeee"
| SKIP_LOWLEVEL_INIT || cpu/samsung || bool || Skip low-level init ||
Certain functions (ie PLL init) and processor features may already be
handled by masked ROM code.

||
|- bgcolor="#eeeeee"
| BOOTBLOCK_OFFSET || cpu/samsung/exynos5250 || hex || Bootblock offset ||
This is where the Coreboot bootblock resides. For Exynos5250,
this value is pre-determined by the vendor-provided BL1.

||
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||
Select this to apply patches to the CPU microcode provided by
AMD without source, and distributed with coreboot, to address
issues in the CPU post production.

Microcode updates distributed with coreboot are not necessarily
the latest version available from AMD. Updates are only applied
if they are newer than the microcode already in your CPU.

Unselect this to let Fam10h CPUs run with microcode as shipped
from factory. No binary microcode patches will be included in the
coreboot image in that case, which can help with creating an image
for which complete source code is available, which in turn might
simplify license compliance.

Microcode updates intend to solve issues that have been discovered
after CPU production. The common case is that systems work as
intended with updated microcode, but we have also seen cases where
issues were solved by not applying the microcode updates.

Note that some operating system include these same microcode
patches, so you may need to also disable microcode updates in
your operating system in order for this option to matter.

||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/geode_gx2 || bool || Add a VSA image ||
Select this option if you have an AMD Geode GX2 vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/geode_gx2 || string || AMD Geode GX2 VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||
Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| XIP_ROM_SIZE || cpu/amd/agesa || hex || ||
Overwride the default write through caching size as 1M Bytes.
On some AMD paltform, one socket support 2 or more kinds of
processor family, compiling several cpu families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash rom,
more space is required to be set as write through caching.

||
|- bgcolor="#eeeeee"
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

||
|- bgcolor="#eeeeee"
| CPU_AMD_SOCKET_G34 || cpu/amd/agesa/family15 || bool || ||
AMD G34 Socket

||
|- bgcolor="#eeeeee"
| CPU_AMD_SOCKET_C32 || cpu/amd/agesa/family15 || bool || ||
AMD C32 Socket

||
|- bgcolor="#eeeeee"
| CPU_AMD_SOCKET_AM3R2 || cpu/amd/agesa/family15 || bool || ||
AMD AM3r2 Socket

||
|- bgcolor="#eeeeee"
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family15 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

||
|- bgcolor="#eeeeee"
| TSC_SYNC_LFENCE || cpu/x86 || bool || ||
The CPU driver should select this if the CPU needs
to execute an lfence instruction in order to synchronize
rdtsc. This is true for all modern AMD CPUs.

||
|- bgcolor="#eeeeee"
| TSC_SYNC_MFENCE || cpu/x86 || bool || ||
The CPU driver should select this if the CPU needs
to execute an mfence instruction in order to synchronize
rdtsc. This is true for all modern Intel CPUs.

||
|- bgcolor="#eeeeee"
| SMP || cpu || bool || ||
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.

||
|- bgcolor="#eeeeee"
| AP_SIPI_VECTOR || cpu || hex || ||
This must equal address of ap_sipi_vector from bootblock build.

||
|- bgcolor="#eeeeee"
| MMX || cpu || bool || ||
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.

||
|- bgcolor="#eeeeee"
| SSE || cpu || bool || ||
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.

||
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool || ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.

||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||
Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
file. Microcode will not be hard-coded into ramstage.

The microcode file and may be removed from the ROM image at a later
time with cbfstool, if desired.

If unsure, select this option.

||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_EXTERNAL || cpu || bool || Include external microcode file ||
Select this option if you want to include an external file containing
the CPU microcode. This will be included as a separate file in CBFS.
A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.

The microcode file and may be removed from the ROM image at a later
time with cbfstool, if desired.

If unsure, select "Generate from tree"

||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_FILE || cpu || string || Path and filename of CPU microcode ||
The path and filename of the file containing the CPU microcode.

||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||
Select this option if you do not want CPU microcode included in CBFS.
Note that for some CPUs, the microcode is hard-coded into the source
tree and is not loaded from CBFS. In this case, microcode will still
be updated. There is a push to move all microcode to CBFS, but this
change is not implemented for all CPUs.

This option currently applies to:
- Intel SandyBridge/IvyBridge
- VIA Nano

Microcode may be added to the ROM image at a later time with cbfstool,
if desired.

If unsure, select "Generate from tree"

The GOOD:
Microcode updates intend to solve issues that have been discovered
after CPU production. The expected effect is that systems work as
intended with the updated microcode, but we have also seen cases where
issues were solved by not applying microcode updates.

The BAD:
Note that some operating system include these same microcode patches,
so you may need to also disable microcode updates in your operating
system for this option to have an effect.

The UGLY:
A word of CAUTION: some CPUs depend on microcode updates to function
correctly. Not updating the microcode may leave the CPU operating at
less than optimal performance, or may cause outright hangups.
There are CPUs where coreboot cannot properly initialize the CPU
without microcode updates
For example, if running with the factory microcode, some Intel
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
will hang when changing the frequency.

Make sure you have a way of flashing the ROM externally before
selecting this option.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

||
|- bgcolor="#eeeeee"
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
This Option allows you to redirect the AMD Northbridge CIMX
Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

||

||
||
|- bgcolor="#6699dd"
! align="left" | Menu: HyperTransport setup || || || ||
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||
This option sets the maximum permissible HyperTransport link
frequency.

Use of this option will only limit the autodetected HT frequency.
It will not (and cannot) increase the frequency beyond the
autodetected limits.

This is primarily used to work around poorly designed or laid out
HT traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||
This option sets the maximum permissible HyperTransport
downlink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||
This option sets the maximum permissible HyperTransport
uplink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||

|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||
This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.

If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.

||
||
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.

||
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.

||
|- bgcolor="#eeeeee"
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int || ||
On some boards it may be neccessary to hard reset early
during resume from S3 if the SLFRCS register indicates that
a memory channel is not guaranteed to be in self-refresh.
On other boards the check always creates a false positive,
effectively making it impossible to resume.

||
|- bgcolor="#eeeeee"
| HAVE_MRC || northbridge/intel/sandybridge || bool || Add a System Agent binary ||
Select this option to add a System Agent binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

||
|- bgcolor="#eeeeee"
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
The path and filename of the file to use as System Agent
binary.

||
|- bgcolor="#eeeeee"
| CBFS_SIZE || northbridge/intel/sandybridge || hex || Size of CBFS filesystem in ROM ||
On Sandybridge and Ivybridge systems the firmware image has to
store a lot more than just coreboot, including:
- a firmware descriptor
- Intel Management Engine firmware
- MRC cache information
This option allows to limit the size of the CBFS portion in the
firmware image.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Geode GX1 video support || || || ||

|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||
Select if RS690 should be setup to support MMCONF.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||
Select the mode in which SATA should be driven. IDE or AHCI.
The default is IDE.

config SATA_MODE_IDE
bool "IDE"

config SATA_MODE_AHCI
bool "AHCI"
||
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb700 || hex || ||
0x0 = Native IDE mode.
0x1 = RAID mode.
0x2 = AHCI mode.
0x3 = Legacy IDE mode.
0x4 = IDE->AHCI mode.
0x5 = AHCI mode as 7804 ID (AMD driver).
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

||
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb700 || bool || ||
n = Disable PCI Bridge Device 14 Function 4.
y = Enable PCI Bridge Device 14 Function 4.

||
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb700 || hex || ||
Set SCI IRQ to 9.
||
|- bgcolor="#eeeeee"
| REDIRECT_SBCIMX_TRACE_TO_SERIAL || southbridge/amd/cimx/sb700 || bool || Redirect AMD Southbridge CIMX Trace to serial console ||
This Option allows you to redirect the AMD Southbridge CIMX Trace
debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

||
|- bgcolor="#eeeeee"
| S3_VOLATILE_POS || southbridge/amd/cimx/sb700 || hex || S3 volatile storage position ||
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.

||
|- bgcolor="#eeeeee"
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
If Combined Mode is enabled. IDE controller is exposed and
SATA controller has control over Port0 through Port3,
IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and
SATA controller has full control of all 6 Ports when operating in non-IDE mode.

||
|- bgcolor="#eeeeee"
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.

||
|- bgcolor="#eeeeee"
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
NATIVE is the default mode and does not require a ROM.

||
|- bgcolor="#eeeeee"
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.

||
|- bgcolor="#eeeeee"
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
sb800 RAID mode must have the two required ROM files.

||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.

||
|- bgcolor="#eeeeee"
| S3_VOLATILE_POS || southbridge/amd/cimx/sb800 || hex || S3 volatile storage position ||
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.

||
|- bgcolor="#eeeeee"
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

||
|- bgcolor="#eeeeee"
| SB800_FWM_POSITION || southbridge/amd/cimx/sb800 || hex || Fan Control ||
Select the method of SB800 fan control to be used. None would be
for either fixed maximum speed fans connected to the SB800 or for
an external chip controlling the fan speeds. Manual control sets
up the SB800 fan control registers. IMC fan control uses the SB800
IMC to actively control the fan speeds.

||
|- bgcolor="#eeeeee"
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
No SB800 Fan control - Do not set up the SB800 fan control registers.

||
|- bgcolor="#eeeeee"
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
Configure the SB800 fan control registers in devicetree.cb.

||
|- bgcolor="#eeeeee"
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
Set up the SB800 to use the IMC based Fan controller. This requires
the IMC rom from AMD. Configure the registers in devicetree.cb.

||
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||
0x0 = Native IDE mode.
0x1 = RAID mode.
0x2 = AHCI mode.
0x3 = Legacy IDE mode.
0x4 = IDE->AHCI mode.
0x5 = AHCI mode as 7804 ID (AMD driver).
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

||
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || ||
n = Disable PCI Bridge Device 14 Function 4.
y = Enable PCI Bridge Device 14 Function 4.

||
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||
Set SCI IRQ to 9.

||
|- bgcolor="#eeeeee"
| S3_VOLATILE_POS || southbridge/amd/cimx/sb900 || hex || S3 volatile storage position ||
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.

||
|- bgcolor="#eeeeee"
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0

||
|- bgcolor="#eeeeee"
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

||
|- bgcolor="#eeeeee"
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool || Add gec firmware ||
Add Hudson 2/3/4 GEC Firmware

||
|- bgcolor="#eeeeee"
| HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || Hudson Firmware rom Position ||
Hudson requires the firmware MUST be located at
a specific address (ROM start address + 0x20000), otherwise
xhci host Controller can not find or load the xhci firmware.

The firmware start address is dependent on the ROM chip size.
The default offset is 0x20000 from the ROM start address, namely
0xFFF20000 if flash chip size is 1M
0xFFE20000 if flash chip size is 2M
0xFFC20000 if flash chip size is 4M
0xFF820000 if flash chip size is 8M
0xFF020000 if flash chip size is 16M
||
|- bgcolor="#eeeeee"
| HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_IDE || southbridge/amd/agesa/hudson || bool || NATIVE ||
NATIVE is the default mode and does not require a ROM.

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_RAID || southbridge/amd/agesa/hudson || bool || RAID ||
HUDSON RAID mode must have the two required ROM files.

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_AHCI || southbridge/amd/agesa/hudson || bool || AHCI ||
AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_LEGACY_IDE || southbridge/amd/agesa/hudson || bool || LEGACY IDE ||
TODO

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_IDE2AHCI || southbridge/amd/agesa/hudson || bool || IDE to AHCI ||
TODO

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_AHCI7804 || southbridge/amd/agesa/hudson || bool || AHCI7804 ||
AHCI ROM Required, and AMD driver required in the OS.

||
|- bgcolor="#eeeeee"
| HUDSON_SATA_IDE2AHCI7804 || southbridge/amd/agesa/hudson || bool || IDE to AHCI7804 ||
AHCI ROM Required, and AMD driver required in the OS.
||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.
||
|- bgcolor="#eeeeee"
| S3_VOLATILE_POS || southbridge/amd/agesa/hudson || hex || S3 volatile storage position ||
For a system with S3 feature, the BIOS needs to save some data to
non-volitile storage at cold boot stage.

||
|- bgcolor="#eeeeee"
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
Select this option to add a CMC state machine binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

||
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
The path and filename of the file to use as CMC state machine
binary.

||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool || ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

||
|- bgcolor="#eeeeee"
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/bd82x6x || bool || Lock Management Engine section ||
The Intel Management Engine supports preventing write accesses
from the host to the Management Engine section in the firmware
descriptor. If the ME section is locked, it can only be overwritten
with an external SPI flash programmer. You will want this if you
want to increase security of your ROM image once you are sure
that the ME firmware is no longer going to change.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||
ACPI Embedded Controller interface. Mostly found in laptops.

||
||
|- bgcolor="#eeeeee"
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool || ||
Interface to COMPAL ENE932 Embedded Controller.

||

||
||
|- bgcolor="#eeeeee"
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool || ||
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.

||

||

||

||

|- bgcolor="#6699dd"
! align="left" | Menu: Devices || || || ||
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||
Execute VGA Option ROMs in coreboot if found. This is required
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
payload.

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

||
|- bgcolor="#eeeeee"
| S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

||
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || device || bool || Run non-VGA Option ROMs ||
Execute non-VGA PCI Option ROMs in coreboot if found.

Examples include IDE/SATA controller Option ROMs and Option ROMs
for network cards (NICs).

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

||
|- bgcolor="#eeeeee"
| ON_DEVICE_ROM_RUN || device || bool || Run Option ROMs on PCI devices ||
Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.

If disabled, only Option ROMs stored in CBFS will be executed by
coreboot. If you are concerned about security, you might want to
disable this option, but it might leave your system in a state of
degraded functionality.

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||
If you select this option, PCI Option ROMs will be executed
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||
If you select this option, the x86emu CPU emulator will be used to
execute PCI Option ROMs.

This option prevents Option ROMs from doing dirty tricks with the
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native Option ROM initialization
method.

This is the default choice for non-x86 systems.

||
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||
Per default, YABEL only allows Option ROMs to access the PCI device
that they are associated with. However, this causes trouble for some
onboard graphics chips whose Option ROM needs to reconfigure the
north bridge.

||
|- bgcolor="#eeeeee"
| YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||
By default, YABEL aborts when the Option ROM tries to write to other
devices' config spaces. With this option enabled, the write doesn't
follow through, but the Option ROM is allowed to go on.
This can create issues such as hanging Option ROMs (if it depends on
that other register changing to the written value), so test for
impact before using this option.

||
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||
YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.

||
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || device || bool || Direct hardware access ||
YABEL consists of two parts: It uses x86emu for the CPU emulation and
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).

When choosing this option, x86emu will pass through all hardware
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents Option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.

||
|- bgcolor="#eeeeee"
| PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||
Detect and enable Common Clock on PCIe links.

||
|- bgcolor="#eeeeee"
| PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||
Detect and enable ASPM on PCIe links.

||

|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
|- bgcolor="#eeeeee"
| VGA_BIOS || device || bool || Add a VGA BIOS image ||
Select this option if you have a VGA BIOS image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||
The path and filename of the file to use as VGA BIOS.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || device || string || VGA device PCI IDs ||
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).

||
|- bgcolor="#eeeeee"
| INTEL_MBI || device || bool || Add an MBI image ||
Select this option if you have an Intel MBI image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| MBI_FILE || device || string || Intel MBI path and filename ||
The path and filename of the file to use as VGA BIOS.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Display || || || ||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || device || bool || Set VESA framebuffer mode ||
Set VESA framebuffer mode (needed for bootsplash)

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || device || bool || VESA framebuffer video mode ||
This option sets the resolution used for the coreboot framebuffer (and
bootsplash screen).

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_KEEP_VESA_MODE || device || bool || Keep VESA framebuffer ||
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH || device || bool || Show graphical bootsplash ||
This option shows a graphical bootsplash screen. The grapics are
loaded from the CBFS file bootsplash.jpg.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || device || string || Bootsplash path and filename ||
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
||

|- bgcolor="#6699dd"
! align="left" | Menu: Generic Drivers || || || ||
|- bgcolor="#eeeeee"
| ELOG || drivers/elog || bool || Support for flash based event log ||
Enable support for flash based event logging.

||
|- bgcolor="#eeeeee"
| ELOG_FLASH_BASE || drivers/elog || hex || Event log offset into flash ||
Offset into the flash chip for the ELOG block.
This should be allocated in the FMAP.

||
|- bgcolor="#eeeeee"
| ELOG_AREA_SIZE || drivers/elog || hex || Size of Event Log area in flash ||
This should be a multiple of flash block size.

Default is 4K.

||
|- bgcolor="#eeeeee"
| ELOG_FULL_THRESHOLD || drivers/elog || hex || Threshold at which flash is considered full ||
When the Event Log size is larger than this it will be shrunk
to ELOG_SHRINK_SIZE. Must be greater than ELOG_AREA_SIZE, and
ELOG_AREA_SIZE - ELOG_FULL_THRESHOLD must be greater than the
maximum event size of 128.

Default is 75% of the log, or 3K.

||
|- bgcolor="#eeeeee"
| ELOG_SHRINK_SIZE || drivers/elog || hex || Resulting size when the event log is shrunk ||
When the Event Log is shrunk it will go to this size.
ELOG_AREA_SIZE - ELOG_SHRINK_SIZE must be less than
CONFIG_ELOG_FULL_THRESHOLD.

Default is 1K.

||
|- bgcolor="#eeeeee"
| ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||
This option will have ELOG store a copy of the flash event log
in a CBMEM region and export that address in SMBIOS to the OS.
This is useful if the ELOG location is not in memory mapped flash,
but it means that events added at runtime via the SMI handler
will not be reflected in the CBMEM copy of the log.

||
|- bgcolor="#eeeeee"
| ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||
This interface is compatible with the linux kernel driver
available with CONFIG_GOOGLE_GSMI and can be used to write
kernel reset/shutdown messages to the event log.

||
|- bgcolor="#eeeeee"
| ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||
Store a monotonic boot number in CMOS and provide an interface
to read the current value and increment the counter. This boot
counter will be logged as part of the System Boot event.

||
|- bgcolor="#eeeeee"
| ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||
This value must be greater than 16 bytes so as not to interfere
with the standard RTC region. Requires 8 bytes.

||
||
|- bgcolor="#eeeeee"
| DRIVER_MAXIM_MAX77686 || drivers/maxim/max77686 || bool || ||
Maxim MAX77686 power regulator

||

||
||
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 will work.
NOTE: Right now you have to set the base address of your OXPCIe952
card to exactly the value that the device allocator would set them
later on, or serial console functionality will stop as soon as the
resource allocator assigns a new base address to the device.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
for the OXPCIe952 controller.

||

||
||
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || drivers/pc80 || bool || PS/2 keyboard init ||
Enable this option to initialize PS/2 keyboards found connected
to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads
(eg, SeaBIOS, Linux) do not require it.
Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require
this option, then you can say N here to speed up boot time.
Otherwise say Y.

||
|- bgcolor="#eeeeee"
| TPM || drivers/pc80 || bool || ||
Enable this option to enable TPM support in coreboot.

If unsure, say N.

||
||
|- bgcolor="#eeeeee"
| RTL8168_ROM_DISABLE || drivers/realtek || bool || Disable RTL8168 ROM ||
Just enough of a driver to make coreboot not look for an Option ROM.
No configuration is necessary for the OS to pick up the device.

||
||
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.

||
||
|- bgcolor="#eeeeee"
| SPI_FLASH || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_SMM || drivers/spi || bool || SPI flash driver support in SMM ||
Select this option if you want SPI flash support in SMM.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_EON || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by EON.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_MACRONIX || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Macronix.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_SPANSION || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Spansion.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_SST || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by SST.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_STMICRO || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by ST MICRO.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_WINBOND || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Winbond.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_NO_FAST_READ || drivers/spi || bool || Disable Fast Read command ||
Select this option if your setup requires to avoid "fast read"s
from the SPI flash parts.

||
|- bgcolor="#eeeeee"
| SPI_FLASH_GIGADEVICE || drivers/spi || bool || ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Gigadevice.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Console || || || ||
|- bgcolor="#eeeeee"
| SERIAL_CONSOLE || console || bool || Serial port console output ||
Send coreboot debug output to a serial port

||
|- bgcolor="#eeeeee"
| EARLY_SERIAL_CONSOLE || console || bool || ||
Use serial console during early (pre-RAM) boot stages

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output (I/O mapped, 8250-compatible) ||
Send coreboot debug output to an I/O mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped, 8250-compatible) ||
Send coreboot debug output to a memory mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_NONSTANDARD_MEM || console || bool || Serial port console output (memory-mapped, device-specific) ||
Send coreboot debug output to a memory mapped serial port console
on a device-specific UART.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
Serial console on COM1/ttyS0 at I/O port 0x3f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
Serial console on COM2/ttyS1 at I/O port 0x2f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
Serial console on COM3/ttyS2 at I/O port 0x3e8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
Serial console on COM4/ttyS3 at I/O port 0x2e8.

||
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex || ||
Map the COM port names to the respective I/O port.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
Set serial port Baud rate to 115200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
Set serial port Baud rate to 57600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
Set serial port Baud rate to 38400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
Set serial port Baud rate to 19200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
Set serial port Baud rate to 9600.

||
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int || ||
Map the Baud rates to an integer.

||
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||
This option allows you to use a so-called USB EHCI Debug device
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Linux "EHCI Debug Device gadget" driver found in recent kernel)
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI
Debug Port capability.

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||
This option selects which physical USB port coreboot will try to
use as EHCI Debug Port first (valid values are: 1-15).

If coreboot doesn't detect an EHCI Debug Port dongle on this port,
it will try all the other ports one after the other. This will take
a few seconds of time though, and thus slow down the booting process.

Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
actual port on your mainboard (potentially also USB pin headers
on your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.

||
|- bgcolor="#eeeeee"
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||
If not selected, the last adapter found will be used.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
Send coreboot debug output to a Ethernet console, it works
same way as Linux netconsole, packets are received to UDP
port 6666 on IP/MAC specified with options bellow.
Use following netcat command: nc -u -l -p 6666

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
Type in either MAC address of logging system or MAC address
of the router.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
This is IP adress of the system running for example
netcat command to dump the packets.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
This is the IP of the coreboot system

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
This is the IO port address for the IO port
on the card, please select some non-conflicting region,
32 bytes of IO spaces will be used (and align on 32 bytes
boundary, qemu needs broader align)

||
|- bgcolor="#eeeeee"
| CONSOLE_CBMEM || console || bool || Send console output to a CBMEM buffer ||
Enable this to save the console output in a CBMEM buffer. This would
allow to see coreboot console output from Linux space.

||
|- bgcolor="#eeeeee"
| CONSOLE_CBMEM_BUFFER_SIZE || console || hex || Room allocated for console output in CBMEM ||
Space allocated for console output storage in CBMEM. The default
value (64K or 0x10000 bytes) is large enough to accommodate
even the BIOS_SPEW level.

||
|- bgcolor="#eeeeee"
| CONSOLE_CAR_BUFFER_SIZE || console || hex || Room allocated for console output in Cache as RAM ||
Console is used before RAM is initialized. This is the room reserved
in the DCACHE based RAM to keep console output before it can be
saved in a CBMEM buffer. 3K bytes should be enough even for the
BIOS_SPEW level.

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||
If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the debug console.

||
|- bgcolor="#eeeeee"
| CMOS_POST || console || bool || Store post codes in CMOS for debugging ||
If enabled, coreboot will store post codes in CMOS and switch between
two offsets on each boot so the last post code in the previous boot
can be retrieved. This uses 3 bytes of CMOS.

||
|- bgcolor="#eeeeee"
| CMOS_POST_OFFSET || console || hex || Offset into CMOS to store POST codes ||
If CMOS_POST is enabled then an offset into CMOS must be provided.
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
defined in the mainboard option table.

||
|- bgcolor="#eeeeee"
| IO_POST || console || bool || Send POST codes to an IO port ||
If enabled, POST codes will be written to an IO port.

||
|- bgcolor="#eeeeee"
| IO_POST_PORT || console || hex || IO port for POST codes ||
POST codes on x86 are typically written to the LPC bus on port
0x80. However, it may be desireable to change the port number
depending on the presence of coprocessors/microcontrollers or if the
platform does not support IO in the conventional x86 manner.

||

|- bgcolor="#eeeeee"
| HAVE_HARD_RESET || toplevel || bool || ||
This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.

||
|- bgcolor="#eeeeee"
| HAVE_OPTION_TABLE || toplevel || bool || ||
This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.

||
|- bgcolor="#eeeeee"
| VGA || toplevel || bool || ||
Build board-specific VGA code.

||
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool || ||
Enable Unified Memory Architecture for graphics.

||
|- bgcolor="#eeeeee"
| HAVE_ACPI_TABLES || toplevel || bool || ||
This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
is configurable by the user via GENERATE_ACPI_TABLES.

||
|- bgcolor="#eeeeee"
| HAVE_MP_TABLE || toplevel || bool || ||
This variable specifies whether a given board has MP table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the MP table is actually generated by coreboot
is configurable by the user via GENERATE_MP_TABLE.

||
|- bgcolor="#eeeeee"
| HAVE_PIRQ_TABLE || toplevel || bool || ||
This variable specifies whether a given board has PIRQ table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.

||
|- bgcolor="#eeeeee"
| MAX_PIRQ_LINKS || toplevel || int || ||
This variable specifies the number of PIRQ interrupt links which are
routable. On most chipsets, this is 4, INTA through INTD. Some
chipsets offer more than four links, commonly up to INTH. They may
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
table specifies links greater than 4, pirq_route_irqs will not
function properly, unless this variable is correctly set.

||
|- bgcolor="#6699dd"
! align="left" | Menu: System tables || || || ||
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
Generate ACPI tables for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
Generate a PIRQ table for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||
Generate SMBIOS tables for this board.

If unsure, say Y.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Payload || || || ||
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
Select this option if you have a payload image (an ELF file)
which coreboot should run as soon as the basic hardware
initialization is completed.

You will be able to specify the location and file name of the
payload image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||
Select this option if you want to build a coreboot image
with a SeaBIOS payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| PAYLOAD_FILO || toplevel || bool || FILO ||
Select this option if you want to build a coreboot image
with a FILO payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || 1.7.1 ||
Stable SeaBIOS version
||
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||
Newest SeaBIOS version
||
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||
Stable FILO version
||
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||
Newest FILO version
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||
The path and filename of the ELF executable file to use as payload.

||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.

||
|- bgcolor="#eeeeee"
| GDB_WAIT || toplevel || bool || Wait for a GDB connection ||
If enabled, coreboot will wait for a GDB connection.

||
|- bgcolor="#eeeeee"
| DEBUG_CBFS || toplevel || bool || Output verbose CBFS debug messages ||
This option enables additional CBFS related debug messages.

||
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
This option enables additional CAR related debug messages.
||
|- bgcolor="#eeeeee"
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
This option enables additional SMM handler relocation related
debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||
This option enables additional ACPI related debug messages.

Note: This option will slightly increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
Print messages related to accesses to certain areas of the virtual
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
Print memory accesses made by option ROM.
Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_TPM || toplevel || bool || Output verbose TPM debug messages ||
This option enables additional TPM related debug messages.

||
|- bgcolor="#eeeeee"
| DEBUG_SPI_FLASH || toplevel || bool || Output verbose SPI flash debug messages ||
This option enables additional SPI flash related debug messages.

||
|- bgcolor="#eeeeee"
| DEBUG_INTEL_ME || toplevel || bool || Verbose logging for Intel Management Engine ||
Enable verbose logging for Intel Management Engine driver that
is present on Intel 6-series chipsets.
||
|- bgcolor="#eeeeee"
| LLSHELL || toplevel || bool || Built-in low-level shell ||
If enabled, you will have a low level shell to examine your machine.
Put llshell() in your (romstage) code to start the shell.
See src/arch/x86/llshell/llshell.inc for details.

||
|- bgcolor="#eeeeee"
| TRACE || toplevel || bool || Trace function calls ||
If enabled, every function will print information to console once
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
of calling function. Please note some printk releated functions
are omitted from trace to have good looking console dumps.
||

|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || bool || ||
Select when the board has a power button which can optionally be
disabled by the user.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || bool || ||
Select when the board has a power button which can optionally be
enabled by the user, e.g. when the board ships with a jumper over
the power switch contacts.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_ENABLE || toplevel || bool || ||
Select when the board requires that the power button is always
enabled.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_DISABLE || toplevel || bool || ||
Select when the board requires that the power button is always
disabled, e.g. when it has been hardwired to ground.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool || ||
Internal option that controls ENABLE_POWER_BUTTON visibility.

||
|- bgcolor="#eeeeee"
| CHROMEOS || vendorcode/google/chromeos || bool || ||
Enable ChromeOS specific features like the GPIO sub table in
the coreboot table. NOTE: Enabling this option on an unsupported
board will most likely break your build.

||
|- bgcolor="#6699dd"
! align="left" | Menu: ChromeOS || || || ||
|- bgcolor="#eeeeee"
| VBNV_OFFSET || vendorcode/google/chromeos || hex || ||
CMOS offset for VbNv data. This value must match cmos.layout
in the mainboard directory, minus 14 bytes for the RTC.

||
|- bgcolor="#eeeeee"
| VBNV_SIZE || vendorcode/google/chromeos || hex || ||
CMOS storage size for VbNv data. This value must match cmos.layout
in the mainboard directory.

||
|- bgcolor="#eeeeee"
| FLASHMAP_OFFSET || vendorcode/google/chromeos || hex || Flash Map Offset ||
Offset of flash map in firmware image

||

|- bgcolor="#eeeeee"
| NO_TPM_RESUME || vendorcode/google/chromeos || bool || ||
On some boards the TPM stays powered up in S3. On those
boards, booting Windows will break if the TPM resume command
is sent during an S3 resume.

||

||

||

||
|}

Coreboot Options

2013-01-11T13:43:32Z

XVilka: Mention of util/optionlist

This is an automatically generated list of '''coreboot compile-time options''' (using coreboot/util/optionlist utility).

Last update: 2011/10/14 00:44:39. (runknown)
{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Option
! align="left" | Source
! align="left" | Format
! align="left" | Short Description
! align="left" | Description
|- bgcolor="#6699dd"
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
| EXPERT || toplevel || bool || Expert mode ||
This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are
doing! You have been warned!

||
|- bgcolor="#eeeeee"
| LOCALVERSION || toplevel || string || Local version string ||
Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.

||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler ||
This option allows you to select the compiler used for building
coreboot.

||
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||
Changes the build process to scan-build is used.
Requires scan-build in path.

||
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||
Where the scan-build report should be stored

||
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || ccache ||
Enables the use of ccache for faster builds.
Requires ccache in path.

||
|- bgcolor="#eeeeee"
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||
Enable this option if you are working on the sconfig
device tree parser and made changes to sconfig.l and
sconfig.y.
Otherwise, say N.

||
|- bgcolor="#eeeeee"
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.

||
|- bgcolor="#eeeeee"
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow Link (i.e. SPI)

||
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||
Include in CBFS the coreboot config file that was used to compile the ROM image

||

|- bgcolor="#6699dd"
! align="left" | Menu: Mainboard || || || ||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||
The following X60 series ThinkPad machines have been verified to
work correctly:

ThinkPad X60s (Model 1702, 1703)
ThinkPad X60 (Model 1709)

||
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||
The following T60 series ThinkPad machines have been verified to
work correctly:

Thinkpad T60p (Model 2007)

||
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
Look on the bottom side for a number like 406-0001-30. The last 2
digits state the PCB revision (3.0 in this example). For 2.0 or older
boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to
power on automatically. You may enable the button only after this
jumper has been removed. New revision boards are not restricted
in this way, and always have the power button enabled.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
If selected, the on-board SSD will act as IDE Slave instead of Master.

||
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8qgi || hex || ||
though UARTs are on the NUVOTON BMC, port 0x164E
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

||
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||
Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file
of the matching size.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
Choose this option if you have a 128 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
Choose this option if you have a 256 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
Choose this option if you have a 512 KB ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
Choose this option if you have a 1024 KB (1 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
Choose this option if you have a 2048 KB (2 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
Choose this option if you have a 4096 KB (4 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
Choose this option if you have a 8192 KB (8 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
Choose this option if you have a 16384 KB (16 MB) ROM chip.

||
|- bgcolor="#eeeeee"
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
The selected mainboard can optionally have the power button tied
to ground with a jumper so that the button appears to be
constantly depressed. If this option is enabled and the jumper is
installed then the board will turn on, but turn off again after a
short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an
actual power button. Select N if you have the jumper installed.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Architecture (x86) || || || ||
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Chipset || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||
Select this to apply patches to the CPU microcode provided by
AMD without source, and distributed with coreboot, to address
issues in the CPU post production.

Microcode updates distributed with coreboot are not necessarily
the latest version available from AMD. Updates are only applied
if they are newer than the microcode already in your CPU.

Unselect this to let Fam10h CPUs run with microcode as shipped
from factory. No binary microcode patches will be included in the
coreboot image in that case, which can help with creating an image
for which complete source code is available, which in turn might
simplify license compliance.

Microcode updates intend to solve issues that have been discovered
after CPU production. The common case is that systems work as
intended with updated microcode, but we have also seen cases where
issues were solved by not applying the microcode updates.

Note that some operating system include these same microcode
patches, so you may need to also disable microcode updates in
your operating system in order for this option to matter.

||
||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||
Select this option if you have an AMD Geode GX2 vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||
Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||
The path and filename of the file to use as VSA.

||
|- bgcolor="#eeeeee"
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

||
|- bgcolor="#eeeeee"
| SMP || cpu || bool || ||
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.

||
|- bgcolor="#eeeeee"
| MMX || cpu || bool || ||
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.

||
|- bgcolor="#eeeeee"
| SSE || cpu || bool || ||
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.

||
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool || ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.

||
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool || ||
Unset this if you don't want the MTRR code to use
subtractive MTRRs

||
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

||
|- bgcolor="#6699dd"
! align="left" | Menu: HyperTransport setup || || || ||
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||
This option sets the maximum permissible HyperTransport link
frequency.

Use of this option will only limit the autodetected HT frequency.
It will not (and cannot) increase the frequency beyond the
autodetected limits.

This is primarily used to work around poorly designed or laid out
HT traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||
This option sets the maximum permissible HyperTransport
downlink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||
This option sets the maximum permissible HyperTransport
uplink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

||

|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||
This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.

If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.

||
||
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.

||
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Geode GX1 video support || || || ||

|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||
Select if RS690 should be setup to support MMCONF.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||
Select the mode in which SATA should be driven. IDE or AHCI.
The default is IDE.

config SATA_MODE_IDE
bool "IDE"

config SATA_MODE_AHCI
bool "AHCI"
||
|- bgcolor="#eeeeee"
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
If Combined Mode is enabled. IDE controller is exposed and
SATA controller has control over Port0 through Port3,
IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and
SATA controller has full control of all 6 Ports when operating in non-IDE mode.

||
|- bgcolor="#eeeeee"
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.

||
|- bgcolor="#eeeeee"
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
NATIVE is the default mode and does not require a ROM.

||
|- bgcolor="#eeeeee"
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.

||
|- bgcolor="#eeeeee"
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
sb800 RAID mode must have the two required ROM files.

||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.

||
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||
0x0 = Native IDE mode.
0x1 = RAID mode.
0x2 = AHCI mode.
0x3 = Legacy IDE mode.
0x4 = IDE->AHCI mode.
0x5 = AHCI mode as 7804 ID (AMD driver).
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

||
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || ||
n = Disable PCI Bridge Device 14 Function 4.
y = Enable PCI Bridge Device 14 Function 4.

||
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||
Set SCI IRQ to 9.

||
|- bgcolor="#eeeeee"
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
Select this option to add a CMC state machine binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

||
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
The path and filename of the file to use as CMC state machine
binary.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
this unless you're sure you don't want the briges setup for VGA.

||
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
Execute VGA option ROMs, if found. This is required to enable
PCI/AGP/PCI-E video cards.

||
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
Execute non-VGA PCI option ROMs, if found.

Examples include IDE/SATA controller option ROMs and option ROMs
for network cards (NICs).

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||
If you select this option, PCI option ROMs will be executed
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)

||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.

This option prevents option ROMs from doing dirty tricks with the
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native option ROM initialization
method.

This is the default choice for non-x86 systems.

||
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||
Per default, YABEL only allows option ROMs to access the PCI device
that they are associated with. However, this causes trouble for some
onboard graphics chips whose option ROM needs to reconfigure the
north bridge.

||
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||
YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.

||
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||
YABEL consists of two parts: It uses x86emu for the CPU emulation and
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).

When choosing this option, x86emu will pass through all hardware
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.

||
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||
ACPI Embedded Controller interface. Mostly found in laptops.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Generic Drivers || || || ||
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 will work.
NOTE: Right now you have to set the base address of your OXPCIe952
card to exactly the value that the device allocator would set them
later on, or serial console functionality will stop as soon as the
resource allocator assigns a new base address to the device.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
that controls the OXPCIe952 controller first.

||
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
for the OXPCIe952 controller.

||

||
||
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.

||
||

|- bgcolor="#6699dd"
! align="left" | Menu: Console || || || ||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
Send coreboot debug output to an I/O mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||
Send coreboot debug output to a memory mapped serial port console.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
Serial console on COM1/ttyS0 at I/O port 0x3f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
Serial console on COM2/ttyS1 at I/O port 0x2f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
Serial console on COM3/ttyS2 at I/O port 0x3e8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
Serial console on COM4/ttyS3 at I/O port 0x2e8.

||
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex || ||
Map the COM port names to the respective I/O port.

||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
Set serial port Baud rate to 115200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
Set serial port Baud rate to 57600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
Set serial port Baud rate to 38400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
Set serial port Baud rate to 19200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
Set serial port Baud rate to 9600.

||
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int || ||
Map the Baud rates to an integer.

||
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||
This option allows you to use a so-called USB EHCI Debug device
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Linux "EHCI Debug Device gadget" driver found in recent kernel)
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI
Debug Port capability.

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||
This option selects which physical USB port coreboot will try to
use as EHCI Debug Port first (valid values are: 1-15).

If coreboot doesn't detect an EHCI Debug Port dongle on this port,
it will try all the other ports one after the other. This will take
a few seconds of time though, and thus slow down the booting process.

Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
actual port on your mainboard (potentially also USB pin headers
on your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.

||
|- bgcolor="#eeeeee"
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||
If not selected, the last adapter found will be used.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
Send coreboot debug output to a Ethernet console, it works
same way as Linux netconsole, packets are received to UDP
port 6666 on IP/MAC specified with options bellow.
Use following netcat command: nc -u -l -p 6666

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
Type in either MAC address of logging system or MAC address
of the router.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
This is IP adress of the system running for example
netcat command to dump the packets.

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
This is the IP of the coreboot system

||
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
This is the IO port address for the IO port
on the card, please select some non-conflicting region,
32 bytes of IO spaces will be used (and align on 32 bytes
boundary, qemu needs broader align)

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.

||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
Map the log level config names to an integer.

||
|- bgcolor="#eeeeee"
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||
If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the debug console.

||

|- bgcolor="#eeeeee"
| HAVE_HARD_RESET || toplevel || bool || ||
This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.

||
|- bgcolor="#eeeeee"
| HAVE_OPTION_TABLE || toplevel || bool || ||
This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.

||
|- bgcolor="#eeeeee"
| VGA || toplevel || bool || ||
Build board-specific VGA code.

||
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool || ||
Enable Unified Memory Architecture for graphics.

||
|- bgcolor="#eeeeee"
| HAVE_ACPI_TABLES || toplevel || bool || ||
This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
is configurable by the user via GENERATE_ACPI_TABLES.

||
|- bgcolor="#eeeeee"
| HAVE_MP_TABLE || toplevel || bool || ||
This variable specifies whether a given board has MP table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the MP table is actually generated by coreboot
is configurable by the user via GENERATE_MP_TABLE.

||
|- bgcolor="#eeeeee"
| HAVE_PIRQ_TABLE || toplevel || bool || ||
This variable specifies whether a given board has PIRQ table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.

||
|- bgcolor="#6699dd"
! align="left" | Menu: System tables || || || ||
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
Generate ACPI tables for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
Generate a PIRQ table for this board.

If unsure, say Y.

||
|- bgcolor="#eeeeee"
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||
Generate SMBIOS tables for this board.

If unsure, say Y.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Payload || || || ||
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
Select this option if you have a payload image (an ELF file)
which coreboot should run as soon as the basic hardware
initialization is completed.

You will be able to specify the location and file name of the
payload image later.

||
|- bgcolor="#eeeeee"
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||
Select this option if you want to build a coreboot image
with a SeaBIOS payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| PAYLOAD_FILO || toplevel || bool || FILO ||
Select this option if you want to build a coreboot image
with a FILO payload. If you don't know what this is
about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

||
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || stable ||
Stable SeaBIOS version
||
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||
Newest SeaBIOS version
||
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||
Stable FILO version
||
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||
Newest FILO version
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||
The path and filename of the ELF executable file to use as payload.

||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.

||

|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
Select this option if you have a VGA BIOS image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
The path and filename of the file to use as VGA BIOS.

||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).

||
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||
Select this option if you have an Intel MBI image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

||
|- bgcolor="#eeeeee"
| MBI_FILE || toplevel || string || Intel MBI path and filename ||
The path and filename of the file to use as VGA BIOS.

||

|- bgcolor="#6699dd"
! align="left" | Menu: Display || || || ||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || toplevel || bool || Set VESA framebuffer mode ||
Set VESA framebuffer mode (needed for bootsplash)

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||
This option sets the resolution used for the coreboot framebuffer (and
bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
some day make this a "choice".

||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_KEEP_VESA_MODE || toplevel || bool || Keep VESA framebuffer ||
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||
This option shows a graphical bootsplash screen. The grapics are
loaded from the CBFS file bootsplash.jpg.

||
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
||

|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.

||
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
This option enables additional CAR related debug messages.
||
|- bgcolor="#eeeeee"
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
This option enables additional SMM handler relocation related
debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||
This option enables additional ACPI related debug messages.

Note: This option will slightly increase the size of the coreboot image.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
Print messages related to accesses to certain areas of the virtual
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
Print memory accesses made by option ROM.
Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

||
|- bgcolor="#eeeeee"
| LLSHELL || toplevel || bool || Built-in low-level shell ||
If enabled, you will have a low level shell to examine your machine.
Put llshell() in your (romstage) code to start the shell.
See src/arch/x86/llshell/llshell.inc for details.

||
|- bgcolor="#eeeeee"
| TRACE || toplevel || bool || Trace function calls ||
If enabled, every function will print information to console once
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
of calling function. Please note some printk releated functions
are omitted from trace to have good looking console dumps.
||

|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex || ||
Select when the board has a power button which can optionally be
disabled by the user.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex || ||
Select when the board has a power button which can optionally be
enabled by the user, e.g. when the board ships with a jumper over
the power switch contacts.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex || ||
Select when the board requires that the power button is always
enabled.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex || ||
Select when the board requires that the power button is always
disabled, e.g. when it has been hardwired to ground.

||
|- bgcolor="#eeeeee"
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool || ||
Internal option that controls ENABLE_POWER_BUTTON visibility.

||
|- bgcolor="#6699dd"
! align="left" | Menu: Deprecated || || || ||
|- bgcolor="#eeeeee"
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a reset.c
file containing a hard_reset() function.

||
|- bgcolor="#eeeeee"
| BOARD_HAS_FADT || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a board-local
FADT in fadt.c. Long-term, those should be moved to appropriate
chipset components (eg. southbridge).

||
|- bgcolor="#eeeeee"
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool || ||
This variable specifies whether a given board has a get_bus_conf.c
file containing information about bus routing.

||
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init ||
Enable this option to initialize PS/2 keyboards found connected
to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads
(eg, SeaBIOS, Linux) do not require it.
Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require
this option, then you can say N here to speed up boot time.
Otherwise say Y.

||
|- bgcolor="#eeeeee"
| PCIE_TUNING || toplevel.deprecated_options || bool || ||
This variable enables certain PCIe optimizations. Right now it's
only ASPM and it's untested.

||

|}

QEMU

2012-12-10T10:04:28Z

XVilka:

You can easily try out coreboot using [http://qemu.org/ QEMU], without having to actually flash the BIOS chip on your real hardware.

== Tutorials ==

* [[QEMU Build Tutorial]] — Starting a Debian GNU/Linux system via coreboot + a Linux kernel, or via coreboot + [[FILO]].
* [[FreeBSD|Booting FreeBSD using coreboot]] — Booting FreeBSD via coreboot + ADLO.

== Ready-made QEMU images ==

Below is a list of various downloadable QEMU images you can use to try out coreboot.

You need a patched version of '''vgabios-cirrus.zip''' for these images to work fine, the version in QEMU's CVS repository does '''not''' yet work. The image from Debian's QEMU package ('''/usr/share/qemu/vgabios-cirrus.bin''') is already patched and works, too.

=== coreboot v2 + SeaBIOS ===

[[File:Qemu seabios.png|thumb|right|[[SeaBIOS]] payload.]]

[[SeaBIOS]] is an open-source legacy BIOS implementation which can be used as a coreboot payload. It implements the standard BIOS calling interfaces that a typical x86 proprietary BIOS implements.

The QEMU image uses coreboot v2 (r4917) and [[SeaBIOS]] (9eebe66a9978165cfa91f2266c97fa5d0aa6ef2e, 2009-11-04) with the following changes to the default '''src/config.h''':

#define CONFIG_COREBOOT 1
#define CONFIG_DEBUG_SERIAL 1
#define CONFIG_COREBOOT_FLASH 1
#define CONFIG_OPTIONROMS_DEPLOYED 0
#define CONFIG_VGAHOOKS 1

Usage:

mkdir foo
cd foo
wget http://www.coreboot.org/images/6/6a/Qemu_coreboot_seabios.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_seabios.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_seabios.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

Replace '''/dev/zero''' above with a real QEMU disk image to actually boot something.

=== coreboot v3 + FILO ===

[[Image:Qemu filo.png|thumb|right|[[FILO]] payload.]]

[[FILO]] is a simple bootloader which can load (e.g.) Linux kernels from disk.

The QEMU image uses coreboot v3 (r672) and [[FILO]] (r45) with a certain configuration (for example: it's looking for '''/boot/grub/menu.lst''' on hda1).

mkdir foo
cd foo
wget http://www.coreboot.org/images/b/b9/Qemu_coreboot_filo.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_filo.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_filo.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

Replace '''/dev/zero''' above with a real QEMU disk image which has a '''/boot/grub/menu.lst''' on '''hda1''' to actually boot something.

=== coreboot + libpayload + coreinfo ===

[[Image:Coreinfo nvram.png|thumb|right|[[coreinfo]] NVRAM dump.]]

This is a small payload called [[coreinfo]].

mkdir foo
cd foo
wget http://www.coreboot.org/images/0/06/Qemu_coreboot_coreinfo.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_coreinfo.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_coreinfo.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + invaders ===

[[Image:Coreboot invaders.png|thumb|right|[[GRUB invaders]] as payload.]]

mkdir foo
cd foo
wget http://www.coreboot.org/images/c/c8/Qemu_coreboot_invaders.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_invaders.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_invaders.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + libpayload + tint ===

[[Image:Coreboot libpayload tint.png|thumb|right|[[tint]] as payload.]]

This is coreboot v3 (r656), [[libpayload]] (r3225), and tint 0.03b patched to be built against libpayload.

mkdir foo
cd foo
wget http://www.coreboot.org/images/6/62/Qemu_libpayload_tint.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_libpayload_tint.zip
unzip Vgabios-cirrus.zip
mv qemu_libpayload_tint.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + Memtest86 ===

[[Image:Qemu memtest.png|thumb|right|[[Memtest86]] payload.]]

This is coreboot v3 (r656) and [[Memtest86]] (3.4) with serial support enabled. The VGA display in QEMU is broken after a few seconds, this is a known issue, but we don't yet know what exactly the problem is.

mkdir foo
cd foo
wget http://www.coreboot.org/images/3/33/Qemu_coreboot_memtest.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_memtest.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_memtest.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + OpenBIOS ===

[[Image:Qemu coreboot openbios.png|thumb|right|[[OpenBIOS]] payload.]]

This is coreboot v3 (r672) and [[OpenBIOS]] (r186).

mkdir foo
cd foo
wget http://www.coreboot.org/images/9/9d/Qemu_coreboot_openbios.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_openbios.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_openbios.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

== Debugging ==

You can use embedded gdbserver features inside qemu.
For example to start gdbserver on localhost 1234 port you need add "-s" option.
Also it's very useful add "-S" option to stop qemu at the start, so you can run
booting process from gdb

qemu -L . -bios coreboot.rom -nographic -s -S

And then you can use gdb for debugging coreboot:
gdb> target remote localhost:1234
gdb> bt [some_address]
gdb> run
gdb> i r

For improve gdb output you can add this to ~/.gdbinit file:
set history save on
set disassembly-flavor intel
display/4i $pc

Also tracing option available in qemu "-d"
You only need choose trace level: in_asm, exec, cpu, out_asm
And qemu place tracing log at the /tmp/qemu.log

{{PD-self}}

File:Qemu coreboot coreinfo.zip

2012-12-10T10:03:36Z

XVilka: XVilka uploaded a new version of "File:Qemu coreboot coreinfo.zip": Using coreboot latest commit 1224626e3b6eef255b9faac60a18807acebc1f3d

[[QEMU]] BIOS image containing coreboot v3 (r647), [[libpayload]] (r3202), and [[coreinfo]] (r3204).

Coreinfo

2012-12-10T09:24:21Z

XVilka: Fixed subversion commands to be git

'''coreinfo''' is a small informational [[Payloads|payload]] for coreboot. Currently, it can display CPU information, PCI information, coreboot table information, show an NVRAM dump, as well as a RAM dump.

== Screenshots ==

<gallery perrow="5">
Image:Coreinfo cpu.png|CPU info
Image:Coreinfo pci.png|PCI info
Image:Coreinfo coreboot.png|coreboot table
Image:Coreinfo nvram.png|NVRAM dump
Image:Coreinfo ramdump.jpg|RAM dump
</gallery>

== Building coreinfo ==

[[libpayload]] and coreinfo are in the '''payloads/''' directory of the coreboot tree. If you have already checked out the tree, you can skip the svn co steps below.

=== libpayload ===

The coreinfo payload uses [[libpayload]], thus you need to get that first and build it:

$ '''git clone http://review.coreboot.org/p/coreboot'''
$ '''cd coreboot/payloads/libpayload'''
$ '''make menuconfig'''
$ '''make install'''

=== coreinfo ===

You can then get coreinfo itself and build it:

$ '''cd coreboot/payloads/coreinfo'''
$ '''make menuconfig'''
$ '''make'''

The file '''build/coreinfo.elf''' is your final coreinfo payload which you can use with coreboot, either on real hardware or in a [[QEMU]] image.

=== coreboot ===

Finally, you have to build coreboot with coreinfo as payload:

$ '''cp coreboot/payloads/coreinfo/build/coreinfo.elf coreboot/payload.elf'''
$ '''cd coreboot'''
$ '''make menuconfig'''

Now enter the '''Payload''' menu and select '''Payload type''' and then '''An ELF executable payload file'''. Then, exit the menu, save your settings, and build coreboot:

$ '''make'''

The file '''build/coreboot.rom''' is your final coreboot image, which also contains the coreinfo payload.

== Running coreinfo in QEMU ==

For running coreboot+coreinfo image in [[QEMU]], you need

1 Previously described steps (build coreboot image for QEMU)

2 Patched version of '''vgabios-cirrus.bin''' in your '''build''' directory:

$ '''cd build'''
$ '''wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip'''
$ '''unzip Vgabios-cirrus.zip'''
$ '''cd ..'''

You can now run coreinfo in [[QEMU]]:

$ qemu-system-i386 -L build -hda /dev/zero -serial stdio

== Ready-made coreinfo QEMU image ==

If you don't want to build libpayload, coreinfo, and coreboot from source, you can also use the [[QEMU#coreboot_v3_.2B_libpayload_.2B_coreinfo|ready-made coreinfo QEMU image]] by following the instructions on that page.

{{PD-self}}

VGA support

2012-12-04T06:40:28Z

XVilka: fixed formatting

== VGA initialization in coreboot ==

Since coreboot v4 you can configure VGA initialization in Kconfig. For older versions of coreboot check the history of this page.

First do:

<source lang="bash">
$ make menuconfig
</source>

Then go
Chipset --->
[*] Setup bridges on path to VGA adapter
[*] Run VGA option ROMs
Option ROM execution type (Native mode) --->

Alternatively you can choose the "Secure mode" to run the VGA option rom in a contained environment.

If you have no on-board graphics, you are done configuring coreboot at this point. You may exit configuration, and run make to get your VGA enabled coreboot image.

=== On-board Video Devices ===

If you run coreboot on a system with on-board graphics, you have to embed a VGA on the top level, enter the file name of your option rom and the PCI ID of the associated graphics device in the form <vendor_id>,<device_id>:

VGA BIOS --->
[*] Add a VGA BIOS image
(oprom-0.rom) VGA BIOS path and filename
(8086,27a2) VGA device PCI IDs

That's it, exit configuration, and run make to get your VGA enabled coreboot image.

== How to retrieve a good video bios ==

=== RECOMMENDED: Extracting from your vendor bios image ===

The recommended method is to take your mainboard vendor's BIOS image and extract the VGA BIOS using a tool called [[bios_extract]].

$ git clone http://review.coreboot.org/p/bios_extract.git

This is the most reliable way:
* You are guaranteed to get an image that fits to your onboard VGA
* Even if your VGA BIOS uses self-modifying code you get a correct image

Decompress your rom image with:
$ ./bios_extract hdmag217.rom

If bios_decode fails with a message like
Using file "hdmag217.rom" (513kB)
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.
Error: Invalid module signature at 0x80581

then you have to cut the flash chip description off the image. In this case the BIOS image is 512KB, so you do
$ dd if=hdmag217.rom of=hdma.rom bs=512k count=1
1+0 records in
1+0 records out
524288 bytes transferred in 0.000883 secs (593688784 bytes/sec)

You will get an output similar to this:

Using file "hdma.rom" (512kB)
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.
0x715FC ( 27134 bytes) -> romexec_0.rom
0x6E1CB ( 13338 bytes) -> strings_0.rom (29401 bytes)
0x6D65D ( 2899 bytes) -> display_0.rom (4128 bytes)
0x6B62E ( 8208 bytes) -> update_0.rom
0x6B1E3 ( 1072 bytes) -> decompcode_0.rom [0x5000:0xB6D0]
0x6564F ( 23421 bytes) -> oprom_0.rom (36864 bytes)
0x65608 ( 44 bytes) -> tcpa_H_0.rom (32 bytes)
0x65592 ( 91 bytes) -> acpi_1.rom (116 bytes)
0x65519 ( 94 bytes) -> acpi_2.rom (244 bytes)
0x654ED ( 13 bytes) -> tcpa_*_0.rom
0x64D4F ( 1927 bytes) -> bioscode_0.rom (31382 bytes) [0xF000:0x856A]
0x60020 ( 19728 bytes) -> romexec_1.rom
0x570D9 ( 36656 bytes) -> oprom_1.rom (61440 bytes)
0x4DB9D ( 38177 bytes) -> oprom_2.rom (63488 bytes)
0x46493 ( 30447 bytes) -> oprom_3.rom (65536 bytes)
0x41DAB ( 18125 bytes) -> logo_0.rom (310162 bytes)
0x39CA5 ( 25439 bytes) -> oprom_4.rom (51200 bytes)
0x36005 ( 15493 bytes) -> setup_0.rom (37682 bytes)
0x325D7 ( 14867 bytes) -> template_0.rom (37728 bytes)
0x2FA36 ( 11142 bytes) -> miser_0.rom (16208 bytes)
0x2E63C ( 5087 bytes) -> tcpa_Q_0.rom (16096 bytes)
0x2D7C3 ( 3678 bytes) -> acpi_0.rom (10464 bytes)
0x1FA2A ( 41023 bytes) -> bioscode_1.rom (56080 bytes) [0xE000:0x40F0]
0x14FE0 ( 43567 bytes) -> bioscode_2.rom (62416 bytes) [0x6000:0xCC30]
0x0EB4C ( 25721 bytes) -> bioscode_3.rom (36976 bytes) [0x6000:0x3BC0]
0x0D0A0 ( 6801 bytes) -> bioscode_4.rom (31856 bytes) [0x5000:0xBF50]

Now you can check the option roms (oprom_?.rom) with the tool romheaders which is part of the [http://openbios.info/FCode_Suite FCode Suite]:

$ romheaders oprom_0.rom

Image 1:
PCI Expansion ROM Header:
Signature: 0x55aa (Ok)
CPU unique data: 0x48 0xeb 0x7b 0x01 0x76 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Pointer to PCI Data Structure: 0x017c

PCI Data Structure:
Signature: 0x50434952 'PCIR' (Ok)
Vendor ID: 0x1002
Device ID: 0x4752
Vital Product Data: 0x0000
PCI Data Structure Length: 0x0018 (24 bytes)
PCI Data Structure Revision: 0x00
Class Code: 0x030000 (VGA Display controller)
Image Length: 0x0048 blocks (36864 bytes)
Revision Level of Code/Data: 0x0421
Code Type: 0x00 (Intel x86)
Last-Image Flag: 0x80 (last image in rom)
Reserved: 0x0000

Platform specific data for x86 compliant option rom:
Initialization Size: 0x48 (36864 bytes)
Entry point for INIT function: 0x80

Congratulations, that's your option rom (compare PCI IDs and Class Code to find it among the option roms).

=== Downloading ===

There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])

For Intel onboard graphics you can download the vbios(vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver.

=== Extracting from the system (if everything else fails) ===

However you might be able to retrieve your on-board video bios with Linux as well.

* Boot up a machine with a commercial bios (not coreboot) with the video card you wish to work under coreboot.
* You can see where and how much your card's bios is using by doing a
<source lang="bash">cat /proc/iomem | grep 'Video ROM'</source>
* From the command line enter: <source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's bios is cached at 0xc0000, and is 64K long.
 <source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source>
This works for many of the VIA Epia boards. 
Alternatively you can automatically generate it using this nice script from Peter Stuge: 
<source lang="bash">
cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \
dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])
</source>
* You now have a video bios image

VGA support

2012-12-04T06:37:11Z

XVilka: Added link for bios_extract page

== VGA initialization in coreboot ==

Since coreboot v4 you can configure VGA initialization in Kconfig. For older versions of coreboot check the history of this page.

First do:

<source lang="bash">
$ make menuconfig
</source>

Then go
Chipset --->
[*] Setup bridges on path to VGA adapter
[*] Run VGA option ROMs
Option ROM execution type (Native mode) --->

Alternatively you can choose the "Secure mode" to run the VGA option rom in a contained environment.

If you have no on-board graphics, you are done configuring coreboot at this point. You may exit configuration, and run make to get your VGA enabled coreboot image.

=== On-board Video Devices ===

If you run coreboot on a system with on-board graphics, you have to embed a VGA on the top level, enter the file name of your option rom and the PCI ID of the associated graphics device in the form <vendor_id>,<device_id>:

VGA BIOS --->
[*] Add a VGA BIOS image
(oprom-0.rom) VGA BIOS path and filename
(8086,27a2) VGA device PCI IDs

That's it, exit configuration, and run make to get your VGA enabled coreboot image.

== How to retrieve a good video bios ==

=== RECOMMENDED: Extracting from your vendor bios image ===

The recommended method is to take your mainboard vendor's BIOS image and extract the VGA BIOS using a tool called [[bios_extract]].

$ git clone http://review.coreboot.org/p/bios_extract.git

This is the most reliable way:
* You are guaranteed to get an image that fits to your onboard VGA
* Even if your VGA BIOS uses self-modifying code you get a correct image

Decompress your rom image with:
<script lang="bash">
$ ./bios_extract hdmag217.rom
</script>

If bios_decode fails with a message like
Using file "hdmag217.rom" (513kB)
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.
Error: Invalid module signature at 0x80581

then you have to cut the flash chip description off the image. In this case the BIOS image is 512KB, so you do
$ dd if=hdmag217.rom of=hdma.rom bs=512k count=1
1+0 records in
1+0 records out
524288 bytes transferred in 0.000883 secs (593688784 bytes/sec)

You will get an output similar to this:

Using file "hdma.rom" (512kB)
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.
0x715FC ( 27134 bytes) -> romexec_0.rom
0x6E1CB ( 13338 bytes) -> strings_0.rom (29401 bytes)
0x6D65D ( 2899 bytes) -> display_0.rom (4128 bytes)
0x6B62E ( 8208 bytes) -> update_0.rom
0x6B1E3 ( 1072 bytes) -> decompcode_0.rom [0x5000:0xB6D0]
0x6564F ( 23421 bytes) -> oprom_0.rom (36864 bytes)
0x65608 ( 44 bytes) -> tcpa_H_0.rom (32 bytes)
0x65592 ( 91 bytes) -> acpi_1.rom (116 bytes)
0x65519 ( 94 bytes) -> acpi_2.rom (244 bytes)
0x654ED ( 13 bytes) -> tcpa_*_0.rom
0x64D4F ( 1927 bytes) -> bioscode_0.rom (31382 bytes) [0xF000:0x856A]
0x60020 ( 19728 bytes) -> romexec_1.rom
0x570D9 ( 36656 bytes) -> oprom_1.rom (61440 bytes)
0x4DB9D ( 38177 bytes) -> oprom_2.rom (63488 bytes)
0x46493 ( 30447 bytes) -> oprom_3.rom (65536 bytes)
0x41DAB ( 18125 bytes) -> logo_0.rom (310162 bytes)
0x39CA5 ( 25439 bytes) -> oprom_4.rom (51200 bytes)
0x36005 ( 15493 bytes) -> setup_0.rom (37682 bytes)
0x325D7 ( 14867 bytes) -> template_0.rom (37728 bytes)
0x2FA36 ( 11142 bytes) -> miser_0.rom (16208 bytes)
0x2E63C ( 5087 bytes) -> tcpa_Q_0.rom (16096 bytes)
0x2D7C3 ( 3678 bytes) -> acpi_0.rom (10464 bytes)
0x1FA2A ( 41023 bytes) -> bioscode_1.rom (56080 bytes) [0xE000:0x40F0]
0x14FE0 ( 43567 bytes) -> bioscode_2.rom (62416 bytes) [0x6000:0xCC30]
0x0EB4C ( 25721 bytes) -> bioscode_3.rom (36976 bytes) [0x6000:0x3BC0]
0x0D0A0 ( 6801 bytes) -> bioscode_4.rom (31856 bytes) [0x5000:0xBF50]

Now you can check the option roms (oprom_?.rom) with the tool romheaders which is part of the [http://openbios.info/FCode_Suite FCode Suite]:

$ romheaders oprom_0.rom

Image 1:
PCI Expansion ROM Header:
Signature: 0x55aa (Ok)
CPU unique data: 0x48 0xeb 0x7b 0x01 0x76 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Pointer to PCI Data Structure: 0x017c

PCI Data Structure:
Signature: 0x50434952 'PCIR' (Ok)
Vendor ID: 0x1002
Device ID: 0x4752
Vital Product Data: 0x0000
PCI Data Structure Length: 0x0018 (24 bytes)
PCI Data Structure Revision: 0x00
Class Code: 0x030000 (VGA Display controller)
Image Length: 0x0048 blocks (36864 bytes)
Revision Level of Code/Data: 0x0421
Code Type: 0x00 (Intel x86)
Last-Image Flag: 0x80 (last image in rom)
Reserved: 0x0000

Platform specific data for x86 compliant option rom:
Initialization Size: 0x48 (36864 bytes)
Entry point for INIT function: 0x80

Congratulations, that's your option rom (compare PCI IDs and Class Code to find it among the option roms).

=== Downloading ===

There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])

For Intel onboard graphics you can download the vbios(vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver.

=== Extracting from the system (if everything else fails) ===

However you might be able to retrieve your on-board video bios with Linux as well.

* Boot up a machine with a commercial bios (not coreboot) with the video card you wish to work under coreboot.
* You can see where and how much your card's bios is using by doing a
<source lang="bash">cat /proc/iomem | grep 'Video ROM'</source>
* From the command line enter: <source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's bios is cached at 0xc0000, and is 64K long.
 <source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source>
This works for many of the VIA Epia boards. 
Alternatively you can automatically generate it using this nice script from Peter Stuge: 
<source lang="bash">
cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \
dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])
</source>
* You now have a video bios image

Bios extract

2012-12-04T06:35:36Z

XVilka: Added page for bios_extract utility

Infrastructure Projects

2012-09-26T08:40:53Z

XVilka: /* Geode issues */

This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.

= In progress =

== Low/High Tables ==

SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.

'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor/chipset
! align="left" | Tested
! align="left" | Comments

|- bgcolor="#eeeeee"
| amd/amdfam10
| ?
| —
|- bgcolor="#eeeeee"
| amd/amdht
| ?
| —
|- bgcolor="#eeeeee"
| amd/amdk8
| ?
| —
|- bgcolor="#eeeeee"
| amd/amdmct
| ?
| —
|- bgcolor="#eeeeee"
| amd/gx1
| ?
| —
|- bgcolor="#eeeeee"
| amd/gx2
| ?
| —
|- bgcolor="#eeeeee"
| amd/lx
| ?
| —
|- bgcolor="#eeeeee"
| intel/e7501
| ?
| —
|- bgcolor="#eeeeee"
| intel/e7520
| ?
| —
|- bgcolor="#eeeeee"
| intel/e7525
| ?
| —
|- bgcolor="#eeeeee"
| intel/i3100
| ?
| —
|- bgcolor="#eeeeee"
| intel/i440bx
| ?
| —
|- bgcolor="#eeeeee"
| intel/i82810
| ?
| —
|- bgcolor="#eeeeee"
| intel/i82830
| ?
| —
|- bgcolor="#eeeeee"
| intel/i855
| ?
| —
|- bgcolor="#eeeeee"
| intel/i945
| style="background:lime" | Y
| Tested on Kontron 986LCD-M and Roda RK886EX
|- bgcolor="#eeeeee"
| via/cn400
| ?
| —
|- bgcolor="#eeeeee"
| via/cn700
| style="background:lime" | Y
| Tested on VIA pc2500e.
|- bgcolor="#eeeeee"
| via/cx700
| ?
| —
|- bgcolor="#eeeeee"
| via/vt8601
| ?
| —
|- bgcolor="#eeeeee"
| via/vt8623
| ?
| —
|- bgcolor="#eeeeee"
| via/vx800
| ?
| —

|}

'''Developers:''' Stefan

== CBFS ==

A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).

'''Status:'''

Upstream, pre-CBFS infrastructure removed.

There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.

Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.

All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor/chipset
! align="left" | ROM enabled
! align="left" | Tiny bootblock
! align="left" | Status / Comments

|- bgcolor="#eeeeee"
| amd/amd8111
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.
|- bgcolor="#eeeeee"
| amd/cs5530
| style="background:lime" | Y
| style="background:red" | N
| Not tested on hardware, yet.
|- bgcolor="#eeeeee"
| amd/cs5535
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| amd/cs5536
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| amd/sb600
| style="background:lime" | Y
| style="background:lime" | Y
| Build- and runtime-tested on siemens/sitemp_g1p1 by [[User:PatrickGeorgi|PatrickGeorgi]].
|- bgcolor="#eeeeee"
| amd/sb700
| style="background:yellow" | Y
| style="background:yellow" | Y
| —

|- bgcolor="#dddddd"
| broadcom/bcm5785
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.

|- bgcolor="#eeeeee"
| intel/esb6300
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i3100
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82371eb
| style="background:lime" | Y
| style="background:yellow" | Y
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]].
|- bgcolor="#eeeeee"
| intel/i82801ax
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801bx
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801cx
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801dx
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801ex
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801gx
| style="background:lime" | Y
| style="background:lime" | Y
| Build- and runtime-tested on Kontron 986LCD-m by PatrickGeorgi

|- bgcolor="#dddddd"
| nvidia/ck804
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.
|- bgcolor="#dddddd"
| nvidia/mcp55
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.

|- bgcolor="#dddddd"
| sis/sis966
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.

|- bgcolor="#eeeeee"
| via/vt8231
| style="background:yellow" | Y
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| via/vt8235
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| via/vt8237r
| style="background:yellow" | Y
| style="background:yellow" | Y
| —
|- bgcolor="#eeeeee"
| via/vt82c686
| style="background:red" | N
| style="background:red" | N
| —

|}

'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe

== Tiny Bootblock ==

Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).

'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).

'''Developers:''' Patrick

== Remove .c includes ==

Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.

'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately.

'''Developers:''' Patrick, Uwe

== Move configuration to Kconfig ==

Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig. <code>util/lint/lint-001-no-global-config-in-romstage</code> helps figuring out what remains to be done.

'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage. AMD/AGESA Boards have platform_cfg.h for which a solution should be found.

'''Developers:''' Patrick, Uwe

== Unify ACPI ==
* Figure out generic ACPI code and deduplicate it.
* Fix issues like http://www.coreboot.org/pipermail/coreboot/2011-May/065179.html

Done:
* Every ACPI board has its own routines to compile the ACPI sources. Unify that.

= More ideas =

== CMOS handling ==

The subprojects are ordered in a way that minimizes lost work.

=== Simplify get_option ===
Replace <code>get_option(VALstart, VALlen, default)</code> with a macro that hides start/len in something like <code>get_option(VAL, default)</code>

=== Implement a new cmos.layout format ===
The current layout is simple to parse, but not so simple to maintain or extend.
Create a format that combines the various fields into a single representation, eg.

<code>
400/8 century enum { 0x19="1900", 0x20="2000", 0x21="2100" }

408/512 some_string string

984/16 checksum checksum 392 983
</code>

=== Implement an include statement ===
That way, we can have global fields (RTC, century byte), per chipset component fields (defined by northbrigde/southbridge/superio), per mainboard fields at their appropriate places.

=== CMOS defaults ===
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.
In the above format, it could simply be a suffix <code>default=VALUE</code>
Also drop the "default" argument in get_options. As components have their own cmos.layout snippets, we can always take those definitions' defaults, even if mainboards don't make use of CMOS themselves.

=== Value overrides ===
A chipset might provide options (eg. SATA/IDE) that a board might override (eg. because it doesn't provide IDE even if the chipset would support it). Allow the mainboard to override config options. This wouldn't just set a new default, but drop the option from CMOS entirely, hardcoding the value in the build. Some autogenerated #ifdef/#define magic might help there.

=== Provide update paths and avoid conflicts in addressing ===
Research topic: How could updates to nvram configuration (eg. new fields) be handled safely, and how could we get away from carving out the CMOS memory space manually? (one proposal: http://article.gmane.org/gmane.linux.bios/64572)

Simple solution: Add smarts to flashrom: When running from coreboot, it has current cmos.layout and the table, as well as the new cmos.layout (and the new defaults). Take new defaults, fill up with current settings, and write the result to CMOS. This provides automatic values for new configuration options.

=== Checksums ===

The Linux kernel driver expects a non-inverted CMOS checksum for the "PC" area. coreboot inverts this checksum, which makes nvram unusable for the driver. This should be fixed.

== Unify UMA / onboard video code and config ==

Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.

== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==

Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.

* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.

== Kconfig TODO ==

Notes / Style guide:

* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.
* Use '''bool''' instead of '''boolean'''.
* Use '''default n''' instead of '''default false'''.

Various post-conversion things to consider:

* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)
** ...

Stuff to port from v3 to v4:

* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).
* Some remaining useful Kconfig options.

== USB Debug Console ==

Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.

== Clean up Assembler / Linker mess ==

* Drop / combine / normalize .ld/.lb/.lds linker scripts.
* Move them to a common place.
* Drop / combine / normalize .inc / .S files.

== Geode issues ==

* Fix / Unify vsmsetup.c.
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.
* Convert openvsa from MASM to something gnu as can use ( Or use JWasm as intermediate solution (it can compile MASM code) http://www.japheth.de/JWasm.html )

== Stack and Suspend/Resume ==

* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.

== Fix Suspend/Resume on AMD64 ==

* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.

== printk into buffer ==

Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).

Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).

== Global variables ==

* Port the global variables framework from v3.
* Make use of it where appropriate.

== Clear phases in romstage ==

* Split up the code (esp. in romstage) into more sensibly separated phases.
* Maybe use v3 for inspiration where the lines can be drawn.

== Refactor SMBUS code ==

We have tons of duplication in the smbus/spd related functions and #defines. Every chipset (and sometimes board) does the same with the exception of the 2 or 3 boards that multiplex spd roms.
* Deduplicate SMBUS related defines, they're virtually everywhere (and all the same)
* Deduplicate the lowlevel functions - they should really be the same (except for some style differences)
* Deduplicate the non-multiplexing highlevel functions. Mark them weak, so multiplexing boards can simply provide their own variant, which override the weak functions automatically

== Move all registers/chip definitions in XML format for all tools ==

For easy creating definitions of new chips, or editing old register definitions, improve readability support, and add support for humanless parsing the logs we decide move all data for msrtool, inteltool, superiotool, etc in XML-based format. See here: [[XML]]

== Device dependency engine ==

We have a couple of places where we want to disable (or otherwise reconfigure) a device if another one is active: SATA and IDE covering the same ports, integrated graphics / plugin video cards, ...
Right now, such things are done "somewhere", usually far away from any meaningful context. This idea isn't as actionable as the others as it's still missing even a sketch of a design.

* Find a good place (or multiple places) where such device decisions can be made
* Refactor the code to make use of it

== Clean out duplicates ==

Tools like http://duplo.giants.ch/ or http://pmd.sourceforge.net/cpd.html might be able to help finding duplicates that can be factored out.

== CONFIG_MAX_PHYSICAL_CPUS ==

CONFIG_MAX_PHYSICAL_CPUS should be dropped. It's set for all boards, but it's only really used by AMD K8 and newer systems (and not on Intel based systems at all).
In the AMD code it is used wrongly:

* for determining which SPD offsets to include
* to determine APIC IDs
* possibly some more things

= Finished =

== Port v3 Resource Allocator ==

The v3 resource allocator should be ported to v4.

'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.

'''Developers:''' Myles

== Config & Build System ==

The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.

'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!

'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi

== Unify text printing functions ==

There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).

'''Status:''' Finished.

'''Developers:''' Patrick, Stefan

== Common payload location ==

Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".

'''Status:''' Finished.

== Fix ALL build warnings ==

* Someone has to do the deed.

'''Status:''' Finished, the build usually issues no warnings. If you see warnings/errors, please report a bug.

== Post codes ==

Find all outb(x, 0x80) and replace them with post_code(). Use common numbers / defines across the boards.

'''Status:''' Finished, except for some local delay routines in early smbus code.

== Use central oprom init ==

* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.
* Use the realmode code for vsmsetup too.

== Use nvramtool for static option table creation ==

Instead of maintaining two tools (build_opt_tbl, nvramtool), maintain only one. This mostly requires adding an binary output writer to nvramtool, a cmos.layout parser already exists.

'''Status:''' Finished, upstream.

'''Developers:''' Vikram

== Local APIC addresses ==

There are several defines in several places that describe the local APIC address:

* LAPIC_ADDR
* LOCAL_APIC_ADDR (even twice)
* LAPIC_DEFAULT_BASE

This should be unified.

'''Developers:''' Patrick

VGA support

2012-09-24T08:45:37Z

XVilka: Fixed bios_extract link

== VGA initialization in coreboot ==

Since coreboot v4 you can configure VGA initialization in Kconfig. For older versions of coreboot check the history of this page.

First do:

<source lang="bash">
$ make menuconfig
</source>

Then go
Chipset --->
[*] Setup bridges on path to VGA adapter
[*] Run VGA option ROMs
Option ROM execution type (Native mode) --->

Alternatively you can choose the "Secure mode" to run the VGA option rom in a contained environment.

If you have no on-board graphics, you are done configuring coreboot at this point. You may exit configuration, and run make to get your VGA enabled coreboot image.

=== On-board Video Devices ===

If you run coreboot on a system with on-board graphics, you have to embed a VGA on the top level, enter the file name of your option rom and the PCI ID of the associated graphics device in the form <vendor_id>,<device_id>:

VGA BIOS --->
[*] Add a VGA BIOS image
(oprom-0.rom) VGA BIOS path and filename
(8086,27a2) VGA device PCI IDs

That's it, exit configuration, and run make to get your VGA enabled coreboot image.

== How to retrieve a good video bios ==

=== RECOMMENDED: Extracting from your vendor bios image ===

The recommended method is to take your mainboard vendor's BIOS image and extract the VGA BIOS using a tool called [http://review.coreboot.org/gitweb?p=bios_extract.git;a=summary bios_extract].

$ git clone http://review.coreboot.org/p/bios_extract.git

This is the most reliable way:
* You are guaranteed to get an image that fits to your onboard VGA
* Even if your VGA BIOS uses self-modifying code you get a correct image

Decompress your rom image with:
<script lang="bash">
$ ./bios_extract hdmag217.rom
</script>

If bios_decode fails with a message like
Using file "hdmag217.rom" (513kB)
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.
Error: Invalid module signature at 0x80581

then you have to cut the flash chip description off the image. In this case the BIOS image is 512KB, so you do
$ dd if=hdmag217.rom of=hdma.rom bs=512k count=1
1+0 records in
1+0 records out
524288 bytes transferred in 0.000883 secs (593688784 bytes/sec)

You will get an output similar to this:

Using file "hdma.rom" (512kB)
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.
0x715FC ( 27134 bytes) -> romexec_0.rom
0x6E1CB ( 13338 bytes) -> strings_0.rom (29401 bytes)
0x6D65D ( 2899 bytes) -> display_0.rom (4128 bytes)
0x6B62E ( 8208 bytes) -> update_0.rom
0x6B1E3 ( 1072 bytes) -> decompcode_0.rom [0x5000:0xB6D0]
0x6564F ( 23421 bytes) -> oprom_0.rom (36864 bytes)
0x65608 ( 44 bytes) -> tcpa_H_0.rom (32 bytes)
0x65592 ( 91 bytes) -> acpi_1.rom (116 bytes)
0x65519 ( 94 bytes) -> acpi_2.rom (244 bytes)
0x654ED ( 13 bytes) -> tcpa_*_0.rom
0x64D4F ( 1927 bytes) -> bioscode_0.rom (31382 bytes) [0xF000:0x856A]
0x60020 ( 19728 bytes) -> romexec_1.rom
0x570D9 ( 36656 bytes) -> oprom_1.rom (61440 bytes)
0x4DB9D ( 38177 bytes) -> oprom_2.rom (63488 bytes)
0x46493 ( 30447 bytes) -> oprom_3.rom (65536 bytes)
0x41DAB ( 18125 bytes) -> logo_0.rom (310162 bytes)
0x39CA5 ( 25439 bytes) -> oprom_4.rom (51200 bytes)
0x36005 ( 15493 bytes) -> setup_0.rom (37682 bytes)
0x325D7 ( 14867 bytes) -> template_0.rom (37728 bytes)
0x2FA36 ( 11142 bytes) -> miser_0.rom (16208 bytes)
0x2E63C ( 5087 bytes) -> tcpa_Q_0.rom (16096 bytes)
0x2D7C3 ( 3678 bytes) -> acpi_0.rom (10464 bytes)
0x1FA2A ( 41023 bytes) -> bioscode_1.rom (56080 bytes) [0xE000:0x40F0]
0x14FE0 ( 43567 bytes) -> bioscode_2.rom (62416 bytes) [0x6000:0xCC30]
0x0EB4C ( 25721 bytes) -> bioscode_3.rom (36976 bytes) [0x6000:0x3BC0]
0x0D0A0 ( 6801 bytes) -> bioscode_4.rom (31856 bytes) [0x5000:0xBF50]

Now you can check the option roms (oprom_?.rom) with the tool romheaders which is part of the [http://openbios.info/FCode_Suite FCode Suite]:

$ romheaders oprom_0.rom

Image 1:
PCI Expansion ROM Header:
Signature: 0x55aa (Ok)
CPU unique data: 0x48 0xeb 0x7b 0x01 0x76 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Pointer to PCI Data Structure: 0x017c

PCI Data Structure:
Signature: 0x50434952 'PCIR' (Ok)
Vendor ID: 0x1002
Device ID: 0x4752
Vital Product Data: 0x0000
PCI Data Structure Length: 0x0018 (24 bytes)
PCI Data Structure Revision: 0x00
Class Code: 0x030000 (VGA Display controller)
Image Length: 0x0048 blocks (36864 bytes)
Revision Level of Code/Data: 0x0421
Code Type: 0x00 (Intel x86)
Last-Image Flag: 0x80 (last image in rom)
Reserved: 0x0000

Platform specific data for x86 compliant option rom:
Initialization Size: 0x48 (36864 bytes)
Entry point for INIT function: 0x80

Congratulations, that's your option rom (compare PCI IDs and Class Code to find it among the option roms).

=== Downloading ===

There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])

For Intel onboard graphics you can download the vbios(vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver.

=== Extracting from the system (if everything else fails) ===

However you might be able to retrieve your on-board video bios with Linux as well.

* Boot up a machine with a commercial bios (not coreboot) with the video card you wish to work under coreboot.
* You can see where and how much your card's bios is using by doing a
<source lang="bash">cat /proc/iomem | grep 'Video ROM'</source>
* From the command line enter: <source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's bios is cached at 0xc0000, and is 64K long.
 <source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source>
This works for many of the VIA Epia boards. 
Alternatively you can automatically generate it using this nice script from Peter Stuge: 
<source lang="bash">
cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \
dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])
</source>
* You now have a video bios image

Laptop

2012-09-24T08:12:06Z

XVilka: Fixed tools links

== Laptops with coreboot Support ==

* coreboot supports the [http://en.getac.com/products/P470/P470_overview.html Getac P470] semi rugged notebook, based on Intel 82945GM/ICH7.
* coreboot supports the [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda RK886EX (Rocky III+)] laptop, based on Intel 82945GM/ICH7.
* coreboot supports one variant of the Lenovo [[Thinkpad X60s]].

== Embedded controllers ==

The remaining issue with supporting netbooks may be open firmware support for the [[Embedded controller]] (EC).
These ECs used to support keyboard scan, lid open/closed, battery charging, power management, etc.

coreboot should work with the "stock" EC firmware. This may still be a challenge because "we don't know what we don't know". Behavior at runtime is fairly standardized, but we don't know what we need to do for initialization - do we need to set up registers, put in tables, kick things, or will it all Just Work (TM)?

== HOWTO to find a way ==

* find a model and manufacturer of your laptop
* download these tools:
# git clone http://review.coreboot.org/p/coreboot
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )
# msrtool ( cd coreboot/util/msrtool ; make ; sudo make install )
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )
* make and install them (make; sudo make install) - you need at least libpci/pciutils
* check that your distro have this tools and install them:
# lspci
# dmesg
# acpitool
# lspnp
# lsusb
* Do this commands:
# lspci -nnvvvxxxx > lscpi.log
# lspnp -vv > lspnp.log
# lsusb -vvv > lsusb.log
# superiotool -deV > superiotool.log
# inteltool -a > inteltool.log
# ectool > ectool.log
# msrtool > msrtool.log
# dmidecode > dmidecode.log
# biosdecode > biosdecode.log
# nvramtool -x > nvramtool.log
# dmesg > dmesg.log
# flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log
# flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log
* Save all logs in safe place, and also rom.bin file.
* try to find information - what EC or Super I/O chip is used in your laptop (may be some info in Service Manuals or Disassembly guides)
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support
* if you see that ectool return looks like 'right' output - you have a big chances for support
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop
* try to find your Super I/O / EC chip datasheet

== Laptop survey ==

This not a list of coreboot supported laptops. This page only lists the chipsets, Super I/Os, flash chips, and especially [[embedded controller]]s used in a few laptops, just for reference purposes.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Model
! align="left" | CPU
! align="left" | Chipset NB
! align="left" | Chipset SB
! align="left" | Super I/O
! align="left" | [[Embedded controller|EC]]
! align="left" | Flash Chip
! align="left" | Flash Size
! align="left" | Flash S.
! align="left" | Flash T.
! align="left" | Owner

|- bgcolor="#dddddd"
| ASUS || S96F/Z96F || Intel Core™2 Duo T7400 || Intel i945 || Intel ICH7 || ITE IT8510E || in Super I/O || ? || ? || ? || ? || [http://www.flashrom.org/pipermail/flashrom/2010-January/001986.html macavity]
|- bgcolor="#eeeeee"
| Acer || Aspire One ZG5 || Intel Atom N270 1.6GHz || Intel 82945GME || Intel NH82801GBM ICH7-M || Winbond WPCE775LA0DG || in Super I/O || Winbond 25x80AVSIG || 8Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Acer || Aspire 3613LC || Intel Celeron M 370 1.5GHz L2: 1MB || Intel 82910GML || Intel FW82801FBM SL7W6 ICH6-M || ? || ? || PMC 0537 PM39LV040-70JCE || 1Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#eeeeee"
| Dell || [[Dell Latitude CPi A366XT|Latitude CPi A366XT]] || PII, 360 MHz || Intel 440BX |||| SMSC FDC37N958FR || in Super I/O || AMD AM29F040B || 512KB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Dell || [[Dell Latitude C610|Latitude C610]] || PIII, 1.2 GHz || Intel i830 |||| SMSC LPC47N252 || in Super I/O || SST SST49LF004A || 512KB || no || PLCC || [mailto:coreboot@miradou.com CybFr]
|- bgcolor="#eeeeee"
| Dell || [[Dell Vostro V13]] || Intel Celeron 743 1.2GHz, L2: 1MB (Ultra Low Voltage) || Mobile Intel GS45 Express GHMC ||Intel 82801IEM ICH9M-E|| none || ITE IT8502E || Winbond 25Q16BVSIG || 2Mb || no || SOIP/PDIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Dell || XPS M1530 || Intel Core™2 Duo T7700 || Intel PM965 || Intel ICH8 || none || Winbond WPC8763L || Winbond 25X16VSIG || 16Mb || ?? || SPI || Corey Osgood
|- bgcolor="#eeeeee"
| Fujitsu-S. || Lifebook S-4572 || PIII, 750 MHz || Intel 82440MX |||| SMSC FDC37N769 || ? || Fujitsu MBM29F400T1 || ? || no || TSOP(?) || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Fujitsu-S. || Lifebook S7110 || Intel Core™2 Duo T7200 || Intel i945 || Intel ICH7 || SMSC LPC47N217 || Fujitsu MB90378 || Spansion S25FL008A2 || 1024 kB || no || SO8 / SPI || twice11
|- bgcolor="#eeeeee"
| Gateway || [[Gateway W730-K8X | W730-K8X]] || Socket 754 |||| ?? || ?? || ?? || SST 39VF040 || ?? || yes || PLCC || [[User:Juri|Juri]]
|- bgcolor="#dddddd"
| Gateway || [[Gateway 6020GZ|6020GZ]] || Celeron M 1.4Ghz || Intel 855GME |||| ?? || ?? || ?? || ?? || no || ?? || [[User:Juri|Juri]]
|- bgcolor="#eeeeee"
| Gericom || Webboy 340S2 || PIII || SiS630 |||| NSC PC87393VJG || NSC PC87570 || Winbond 29C020 || 256 kB || yes || PLCC || [http://thread.gmane.org/gmane.linux.bios/13081 NS]
|- bgcolor="#dddddd"
| Getac || P470 || Intel® Core 2 Duo Mobile || Intel 945 || Intel ICH7 || ? || ? || ? || 8Mb || no || SPI / SOIC8 || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#eeeeee"
| Highscreen || XD 14-C1700 || Intel Celeron 1.7 GHz || SiS650 |||| NSC PC87391(?) || ? || EON EN29F040(A) || 512 kB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| HP || Omnibook XE3(L) || PIII, 750 MHz || Intel 82371MB ||Intel PIIX4M || SMSC FDC37N869 || NSC PC87570 || SST 28SF040A || 512 kB || no || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| IBM || Thinkpad T30 || Intel P4 Mobile, 1.8 GHz || Intel i845 || Intel ICH3-M || NSC PC87392 || Renesas H8S 64F3169ATE10 || ST M50FW080N5 || 1024 kB || no || TSOP40 / FWH || edgecase
|- bgcolor="#dddddd"
| IBM || Thinkpad X60s || Intel Core Duo CPU L2300 || Intel i945GM || Intel ICH7-M || NSC PC87392 (in Ultrabase) || Renesas H8S2161B || MX25L1605D || 2048 kB || no || SOIC-8 || [[User:SvenS|Sven Schnelle]]
|- bgcolor="#dddddd"
| MSI || Wind U100 || Intel Atom N280 1.66Ghz || Intel 945GSE || Intel ICH7-M || ? || ENE KB3310 || SST MX25L8005 || 8 Mb|| no || TSOP40 / SPI || ?
|- bgcolor="#eeeeee"
| One || [http://www.a110wiki.de A110] || VIA C7-M ULV 1.0 GHz || VIA VX800 |||| none || ENE KB3310 || ? || ? || no || ? || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Panasonic || Toughbook CF-25 || P166MMX || FW82439TX (430TX) || FW82371AB || NSC PC87336VJG || Renesas 3886 || SST SST29EE020 || 256 kB || no || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Roda || Rocky III+ RK886EX || Intel® Core 2 Duo Mobile T5500 || Intel 945 || Intel ICH7 || SMSC® LPC47N227 || Renesas M38859 || SST SST49LF080 || 8Mb || yes || PLCC || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#dddddd"
| Roda || Rocky II+ RT686 || Intel Pentium III || Intel 430BX || Intel FW82371EB || SMSC® FDC37N769 || Renesas M38867M8A || SST SST29LE020 || 256KB || yes || PLCC/parallel || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| Sony || Vaio Picturebook PCG-C1XD || P2 400 || 443ZX |||| ? || ? || ST M29W004BT || 512 kB || no || || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Sony || Vaio Picturebook PCG-C1X || P266MMX || 430TX |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Toshiba || Libretto 50M PA1243CM || P133 || custom FPGA |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Toshiba || Satellite A80-117 || Intel Celeron || Intel 915GM || Intel ICH6 || SMSC LPC47N217 || ENE KB910 || ? || 1024 kB || no || TSOP (?) || [[User:Uwe|UH]]

|}


1 According to the vendor BIOS update tool. 
2 Nice thing: EC/Flash is not shared, so you can erase the whole flash during system operation (this was tested). 


Further links:

* [http://tuxmobil.org/mylaptops.html Tuxmobil Laptop Survey]
* [http://mcelrath.org/laptops.html Laptops/Notebooks with Linux Preinstalled]
* [http://www.fsf.org/campaigns/free-bios.html The Free Software Foundation's Campaign for Free BIOS]

== Mailinglist discussion ==

A few earlier coreboot discussions on laptops are linked here, you might get useful information out of them:

* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010985.html Any update on coreboot for laptops]
* [http://comments.gmane.org/gmane.linux.bios/13081 Notebook 340s2 (sis630) 256k Flash]
* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010972.html yet another reason to use coreboot in laptops I guess]
* [http://www.coreboot.org/pipermail/linuxbios/2005-April/011429.html coreboot laptop hunt wiki page]
* [http://www.coreboot.org/pipermail/linuxbios/2005-March/011140.html HP Pavillion ZV5000 (Laptop)]
* [http://www.coreboot.org/pipermail/linuxbios/2005-July/011942.html SA1100]
* [http://www.coreboot.org/pipermail/linuxbios/2003-September/004954.html Laptop with Sis 650 chipset]
* [http://www.coreboot.org/pipermail/linuxbios/2006-September/015551.html coreboot on Laptops]

== Who really makes your laptop? ==

There are several various brands of laptops, but there are only a few actual laptop makers.

Name brand companies like Hewlet Packard, Compaq, IBM, Dell, Gateway, Sony, Micron, Toshiba and others; including Alienware and Voodoo do not make their own laptops. The exceptions are Asus and Apple, and even Apple doesn't make all of their laptops.

Original Design Manufacturers (ODM) make the laptops for Original Equipment Manufacturers (OEM). They in turn, add their preloaded hard drives and sell them to consumers. This is why a laptop is a bit more complicated to support with coreboot. The OEM's may not even have all the specifications for the laptop since the ODM has done all the design and assembly.

Some laptop ODMs are:

* [http://www.quantatw.com Quanta] makes laptops for Sony, Dell, and IBM
* [http://www.inventec.com/ Inventec] and [http://www.arima.com.tw/ Arima] make the Compaq line
* [http://www.compal.com/ Compal] also makes IBM and Dell lines, as well as Hewlett Packard
* [http://www.clevo.com.tw/ Clevo] makes the popular Alienware and Voodoo gaming laptops

Further links:

* [http://www.laptopworldwide.com/laptops.html Makers of Laptops]
* [http://tuxmobil.org/laptop_oem.html Laptop and NoteBook Manufacturer - OEM/ODM Relation Matrix]
* [http://tuxmobil.org/reseller.html Where to Buy a Preinstalled Linux Laptop, Notebook, Mobile Phone or PDA? - Vendor Overview]

== Random product links ==

The following list is a out of date. These were laptops of interest as possible candidates for coreboot support. Most, if not all of these laptops are no longer available. It is only here for reference.

VIA has a list of many netbooks at [http://via.com.tw/en/products/notebook/notebook.jsp VIA Partner Mobility Devices].

VIA also has information on other mobile platforms at [http://via.com.tw/en/products/notebook/index.jsp VIA Mobility Platform].

The [http://www.a110wiki.de Quanta IL1] vx800 based reference design covers similar models/clones such as:

*[http://www.one.de/shop/one-notebooks-one-mini-notebooks-c-213_214.html One Mini A110/A115/A120/A140/A150/A470]
*[http://preview.tinyurl.com/5zbzl6 Airis Kira 100/350/740]
*[http://www.norhtec.com/products/gecko/index.html Norhtec Gecko]
*[http://www.pioneercomputers.com.au/products/configure.asp?c1=3&c2=12&id=2458 Pioneer DreamBook Light IL1]
*[http://www.ctlcorp.com/v4/p-697-ctl-il1a-89-netbook-with-windows-xp-home.aspx CTL IL1] More [http://www.a110wiki.de/wiki/CTL_IL1 CTL IL1 info] with tear-down pics.
*[http://www.aci-asia.com/html/Ethos_7.html ACi Ethos 7]
*[http://www.ilikeblue.net/products/umpc.htm BDSI Deep Blue H1]

Other vx800 based netbooks:

*[http://www.everex.com/products/cloudbook_max/cloudbook_max.htm Everex CloudBook MAX]
*[http://www.fic.com.tw/product/ce2a1.aspx FIC CE2A1]

Netbook designs that use the VIA vx700 chipset:

*[http://www.sylvaniacomputers.com/products.php?p=g Sylvania G]
*[http://www.everex.com/products/cloudbook/cloudbook.htm Everex Cloudbook]
*[http://www.fic.com.tw/product/ce260.aspx FIC CE260]
*[http://www.fic.com.tw/product/ce268.aspx FIC CE268]

AMD 690/600 laptops:

*[http://reviews.cnet.com/laptops/acer-extensa-4420-5963/4505-3121_7-33361062.html Acer Extensa 4420]
*[http://www.raondigital.com EVERUN NOTE]

Intel Atom with i945 chipset netbooks:

*[http://en.wikipedia.org/wiki/Aspire_One Acer Aspire One]
*[http://en.wikipedia.org/wiki/MSI_Wind_PC MSI Wind]
*[http://en.wikipedia.org/wiki/ASUS_Eee_PC ASUS eeePC]

EHCI Debug Port

2012-09-23T20:42:22Z

XVilka: Fixed lspci command

[[Image:PLX_NET20DC.jpg|thumb|right|Ajays NET20DC USB Debug Device.]]

Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.

The '''EHCI Debug Port''' is an optional capability of EHCI controllers which can be used for that purpose.

All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.

While the '''Debug Class''' functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.

== Supported chipsets ==

The following southbridges have USB debug support in coreboot:

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status
! align="left" | Comments

|- bgcolor="#eeeeee" valign="top"
| AMD
| SB600
| style="background:lime" | OK
| Tested by [[User:Uwe|Uwe Hermann]].
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB700
| style="background:orange" | WIP
| Probably won't work, a patch is being prepared.

|- bgcolor="#dddddd" valign="top"
| Intel
| 82801GX (ICH7)
| style="background:lime" | OK
| Tested by [[User:SvenS|Sven Schnelle]] on Lenovo Thinkpad X60/T60.
|

|- bgcolor="#eeeeee" valign="top"
| NVIDIA
| MCP55
| style="background:lime" | OK
| Tested by [[User:Uwe|Uwe Hermann]]. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.

|- bgcolor="#dddddd" valign="top"
| SiS
| SiS966
| style="background:yellow" | Untested
| '''Note:''' It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).

|}

== Using the EHCI debug port ==

=== usb_debug kernel module and minicom ===

To get a USB debug console, enable '''CONFIG_USBDEBUG''' (menu option '''USB 2.0 EHCI debug dongle support''') in coreboot's kconfig.

On your "host PC" you need a Linux system which is recent enough to provide the '''usb_debug''' kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a '''/dev/ttyUSB0''' device to which you can connect as usual using any serial terminal program, e.g. '''minicom''' (115200, 8n1).

TODO: Is the Baud rate actually configurable somewhere?

You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.

Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.

=== usb_debug_io.c ===

As an alternative, you can also use [http://tracker.coreboot.org/trac/coreboot/ticket/57 this small libusb-based user-space program] on the host PC to retrieve the coreboot logs.

== Finding the USB debug port ==

Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port is rather difficult because you need to look at lots of information.

Carl-Daniel Hailfinger has written [http://coreboot.org/pipermail/coreboot/2008-September/038635.html a script] which can help finding that port.

== Hardware capability ==

The Debug Port is optional, please check if EHCI controllers near you support it:

$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do
$ ''' lspci -vs $i'''
$ '''done'''
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
Subsystem: IBM Unknown device 0566
Flags: bus master, medium devsel, latency 0, IRQ 5
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [50] Power Management version 2
Capabilities: [58] '''Debug port'''

Look for a line like the last one above. Please include the PCI device ID too:

$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do
$ ''' lspci -ns $i'''
$ '''done'''
00:1d.7 0c03: 8086:265c (rev 03)

If your controller isn't already listed below then please add it or send an email to the [[Mailinglist|mailing list]] if you don't have a wiki account yet and want one, or want us to add your controller to the page.

=== Controllers verified to have the debug port capability ===

* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
* 8086:24cd Intel ICH4/ICH4-M
* 8086:24dd Intel ICH5
* 8086:265c Intel ICH6
* 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)
* 8086:27cc Intel ICH7
* 8086:2836 Intel ICH8
* 8086:283a Intel ICH8
* 8086:293a Intel ICH9 (rev 2)
* 8086:3a3a Intel ICH10
* 8086:3a3c Intel ICH10
* 10de:0088 NVIDIA MCP2A (rev a2)
* 10de:005b NVIDIA CK804 (rev a3)
* 10de:026e NVIDIA MCP51 (rev a3)
* 10de:036d NVIDIA MCP55 (rev a2)
* 10de:03f2 NVIDIA MCP61 (rev a3)
* 1002:4386 ATI/AMD SB600
* 1002:4396 ATI/AMD SB700
* 1106:3104 VIA VX800 (rev 90)

=== Controllers verified to lack the debug port capability ===

* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)
* 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)
* 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)
* 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
* 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)
* 1039:7002 SiS EHCI (rev 00)

== Where to buy ==

Currently there seems to be only two devices which can use the EHCI Debug Port, the '''NET20DC''' and the '''AMIDebug RX'''.

=== NET20DC ===

* [http://web.archive.org/web/20080219120613/http://www.plxtech.com/products/NET2000/NET20DC/default.asp http://www.plxtech.com/products/NET2000/NET20DC/default.asp] (archive.org)
* http://www.semiconductorstore.com/cart/pc/viewPrd.asp?idproduct=12083
* http://www.semiconductorstore.com/pages/asp/supplier.asp?pl=0121
* http://www.ajaystech.com/net20dc.htm
* http://www.ajaystech.com/resources.htm

=== AMIDebug RX ===

* http://www.ami.com/amidebugrx/

== DIY ==

Or you can make your own usb debug dongle. See schematics and PCB here:
And software for this dongle here: http://git.stackframe.org/?p=fx2lib;a=summary

== More information ==

* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) — The Debug Port is described in Appendix C.
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) — This is what has to be connected to the EHCI controller.
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) — ''dead URL''
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]
* http://coreboot.org/pipermail/coreboot/2006-December/thread.html#17480
* http://lkml.org/lkml/2006/12/1/214
* http://www.usb.org/developers/presentations/pres0602/john_keys.pdf
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5c05917e7fe313a187ad6ebb94c1c6cf42862a0b Linux early USB Debug Port support finally commited]
* [http://www.kernel.org/doc/Documentation/x86/earlyprintk.txt early printk support in Linux]
* http://www.spinics.net/lists/linux-usb/msg32912.html (Linux USB EHCI Debug Port device gadget)

EHCI Debug Port

2012-09-07T12:30:59Z

XVilka: Added WIP tool

[[Image:PLX_NET20DC.jpg|thumb|right|Ajays NET20DC USB Debug Device.]]

Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.

The '''EHCI Debug Port''' is an optional capability of EHCI controllers which can be used for that purpose.

All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.

While the '''Debug Class''' functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.

== Supported chipsets ==

The following southbridges have USB debug support in coreboot:

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Southbridge
! align="left" | Status
! align="left" | Comments

|- bgcolor="#eeeeee" valign="top"
| AMD
| SB600
| style="background:lime" | OK
| Tested by [[User:Uwe|Uwe Hermann]].
|- bgcolor="#eeeeee" valign="top"
| AMD
| SB700
| style="background:orange" | WIP
| Probably won't work, a patch is being prepared.

|- bgcolor="#dddddd" valign="top"
| Intel
| 82801GX (ICH7)
| style="background:lime" | OK
| Tested by [[User:SvenS|Sven Schnelle]] on Lenovo Thinkpad X60/T60.
|

|- bgcolor="#eeeeee" valign="top"
| NVIDIA
| MCP55
| style="background:lime" | OK
| Tested by [[User:Uwe|Uwe Hermann]]. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.

|- bgcolor="#dddddd" valign="top"
| SiS
| SiS966
| style="background:yellow" | Untested
| '''Note:''' It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).

|}

== Using the EHCI debug port ==

=== usb_debug kernel module and minicom ===

To get a USB debug console, enable '''CONFIG_USBDEBUG''' (menu option '''USB 2.0 EHCI debug dongle support''') in coreboot's kconfig.

On your "host PC" you need a Linux system which is recent enough to provide the '''usb_debug''' kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a '''/dev/ttyUSB0''' device to which you can connect as usual using any serial terminal program, e.g. '''minicom''' (115200, 8n1).

TODO: Is the Baud rate actually configurable somewhere?

You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.

Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.

=== usb_debug_io.c ===

As an alternative, you can also use [http://tracker.coreboot.org/trac/coreboot/ticket/57 this small libusb-based user-space program] on the host PC to retrieve the coreboot logs.

== Finding the USB debug port ==

Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port is rather difficult because you need to look at lots of information.

Carl-Daniel Hailfinger has written [http://coreboot.org/pipermail/coreboot/2008-September/038635.html a script] which can help finding that port.

== Hardware capability ==

The Debug Port is optional, please check if EHCI controllers near you support it:

$ '''lspci -vs $(lspci|grep EHCI|cut -f1 -d' ')'''
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
Subsystem: IBM Unknown device 0566
Flags: bus master, medium devsel, latency 0, IRQ 5
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [50] Power Management version 2
Capabilities: [58] '''Debug port'''

Look for a line like the last one above. Please include the PCI device ID too:

$ '''lspci -ns $(lspci|grep EHCI|cut -f1 -d' ')'''
00:1d.7 0c03: 8086:265c (rev 03)

If your controller isn't already listed below then please add it or send an email to the [[Mailinglist|mailing list]] if you don't have a wiki account yet and want one, or want us to add your controller to the page.

=== Controllers verified to have the debug port capability ===

* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
* 8086:24cd Intel ICH4/ICH4-M
* 8086:24dd Intel ICH5
* 8086:265c Intel ICH6
* 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)
* 8086:27cc Intel ICH7
* 8086:2836 Intel ICH8
* 8086:283a Intel ICH8
* 8086:293a Intel ICH9 (rev 2)
* 8086:3a3a Intel ICH10
* 8086:3a3c Intel ICH10
* 10de:0088 NVIDIA MCP2A (rev a2)
* 10de:005b NVIDIA CK804 (rev a3)
* 10de:026e NVIDIA MCP51 (rev a3)
* 10de:036d NVIDIA MCP55 (rev a2)
* 10de:03f2 NVIDIA MCP61 (rev a3)
* 1002:4386 ATI/AMD SB600
* 1002:4396 ATI/AMD SB700
* 1106:3104 VIA VX800 (rev 90)

=== Controllers verified to lack the debug port capability ===

* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)
* 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)
* 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)
* 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
* 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)
* 1039:7002 SiS EHCI (rev 00)

== Where to buy ==

Currently there seems to be only two devices which can use the EHCI Debug Port, the '''NET20DC''' and the '''AMIDebug RX'''.

=== NET20DC ===

* [http://web.archive.org/web/20080219120613/http://www.plxtech.com/products/NET2000/NET20DC/default.asp http://www.plxtech.com/products/NET2000/NET20DC/default.asp] (archive.org)
* http://www.semiconductorstore.com/cart/pc/viewPrd.asp?idproduct=12083
* http://www.semiconductorstore.com/pages/asp/supplier.asp?pl=0121
* http://www.ajaystech.com/net20dc.htm
* http://www.ajaystech.com/resources.htm

=== AMIDebug RX ===

* http://www.ami.com/amidebugrx/

== DIY ==

Or you can make your own usb debug dongle. See schematics and PCB here:
And software for this dongle here: http://git.stackframe.org/?p=fx2lib;a=summary

== More information ==

* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) — The Debug Port is described in Appendix C.
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) — This is what has to be connected to the EHCI controller.
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) — ''dead URL''
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]
* http://coreboot.org/pipermail/coreboot/2006-December/thread.html#17480
* http://lkml.org/lkml/2006/12/1/214
* http://www.usb.org/developers/presentations/pres0602/john_keys.pdf
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5c05917e7fe313a187ad6ebb94c1c6cf42862a0b Linux early USB Debug Port support finally commited]
* [http://www.kernel.org/doc/Documentation/x86/earlyprintk.txt early printk support in Linux]
* http://www.spinics.net/lists/linux-usb/msg32912.html (Linux USB EHCI Debug Port device gadget)

Coreboot Symposium 2008

2012-08-16T08:45:45Z

XVilka: Added to 'Meetings' category

== Introduction ==

The coreboot symposium 2008 was held in Denver, April 3 – 5, 2008 during the High Performance Computer Science Week (HPCSW).

== Agenda ==

general: breaks at 10-10:30, 12-1, 3-3:30

=== Thursday ===

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Time
! align="left" | Speaker
! align="left" | Topic

|- bgcolor="#eeeeee" valign="top"
| 1:00-2:00
| Ron Minnich
| Opening of the meeting and discussion of the last year

|- bgcolor="#dddddd" valign="top"
| 2:00-3:00
| Stefan Reinauer
| Automated Testbed, GSoC 2007, 2008

|- bgcolor="#eeeeee" valign="top"
| 3:00-3:30
|
| break

|- bgcolor="#dddddd" valign="top"
| 3:30-4:00
| Stefan Reinauer
| coresystems' various BIOS customers, recent ports and other related work

|- bgcolor="#eeeeee" valign="top"
| 4:00-end
|
| hack session -- set up boards and prioritize the goals of the rest of the time

|}

=== Friday ===

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Time
! align="left" | Speaker
! align="left" | Topic

|- bgcolor="#eeeeee" valign="top"
| 8:30-10:00
| Marc Jones (AMD)
| AMD talks about whatever they want :-)
- consumer issues

- what's going on

- new ports this year

- K10?

[[media:Coreboot_summit_08.pdf|slides]]

|- bgcolor="#dddddd" valign="top"
| 10:00-10:30
|
| break

|- bgcolor="#eeeeee" valign="top"
| 10:30-12:00
| Marc Karasek (Sun)
| Marc talks about his work at Sun with SimNow

|- bgcolor="#dddddd" valign="top"
| 12:00-1:00
|
| Lunch

|- bgcolor="#eeeeee" valign="top"
| 1:00-3:00
| Ron Minnich
| Ron gives an overview of v3, from the smallest to the large bits.
Sample build/burn session

|- bgcolor="#dddddd" valign="top"
| 3:00-3:30
|
| break

|- bgcolor="#eeeeee" valign="top"
| 3:30-4:00
|
| open questions (please add some)
1. how do we tell when a board is good enough to move from v2 to v3?

What's the test?

2. What pending issues are there?

|- bgcolor="#dddddd" valign="top"
| 4:00-5:00
| Ward Vandewege
| The view from the FSF ([[media:Ward-vandewege-coreboot-talk-20080404-slides.pdf|slides]] and [[media:Ward-vandewege-coreboot-talk-20080404-narrative.pdf|narrative]])

|}

=== Saturday ===

* hack all day. We hope to fix the problems we prioritized Thursday.

== What needs to be brought ==

* monitor
* power supplies
* ByteBlaster II

== Who is bringing what ==

'''Ron:''' dbe61 and dbe62. Alix 1C. Alix LPC pod. Artec LPC pod. MINI PCI and PCI post cards. T23 with ubuntu. Outlet strips. FS2 if it arrives from LANL on time (it may not). USB hubs? ISDN card that causes Alix 1.c failure.
Ethernet switch. USB PCI card for testing Alix 1.C. Somebody bring some cat 5 cables -- I forgot mine! Camera.
I'm now in Denver!

'''Ward:''' alix2c3, Artec LPC dongle. alix.1c, usb-to-serial adapter, null-modem cable, philips screwdriver, bios savior, some plcc bios chips

'''Stefan:''' Advantech PCM-5820, possibly other boards, Artec LPC Dongle, JTAG cables on Request, Galep-5 Flash Writer, Flash Plaice(?)

'''Jordan:''' Norwich, FS2, ROM emulator, monitor, PS/2 keyboard, serial cable, laptop and lots of code.

'''MarcJ:''' Norwich, DB800, DBE61, ROM emulators, fs2, keyboard, cables, monitor, hd, atx power, etc. - any requests?

== Current show stopper issues ==

* ALIX1.C and DB800 lockup if MFGPT are enabled in kernel.
* ALIX1.C interrupt flood if ISDN card is enabled (may be related to MFGPT issue).
* DBE62 RAM timing is wrong.
* DBE62 PLL reset gives wrong value on auto setting.
* SiS card can't program 2M flash part.

See also [http://www.coreboot.org/pipermail/coreboot/2008-March/032455.html Denver meeting discussion topics] for more ideas.

[[Category:Meetings]]

FOSDEM 2012

2012-08-16T08:42:49Z

XVilka: Added to 'Meetings' category

== Time and Place ==

Saturday and Sunday, 4th and 5th of February 2012, at FOSDEM2012 in Brussels, Belgium.

== FOSDEM? ==

[http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 11 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).

== coreboot+flashrom talk ==

[http://fosdem.org/2012/schedule/event/coreboot_laptops coreboot - The last frontier: Laptops]
*Speaker: Carl-Daniel Hailfinger
*Day: Sunday
*Room: Janson
*Start time: 12:00
*End time: 12:50

== coreboot+flashrom booth/stand ==

coreboot+flashrom have a joint booth at FOSDEM, AW building. Please stop by.

== Organizational info ==

See [[Talk:FOSDEM 2012]]

See [[FOSDEM 2011]] and [[Talk:FOSDEM 2011]] for info on what we did last year.

[[Category:Meetings]]

FOSDEM 2011

2012-08-16T08:42:27Z

XVilka: Added to 'Meetings' category

== Time and Place ==

Saturday and Sunday, 5th and 6th of February 2011, at FOSDEM2011 in Brussels, Belgium.

== FOSDEM? ==

[http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 11 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).

== coreboot+flashrom talks ==

Sat 14:00-14:15 [http://fosdem.org/2011/schedule/event/coreboot Coreboot: x86 system boot and initialization] Rudolf Marek, Room Ferrer (Lightning talks)

Sat 14:20-14:35 [http://fosdem.org/2011/schedule/event/flashrom flashrom: Run your BIOS/EFI/firmware updates under any free OS] Carl-Daniel Hailfinger, Room Ferrer (Lightning talks)

Sun 14:00-14:30 [http://fosdem.org/2011/schedule/event/ram Cold boot attacks on RAM readout] Carl-Daniel Hailfinger, Room Lameere (Embedded devroom)

Sun 14:30-15:00 [http://fosdem.org/2011/schedule/event/fast_x86_boot Really fast x86 boot] Rudolf Marek, Room Lameere (Embedded devroom)

== coreboot+flashrom booth/stand ==

coreboot+flashrom have a joint booth at FOSDEM, AW building, booth 08. Please stop by.

== Organizational info ==

See [[Talk:FOSDEM 2011]]

[[Category:Meetings]]

FOSDEM 2010

2012-08-16T08:42:02Z

XVilka: Added to 'Meetings' category

== Time and Place ==

Saturday, 6th of February 2010, at FOSDEM2010 in Brussels, Belgium.

== FOSDEM? ==

[http://www.fosdem.org FOSDEM] is simply the biggest free software developers event in Europe. For the last 10 years, on one weekend in February, a campus from the Brussels Free University gets raided by some 5000 open source developers and enthusiasts. There are main tracks with high profile talks, there are project specific devrooms with talks and hands on session, there are booths, and all of it is free (although donations are appreciated).

== Coreboot DevRoom ==

Coreboot will have its very first DevRoom at FOSDEM this year. We will have [http://archive.fosdem.org/2009/maps/campus AW.124], which can hold 60 people, from 13:00 to 19:00. We will have talks and hands-on sessions there and generally be very cool and interesting :)

=== Schedule ===

* 13:00 : Peter Stuge - coreboot introduction
* 14:00 : Peter Stuge - coreboot and PC technical details
* 15:00 : Rudolf Marek - ACPI and Suspend/Resume under coreboot.
* 16:00 : Rudolf Marek - coreboot board porting.
* 17:00 : Carl-Daniel Hailfinger - Flashrom.
* 18:00 : Luc Verhaegen - Flash Enable BIOS Reverse Engineering.

=== Talks ===

* Peter Stuge - coreboot introduction

The BIOS and it's successor EFI are considered by many to be the final frontier for open source software in commodity PCs. This talk introduces the open source BIOS replacement coreboot (formerly known as LinuxBIOS) and the projects that surround it, including many popular payloads that combine with coreboot to make up an innovative firmware for PCs. The talk also looks at the 10 year long history of the project, describes the current state of development and considers some possibilities for the future.

* Peter Stuge - coreboot and PC technical details

A modern PC is quite different from the 1980s original, and while the BIOS still lingers after 30 years it must now solve many tricky problems. When the original PC with it's pre-ISA expansion bus was powered on, it was almost immediately ready to run an application. Today's PC can have several multicore CPUs interconnected by HyperTransport, Front Side Bus or QuickPath, DDR3 RAM on each CPU, and a large number of buses and peripherals. Many components require increasingly complex initialization to be implemented in software. This talk describes the technical challenges encountered by coreboot developers and their solutions.

* Rudolf Marek - ACPI and Suspend/Resume under coreboot.

Ever wanted to know more about ACPI? This talk will introduce the software part of ACPI as well as provide the necessary hardware details to get the bigger picture. A tour through the Coreboot ACPI implementation will be given, and the nitty-gritty details of the suspend and resume procedure will be explained.

* Rudolf Marek - coreboot board porting

You don't like your BIOS? Want coreboot instead? Here is my story... This talk introduces some strategies for porting coreboot to new hardware. We go over the information gathering stage, data-mining, datasheet usage and common gotchas. The porting of a new motherboard but with existing chipset support, as well as kick-starting a new chipset port, are explained.

* Carl-Daniel Hailfinger - Flashrom, the universal flash tool.

Flashrom is the open source utility of choice to identify, read, write, verify and erase flash chips. It is commonly used to flash BIOSes from under Linux, *BSD, OpenSolaris and Mac OS X, but it also has the ability to reflash graphics cards, SATA controllers, network cards and one game console. A wide variety of external programmers is supported as well, from ultra-cheap homemade setups to high end commercial machines. Hotflashing and crossflashing complete the feature set. This talk introduces flashrom, and explains its structure and implementation. Common issues and future directions are explained, and even a demonstration will be given.

* Luc Verhaegen - Flash enable BIOS reverse engineering.

Many board makers provide extra write protection for their BIOS chips. The developers at the flashrom project have to devote part of their time on finding out what protection is present and how this can be disabled. Some of this information comes from the BIOS itself, and the procedures for some common BIOSes, and the tools involved will be introduced in this talk. Part of the time will be spent on digging through an actual BIOS with a crude tool like ndisasm.

=== Information for Speakers ===

A DevRoom at FOSDEM contains a sometimes working network (several thousand people are trying to use wireless at the same time), power, an LCD projector and some whiteboards. Next to that, the room will be filled with highly interested free software people, some of which you know or will get to know after your talk. It always is a very friendly and highly interested audience that can handle very technical information well. Talks should not be kept shallow at all as little pandering is needed. Talks should generally last about 45 minutes, so that there is some time for people to move in and out of the room or to come and talk to you directly.

If you want to give a talk at this DevRoom (and as you can see, there are plenty of slots still available), please contact Luc Verhaegen (libv) by dropping him an email at libv at skynet dot be.

== Further information ==

The [http://www.fosdem.org FOSDEM website] contains tons of information on the event itself, transportation, getting around in brussels, finding hotels, pretty much everything you need. Next to that, there are [http://www.fosdem.org/2010/archives archives] of the website for the previous years, where you can find out about previous talks and shedules.

== Flashrom speed talk at Alt-OS devroom ==
Proposed time: Sunday 12:45-13:00

Porting challenge: Flashrom, the universal flash tool

Flashrom is the open source utility of choice to read and write flash chips and a real porting challenge because it needs full hardware access from userspace. Some say that only X.org needs a similar level of hardware access. Flashrom is working under Linux, *BSD, OpenSolaris, Mac OS X and Windows (somewhat) and people use it to reflash BIOSes, graphics/network/SATA cards, a game console and to control a boatload of external flash programmers.

This talk gives a short overview of flashrom and its architecture, and then goes into detail about the work needed to port it to your favourite OS.

[[Category:Meetings]]

LinuxTag 2009

2012-08-16T08:41:23Z

XVilka: Added to 'Meetings' category

==Booth location==

Hall 7.2a 106

==Who will be there==

*[[User:Stuge|Peter Stuge]]
*[[User:Rminnich|Ron Minnich]] (on Thursday)
*Paul Menzel

==What needs to be brought==

*flat screen monitor
**Paul will bring a 17" flat screen.

*flyers, information material
**Peter will bring a nice poster and print flyers at the printing service on site

*4-in-1 Monitor switch
**Peter

*ethernet switch
**Peter

*power strip (1 for the booth)
**Peter

*keyboard
**Peter

*tools (screw driver, etc.)
**Peter

*OGD-1 (Open Graphics Card)
**Peter

*ethernet card which flashrom supports?

==Ideas for presentation==
===Goals===
* Make coreboot known to more people.
* Show flashrom and how it now also supports ethernet cards and SATA cards and runs also on BSD and Solaris.
* Get more developers.
* Get in touch with hardware vendors.
* Present coreboot and flashrom in 2 slides of 1 minute each at the project's Fast Forward session

===Ideas===
* To catch the attention of the visitors, we should have a catchy slogan being displayed on the flat screen.
** „BIOS and EFI are last century. Join the millenium with coreboot.“
** Peter uses "coreboot - Beyond the final frontier" - maybe too cheesy?

===How to answer best the following questions?===
* Is my board supported?
** We can say that additionally to AMD and VIA now even a rather recent board with an Intel chipset ([[Kontron_986LCD-M_mITX]]) is supported.
** But the main problem will be that AMD still has not yet released the code for their 780(?) chipsets. The VIA VX855 is the most recent chipset, it is only now being made available for mainboard vendors and one of VIA's customers has already contributed support for the chipset to coreboot.
* What benefit does it have?
** Boot speed, no BIOS label cost, open source, reviewable, written in C not assembly, unified codebase for all chipsets and boards, innovative way of booting x86 (payloads) but also legacy compatible (SeaBIOS)
* How do I profit from it?
** Board vendors easy: no BIOS label cost
** Chipset vendors: happy customers because they have an easy to work with firmware
** Appliance vendors: allows near-instant on for simple applications using libpayload
** End users: open source, boot speed, configurability
** Security conscious users: Easy to review
* Is not hibernate/suspend the future?
** coreboot is getting better at ACPI all the time
** With very fast booting firmware, maybe computers can shut down more often?

== See also ==

* http://www.linuxtag.org
* http://www.linuxtag.org/2009/de/besucher/ausstellung.html

[[Category:Meetings]]

LinuxBIOS Symposium 2006

2012-08-16T08:41:00Z

XVilka: Added to 'Meetings' category

== Time and Date ==

The LinuxBIOS Symposium 2006 took place in Hamburg, Germany from October 1st to October 3rd 2006.

== Photos of the Symposium ==

* [http://photos.vandewege.net/photos.cgi?lib=2003&set=LBsymposium2006 Ward's photos]
* [http://www.stefan-reinauer.de/ Stefan's photos]
* [http://mbgokhale.org/Photos.html Ron's photos]

== Agenda ==

The agenda is available [http://coresystems.de/PDFs/Symposium-Agenda.pdf here].

== Talks & Discussion ==

=== Stefan Reinauer ===

* [http://coresystems.de/PDFs/Opening.pdf Opening]
* [http://coresystems.de/PDFs/IntegratorsGuide.pdf Integrator's Guide]
* [http://coresystems.de/PDFs/DevelopmentGuidelines.pdf Development Guidelines]
* [http://coresystems.de/PDFs/ACPI.pdf ACPI in LinuxBIOS]
* [http://coresystems.de/PDFs/Future.pdf The future of LinuxBIOS]
* [http://coresystems.de/PDFs/Payload.pdf What is the best Payload?]
* [http://coresystems.de/PDFs/ProgrammersManual.pdf Programmer's Manual]
* [http://coresystems.de/PDFs/DatasheetTrouble.pdf Datasheet Trouble]
* [http://coresystems.de/PDFs/LinuxBIOS-QA.pdf Automatic Regression Testing]
* [http://coresystems.de/PDFs/TargetingMillions.pdf Targeting Millions]

=== Peter Stuge ===

* [http://stuge.se/lb.eu/ Slides from Peter's Talk]
* [http://www.youtube.com/watch?v=2jP4gBPAgTA Peter Stuge's Embedded Car Audio System I] (Flash video)
* [http://www.youtube.com/watch?v=kl1OWxbWCkA Peter Stuge's Embedded Car Audio System II] (Flash video)

=== Jiming Sun, Sohoon Lee ===

* [http://www.linuxbios.org/data/LinuxBIOS%20AMD%202006%20Final_10-02-2006.pdf AMD's LinuxBIOS enablement strategy]

=== Ronald Minnich ===

* All of [http://linuxbios.org/data/V3.pdf Ron's talks] in a single PDF.

=== Yinghai Lu ===

* [http://linuxbios.org/data/yhlu/LinuxBIOS_CAR_09142006.pdf LinuxBIOS CAR 2006/09/14]
* [http://linuxbios.org/data/yhlu/cache_as_ram_lb_09142006.pdf Part II]

== Hardware ==

We were having a real Hacker's Paradise at the Symposium, amongst others:

=== Uwe Hermann ===

* 3 USB-to-PS2 converters
* ca. 10 PLCC chips of various brands/sizes
* ca. 5 DIP chips of various brands/sizes
* a test laptop (SIS 650/691) with socketed PLCC chip:
* Maybe one or two motherboards, if there's room left

=== Ron Minnich ===
* usb to serial (2)
* 1M flash parts 49lf008a
* 512K flash parts. 49lf004
* epia that works
* digital logic msm800sev that is in progress
* lippert frontrunner that is in progress.
* serial and ethernet cables.
* several enet switches.
* outlet strips
* CF cards
* IDE->CF adapters
* USB storage dongles
* RUMBA board for burning flash parts.
* PCMCIA->CF
* USB->CF
* several IBM power warts
* 3 OLPC

=== Richard Smith ===

* 1 OLPC
* USB -> 3.5 IDE HD
* a couple of 3.5 IDE HD's
* USB CDR/DVD burner.
* ASUS P2B i440bx mother board
* 4 in 1 screwdriver.
* Small screwdriver for pulling DIPs
* Several 29F040b PLCC, Some DIPs I pulled from old motherboards
* ATX powersupply
* USB mouse.
* Small PS/2 keyboard
* USB -> PS/2 adapter.
* several cheap not surge protected powerstrips. (If they blow up no loss)
* serveral EU to US plug adapters.

Stuff I was bringing but decided not to

* 500W 220 -> 110V transformer. (this thing is a cavity search waiting to happen)
* USB -> 2.5 IDE HD (Needs above)
* Max Speed Max Term motherboard (needs above)

=== Peter Stuge ===
* mostly working EPIA-MII with 6-26v 60w atx picoPSU
* a spare samsung 256mb ddr ram
* ide2cf
* pcmcia2cf
* cf cards
* soekris net4801
* soekris net4826
* prism2/atheros minipci/pci/pcmcia abg/bg/b wifi cards
* pci 1394a without rom
* old agp/pci vga cards with rom
* pci aha-2940au scsi with rom
* 8x100 ethernet switch, some 10m cables, parts for making cables
* usb2serial
* sata/ata/usb/1394/nullmodem cables
* usb flash drive if I can find one
* some plcc 512k am29lf040b and one 256k sst39sf020a
* plcc remover tool
* miniature screwdrivers (aka diy plcc remover tool)
* usb2sata 3.5" case
* usb fdd
* usb hub(s)
* ac-12v 1.5a psu
* ac-12v 2.5a psu
* ac-3/5/9/12v 2.5a psu
* ac-power-over-ethernet injector
* a dumb euro power strip or two
* a 5m extension cord or two
* cd-r/dvd-r media
* flashlight
* 10" gray vga crt
* ps/2 .se keyboard

=== Stefan Reinauer ===

* Via Epia-M
* GBit Switch
* WIFI Routers
* Galep IV Flash burner for DIL and PLCC
* some power strips
* CE power chords
* remote power switch
* USB->CF
* Bios Savior+USB control
* chip pullers
* a USB keyboard
* some serial cables (nullmodem)
* usb2serial converter
* usb debug device
* usb flash stick + usb hard drive
* usb hub
* (multimeter+soldering iron)
* Beamer

=== Ward Vandewege ===
* Bios Savior (512KB)
* plcc removal tool
* Serial cable (DB9 female/DB9 female)
* USB to serial cable (DB9 male)
* USB -> 2.5 IDE case with 2.5" IDE drive
* IDE 3.5" -> 2.5" converters
* couple of EU -> US plug converters
* lots of anti-drm and GNU/linux stickers

[[Category:Meetings]]

LinuxTag 2007 Workshop

2012-08-16T08:40:31Z

XVilka: Added to 'Meetings' category

Also see the [http://www.linuxtag.org/2007/de/community/workshops/workshops/eventdetail.html?talkid=264 workshop page on linuxtag.org].

Level: Intermediate / Advanced
Max number of attendees: 20
Length: Circa 2 hours

LinuxBIOS developers walk through how to configure and compile a LinuxBIOS that can be used to boot a Linux system on your VIA EPIA, EPIA-M or EPIA-MII from a boot server on the network, from a local IDE device or from a CompactFlash card. (CF is only available on EPIA-MII but with an adapter the CF card works exactly like an IDE device)

==== The workshop teaches attendees how to ====
[[Image:Pushpin_roms_2.jpg|thumb|Pushpin flash]]

* configure and build EtherBoot for their EPIA board to boot from network
* configure and build LinuxBIOS with VGA support and the EtherBoot payload
* hotswap flash chips
* flash the new LinuxBIOS to an empty flash chip in Linux
* configure and build FILO for their EPIA board to boot from IDE or CF
* finally rebuild LinuxBIOS using FILO as payload instead of EtherBoot

* optional: configure a boot server
(the presenter will run a boot server for those who can only bring their EPIA board)

==== Attendees should bring the following to the workshop ====
* an EPIA, EPIA-M or EPIA-MII board with power supply, keyboard and monitor or serial console
* an x86 Linux system with gcc 4.x (this can be either on the EPIA board or on a separate system)
* if you bring two systems (e.g. EPIA+laptop), remember to bring a crossover network cable
* one straight networking cable for each system
* one spare flash chip for the EPIA board or EUR 6 to purchase a pushpin flashchip

Attendees are expected to have experience with Linux system administration, open source software compilation and installation, and boot loaders.

[[Category:Meetings]]

LinuxTag 2008

2012-08-16T08:40:01Z

XVilka: Added to 'Meetings' category

==Highlights==

We will be having three [http://www.linuxtag.org/2008/de/community/workshops.html workshops]:
* Thursday, 2008-05-29, 15:00-16:00. [http://www.linuxtag.org/2008/de/community/workshops/workshops0/eventdetail.html?talkid=306 Peter: Flashrom (english)]
* Thursday, 2008-05-29, 16:00-17:00. [http://www.linuxtag.org/2008/de/community/workshops/workshops0/eventdetail.html?talkid=317 Carl-Daniel: Flashrom (german)]
* Saturday, 2008-05-31, 14:00-16:00. [http://www.linuxtag.org/2008/de/community/workshops/workshops0/eventdetail.html?talkid=305 Carl-Daniel: Porting to Alix.1C,Alix.2C3 or DBE61 (german)]

==Booth location==

Hall 7.2b 112, at the "Embedded" booth, together with GPE, GPE Phone Edition, embedded GNUstep, oBiCo, Open Embedded, T2 SDE, Tntnet.

==Who will be there==

*Peter Stuge
*Paul Menzel
*Carl-Daniel Hailfinger

==Booth plan==

We'll get one bar stool and one counter (Length x Width x Height 0.65 x 0.65 x 1 m). The counter is lockable. All bar stools are missing from the booth plan, but they will be there. All 8 projects at our booth will share one sofa and maybe one table+chairs.

[http://www.copynpaste.de/lt08/booths/2B112-Embedded.pdf Booth plan, 358k PDF]

==Problems==

==What needs to be brought==

*Flat screen monitor
**Paul brings a 15" flat screen. Thanks!

*4-in-1 Monitor switch
**Peter brings one on Wednesday
**Once Peter leaves, we won't need the Monitor switch anymore

*Ethernet switch (for the workshop, >20 ports would be preferable)
**Peter is bringing one
**Carl-Daniel is bringing one
**We'll just exchange switches when Peter leaves

*Power strip (1 for the booth, 1 big for the workshop)
**Carl-Daniel brings one with 12 sockets on Thursday

*Artec dongles (for demos and the workshop)
**Carl-Daniel brings one (currently slightly defective) on Thursday
**Martin-Eric (Artec) brings a few

*Artec ThinCan DBE61 (for demos and the workshop)
**Carl-Daniel brings one on Thursday. v3 RAMinit is still not working due to defective dongle.

*PC Engines Alix.1C (for demos and the workshop)
**Peter brings one
**Carl-Daniel brings one

*Serial cables for DBE61 and Alix.1C
**Carl-Daniel is trying to get 2 USB-Serial cables delivered to the booth.

*PS/2 keyboard
** Peter brings one on Wednesday

*USB keyboard
**Carl-Daniel brings one on Thursday

*LPC flash chips
**Carl-Daniel will bring a few if he can find them.

== See also ==

* http://www.linuxtag.org
* http://www.linuxtag.org/2008/de/besucher/ausstellung/ausstellerliste.html

[[Category:Meetings]]

LinuxBIOS Summit 2005

2012-08-16T08:39:11Z

XVilka: Added to 'Meetings' category

= LinuxBIOS Summit =

Expect more information, such as papers and presentations held at the LinuxBIOS summit 2005 soon.

LinuxBIOS Summit was Oct. 11-13, Santa Fe, New Mexico, USA. See the [http://www.linuxbios.org/data/LB_Summit.pdf agenda] for more information.

Richard Bruner, AMD Fellow, was be a featured speaker. We had a number of interesting speakers lined up, and were be describing new developments, such as the use of Linux Kconfig for LinuxBIOS configuration.

Title: AMD's Roadmap for Free Firmware (as in Beer)

Speaker: Rich Brunner, AMD Fellow

Abstract: This will be a discussion of the upcoming AMD Processor
roadmap, AMD plans for supporting LinuxBIOS, and AMD's
directions for the future of firmware.

Speaker BIO:

Richard A. Brunner is the Software Architect for Advanced Micro
Devices' AMD64 Architecture. He is an AMD fellow and is responsible
for driving the technical direction of AMD's AMD64 software strategy
for operating systems, device drivers, compilers, libraries, OS/firmware
interaction, performance optimizations, and 3rd party tools. Richard
led AMD's initial involvement into the Unified Extensible Firmware
Interface (UEFI) forum.

Richard holds a Masters of Science degree in Computer Engineering from
Rensselaer Polytechnic Institute and a Bachelor of Science degree in
Electrical Engineering from Case Western Reserve University. He holds
patents in computer architecture and has presented
extensively including Hot Chips, Siggraph, WinHec,
Linux Kernel Summit, Linux World, Ottawa Linux Symposium.

== Invitation ==

----------------------------------------------
Ronald G. Minnich writes:

Just hold these dates: october 11-13, 2005

We've arranged for the lacsi symposium, in santa fe:
http://lacsi.rice.edu/symposium/ to set up 2.5 days
for a linuxbios summit. The info on the linuxbios track,
hotels, etc. should be on that web page later today
or tomorrow. We hope to have vendor talks, and
discussions on where we as a community are going
with linuxbios.

The time of year is nice in santa fe, new mexico is
beautiful, the food is great, the hotel is very
pleasant: do consider coming! We'd like to see all of
you folks out here.

Vendors on this list, if you have something you'd like
to talk about, please get back to me.

thanks

ron

---------------------------------------

== Agenda ==

We are working on the agenda for LinuxBIOS summit. Here is a draft
version. Please give us any suggestion and help you have.

We categorized the attendance into three parties, the vendors, the users
and the developers. We hope the three parties can each describe their
past experience, outstanding problems and future directions such that
these three parties can help each other.

=== Oct. 11th ===

The first day will be focus on current status report. We are going to
have

==== Vendor Presentation ====

1. Richard Bruner from AMD will talk about AMD's plan on LinuxBIOS and their roadmap for their products.

2. LNXI will give us their experience on integrating LinuxBIOS in their cluster products.

3. Terra soft will give us their plan of using LinuxBIOS in their PPC 970 products.

==== User Experience ====

Users from Sandia and Los Alamos will talk on their experience of using LinuxBIOS in clusters.

==== Developer Status Report ====

Developers will give presentations and hands-on demo of recent development. Topics includes:

1. Dual Core support for AMD K8

2. Cache As Ram support for Intel and AMD processors.

3. Integrating VGA BIOS support in your LinuxBIOS.

=== Oct. 12th ===

On the second day we will focus on making LinuxBIOS more friendly for
people of the three parties:

==== User Friendly ====

1. User Interface: What kind of default payload and/or user interface are we going to use? Do we want it to be command line or menu style?

2. User's Manual.

==== Developer Friendly ====

1. KConfig: Josiah England will show us his work on using KConfig to replace the current config tool.

2. Development Model: What is the svn commit and release process?

3. Device Object Model: People still complain about the complexity of the current device model. Can we make it easier to work with?
What is the impact of a new config too like #1 on the device model? How are we going to generate PIRQ/ACPI etc. tables?

4. Programmer's Manual.

==== Vendor Friendly ====

1. We need to discuss the possibility of signing N-party NDA with vendors for
their unreleased products.

2. How can we ensure 3rd party that our code is clean and free of legal trouble?

3. Binary blob and EFI/Tiano Interface. How are we going to play nice with Intel?

==== Hackathon ====

If anyone get inspired during the discussion, start implement your idea immediately!!

=== Oct. 13th ===

On the third day we will look forward further into the future:

==== Crazy Ideas ====

1. FreeFI: Possible name change and official FSF sponsorship.

2. LinuxBIOS as Linux: Ron just doesn't give up his old LinuxBIOS==Linux idea. He will show how he is recycling it.

==== Homework Assignment ====

Hey, you had a good time. It is time to do your homework now.

== Registration ==

The registration fee is Registration is $350 until September 5, then $400 until October 5 or on-site.

To register for the LinuxBIOS summit, please go to
http://lacsi.rice.edu/symposium/.

[[Category:Meetings]]

Msrtool

2012-06-30T22:57:26Z

XVilka: svn -> git fixes

'''msrtool''' is a small utility that dumps chipset-specific MSR registers.

== Supported OSes and chipsets ==

'''OSes:'''

* Linux with /dev/cpu/*/msr
* Darwin / OS X with DirectIO
* FreeBSD with /dev/cpuctl*

'''Chipsets:'''

* AMD Geode GX2
* AMD Geode LX
* AMD Geode CS5536
* AMD K8
* Intel Pentium III and later

== Installation ==

'''Manual installation'''

$ '''git clone http://review.coreboot.org/p/coreboot.git'''
$ '''cd coreboot/util/msrtool'''
$ '''./configure'''
$ '''make'''
$ '''sudo make install'''

You can [http://review.coreboot.org/gitweb?p=coreboot.git browse the msrtool source code] using the gitweb interface.

== Usage ==

Show basic information:

$ '''msrtool'''

Please see '''msrtool -h''' for information on various other options.

{{PD-self}}

FILO

2012-06-22T09:35:59Z

XVilka: Removed obsolete FILO-0.5 subversion link

[[Image:Qemu filo.png|thumb|right|FILO trying to load menu.lst.]]
[[Image:Qemu filo prompt.png|thumb|right|FILO prompt.]]

'''FILO''' is a bootloader which loads boot images from a local filesystem,
without help from legacy BIOS services.

Expected usage is to flash it into the BIOS ROM together with coreboot.

== Download FILO ==

Download the latest version of FILO from Git with

$ git clone http://review.coreboot.org/p/filo.git

You can also browse the source code online at
http://review.coreboot.org/gitweb?p=filo.git

== Features ==

* Supported boot devices: IDE hard disk, SATA hard disk, CD-ROM, and system memory (ROM)
* Supported filesystems: ext2, fat, jfs, minix, reiserfs, xfs, and iso9660
* Supported image formats: ELF and [b]zImage (a.k.a. /vmlinuz)
* Supports boot disk image of El Torito bootable CD-ROM. "hdc1" means the boot disk image of the CD-ROM at hdc.
* Supports loading image from raw device with user-specified offset
* Console on VGA + keyboard, serial port, or both
* Line editing with ^H, ^W and ^U keys to type arbitrary filename to boot
* Full support for the ELF Boot Proposal (where is it btw, Eric)
* Auxiliary tool to compute checksum of ELF boot images
* Full 32-bit code, no BIOS calls
* uses [[libpayload]]

== Requirements ==

Only the x86 (x64) architecture is currently supported. Some efforts have
been made to get FILO running on PPC. Contact the [[Mailinglist|coreboot mailinglist]]
for more information.

Recent version of GNU toolchain is required to build.

We have tested with Debian/woody (gcc 2.95.4, binutils 2.12.90.0.1,
make 3.79.1), Debian/sid (gcc 3.3.2, binutils 2.14.90.0.6,
make 3.80) and different versions of SUSE Linux from 9.0 to 11.0.

FILO will use the coreboot crossgcc if you have it built and it can be found.

FILO uses coreboot's '''libpayload'''. It is easiest to locate and build FILO in the '''coreboot/payloads''' directory.

== Building on 64-bit OS specifics ==

If you will be building FILO on AMD64 platform for Debian install the '''gcc-multilib''' package.

x64/AMD64 machines work fine when compiling FILO in 32-bit mode.
(coreboot uses 32-bit mode and Linux kernel does the transition to 64-bit mode)

== Preparation ==

Before you can build FILO, you have to build libpayload. If your filo directory is located inside the coreboot/payloads directory, you don't have to do anything special. If for some reason you want to compile FILO of the coreboot/payloads directory, you will need to tell the makefile where libpayload is. Open filo/Makefile in your favorite text editor and change this line

export LIBCONFIG_PATH := $(src)/../libpayload

to match the location of the libpayload directory on your system:

export LIBCONFIG_PATH := /home/YOUR_USER_NAME/PATH_TO_COREBOOT/payloads/libpayload

== Configuration ==

Configure FILO (and libpayload) using the Kconfig interface:

$ make menuconfig

This will run menuconfig twice -- the first time for libpayload, the second time for FILO.

== Building ==

Then running make will build filo.elf, the ELF boot image of FILO.
$ make

If you are compiling on an AMD64 platform and compiler complains, instead of "make" you need to write

$ make CC="gcc -m32" LD="ld -b elf32-i386" HOSTCC="gcc" AS="as --32"

Use '''build/filo.elf''' as your payload of coreboot, or a boot image for
[[Etherboot]].

Alternatively, you can build libpayload and FILO in one go using the build.sh script, with the drawback that you'll get the default options for both of them:
$ ./build.sh

Here is the short listing how to build FILO from svn
cd coreboot/payloads
git clone http://review.coreboot.org/p/filo.git
cd filo
make config
make

== Credits ==

* This software was originally developed by SONE Takeshi <ts1@tsn.or.jp>
* It has been significantly enhanced and is now maintained by [mailto:stepan@coresystems.de Stefan Reinauer].
* It uses libpayload from Uwe Hermann and Jordan Crouse

== Troubleshooting ==

If you experience trouble compiling or using FILO, please report with a build log or detailed error description to the [[Mailinglist|coreboot mailing list]].

== Notes ==

=== CD-ROM Booting ===

To boot a CD-ROM or DVD you only need to specify the drive '''without a partition number'''. For example to boot to the primary drive on the secondary IDE channel you would use '''hdc''' and not '''hdc1''' in FILO.

=== Grub-like Interface ===
If you are using FILO with '''CONFIG_USE_GRUB''', and want to boot to your Linux install disk you have to do a mixture of GRUB and FILO commands.

Like GRUB you have to append a kernel (and parameters), then an initrd, and give a boot command.
Like FILO you have to give absolute paths.

Example to boot to a GeeXboX install CD-ROM:
filo> kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom installator
Press <ENTER>
filo> initrd hdc:/GEEXBOX/boot/initrd.gz
Press <ENTER>
filo> boot
Press <ENTER>

Your system will now boot right into the Linux install.

=== NVRAM Parsing ===

FILO parses the following NVRAM variables:

* 'boot_devices' can contain a list of boot devices seperated by semicolons. FILO will try to load filo.lst / menu.lst from any of these devices.
Example how to set:
nvramtool -w "boot_devices=hda1:/boot/filo;hdc:"

FILO

2012-06-21T15:41:28Z

XVilka: Switch from Subversion to Git commands and links

[[Image:Qemu filo.png|thumb|right|FILO trying to load menu.lst.]]
[[Image:Qemu filo prompt.png|thumb|right|FILO prompt.]]

'''FILO''' is a bootloader which loads boot images from a local filesystem,
without help from legacy BIOS services.

Expected usage is to flash it into the BIOS ROM together with coreboot.

== Download FILO ==

Download the latest version of FILO from Git with

$ git clone http://review.coreboot.org/p/filo.git

Alternatively you may still download the obsolete filo 0.5.6 release at

$ svn co svn://coreboot.org/filo/branches/filo-0.5

You can also browse the source code online at
http://review.coreboot.org/gitweb?p=filo.git

== Features ==

* Supported boot devices: IDE hard disk, SATA hard disk, CD-ROM, and system memory (ROM)
* Supported filesystems: ext2, fat, jfs, minix, reiserfs, xfs, and iso9660
* Supported image formats: ELF and [b]zImage (a.k.a. /vmlinuz)
* Supports boot disk image of El Torito bootable CD-ROM. "hdc1" means the boot disk image of the CD-ROM at hdc.
* Supports loading image from raw device with user-specified offset
* Console on VGA + keyboard, serial port, or both
* Line editing with ^H, ^W and ^U keys to type arbitrary filename to boot
* Full support for the ELF Boot Proposal (where is it btw, Eric)
* Auxiliary tool to compute checksum of ELF boot images
* Full 32-bit code, no BIOS calls
* uses [[libpayload]]

== Requirements ==

Only the x86 (x64) architecture is currently supported. Some efforts have
been made to get FILO running on PPC. Contact the [[Mailinglist|coreboot mailinglist]]
for more information.

Recent version of GNU toolchain is required to build.

We have tested with Debian/woody (gcc 2.95.4, binutils 2.12.90.0.1,
make 3.79.1), Debian/sid (gcc 3.3.2, binutils 2.14.90.0.6,
make 3.80) and different versions of SUSE Linux from 9.0 to 11.0.

FILO will use the coreboot crossgcc if you have it built and it can be found.

FILO uses coreboot's '''libpayload'''. It is easiest to locate and build FILO in the '''coreboot/payloads''' directory.

== Building on 64-bit OS specifics ==

If you will be building FILO on AMD64 platform for Debian install the '''gcc-multilib''' package.

x64/AMD64 machines work fine when compiling FILO in 32-bit mode.
(coreboot uses 32-bit mode and Linux kernel does the transition to 64-bit mode)

== Preparation ==

Before you can build FILO, you have to build libpayload. If your filo directory is located inside the coreboot/payloads directory, you don't have to do anything special. If for some reason you want to compile FILO of the coreboot/payloads directory, you will need to tell the makefile where libpayload is. Open filo/Makefile in your favorite text editor and change this line

export LIBCONFIG_PATH := $(src)/../libpayload

to match the location of the libpayload directory on your system:

export LIBCONFIG_PATH := /home/YOUR_USER_NAME/PATH_TO_COREBOOT/payloads/libpayload

== Configuration ==

Configure FILO (and libpayload) using the Kconfig interface:

$ make menuconfig

This will run menuconfig twice -- the first time for libpayload, the second time for FILO.

== Building ==

Then running make will build filo.elf, the ELF boot image of FILO.
$ make

If you are compiling on an AMD64 platform and compiler complains, instead of "make" you need to write

$ make CC="gcc -m32" LD="ld -b elf32-i386" HOSTCC="gcc" AS="as --32"

Use '''build/filo.elf''' as your payload of coreboot, or a boot image for
[[Etherboot]].

Alternatively, you can build libpayload and FILO in one go using the build.sh script, with the drawback that you'll get the default options for both of them:
$ ./build.sh

Here is the short listing how to build FILO from svn
cd coreboot/payloads
git clone http://review.coreboot.org/p/filo.git
cd filo
make config
make

== Credits ==

* This software was originally developed by SONE Takeshi <ts1@tsn.or.jp>
* It has been significantly enhanced and is now maintained by [mailto:stepan@coresystems.de Stefan Reinauer].
* It uses libpayload from Uwe Hermann and Jordan Crouse

== Troubleshooting ==

If you experience trouble compiling or using FILO, please report with a build log or detailed error description to the [[Mailinglist|coreboot mailing list]].

== Notes ==

=== CD-ROM Booting ===

To boot a CD-ROM or DVD you only need to specify the drive '''without a partition number'''. For example to boot to the primary drive on the secondary IDE channel you would use '''hdc''' and not '''hdc1''' in FILO.

=== Grub-like Interface ===
If you are using FILO with '''CONFIG_USE_GRUB''', and want to boot to your Linux install disk you have to do a mixture of GRUB and FILO commands.

Like GRUB you have to append a kernel (and parameters), then an initrd, and give a boot command.
Like FILO you have to give absolute paths.

Example to boot to a GeeXboX install CD-ROM:
filo> kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom installator
Press <ENTER>
filo> initrd hdc:/GEEXBOX/boot/initrd.gz
Press <ENTER>
filo> boot
Press <ENTER>

Your system will now boot right into the Linux install.

=== NVRAM Parsing ===

FILO parses the following NVRAM variables:

* 'boot_devices' can contain a list of boot devices seperated by semicolons. FILO will try to load filo.lst / menu.lst from any of these devices.
Example how to set:
nvramtool -w "boot_devices=hda1:/boot/filo;hdc:"

GRUB2

2012-06-01T11:25:11Z

XVilka: Link outdated and no longer available

'''[https://www.gnu.org/software/grub/grub.html GRUB2]''' is a modular, multiboot-capable bootloader for many operating systems that can be used as a payload for coreboot.

== Status ==

* The mainline version of GRUB2 has a [http://grub.enbug.org/CoreBoot wiki page on the coreboot port] (Update: no longer available)
* Additional information about our former GRUB2 effort (which was part of Google Summer of Code 2007) can be found in the history of this page. Don't expect any link there to work.
* As an alternative, you could consider using [[FILO]]. Both FILO and GRUB2 have various advantages and disadvantages. Which of the two is better suited depends on your requirements.
* Yet another alternative is to not put GRUB into the BIOS ROM, but have it run from your disk as you would with a vendor BIOS. For that, you can use [[SeaBIOS]] as payload, which will then be able to run either GRUB1 or GRUB2 from your disk.

CBFS

2012-06-01T11:22:11Z

XVilka: Fixed old link to new in the current git tree

The '''coreboot CBFS Specification''' was originally announced [http://www.coreboot.org/pipermail/coreboot/2008-December/043442.html here].

See [http://review.coreboot.org/gitweb?p=coreboot.git;a=blob_plain;f=documentation/cbfs.txt;hb=HEAD cbfs.txt] for details.

Talk:Coreboot v3

2012-06-01T11:14:39Z

XVilka: Created page with "Coreboot v3 now deprecated, so this page needed only for history/educational purposes. So it will be nice to have such page (with images) for coreboot v4. Something like exten..."

Coreboot v3 now deprecated, so this page needed only for history/educational purposes. So it will be nice to have such page (with images) for coreboot v4.
Something like extended version of "coreboot overview" section on http://www.coreboot.org/Developer_Manual

Talk:Coreboot 4.1

2012-06-01T11:04:47Z

XVilka: Created page with "3-years old april joke - may be need something new?"

3-years old april joke - may be need something new?

Bayou

2012-06-01T11:02:16Z

XVilka: Fixed downloading from Subversion to Git

[[Image:Bayou-screenshot-menu.jpg|thumb|right|The chooser menu with two options.]]
[[Image:Bayou-screenshot-info.jpg|thumb|right|The same chooser menu showing the PAYLOAD_PARAM data passed by coreinfo.]]
[[Image:Bayou-screenshot-serial.jpg|thumb|right|The same chooser menu over serial.]]
[[Image:Bayou-screenshot-timeout.jpg|thumb|right|The timeout message. If the key isn't pressed, then the menu is displayed.]]

'''Bayou''' is the working name for a coreboot [[Payloads|payload]] that can choose, load and run other payloads from a LAR archive on the ROM.

== Building ==

First, get and build [[libpayload]]:

$ '''git clone http://review.coreboot.org/p/coreboot'''
$ '''cd payloads/libpayload'''
$ '''make menuconfig'''
$ '''make'''

Then, get and build Bayou itself:

$ '''cd ../bayou'''

Now, you'll need to create a '''bayou.xml''' file containing the menu entries you like. Start by copying and then editing the sample file '''bayou.xml.example''' (and copying all required payloads in the current directory).

$ '''cp bayou.xml.example bayou.xml'''

Then actually build Bayou:

$ '''make'''

The file '''bayou.elf''' is your finale Bayou payload file, which you can use for coreboot.

== Why "Bayou"? ==

We need a little bit of originality in the names of our payloads, as Peter discusses [http://www.coreboot.org/pipermail/coreboot/2008-April/033219.html here]. In the grand tradition of [http://en.wikipedia.org/wiki/El_Torito_%28CD-ROM_standard%29 El Torito], we decided to name the project after the restaurant where we ate lunch and debated the payload chooser during the coreboot summit 2008 in Denver: [http://denver.citysearch.com/profile/1823003/denver_co/bayou_bob_s_seafood_southern_cookin.html Bayou Bob's]. The word ''bayou'' is French in origin, but it famously describes slow or stagnant streams and swamps in the southern United States (see also [http://en.wikipedia.org/wiki/Bayou Bayou at wikipedia]. The name in no way describes the project itself, which should neither be slow nor swampy.

== Usage Models ==

The following are the two usage models for the payload:

=== Graphical chooser ===

This usage model presents a menu to the user containing the descriptive names of all the payloads in the LAR. The user selects an item from the list, and Bayou loads and runs the payload. If the payload is responsible enough to be able to exit cleanly (as all libpayload payloads should be able to do) and return control to Bayou, then the user can select a different payload.

=== Chaining ===

Chaining is a non-interactive usage model wherein Bayou will load and execute a series of payloads in order. The payloads must be able to return control to Bayou cleanly (except the "final" payload which isn't expected to return). This will loosely imitate a traditional BIOS in that one could define a "BIOS setup screen" payload that ran before FILO or other kernel bootloader.

== Architecture ==

The architecture of Bayou is rather simple. It is a [[libpayload]] based application with code for reading and loading payloads from a LAR and a front end user interface. The Bayou code itself lives below 640k so that it can stay resident when loading payloads that would typically locate themselves at 1Mb or higher. Payloads that want to work cleanly with Bayou should not write to memory below 640k unless it is a "final" payload (i.e. something that will not return to Bayou, such as the Linux kernel). Bayou will read, load and execute payloads encoded in the [[SELF|Simple Executable Loader Format]], decompressing them if needed (with lzma).

== Behavior ==

When Bayou starts, it will find and read the '''Bayou Payload Table (BPT)''' (see below). There are three different paths that can be followed, depending on the value of the '''timeout''' field:

* If the timeout field is greater then 0 but not 0xFF, then Bayou will display a countdown message on the screen. If the user presses F1, then the chooser menu will be displayed. If the user does not press a key in the alloted time then Bayou will automatically start the item in the payload table that is marked as 'default'.
Please press F1 for the menu. Timeout in (3) seconds...
* If the timeout field is zero, then the default item will be chosen immediately without a timeout.
* If the timeout field is 0xFF. then the chooser menu will be shown immediately without a timeout.

When the menu is displayed, it will list all top level items in the Bayou Payload Table, both chooser and chain items. When a chain item is selected from the menu (or as the 'default' item), then each of the sub-items listed in the payload table will be executed in order. Each sub-payload item is expected to return control to Bayou, except the last one. If a payload fails to return control, then the rest of the chain will not be executed.

== Configuration ==

The ROM image with LAR + coreboot v3 is very dynamic in nature. New blobs of data can be added at any time during the build process or during runtime. This means that the Bayou configuration cannot be static - it must be able to grow and change with the LAR.

=== Bayou Payload Table ===

The payload table describes which payloads to manage, both in chooser and in chained mode. The table is stored as a LAR file with the name '''bayou_payload_table'''. The table is organized like follows:

{| border="1"
|- bgcolor="#6699ff"
|-
| Global configuration
|-
| Payload tables
|}

The global configuration header controls general Bayou behavior:

{| border="1"
|- bgcolor="#6699ff"
!Field
!Size
!Description
|-
| ID || 4 bytes || An identifier that indicates the file is a Bayou Payload Table. the value will be 'BPT0' or in hex: 0x305405042 (in little endian)
|-
| Timeout || 1 bytes || if the value of this field is 0, then the default item in the payload list will be executed immediately. If this value is 254 (0xFF), then the chooser menu will be displayed immediately. Any value between 1 and 254 indicates the amount of time (in seconds) that the system should wait.
|-
| Padding || 11 bytes || Unused space padding out to 16 byte alignment. This may be used in the future
|}

Following the configuration header is the list of payloads. There are three types of possible items in the list:
* A chooser item is displayed in a list of other items on a menu. Each chooser item is associated with a single payload.
* A master chain item describes a chain of items that are to be executed one after another. Master chain items specify a title and may be displayed on the chooser menu.
* A number of sub chain items are tied to a master chain item and point to the specific payloads to be executed in the chain.

{| border="1"
|- bgcolor="#6699ff"
!Field
!Size
!Description
|-
| index || 1 byte || An index number for the entry - sub items will use this as the value of its 'parent' field
|-
| parent || 1 byte || For sub chain items this lists the index of the master chain item that the payload is attached to. Chooser and master chain items are always at the toplevel and should have a parent of '0'
|-
| type || 1 byte || Specifies the type of the entry. Possible values are 0x01 - chooser item, 0x02 - master chain item, 0x03 sub-chain item
|-
| flags || 1 byte || This bit field describes various flags that modify the item. Possible values are bit 0 - default item (executed after timeout), bit 1 - do not show in chooser menu
|-
| title || 64 bytes || This is a name displayed by the chooser for the item. It is required for master chain items, but not for chooser items. If not NULL, this will replace any names specified by the payload. This should be null for sub chain items
|-
| nlen || 4 bytes || Length of the payload name, in bytes. This should be 0 for master chain items.
|-
| name || 'nlen' bytes || Specifies the name of the LAR file for the payload associated with this entry. Only valid for sub-chain items and chooser items.
|}

== Payload Parameters ==

There are several parameters that the payload can set to control the behavior of Bayou. These are passed in through the PARAMS section in the SELF:

{| border="1"
|- bgcolor="#6699ff"
!Parameter
!Description
|-
| name || This is the short name of the payload, which is displayed in the log and in the chooser menu if 'listname' is not defined
|-
| listname || This is the name shown in the chooser menu
|-
| desc || This is a verbose description of the application that will be displayed in the "help" section in the chooser menu
|}

The following is an example of macros a typical payload would use to set the above values:

PAYLOAD_PARAM(name,"coreinfo");
PAYLOAD_PARAM(listname,"System Information");
PAYLOAD_PARAM(desc,"Display information about the system");

== Changes to coreboot ==

In order to support Bayou, some drastic changes need to be made to coreboot and associated projects. The following is a short synopsis of these changes.

=== Coreboot ===

* Coreboot needs to be modified to understand and load the [[SELF]] format.
* The LAR design needs to be modified so that coreboot can identify and boot the "default" payload. Captain Obvious says: call it '''payload/default''' (or normal, or whatever). No evil bit in LAR required to find it.

=== LAR ===

* The LAR utility must be modified to build LAR images with SELF payloads.
* The LAR utility needs to be modified to allow the user to specify a long descriptive name to be included in the NAME segment.
* A rewrite of the frontend of the LAR utility may be needed to fully support all the features.

Instead of modifying LAR and putting even more features into it, how about creating an '''elf2self''' (and back) tool, and just add those files into lar?
Sure, it's another build step, but it's "one tool for one job", allows for interesting development, adoption of SELF beyond coreboot, ... - and we really already have enough build steps that this additional one won't hurt either.

=== Buildrom ===

* Buildrom must be adapted to build multiple payloads during the same run.

=== Libpayload ===

* Add generic LAR walking code ('''done''').
* Ensure that libpayload based payloads can cleanly return control to the master payload.
* Modify the build system to allow the configuration system to modify the payload entry point.

Talk:Bento

2012-06-01T10:59:38Z

XVilka: Created page with "Looks like this page not informative and too old - may be deprecated and need to be removed?"

Looks like this page not informative and too old - may be deprecated and need to be removed?

Talk:Biosdistro

2012-06-01T10:30:55Z

XVilka: Created page with "Deprecated page, I think it can be removed, as coreboot have nice Kconfig system and removed link. See discussion for this page too Talk:Build_coreboot_using_LBdistro"

Deprecated page, I think it can be removed, as coreboot have nice Kconfig system and removed link.
See discussion for this page too [[Talk:Build_coreboot_using_LBdistro]]

Talk:Build coreboot using LBdistro

2012-06-01T10:27:55Z

XVilka: Created page with "Deprecated page, I think it can be removed, as coreboot have nice Kconfig system."

Deprecated page, I think it can be removed, as coreboot have nice Kconfig system.

Libpayload

2012-06-01T10:23:54Z

XVilka: Fixed downloading from Subversion to Git

'''libpayload''' is a small BSD-licensed static library (a lightweight implementation of common and useful functions) intended to be used as a basis for coreboot [[payloads]].

The benefits of linking a coreboot payload against libpayload are:

* Payloads do not have to implement and maintain low-level code for I/O, common functions, etc.
* Payloads can be recompiled and deployed for CPU architectures supported by coreboot in the future.
* The libpayload functions can be tested and scrutinized outside payload development.
* Payloads themselves may be partly host-tested, e.g. against an emulation libpayload.

''Just give us a main() and a pocket full of dreams and we'll do the rest.''

== Features ==

* Provides a [[Libpayload#Libc_coverage|subset of libc functions]] (e.g. malloc, printf, strcmp, etc).
* Provides an optional tiny (n)curses implementation.
* Provides various small drivers for
** keyboard
** PC speaker
** NVRAM/CMOS access
** serial console
** VGA
** Geode framebuffer
** USB stack
* Reads and parses the coreboot table.

== Design ==

* [[Payload API|Discussion of the API for passing parameters to the payload]]

== Payloads using libpayload ==

* [[FILO]] is a bootloader which loads boot images from a local filesystem, without help from legacy BIOS services.
* [[coreinfo]] is a small payload which can display system information such as PCI info, or an NVRAM dump.
* [[GRUB invaders]] has been ported successfully to libpayload (patch pending).
* [[tint]] (a "falling blocks" game) has been successfully ported to libpayload.
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=scripts/kconfig/lxdialog;hb=HEAD lxdialog] from the Linux '''kconfig''' utility has been ported to be usable when linked with libpayload (patch pending).

== Downloading and building libpayload ==

It is now in main coreboot git tree (see [[Download_coreboot]] for additional reference)

$ '''git clone http://review.coreboot.org/p/coreboot'''
$ '''cd payloads/libpayload'''
$ '''make menuconfig'''
$ '''make install'''

Here [http://review.coreboot.org/#/q/status:open+project:coreboot+message:libpayload,n,z gerrit] you can find pending patches for libpayload

== Documentation ==

See the autogenerated documentation for libpayload [http://qa.coreboot.org/docs/libpayload/ here].

== Libc coverage ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Status
! align="left" | Function/Macro/Variable

|- bgcolor="#6699ff"
| colspan=2 | '''assert.h'''
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | no
| assert()

|- bgcolor="#6699ff"
| colspan=2 | '''ctype.h'''
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isalnum(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isalpha(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isascii(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isblanc(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int iscntrl(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isdigit(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isgraph(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int islower(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isprint(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int ispunct(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isspace(int character)
|-
|- bgcolor="#dddddd" valign="top"
| style="background:lime" | yes
| int isupper(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int isxdigit(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int tolower(int character)
|-
|- bgcolor="#eeeeee" valign="top"
| style="background:lime" | yes
| int toupper(int character)

|- bgcolor="#6699ff"
| colspan=2 | '''errno.h'''
|-
| style="background:lime" | no
| <code>errno</code> (global)

|- bgcolor="#6699ff"
| colspan=2 | '''float.h'''

|- bgcolor="#6699ff"
| colspan=2 | '''limits.h'''

|- bgcolor="#6699ff"
| colspan=2 | '''locale.h'''
|-
| style="background:red" | no
| <code>char *setlocale(int category, const char *locale)</code>
|-
| style="background:red" | no
| <code>struct lconv *localeconv(void)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''math.h'''
|-
| style="background:red" | no
| <code>double exp(double x)</code>
|-
| style="background:red" | no
| <code>double log(double x)</code>
|-
| style="background:red" | no
| <code>double log10(double x)</code>
|-
| style="background:red" | no
| <code>double pow(double x, double y)</code>
|-
| style="background:red" | no
| <code>double sqrt(double x)</code>
|-
| style="background:red" | no
| <code>double ceil(double x)</code>
|-
| style="background:red" | no
| <code>double floor(double x)</code>
|-
| style="background:red" | no
| <code>double fabs(double x)</code>
|-
| style="background:red" | no
| <code>double ldexp(double x, int n)</code>
|-
| style="background:red" | no
| <code>double frexp(double x, int* exp)</code>
|-
| style="background:red" | no
| <code>double modf(double x, double* ip)</code>
|-
| style="background:red" | no
| <code>double fmod(double x, double y)</code>
|-
| style="background:red" | no
| <code>double sin(double x)</code>
|-
| style="background:red" | no
| <code>double cos(double x)</code>
|-
| style="background:red" | no
| <code>double tan(double x)</code>
|-
| style="background:red" | no
| <code>double asin(double x)</code>
|-
| style="background:red" | no
| <code>double acos(double x)</code>
|-
| style="background:red" | no
| <code>double atan(double x)</code>
|-
| style="background:red" | no
| <code>double atan2(double y, double x)</code>
|-
| style="background:red" | no
| <code>double sinh(double x)</code>
|-
| style="background:red" | no
| <code>double cosh(double x)</code>
|-
| style="background:red" | no
| <code>double tanh(double x)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''setjmp.h'''
|-
| style="background:red" | no
| <code>int setjmp(jmp_buf env)</code>
|-
| style="background:red" | no
| <code>void longjmp(jmp_buf env, int val)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''signal.h'''
|-
| style="background:red" | no
| <code>void (*signal(int sig, void (*handler)(int)))(int)</code>
|-
| style="background:red" | no
| <code>int raise(int sig)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''stdarg.h'''
|-
| style="background:red" | no
| <code>void va_start(va_list ap, lastarg)</code>
|-
| style="background:red" | no
| <code>type va_arg(va_list ap, type)</code>
|-
| style="background:red" | no
| <code>void va_end(va_list ap)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''stddef.h'''

|- colspan=2
| TODO

|- bgcolor="#6699ff"
| colspan=2 | '''stdio.h'''
|-
| style="background:red" | no
| <code>FILE* fopen(const char* filename, const char* mode)</code>
|-
| style="background:red" | no
| <code>FILE* freopen(const char* filename, const char* mode, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fflush(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fclose(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int remove(const char* filename)</code>
|-
| style="background:red" | no
| <code>int rename(const char* oldname, const char* newname)</code>
|-
| style="background:red" | no
| <code>FILE* tmpfile()</code>
|-
| style="background:red" | no
| <code>char* tmpnam(char s[L_tmpnam])</code>
|-
| style="background:red" | no
| <code>int setvbuf(FILE* stream, char* buf, int mode, size_t size)</code>
|-
| style="background:red" | no
| <code>void setbuf(FILE* stream, char* buf)</code>
|-
| style="background:red" | no
| <code>int fprintf(FILE* stream, const char* format, ...)</code>
|-
| style="background:lime" | yes
| <code>int printf(const char* format, ...)</code>
|-
| style="background:lime" | yes
| <code>int sprintf(char* s, const char* format, ...)</code>
|-
| style="background:lime" | yes
| <code>int snprintf(char* s, size_t size, const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int vfprintf(FILE* stream, const char* format, va_list arg)</code>
|-
| style="background:lime" | yes
| <code>int vprintf(const char* format, va_list arg)</code>
|-
| style="background:lime" | yes
| <code>int vsprintf(char* s, const char* format, va_list arg)</code>
|-
| style="background:lime" | yes
| <code>int vsnprintf(char* s, size_t size, const char* format, va_list arg)</code>
|-
| style="background:red" | no
| <code>int fscanf(FILE* stream, const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int scanf(const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int sscanf(char* s, const char* format, ...)</code>
|-
| style="background:red" | no
| <code>int fgetc(FILE* stream)</code>
|-
| style="background:red" | no
| <code>char* fgets(char* s, int n, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fputc(int c, FILE* stream)</code>
|-
| style="background:red" | no
| <code>char* fputs(const char* s, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int getc(FILE* stream)</code>
|-
| style="background:lime" | yes
| <code>int getchar(void)</code>
|-
| style="background:red" | no
| <code>char* gets(char* s)</code>
|-
| style="background:red" | no
| <code>int putc(int c, FILE* stream)</code>
|-
| style="background:lime" | yes
| <code>int putchar(int c)</code>
|-
| style="background:lime" | yes
| <code>int puts(const char* s)</code>
|-
| style="background:red" | no
| <code>int ungetc(int c, FILE* stream)</code>
|-
| style="background:red" | no
| <code>size_t fread(void* ptr, size_t size, size_t nobj, FILE* stream)</code>
|-
| style="background:red" | no
| <code>size_t fwrite(const void* ptr, size_t size, size_t nobj, FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fseek(FILE* stream, long offset, int origin)</code>
|-
| style="background:red" | no
| <code>long ftell(FILE* stream)</code>
|-
| style="background:red" | no
| <code>void rewind(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int fgetpos(FILE* stream, fpos_t* ptr)</code>
|-
| style="background:red" | no
| <code>int fsetpos(FILE* stream, const fpos_t* ptr)</code>
|-
| style="background:red" | no
| <code>void clearerr(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int feof(FILE* stream)</code>
|-
| style="background:red" | no
| <code>int ferror(FILE* stream)</code>
|-
| style="background:red" | no
| <code>void perror(const char* s)</code>

|}

| valign="top"|

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Status
! align="left" | Function/Macro/Variable

|- bgcolor="#6699ff"
| colspan=2 | '''stdlib.h'''
|-
| style="background:lime" | yes
| <code>int abs(int n)</code>
|-
| style="background:lime" | yes
| <code>long labs(long n)</code>
|-
| style="background:lime" | yes
| <code>long long llabs(long long n)</code>
|-
| style="background:red" | no
| <code>div_t div(int num, int denom)</code>
|-
| style="background:red" | no
| <code>ldiv_t ldiv(long num, long denom)</code>
|-
| style="background:red" | no
| <code>double atof(const char* s)</code>
|-
| style="background:red" | no
| <code>int atoi(const char* s)</code>
|-
| style="background:red" | no
| <code>long atol(const char* s)</code>
|-
| style="background:red" | no
| <code>double strtod(const char* s, char** endp)</code>
|-
| style="background:lime" | no
| <code>long strtol(const char* s, char** endp, int base)</code>
|-
| style="background:lime" | yes
| <code>unsigned long strtoul(const char* s, char** endp, int base)</code>
|-
| style="background:lime" | yes
| <code>void* calloc(size_t nobj, size_t size)</code>
|-
| style="background:lime" | yes
| <code>void* malloc(size_t size)</code>
|-
| style="background:lime" | yes
| <code>void* realloc(void* p, size_t size)</code>
|-
| style="background:lime" | yes
| <code>void free(void* p)</code>
|-
| style="background:lime" | yes
| <code>void * memalign (size_t align, size_t size)</code>
|-
| style="background:lime" | yes
| <code>void abort()</code>
|-
| style="background:lime" | no
| <code>void exit(int status)</code>
|-
| style="background:red" | no
| <code>int atexit(void (*fcm)(void))</code>
|-
| style="background:red" | no
| <code>int system(const char* s)</code>
|-
| style="background:red" | no
| <code>char* getenv(const char* name)</code>
|-
| style="background:red" | no
| <code>void* bsearch(const void* key, const void* base, size_t n, size_t size, int (*cmp)(const void* keyval, const void* datum))</code>
|-
| style="background:red" | no
| <code>void qsort(void* base, size_t n, size_t size, int (*cmp)(const void*, const void*))</code>
|-
| style="background:lime" | yes
| <code>int rand(void)</code>
|-
| style="background:lime" | yes
| <code>void srand(unsigned int seed)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''string.h'''
|-
| style="background:lime" | yes
| <code>char* strcpy(char* s, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strncpy(char* s, const char* ct, size_t n)</code>
|-
| style="background:lime" | no
| <code>char* strcat(char* s, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strncat(char* s, const char* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>int strcmp(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>int strncmp(const char* cs, const char* ct, size_t n)</code>
|-
| style="background:red" | no
| <code>int strcoll(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strchr(const char* cs, int c)</code>
|-
| style="background:lime" | no
| <code>char* strrchr(const char* cs, int c)</code>
|-
| style="background:lime" | no
| <code>size_t strspn(const char* cs, const char* ct)</code>
|-
| style="background:lime" | no
| <code>size_t strcspn(const char* cs, const char* ct)</code>
|-
| style="background:red" | no
| <code>char* strpbrk(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>char* strstr(const char* cs, const char* ct)</code>
|-
| style="background:lime" | yes
| <code>size_t strlen(const char* cs)</code>
|-
| style="background:lime" | yes
| <code>size_t strnlen(const char* cs, size_t maxlen)</code>
|-
| style="background:lime" | yes
| <code>char * strdup (const char *s)</code>
|-
| style="background:red" | no
| <code>char* strerror(int n)</code>
|-
| style="background:lime" | no
| <code>char* strtok(char* s, const char* t)</code>
|-
| style="background:lime" | no
| <code>char* strtok_r(char* s, const char* t, char **p)</code>
|-
| style="background:red" | no
| <code>size_t strxfrm(char* s, const char* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>void* memcpy(void* s, const void* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>void* memmove(void* s, const void* ct, size_t n)</code>
|-
| style="background:lime" | yes
| <code>int memcmp(const void* cs, const void* ct, size_t n)</code>
|-
| style="background:red" | no
| <code>void* memchr(const void* cs, int c, size_t n)</code>
|-
| style="background:lime" | yes
| <code>void* memset(void* s, int c, size_t n)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''time.h'''
|-
| style="background:red" | no
| <code>clock_t clock(void)</code>
|-
| style="background:lime" | yes
| <code>int gettimeofday (struct timeval *tv, void *tz)</code>
|-
| style="background:red" | no
| <code>time_t time(time_t* tp)</code>
|-
| style="background:red" | no
| <code>double difftime(time_t time2, time_t time1)</code>
|-
| style="background:red" | no
| <code>time_t mktime(struct tm* tp)</code>
|-
| style="background:red" | no
| <code>char* asctime(const struct tm* tp)</code>
|-
| style="background:red" | no
| <code>char* ctime(const time_t* tp)</code>
|-
| style="background:red" | no
| <code>struct tm* gmtime(const time_t* tp)</code>
|-
| style="background:red" | no
| <code>struct tm* localtime(const time_t* tp)</code>
|-
| style="background:red" | no
| <code>size_t strftime(char* s, size_t smax, const char* fmt, const struct tm* tp)</code>

|- bgcolor="#6699ff"
| colspan=2 | '''unistd.h'''
|-
| style="background:lime" | yes
| <code>int exec (long addr, int argc, char **argv)</code>

|}
|}

== Usage example ==

Here's an example of a very simple payload (hello.c) and how to build it:

<source lang="C">
#include <libpayload.h>

int main(void)
{
printf("Hello, world!\n");
halt();
return 0;
}
</source>

Building the payload:

$ '''lpgcc -o hello.elf hello.c'''

{{PD-self}}

QEMU

2011-03-25T19:14:20Z

XVilka: Added notes about debugging coreboot with qemu

You can easily try out coreboot using [http://qemu.org/ QEMU], without having to actually flash the BIOS chip on your real hardware.

== Tutorials ==

* [[QEMU Build Tutorial]] — Starting a Debian GNU/Linux system via coreboot + a Linux kernel, or via coreboot + [[FILO]].
* [[FreeBSD|Booting FreeBSD using coreboot]] — Booting FreeBSD via coreboot + ADLO.

== Ready-made QEMU images ==

Below is a list of various downloadable QEMU images you can use to try out coreboot.

You need a patched version of '''vgabios-cirrus.zip''' for these images to work fine, the version in QEMU's CVS repository does '''not''' yet work. The image from Debian's QEMU package ('''/usr/share/qemu/vgabios-cirrus.bin''') is already patched and works, too.

=== coreboot v2 + SeaBIOS ===

[[File:Qemu seabios.png|thumb|right|[[SeaBIOS]] payload.]]

[[SeaBIOS]] is an open-source legacy BIOS implementation which can be used as a coreboot payload. It implements the standard BIOS calling interfaces that a typical x86 proprietary BIOS implements.

The QEMU image uses coreboot v2 (r4917) and [[SeaBIOS]] (9eebe66a9978165cfa91f2266c97fa5d0aa6ef2e, 2009-11-04) with the following changes to the default '''src/config.h''':

#define CONFIG_COREBOOT 1
#define CONFIG_DEBUG_SERIAL 1
#define CONFIG_COREBOOT_FLASH 1
#define CONFIG_OPTIONROMS_DEPLOYED 0
#define CONFIG_VGAHOOKS 1

Usage:

mkdir foo
cd foo
wget http://www.coreboot.org/images/6/6a/Qemu_coreboot_seabios.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_seabios.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_seabios.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

Replace '''/dev/zero''' above with a real QEMU disk image to actually boot something.

=== coreboot v3 + FILO ===

[[Image:Qemu filo.png|thumb|right|[[FILO]] payload.]]

[[FILO]] is a simple bootloader which can load (e.g.) Linux kernels from disk.

The QEMU image uses coreboot v3 (r672) and [[FILO]] (r45) with a certain configuration (for example: it's looking for '''/boot/grub/menu.lst''' on hda1).

mkdir foo
cd foo
wget http://www.coreboot.org/images/b/b9/Qemu_coreboot_filo.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_filo.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_filo.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

Replace '''/dev/zero''' above with a real QEMU disk image which has a '''/boot/grub/menu.lst''' on '''hda1''' to actually boot something.

=== coreboot v3 + libpayload + coreinfo ===

[[Image:Coreinfo nvram.png|thumb|right|[[coreinfo]] NVRAM dump.]]

This is a small payload called [[coreinfo]].

mkdir foo
cd foo
wget http://www.coreboot.org/images/0/06/Qemu_coreboot_coreinfo.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_coreinfo.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_coreinfo.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + invaders ===

[[Image:Coreboot invaders.png|thumb|right|[[GRUB invaders]] as payload.]]

mkdir foo
cd foo
wget http://www.coreboot.org/images/c/c8/Qemu_coreboot_invaders.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_invaders.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_invaders.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + libpayload + tint ===

[[Image:Coreboot libpayload tint.png|thumb|right|[[tint]] as payload.]]

This is coreboot v3 (r656), [[libpayload]] (r3225), and tint 0.03b patched to be built against libpayload.

mkdir foo
cd foo
wget http://www.coreboot.org/images/6/62/Qemu_libpayload_tint.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_libpayload_tint.zip
unzip Vgabios-cirrus.zip
mv qemu_libpayload_tint.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + Memtest86 ===

[[Image:Qemu memtest.png|thumb|right|[[Memtest86]] payload.]]

This is coreboot v3 (r656) and [[Memtest86]] (3.4) with serial support enabled. The VGA display in QEMU is broken after a few seconds, this is a known issue, but we don't yet know what exactly the problem is.

mkdir foo
cd foo
wget http://www.coreboot.org/images/3/33/Qemu_coreboot_memtest.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_memtest.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_memtest.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

=== coreboot v3 + OpenBIOS ===

[[Image:Qemu coreboot openbios.png|thumb|right|[[OpenBIOS]] payload.]]

This is coreboot v3 (r672) and [[OpenBIOS]] (r186).

mkdir foo
cd foo
wget http://www.coreboot.org/images/9/9d/Qemu_coreboot_openbios.zip
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip
unzip Qemu_coreboot_openbios.zip
unzip Vgabios-cirrus.zip
mv qemu_coreboot_openbios.bin bios.bin
cd ..
qemu -L foo -hda /dev/zero -serial stdio

== Debugging ==

You can use embedded gdbserver features inside qemu.
For example to start gdbserver on localhost 1234 port you need add "-s" option.
Also it's very useful add "-S" option to stop qemu at the start, so you can run
booting process from gdb

qemu -L . -bios coreboot.rom -nographic -s -S

And then you can use gdb for debugging coreboot:
gdb> target remote localhost:1234
gdb> bt [some_address]
gdb> run
gdb> i r

For improve gdb output you can add this to ~/.gdbinit file:
set history save on
set disassembly-flavor intel
display/4i $pc

Also tracing option available in qemu "-d"
You only need choose trace level: in_asm, exec, cpu, out_asm
And qemu place tracing log at the /tmp/qemu.log

{{PD-self}}

GSoC

2011-03-18T20:19:42Z

XVilka: /* Multiple GUIs for flashrom */ - fixes

= Google Summer of Code 2011 =

http://1.bp.blogspot.com/-61a6mHfP1bU/TWbmtb5TAAI/AAAAAAAAABo/w56YXLjXDGY/s400/GSOC_2011_300x200px.png

Welcome to the [http://www.google-melange.com/ Google Summer of Code(tm)] page of the [[Welcome to coreboot|coreboot project]].

Apply for a coreboot GSoC project at: http://www.google-melange.com/gsoc/org/show/google/gsoc2011/coreboot

This year, coreboot also tries to host some flashrom projects.

== Deadlines ==

Make sure you check the https://socghop.appspot.com/document/show/gsoc_program/google/gsoc2011/timeline

= Why work for coreboot =

Why would you like to work for coreboot?

* coreboot offers you the opportunity to work with modern technology "right on the iron".
* Your application will be available to users worldwide and promoted along with all other coreboot projects.
* We are a very passionate team - so you will interact directly with the project initiators and project leaders.
* We have a large, helpful community. Over 100 experts in hardware and firmware lurk on our mailing list, many of them waiting to help you.

= Summer of Code Application =

Please complete the standard Google SoC 2011 application. Prospective corebot GSoC student should provide the following information as part of their application.

:Name:
:Email:
:IM/IRC/Skype/other contact:

:Country/Timezone:
:School:
:Degree Program:
:Year:

:Most students have some time off planned during GSoC. Do you have any vacations? When and how long?

:coreboot welcomes students from all backgrounds and levels of experience. To be seriously consider for coreboot GSoC, we recommend joining the mailing list and IRC channel. Introduce yourself and mention that you are a prospective GSoC student. Ask questions and discuss the project that you are considering. Community involvement is a key component of coreboot development. By the time you have submitted your application, you should have downloaded, built a and booted coreboot in QEMU, SimNow, or on real hardware. Please, email your serial output results to the mailing list.

:The following information will help coreboot match students with mentors and projects.

:Please comment on your software and firmware experience.

:Have you participated in the coreboot community before?

:Have you contributed to an open source project? Which one? What was your experience?

:Have you built and run coreboot? Did you have problems?

:Bonus, Did you find and fix a coreboot bug? Did you send a patch to the email list?

:Please provide an overview of your project and a break down your project in small specific goals. Explain what risks or potential problems your project might experience. What would you expect as a minimum level of success? Do you have a stretch goal?

Feel free to keep your application short. A 15 page essay is no better than a 2 page summary. If you wish to write 15 pages, you are of course welcome to do so, and we will gladly put your paper up on the web page. But it is not required for the application.

== How to apply ==

The Drupal project has a great page on [http://drupal.org/node/59037 How to write an SOC application].

Please also read Google's [http://code.google.com/p/google-summer-of-code/wiki/AdviceforStudents Advice for Students].

== Some Caveats ==

* Google Summer-of-Code projects are a full (day-) time job. This means we expect roughly 30-40 hours per week on your project, during the three months of coding. Obviously we have flexibility, but if your schedule (exams, courses) does not give you this amount of spare time, then maybe you should not apply.
* Getting paid by Google requires that you meet certain milestones. First, you must be in good standing with the community before the official start of the program. We suggest you post some design emails to the mailing list, and get feedback on them, both before applying, and during the "community bonding period" between acceptance and official start. Also, you must have made progress and committed significant code before the mid-term point.
* We require accepted students to have a blog, where you will write about your project on a regular basis. This is so that the community at large can be involved and help you. SoC is not a private contract between your mentor and you. http://blogs.coreboot.org/

Note that "regular basis" in the last item does _not_ mean "3 days before evaluation deadlines". You should be "around" all the time (reporting your feedback, sending in partial successes).
We don't expect our students to be experts in our problem domain, but we don't want you to fail because some basic misunderstanding was in your way of completing the task.

== Time Frame ==

'''DEADLINE FOR STUDENT APPLICATIONS:''' Students who are interested in working on a coreboot-related GSoC project must apply between '''March 28, 2011''' and '''April 8, 2011'''! If you want to apply, please get in contact with us right away, not just when you send your application!

== Student requirements ==

We will only accept your proposal if you have demonstrated that you can work with our codebase. For that, you have to send a patch to the list which is acceptable. Just ask for simple tasks on the mailing list or on IRC.

= Contact =

If you are interested in becoming a GSoC student, please contact [mailto:marcj303@gmail.com Marc Jones].

There is also an IRC channel on irc.freenode.net: #coreboot

= Possible ideas =
The following are some ideas that have come up in the community. Some are more or less suitable for GSoC and prospective students' application should expand on some ideas and pair back others.

== flashrom ==

Note: The list below is an idea collection. Individual list items are simple enough to serve only as partial GSoC task, but they are grouped to reasonable tasks. If you're interested, please talk to us on the flashrom mailing list and/or on IRC irc://irc.freenode.net/#flashrom

''[http://www.flashrom.org/GSoC/2010 http://www.flashrom.org/GSoC/2010] has more flashrom ideas and suggestions.''

=== Multiple UIs for flashrom ===
* flashrom TUI (text mode user interface) (for command line and flashrom-as-payload)
* flashrom GUI (graphics mode user interface) (should be cross-platform, Sean Nelson has preliminary code you can base this on)

=== Recovery of dead boards and onboard flash updates ===
* flashrom as payload
* flashrom remote flashing for coreboot panic room mode
* flashrom remote flashing with modified SerialICE

=== SPI bitbanging hardware support ===
* flashrom support for Nvidia SPI chipset hardware
* flashrom support for RayeR SPIPGM hardware
* flashrom support for [[Paraflasher]] hardware
* flashrom support for Willem hardware
* flashrom support for some-yet-uninvented cheap universal LPC/FWH/SPI flasher hardware
* flashrom support for bitbanging LPC/FWH (code exists, Uwe Hermann
* flashrom support for bitbanging Parallel

=== Generic flashrom infrastructure improvements ===
* flashrom support for automatic recovery in case something goes wrong
* flashrom support for partial reflashing
* flashrom support for bytewise flashing (similar to the point above)

== Infrastructure for automatic code checking ==
We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
* Use LLVM's static code checking facilities, report regressions.
* Work on code coverage support for coreboot code (dump data into ram, or via serial. Provide tools to fetch it). Analyse that data.

=== Links ===
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker]
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]
* Coverage: [http://ltp.sourceforge.net/test/coverage/lcov.php LCOV], [http://ggcov.sourceforge.net GGCOV]

=== Mentors ===
* [[User:Stepan|Stefan Reinauer]]

== coreboot ports for Family14 mainboards ==
Identify potential mainboards to port based on the recently released AMD Family 14 support. The goal would be to support publicly available plaftorms with a number of payloads and operating systems.

=== Mentor ===
*

== coreboot ACPI/S3/power managment ==
coreboot has support for ACPI tables and S3 support for some platforms, but it is very mainboard specific. Create a generic solution for ACPI table generation and S3 support.

=== Mentor ===
*

== coreboot test suite ==
Create a test suite to gather and report coreboot mainboard and payload settings. This project may leverage libpayload, coreinfo, memtest86, BITS, and other tools. The goal is to help coreboot developers identify problems and to test coreboot features.

=== Links ===
* [http://biosbits.org/ BITS]

=== Mentor ===
*

==coreboot port to Marvell ARM SOC's with PCIe==
[http://www.marvell.com/products/processors/embedded/kirkwood/ Marvell Processors] These ARM SOC's with PCIe will become popular in netbooks later this year. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.

Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family.
We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed.

=== Mentors ===
* Bari Ari
* [[User:Rminnich|Ron Minnich]]

== coreboot panic room ==

Create a safe boot solution for coreboot to easily and cheaply recover the system in case of a panic().

Ron would like to base this solution around SerialICE. The basic idea is that the system always boots to SerialICE. There is a test in CMOS for 'last boot worked' and, if this is set, SerialICE finds a coreboot in cbfs and runs it. If 'last boot worked' is not set, or the user hits some magic keyboard sequence, SerialICE takes control.

SerialICE needs to be extended (not much) to make this work. Having this capability would make it possible for Ron to get some very hard ports working that are just not possible today. At the same time, there are lots of hardware boards to test this idea on, so it should be easy to get it working.

It might be possible to integrate this into the coreboot build as a bootblock option (in the same spot as the fallback/normal switch and the simple loader).

=== Mentors ===
* [[User:Rminnich|Ron Minnich]]

== coreboot cheap testing rig ==
The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/Slides-LinuxBIOS-QA.pdf Quality Assurance Talk (Slides)]
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestIntegrationManual.pdf Test Integration Manual]
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/DevelopersManual.pdf Test Developers Manual]
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestSpecification.pdf Test Specification]

The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as X10, it's possible to drop the testing costs per board significantly.

=== Links ===
* http://qa.coresystems.de

=== Mentors ===
* [[User:Stepan|Stefan Reinauer]]

== Board config infrastructure ==

Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.

=== Links ===
* ?

=== Mentors ===
* ?

== Refactor AMD code ==

AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.

=== Links ===
* ?

=== Mentors ===
* [[User:Stepan|Stefan Reinauer]]

=== Laptop support ===

This one is really HARD. If you're lucky and if you have datasheets, you can do it in maybe 1 month. If you're unlucky, it can take the whole GSoC or more. If there is interest, we'll try to find an embedded controller which won't cause you to give up in frustration. Still, it might be beneficial if you're willing to solder.
* flashrom support for embedded controllers (ECs) in laptops

=== Links ===
* [http://www.flashrom.org/ flashrom]

=== Mentors ===
* ?

== Your own Project Ideas ==

We have come up with some ideas for cool Summer of Code projects here. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases.

But of course your application does not need to be based on any of the ideas listed below. The opposite: Maybe you have a great idea that we just didn't think of yet. Please let us know!

Feel free to contact us at the email address above, and don't hesitate to suggest whatever you have in mind.

= Previous Summer of Code projects =

We successfully participated in Google's Summer of Code in 2007, 2008, 2009, and 2010. See our [[Previous GSoC Projects|list of previous GSoC projects]].

XML

2011-02-15T18:19:04Z

XVilka: Added XML definitions

== Targets ==

* msrtool (partially done)
* superiotool (partially done)
* inteltool

== Possible ways ==

* Codegeneration (already implemented - see https://bitbucket.org/droiddev/pygen/wiki/Home )
* Use xml format always - read/write it in runtime
* Embedding data from xml files into target elf file at build stage.

Now, we think, preffered way - embedding data from xml into elf file

== Output ==

Improve possibility of export/output in XML format for easy automated parse output of utils

== Sample ==

Example for Super I/O definitions:
<pre>
<?xml version="1.0" encoding="UTF-8"?>
<sioarray name="ite" description="ite superios">
<sio model="IT8228E" id="0x8228" >
</sio>
<sio model="IT8500B/E" id="0x8500" >
<noldn>
<reg address="0x20" default_value="0x85" />
<reg address="0x21" default_value="0x0" />
<reg address="0x22" default_value="0x1" />
<reg address="0x23" default_value="0x1" />
<reg address="0x25" default_value="0x0" />
<reg address="0x2d" default_value="0x0" />
<reg address="0x2e" default_value="NANA" />
<reg address="0x2f" default_value="NANA" />
<reg address="0x30" default_value="0x0" />
</noldn>
<ldn number="0x4" name="System Wake-Up Control (SWUC)" description="">
<reg address="0x30" default_value="0x0" />
<reg address="0x60" default_value="0x0" />
<reg address="0x61" default_value="0x0" />
<reg address="0x62" default_value="0x0" />
<reg address="0x63" default_value="0x0" />
<reg address="0x70" default_value="0x0" />
<reg address="0x71" default_value="0x1" />
</ldn>
</sio>
<sio model="IT8513E/F/G" id="0x8513" >
</sio>
</sioarray>
</pre>

Example for MSR definitions
<pre>
<?xml version="1.0" encoding="UTF-8"?>
<msrarray name="k8" description="bla-bla">
<cpu family="0x6" model="0x17" stepping="5" />
<msr address="0xc0000080" type="rw" name="EFER Register" description="Extended Feature Enable Register">
<bitfield start="63" size="32" name="RSVD" description="Reserved" type="hex">
</bitfield>
<bitfield start="31" size="18" name="RSVD" description="Reserved" type="hex">
</bitfield>
<bitfield start="14" size="1" name="FFXSR:" description="Fast FXSAVE/FRSTOR Enable" type="dec">
<value number="0" description="FXSAVE/FRSTOR disabled" />
<value number="1" description="FXSAVE/FRSTOR enabled" />
</bitfield>
<bitfield start="13" size="1" name="LMSLE:" description="Long Mode Segment Limit Enable" type="dec">
<value number="0" description="Long mode segment limit check disabled" />
<value number="1" description="Long mode segment limit check enabled" />
</bitfield>
</msr>
</msrarray>
</pre>

== First goal ==

We need unify XML format data:
<pre>
<?xml version="1.0" encoding="UTF-8"?>
<domain name="MSR" description="CPU Model Specific Registers definitions">
<regarray name="k8" vendor="AMD" description="AMD K8 CPU definitions" type="msrarray">
<reg type="msr" address="0xc0000080" type="rw" name="EFER Register" description="Extended Feature Enable Register">
<bitarray start="13" size="1" name="LMSLE:" description="Long Mode Segment Limit Enable" type="dec">

<value number="0" description="Long mode segment limit check disabled" />
<value number="1" description="Long mode segment limit check enabled" />
</bitarray>
</reg>
</regarray>
</domain>
<domain name="SIO" description="Super I/O defitions">
<regarray name="it8500" vendor="ITE" description="ITE IT8500 definitions" type="sioarray">
<reg type="sio" address="0x80" type="rw" name="Some Register" description="Extended Feature Enable Register">
<value number="0" description="Long mode segment limit check disabled" />
<value number="1" description="Long mode segment limit check enabled" />
</reg>
</domain>
</pre>

== Possible features, other ideas ==

Use gzip or lzma-packed xml base

Infrastructure Projects

2011-02-15T18:02:28Z

XVilka: Added XML-project page link and small description

This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.

= In progress =

== Low/High Tables ==

SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.

'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor/chipset
! align="left" | Tested
! align="left" | Comments

|- bgcolor="#eeeeee"
| amd/amdfam10
| ?
| —
|- bgcolor="#eeeeee"
| amd/amdht
| ?
| —
|- bgcolor="#eeeeee"
| amd/amdk8
| ?
| —
|- bgcolor="#eeeeee"
| amd/amdmct
| ?
| —
|- bgcolor="#eeeeee"
| amd/gx1
| ?
| —
|- bgcolor="#eeeeee"
| amd/gx2
| ?
| —
|- bgcolor="#eeeeee"
| amd/lx
| ?
| —
|- bgcolor="#eeeeee"
| intel/e7501
| ?
| —
|- bgcolor="#eeeeee"
| intel/e7520
| ?
| —
|- bgcolor="#eeeeee"
| intel/e7525
| ?
| —
|- bgcolor="#eeeeee"
| intel/i3100
| ?
| —
|- bgcolor="#eeeeee"
| intel/i440bx
| ?
| —
|- bgcolor="#eeeeee"
| intel/i82810
| ?
| —
|- bgcolor="#eeeeee"
| intel/i82830
| ?
| —
|- bgcolor="#eeeeee"
| intel/i855
| ?
| —
|- bgcolor="#eeeeee"
| intel/i945
| style="background:lime" | Y
| Tested on Kontron 986LCD-M and Roda RK886EX
|- bgcolor="#eeeeee"
| via/cn400
| ?
| —
|- bgcolor="#eeeeee"
| via/cn700
| style="background:lime" | Y
| Tested on VIA pc2500e.
|- bgcolor="#eeeeee"
| via/cx700
| ?
| —
|- bgcolor="#eeeeee"
| via/vt8601
| ?
| —
|- bgcolor="#eeeeee"
| via/vt8623
| ?
| —
|- bgcolor="#eeeeee"
| via/vx800
| ?
| —

|}

'''Developers:''' Stefan

== CBFS ==

A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).

'''Status:'''

Upstream, pre-CBFS infrastructure removed.

There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.

Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.

All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Vendor/chipset
! align="left" | ROM enabled
! align="left" | Tiny bootblock
! align="left" | Status / Comments

|- bgcolor="#eeeeee"
| amd/amd8111
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.
|- bgcolor="#eeeeee"
| amd/cs5530
| style="background:lime" | Y
| style="background:red" | N
| Not tested on hardware, yet.
|- bgcolor="#eeeeee"
| amd/cs5535
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| amd/cs5536
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| amd/sb600
| style="background:yellow" | Y
| style="background:yellow" | Y
| —
|- bgcolor="#eeeeee"
| amd/sb700
| style="background:yellow" | Y
| style="background:yellow" | Y
| —

|- bgcolor="#dddddd"
| broadcom/bcm5785
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.

|- bgcolor="#eeeeee"
| intel/esb6300
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i3100
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82371eb
| style="background:lime" | Y
| style="background:yellow" | Y
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]].
|- bgcolor="#eeeeee"
| intel/i82801ax
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801bx
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801cx
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801dx
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801ex
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| intel/i82801gx
| style="background:red" | N
| style="background:red" | N
| —

|- bgcolor="#dddddd"
| nvidia/ck804
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.
|- bgcolor="#dddddd"
| nvidia/mcp55
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.

|- bgcolor="#dddddd"
| sis/sis966
| style="background:yellow" | Y
| style="background:yellow" | Y
| Not tested on hardware, yet.

|- bgcolor="#eeeeee"
| via/vt8231
| style="background:yellow" | Y
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| via/vt8235
| style="background:red" | N
| style="background:red" | N
| —
|- bgcolor="#eeeeee"
| via/vt8237r
| style="background:yellow" | Y
| style="background:yellow" | Y
| —
|- bgcolor="#eeeeee"
| via/vt82c686
| style="background:red" | N
| style="background:red" | N
| —

|}

'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe

== Tiny Bootblock ==

Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).

'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).

'''Developers:''' Patrick

== Remove .c includes ==

Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.

'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately.

'''Developers:''' Patrick, Uwe

== Move configuration to Kconfig ==

Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig. <code>util/lint/lint-001-no-global-config-in-romstage</code> helps figuring out what remains to be done.

'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage.

'''Developers:''' Patrick, Uwe

== Unify ACPI ==
* Also, figure out generic ACPI code and deduplicate it.

Done:
* Every ACPI board has its own routines to compile the ACPI sources. Unify that.

== Post codes ==

Find all outb(x, 0x80) and replace them with post_code(). Use common numbers / defines across the boards.

= More ideas =

== CMOS handling ==

The subprojects are ordered in a way that minimizes lost work.

=== Simplify get_option ===
Replace <code>get_option(VALstart, VALlen, default)</code> with a macro that hides start/len in something like <code>get_option(VAL, default)</code>

=== Use nvramtool for static option table creation ===
Instead of maintaining two tools (build_opt_tbl, nvramtool), maintain only one. This mostly requires adding an binary output writer to nvramtool, a cmos.layout parser already exists

=== Implement a new cmos.layout format ===
The current layout is simple to parse, but not so simple to maintain or extend.
Create a format that combines the various fields into a single representation, eg.

<code>
400/8 century enum { 0x19="1900", 0x20="2000", 0x21="2100" }

408/512 some_string string

984/16 checksum checksum 392 983
</code>

=== Implement an include statement ===
That way, we can have global fields (RTC, century byte), per chipset component fields (defined by northbrigde/southbridge/superio), per mainboard fields at their appropriate places.

=== CMOS defaults ===
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.
In the above format, it could simply be a suffix <code>default=VALUE</code>
Also drop the "default" argument in get_options. As components have their own cmos.layout snippets, we can always take those definitions' defaults, even if mainboards don't make use of CMOS themselves.

=== Value overrides ===
A chipset might provide options (eg. SATA/IDE) that a board might override (eg. because it doesn't provide IDE even if the chipset would support it). Allow the mainboard to override config options. This wouldn't just set a new default, but drop the option from CMOS entirely, hardcoding the value in the build. Some autogenerated #ifdef/#define magic might help there.

=== Provide update paths and avoid conflicts in addressing ===
Research topic: How could updates to nvram configuration (eg. new fields) be handled safely, and how could we get away from carving out the CMOS memory space manually? (one proposal: http://article.gmane.org/gmane.linux.bios/64572)

== Unify UMA / onboard video code and config ==

Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.

== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==

Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.

* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.

== Kconfig TODO ==

Notes / Style guide:

* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.
* Use '''bool''' instead of '''boolean'''.
* Use '''default n''' instead of '''default false'''.

Various post-conversion things to consider:

* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)
** ...

Stuff to port from v3 to v4:

* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).
* Some remaining useful Kconfig options.

== USB Debug Console ==

Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.

== Clean up Assembler / Linker mess ==

* Drop / combine / normalize .ld/.lb/.lds linker scripts.
* Move them to a common place.
* Drop / combine / normalize .inc / .S files.

== Geode issues ==

* Fix / Unify vsmsetup.c.
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.

== Use central oprom init ==

* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.
* Use the realmode code for vsmsetup too.

== Stack and Suspend/Resume ==

* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.

== Fix Suspend/Resume on AMD64 ==

* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.

== printk into buffer ==

Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).

Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).

== Global variables ==

* Port the global variables framework from v3.
* Make use of it where appropriate.

== Clear phases in romstage ==

* Split up the code (esp. in romstage) into more sensibly separated phases.
* Maybe use v3 for inspiration where the lines can be drawn.

== Refactor SMBUS code ==

We have tons of duplication in the smbus/spd related functions and #defines. Every chipset (and sometimes board) does the same with the exception of the 2 or 3 boards that multiplex spd roms.
* Deduplicate SMBUS related defines, they're virtually everywhere (and all the same)
* Deduplicate the lowlevel functions - they should really be the same (except for some style differences)
* Deduplicate the non-multiplexing highlevel functions. Mark them weak, so multiplexing boards can simply provide their own variant, which override the weak functions automatically

== Move all registers/chip definitions in XML format for all tools ==

For easy creating definitions of new chips, or editing old register definitions, improve readability support, and add support for humanless parsing the logs we decide move all data for msrtool, inteltool, superiotool, etc in XML-based format. See here: [[XML]]

= Finished =

== Port v3 Resource Allocator ==

The v3 resource allocator should be ported to v4.

'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.

'''Developers:''' Myles

== Config & Build System ==

The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.

'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!

'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi

== Unify text printing functions ==

There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).

'''Status:''' Finished.

'''Developers:''' Patrick, Stefan

== Common payload location ==

Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".

'''Status:''' Finished.

== Fix ALL build warnings ==

* Someone has to do the deed.

'''Status:''' Finished, the build usually issues no warnings. If you see warnings/errors, please report a bug.

Dell Vostro V13

2010-12-18T18:05:07Z

XVilka: Added ODM info

Dell Vostro V13 - laptop with ICH-9M chipset.

It manufactured by Inventec - board name 6050A2296601-MB-A02 P08S2

== Hardware ==

'''Overview:'''

* '''Northbridge:''' Mobile Intel GS45 Express GHMC with integrated video
* '''Southbridge:''' Intel I/O Controller Hub 9-ME (ICH9M-E) 82801IEM
* '''Super I/O:''' ITE IT8502E
** The Super I/O also "contains" the embedded controller (EC), which is an 8051 derivate.
* '''Audio controller:'''
* '''ExpressCard controller:'''
* '''ROM/BIOS chip:''' Winbond 25Q16BVSIG (SOIP/PDIP, 2 Mb, SPI, soldered)

'''lspci -tvnn:'''
<pre>
-[0000:00]-+-00.0 Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40]
+-02.0 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42]
+-02.1 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43]
+-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937]
+-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938]
+-1a.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939]
+-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c]
+-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e]
+-1c.0-[01-02]--
+-1c.1-[03-04]--
+-1c.2-[05-06]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
+-1c.3-[07-08]--
+-1c.4-[09-0a]----00.0 Broadcom Corporation BCM4312 802.11b/g [14e4:4315]
+-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934]
+-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935]
+-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936]
+-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a]
+-1e.0-[0b]--
+-1f.0 Intel Corporation ICH9M-E LPC Interface Controller [8086:2917]
+-1f.2 Intel Corporation ICH9M/M-E SATA AHCI Controller [8086:2929]
\-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930]
</pre>

'''cat /proc/cpuinfo:'''
<pre>
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 23
model name : Intel(R) Celeron(R) CPU 743 @ 1.30GHz
stepping : 10
cpu MHz : 1297.056
cache size : 1024 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 13
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl tm2 ssse3 cx16 xtpr pdcm xsave lahf_lm
bogomips : 2594.11
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
</pre>

==Photos==

{{GPL}}

Superiotool

2010-09-26T16:52:45Z

XVilka: /* Support of various devices */

'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.

This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.

<gallery>
Image:Ite it8705f.jpg|ITE IT8705F
Image:Winbond w83977ef.jpg|Winbond W83977EF
</gallery>

== Support of various devices ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ALi
| M1535/M1535D/M1535+/M1535D+
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5105
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5107
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5109
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5113
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5119
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M512x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513x
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xB
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M514x
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ASUS
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]
| —

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71862FG / F71863FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71872F/FG / F71806F/FG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71882FG/F71883FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F8000
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C711
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C712
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C721
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C735
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8228E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8502E/F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8510E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8511E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8512E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8661F/IT8770F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F/IT8687R
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8673F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT86793
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8702F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8703F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8705F/AF / IT8700F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8706R
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8708F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8710F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8711F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8718F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8720F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8722F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8726F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8761E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8780F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| HMC
| HMC83755
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Holtek
| HT6552IR
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS307
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS308
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS309
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS317
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS338
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS351
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97307
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87309
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87360
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87351
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87364
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87365
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87363
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87366
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8739x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87591x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8741x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87372
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8374L
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87427
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87373
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xFR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N971
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N972
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N252
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M172
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xAPM
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C67x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B80x/FDC37M707
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N958FR
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B77x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B78x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M602
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M60x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B72x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M81x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B27x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B37x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47U33x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B34x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S42x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M10x/112/13x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B357
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M14x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M15x/192/997
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S45x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M292
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B387
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B397
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M182
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M584
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| DME1737
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5504
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N217
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5514D-NS
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3112
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3114
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3116
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5317
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5027
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH4307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669FR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N237
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N769
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N3869/FDC37N869
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N227
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SIO10N268
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C665GT/IR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C666GT
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS6801
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS950
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686A/VT82C686B
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977CTF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977EF/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627SF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697HF/F/HG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83L517D/D-F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83637HF/HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627THF/THG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627UHG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83667HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977F-A/G-A/AF-A/AG-A
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977AF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977TF
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627HF/F/HG/G
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697SF/UF/UG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627EHF/EF/EHG/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877AF
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877TF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| WPCD376I
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM82C862
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8663BF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8669
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8670
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

|}

'''Extended dumps (EC, HWM) available for:'''

Use the '''--extra-dump''' option to see the contents of these registers.

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| Winbond
| W83627THF/THG HWM
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|- bgcolor="#eeeeee" valign="top"
| SMSC
| LPC47N227 runtime register block
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}


1 Previosly National Semiconductor, now bought by Winbond. 
2 Register dump output from a running coreboot system (vs. proprietary BIOS). 


== Installation ==

'''Manual installation'''

$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool
$ cd superiotool
$ make
$ sudo make install

'''Debian / Ubuntu'''

$ apt-get install superiotool

'''Fedora'''

$ yum install superiotool

== Usage ==

Probe/detect the Super I/O in your mainboard:

$ superiotool

Register dump as table of hex-values (if the Super I/O is detected):

$ superiotool -d

Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.

{{GPL}}

Superiotool

2010-09-25T08:14:49Z

XVilka:

'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.

This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.

<gallery>
Image:Ite it8705f.jpg|ITE IT8705F
Image:Winbond w83977ef.jpg|Winbond W83977EF
</gallery>

== Support of various devices ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ALi
| M1535/M1535D/M1535+/M1535D+
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5105
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5107
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5109
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5113
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5119
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M512x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513x
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xB
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M514x
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ASUS
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]
| —

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71862FG / F71863FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71872F/FG / F71806F/FG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71882FG/F71883FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F8000
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C711
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C712
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C721
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Chips&Tech
| F82C735
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8228E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8502E/F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8510E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8511E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8661F/IT8770F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F/IT8687R
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8673F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT86793
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8702F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8703F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8705F/AF / IT8700F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8706R
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8708F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8710F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8711F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8718F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8720F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8722F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8726F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8761E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8780F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| HMC
| HMC83755
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Holtek
| HT6552IR
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS307
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS308
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS309
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS317
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS338
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS351
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97307
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87309
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87360
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87351
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87364
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87365
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87363
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87366
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8739x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87591x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8741x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87372
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8374L
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87427
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87373
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xFR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N971
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N972
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N252
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M172
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xAPM
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C67x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B80x/FDC37M707
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N958FR
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B77x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B78x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M602
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M60x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B72x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M81x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B27x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B37x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47U33x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B34x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S42x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M10x/112/13x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B357
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M14x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M15x/192/997
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S45x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M292
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B387
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B397
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M182
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M584
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| DME1737
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5504
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N217
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5514D-NS
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3112
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3114
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3116
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5317
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5027
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH4307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669FR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N237
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N769
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N3869/FDC37N869
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N227
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SIO10N268
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C665GT/IR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C666GT
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS6801
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS950
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686A/VT82C686B
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977CTF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977EF/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627SF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697HF/F/HG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83L517D/D-F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83637HF/HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627THF/THG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627UHG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83667HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977F-A/G-A/AF-A/AG-A
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977AF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977TF
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627HF/F/HG/G
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697SF/UF/UG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627EHF/EF/EHG/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877AF
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877TF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| WPCD376I
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM82C862
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8663BF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8669
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8670
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

|}

'''Extended dumps (EC, HWM) available for:'''

Use the '''--extra-dump''' option to see the contents of these registers.

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| Winbond
| W83627THF/THG HWM
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|- bgcolor="#eeeeee" valign="top"
| SMSC
| LPC47N227 runtime register block
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}


1 Previosly National Semiconductor, now bought by Winbond. 
2 Register dump output from a running coreboot system (vs. proprietary BIOS). 


== Installation ==

'''Manual installation'''

$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool
$ cd superiotool
$ make
$ sudo make install

'''Debian / Ubuntu'''

$ apt-get install superiotool

'''Fedora'''

$ yum install superiotool

== Usage ==

Probe/detect the Super I/O in your mainboard:

$ superiotool

Register dump as table of hex-values (if the Super I/O is detected):

$ superiotool -d

Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.

{{GPL}}

Superiotool

2010-09-25T07:55:23Z

XVilka: Updated table of supported and unsupported devices

'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.

This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.

<gallery>
Image:Ite it8705f.jpg|ITE IT8705F
Image:Winbond w83977ef.jpg|Winbond W83977EF
</gallery>

== Support of various devices ==

{| border="0" valign="top"
| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ALi
| M1535/M1535D/M1535+/M1535D+
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5113
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M5119
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M512x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513x
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xB
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M513xF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| ALi
| M514x
| style="background:red" | No
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ASUS
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]
| —

|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71862FG / F71863FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71872F/FG / F71806F/FG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71882FG/F71883FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F71805F/FG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Fintek
| F8000
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#dddddd" valign="top"
| ITE
| IT8228E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8502E/F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8510E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8511E/TE/G
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8661F/IT8770F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8671F/IT8687R
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8673F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT86793
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8702F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8703F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8705F/AF / IT8700F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8706R
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8708F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8710F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8711F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8712F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8716F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8718F
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8720F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8722F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8726F
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8761E
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| ITE
| IT8780F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS307
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS308
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS309
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS317
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS338
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| NS351
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97307
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC97317
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87309
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87360
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87351
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87364
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87365
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87363
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87366
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8739x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87591x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8741x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87372
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC8374L
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87427
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| NSC1
| PC87373
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xFR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N971
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N972
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N252
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M172
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C93xAPM
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C67x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B80x/FDC37M707
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N958FR
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B77x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B78x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M602
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M60x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37B72x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37M81x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B27x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B37x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47U33x
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B34x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S42x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M10x/112/13x
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B357
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M14x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M15x/192/997
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47S45x
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M292
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B387
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47B397
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M182
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47M584
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| A8000
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| DME1737
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5504
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N217
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5514D-NS
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3112
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3114
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH3116
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5317
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH5027
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SCH4307
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C669FR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N237
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N769
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37N3869/FDC37N869
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| LPC47N227
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| SIO10N268
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C665GT/IR
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SMSC
| FDC37C666GT
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS6801
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| SiS
| SIS950
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

| valign="top"|

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#dddddd" valign="top"
| VIA
| VT82C686A/VT82C686B
| style="background:lime" | Yes
| style="background:red" | No
| —
| —

|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977CTF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977EF/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627SF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697HF/F/HG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83L517D/D-F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83637HF/HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627THF/THG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627DHG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627UHG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83667HG
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977F-A/G-A/AF-A/AG-A
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977AF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977TF
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83977ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627HF/F/HG/G
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83697SF/UF/UG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83627EHF/EF/EHG/EG
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877F
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877AF
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877TF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| W83877ATF
| style="background:lime" | Yes
| style="background:red" | No
| —
| —
|- bgcolor="#eeeeee" valign="top"
| Winbond
| WPCD376I
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8663BF
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8669
| style="background:red" | No
| style="background:red" | No
| —
| —
|- bgcolor="#dddddd" valign="top"
| UMC
| UM8670
| style="background:red" | No
| style="background:red" | No
| —
| —
|}

|}

'''Extended dumps (EC, HWM) available for:'''

Use the '''--extra-dump''' option to see the contents of these registers.

{| border="0" style="font-size: smaller" valign="top"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Super I/O
! align="left" | Detect
! align="left" | Dump
! align="left" | BIOS
! align="left" | CB2

|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8716F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]
| —
|- bgcolor="#eeeeee" valign="top"
| ITE
| IT8718F EC
| style="background:lime" | Yes
| style="background:lime" | Yes
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]
| —

|- bgcolor="#dddddd" valign="top"
| Winbond
| W83627THF/THG HWM
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|- bgcolor="#eeeeee" valign="top"
| SMSC
| LPC47N227 runtime register block
| style="background:lime" | Yes
| style="background:lime" | Yes
| —
| —

|}


1 Previosly National Semiconductor, now bought by Winbond. 
2 Register dump output from a running coreboot system (vs. proprietary BIOS). 


== Installation ==

'''Manual installation'''

$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool
$ cd superiotool
$ make
$ sudo make install

'''Debian / Ubuntu'''

$ apt-get install superiotool

'''Fedora'''

$ yum install superiotool

== Usage ==

Probe/detect the Super I/O in your mainboard:

$ superiotool

Register dump as table of hex-values (if the Super I/O is detected):

$ superiotool -d

Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.

{{GPL}}

Embedded controller

2010-09-07T21:19:40Z

XVilka: /* Embedded controller table */

The '''embedded controller''' is a small microcontroller typically used in laptops for various purposes.

== Supported by coreboot ==

=== Renesas M3885/M3886 ===

These ECs are supported by coreboot. There are several versions, with flash and with mask roms. Only the flash versions are update-able. These ECs are Family 740 based. A development environment including compiler and simulator is available from Renesas.

=== ENE KB3310/KB3910/KB3920 ===

Very common ECs in netbooks are the KB3310, KB3910 and KB3920 from [http://www.ene.com.tw/en/index.asp ENE Technology]. The ENE ECs are 8051 based.

The Quanta IL1 reference design seems to use ENE3310 controller. The q1d25i.rom was examined. The EC code is on 0xFFF00000 on One Mini A110. Its 64KB big HOLE0.ROM.

More discussion and info on the ENE EC's:

* ENE [http://wiki.laptop.org/images/a/ab/KB3700-ds-01.pdf KB3700 datasheet].
* [http://forum.eeeuser.com/viewtopic.php?pid=99076 eeeUser Discussion]
* [http://code.google.com/p/eeetune/wiki/KBMemoryMap Memory map of ENE KB3310]
* [https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/ 8051 simulator]
* [http://dev.laptop.org/git?p=projects/olpcflash;a=blob;f=olpcflash.c;hb=HEAD OpenEC Firmware]
* [http://wiki.laptop.org/go/OpenEC OpenEC Project]
* [http://www.cagnulein.com/tmp/eee.c-20080812 Example code] that makes use of the KB3310's "Index IO" access functions.

=== Renesas H8 ===

Some ECs are H8 based.

* [http://www.gnuh8.org/ port of the GNU compiler suite to the H8]
* [http://wunderkis.de/h8-gcc/h8tools.tar.gz H8 bootloader]
* [http://h8300-hms.sourceforge.net/ sourceforge project for H8/300]

== Embedded controller table ==

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Model
! align="left" | Type
! align="left" | Architecture
! align="left" | Datasheet(s)
! align="left" | Comments

|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || KB910 || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || KB926C || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || KB926D || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || KB3310 || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || KB3700 || EC || 8bit, 8051 core || [http://wiki.laptop.org/images/a/ab/KB3700-ds-01.pdf] || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || [http://www.ene.com.tw/en/product_detail.asp?pid=366&id=2256 KB3910] || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || [http://www.ene.com.tw/en/product_detail.asp?pid=366&id=2268 KB3920] || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || [http://www.ene.com.tw/en/product_detail.asp?pid=366&id=2269 KB3925] || EC || 8bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.ene.com.tw/en/index.asp ENE] || [http://www.ene.com.tw/en/product_detail.asp?pid=366&id=2270 KB3926] || EC || 8bit, 8051 core || ? || —

|- bgcolor="#dddddd"
| [http://www.fujitsu.com Fujitsu] || MB90378 || EC || 16bit, F2MC-16LX family || [http://edevice.fujitsu.com/fj/DATASHEET/e-ds/e713740.pdf] || —

|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || IT8500 || EC & Super I/O || ? || ? || Source: [http://gmb.viatech.com.cn/resource/downloads/VGTF-Autumn/ITE/ITE.pdf]
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || IT8502E || EC & Super I/O || 8bit, 8032 core (8051 compatible) || ? || Source: [http://de.viatech.com/de/initiatives/spearhead/surfboard_c855/] [http://gmb.viatech.com/resource/jsp/PartnersSolutions/Partners/ITE/index.jsp]
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || [http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=6,79 IT8510E/TE/G] || EC & Super I/O || 8bit, 8032 core (8051 compatible) || ? || —
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || [http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=6,80 IT8511E/TE/G] || EC & Super I/O || 8bit, 8032 core (8051 compatible) || ? || —
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || [http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=6,81 IT8512E/F/G] || EC & Super I/O || 8bit, 8032 core (8051 compatible) || ? || —
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || [http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=6,82 IT8513E/F/G] || EC & Super I/O || 8bit, 8032 core (8051 compatible) || ? || —
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || IT8516 || EC & Super I/O || ? || ? || Source: [http://gmb.viatech.com.cn/resource/downloads/VGTF-Autumn/ITE/ITE.pdf]
|- bgcolor="#eeeeee"
| [http://www.ite.com.tw/EN/index.aspx ITE] || [http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=6,84 IT8301E] || External GPIO chip || ? || ? || —

|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || 87541V || EC || 16 bit, CR16B core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || PC975513 || EC || 16 bit, CR16B core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/ECAndNBKeyboardController/ECAndNBKeyboardController/W83L951DG_W83L951FG.htm W83L951DG/FG]4 || EC || 8 bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/ECAndNBKeyboardController/ECAndNBKeyboardController/W83L951ADG_W83L951AFG.htm W83L951ADG/AFG]4 || EC || 8 bit, 8051 core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/ECAndNBKeyboardController/AdvancedEmbeddedController/WPC8769L.htm WPC8765L/WPC8769L]4 || EC || 16 bit, ? core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/ECAndNBKeyboardController/AdvancedEmbeddedController/WPC8763L.htm WPC8763L]4 || EC || 16 bit, CR16CPlus core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || [http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ComputerIC/ECAndNBKeyboardController/AdvancedEmbeddedController/WPCE775x.htm WPCE775x]4 || EC || 16 bit, CR16CPlus core || ? || —
|- bgcolor="#eeeeee"
| [http://www.nuvoton.com/ Nuvoton] || NPCE78nx || EC || ? || ? || —

|- bgcolor="#dddddd"
| [http://eu.renesas.com/ Renesas] || [http://eu.renesas.com/fmwk.jsp?cnt=3885_root.jsp&fp=/products/mpumcu/740_family/38000_740_series/3885_group/ M38859]1 || EC || 8bit, 740 family || [http://documentation.renesas.com/eng/products/mpumcu/e3885g.pdf] || —
|- bgcolor="#dddddd"
| [http://eu.renesas.com/ Renesas] || [http://eu.renesas.com/fmwk.jsp?cnt=3886_root.jsp&fp=/products/mpumcu/740_family/38000_740_series/3886_group/ M38867M8A]1 || EC || 8bit, 740 family || [http://documentation.renesas.com/eng/products/mpumcu/e3886g.pdf] || —
|- bgcolor="#dddddd"
| [http://eu.renesas.com/ Renesas] || [http://eu.renesas.com/fmwk.jsp?cnt=h8s2117_root.jsp&fp=/products/mpumcu/h8s_family/h8s2100_series/h8s2117_group H8S/2117R]2 || EC || 16 bit, H8S family || ? || Source: [http://www.intelcommsalliance.com/kshowcase/view/view_item/4ddd1dbe78eb6b235cc4f07eabb79ae562ae690e]
|- bgcolor="#dddddd"
| [http://eu.renesas.com/ Renesas] || H8S/2161B2 || EC || 16 bit, H8S family || ? || Source: [http://www.thinkwiki.org/wiki/Embedded_Controller_Chips], [http://www.thinkwiki.org/wiki/Embedded_Controller_Firmware], [http://forum.thinkpads.com/viewtopic.php?t=20958], [http://www.thinkwiki.org/wiki/Renesas_H8S/2161BV]
|- bgcolor="#dddddd"
| [http://eu.renesas.com/ Renesas] || H8S/2169AV 2 || EC || 16 bit, H8S family || ? || Source: [http://www.thinkwiki.org/wiki/Embedded_Controller_Chips], [http://www.thinkwiki.org/wiki/Embedded_Controller_Firmware], [http://forum.thinkpads.com/viewtopic.php?t=20958]
|- bgcolor="#dddddd"
| [http://eu.renesas.com/ Renesas] || H8S/64F3169ATE102 || EC || 16 bit, H8S family || ? || —

|- bgcolor="#eeeeee"
| [http://www.national.com NSC] || PC87570 || EC & Super I/O || ? || ? || —

|- bgcolor="#dddddd"
| [http://www.smsc.com/ SMSC] || FDC37N958FR || EC & Super I/O || ? || ? || —
|- bgcolor="#dddddd"
| [http://www.smsc.com/ SMSC] || LPC47N252 || EC & Super I/O || ? || ? || —
|- bgcolor="#dddddd"
| [http://www.smsc.com/ SMSC] || [http://www.smsc.com/index.php?tid=252&pid=173 MEC1308] || EC || 8bit, 8051 core || ? || —
|- bgcolor="#dddddd"
| [http://www.smsc.com/ SMSC] || [http://www.smsc.com/index.php?tid=252&pid=172 KBC1122/KBC1122P] || EC & Super I/O || 8bit, 8051 core || ? || —

|- bgcolor="#eeeeee"
| [http://www.sst.com/ SST] || [http://www.sst.com/about_sst/news/detail.dot?crumbTitle=NewsDetail&id=320 SST79LF008] || EC & Super I/O & BIOS flash || 8bit, 8051 core || ? || —

|}


1 Previously Mitsubishi, now Renesas. 
2 Previously Hitachi, now Renesas. 
3 Previously National (NSC), then Winbond, now Nuvoton. 
4 Previously Winbond, now Nuvoton. 


== Embedded controller photos ==

<gallery>
File:Dell_latitude_cpi_a366xt_superio.jpg|SMSC FDC37N958FR
File:Dell_latitude_c610_superio.jpg|SMSC LPC47N252
</gallery>

== Toolchains ==

TODO

{{PD-self}}

Laptop

2010-09-05T16:57:28Z

XVilka: /* HOWTO to find a way */

== Recent progress of coreboot on laptops ==

* coreboot supports the [http://en.getac.com/products/P470/P470_overview.html Getac P470] semi rugged notebook, based on Intel 82945GM/ICH7.
* coreboot supports the [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda RK886EX (Rocky III+)] laptop, based on Intel 82945GM/ICH7.
* VIA has recently released open documentation for the VX700 and VX800 chipsets at the [http://linux.via.com.tw/support/downloadFiles.action VIA Download Portal].

== Embedded controllers ==

The remaining issue with supporting netbooks may be open firmware support for the [[Embedded controller]] (EC).
These ECs used to support keyboard scan, lid open/closed, battery charging, power management, etc.

coreboot should work with the "stock" EC firmware. This may still be a challenge because "we don't know what we don't know". Behavior at runtime is fairly standardized, but we don't know what we need to do for initialization - do we need to set up registers, put in tables, kick things, or will it all Just Work (TM)?

== HOWTO to find a way ==

* find a model and manufacturer of your laptop
* download these tools:
#superiotool ( svn co svn://coreboot.org/coreboot/trunk/util/superiotool )
#inteltool ( svn co svn://coreboot.org/coreboot/trunk/util/inteltool )
#ectool ( svn co svn://coreboot.org/coreboot/trunk/util/ectool )
#dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )
#msrtool (svn co svn://coreboot.org/coreboot/trunk/util/msrtool )
#nvramtool ( svn co svn://coreboot.org/coreboot/trunk/util/nvramtool )
#flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )
* make and install them (make; sudo make install) - you need at least libpci/pciutils
* check that your distro have this tools and install them:
#lspci
#dmesg
#acpitool
#lspnp
#lsusb
* Do this commands:
# lspci -nnvvvxxxx > lscpi.log
# lspnp -vv > lspnp.log
# lsusb -vvv > lsusb.log
# superiotool -deV > superiotool.log
# inteltool -a > inteltool.log
# ectool > ectool.log
# msrtool > msrtool.log
# dmidecode > dmidecode.log
# biosdecode > biosdecode.log
# nvramtool -x > nvramtool.log
# dmesg > dmesg.log
# flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log
# flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log
* Save all logs in safe place, and also rom.bin file.
* try to find information - what EC or Super I/O chip is used in your laptop (may be some info in Service Manuals or Disassembly guides)
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support
* if you see that ectool return looks like 'right' output - you have a big chances for support
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop
* try to find your Super I/O / EC chip datasheet

== Laptop survey ==

This page attempts to list chipsets, Super I/Os, flash chips, and especially [[embedded controller]]s used in various laptops.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Model
! align="left" | CPU
! align="left" | Chipset NB
! align="left" | Chipset SB
! align="left" | Super I/O
! align="left" | [[Embedded controller|EC]]
! align="left" | Flash Chip
! align="left" | Flash Size
! align="left" | Flash S.
! align="left" | Flash T.
! align="left" | Owner

|- bgcolor="#dddddd"
| ASUS || S96F/Z96F || Intel Core™2 Duo T7400 || Intel i945 || Intel ICH7 || ITE IT8510E || in Super I/O || ? || ? || ? || ? || [http://www.flashrom.org/pipermail/flashrom/2010-January/001986.html macavity]
|- bgcolor="#eeeeee"
| Acer || Aspire One ZG5 || Intel Atom N270 1.6GHz || Intel 82945GME || Intel NH82801GBM ICH7-M || Winbond WPCE775LA0DG || in Super I/O || Winbond 25x80AVSIG || 8Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Acer || Aspire 3613LC || Intel Celeron M 370 1.5GHz L2: 1MB || Intel 82910GML || Intel FW82801FBM SL7W6 ICH6-M || ? || ? || PMC 0537 PM39LV040-70JCE || 1Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#eeeeee"
| Dell || [[Dell Latitude CPi A366XT|Latitude CPi A366XT]] || PII, 360 MHz || Intel 440BX |||| SMSC FDC37N958FR || in Super I/O || AMD AM29F040B || 512KB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Dell || [[Dell Latitude C610|Latitude C610]] || PIII, 1.2 GHz || Intel i830 |||| SMSC LPC47N252 || in Super I/O || SST SST49LF004A || 512KB || no || PLCC || [mailto:coreboot@miradou.com CybFr]
|- bgcolor="#eeeeee"
| Dell || [[Dell Vostro V13]] || Intel Celeron 743 1.2GHz, L2: 1MB (Ultra Low Voltage) || Mobile Intel GS45 Express GHMC ||Intel 82801IEM ICH9M-E|| none || ITE IT8502E || Winbond 25Q16BVSIG || 2Mb || no || SOIP/PDIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Dell || XPS M1530 || Intel Core™2 Duo T7700 || Intel PM965 || Intel ICH8 || none || Winbond WPC8763L || Winbond 25X16VSIG || 16Mb || ?? || SPI || Corey Osgood
|- bgcolor="#eeeeee"
| Fujitsu-S. || Lifebook S-4572 || PIII, 750 MHz || Intel 82440MX |||| SMSC FDC37N769 || ? || Fujitsu MBM29F400T1 || ? || no || TSOP(?) || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Fujitsu-S. || Lifebook S7110 || Intel Core™2 Duo T7200 || Intel i945 || Intel ICH7 || SMSC LPC47N217 || Fujitsu MB90378 || Spansion S25FL008A2 || 1024 kB || no || SO8 / SPI || twice11
|- bgcolor="#eeeeee"
| Gateway || [[Gateway W730-K8X | W730-K8X]] || Socket 754 |||| ?? || ?? || ?? || SST 39VF040 || ?? || yes || PLCC || [[User:Juri|Juri]]
|- bgcolor="#dddddd"
| Gateway || [[Gateway 6020GZ|6020GZ]] || Celeron M 1.4Ghz || Intel 855GME |||| ?? || ?? || ?? || ?? || no || ?? || [[User:Juri|Juri]]
|- bgcolor="#eeeeee"
| Gericom || Webboy 340S2 || PIII || SiS630 |||| NSC PC87393VJG || NSC PC87570 || Winbond 29C020 || 256 kB || yes || PLCC || [http://thread.gmane.org/gmane.linux.bios/13081 NS]
|- bgcolor="#dddddd"
| Getac || P470 || Intel® Core 2 Duo Mobile || Intel 945 || Intel ICH7 || ? || ? || ? || 8Mb || no || SPI / SOIC8 || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#eeeeee"
| Highscreen || XD 14-C1700 || Intel Celeron 1.7 GHz || SiS650 |||| NSC PC87391(?) || ? || EON EN29F040(A) || 512 kB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| HP || Omnibook XE3(L) || PIII, 750 MHz || Intel 82371MB ||Intel PIIX4M || SMSC FDC37N869 || NSC PC87570 || SST 28SF040A || 512 kB || no || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| IBM || Thinkpad T30 || Intel P4 Mobile, 1.8 GHz || Intel i845 || Intel ICH3-M || NSC PC87392 || Renesas H8S 64F3169ATE10 || ST M50FW080N5 || 1024 kB || no || TSOP40 / FWH || edgecase
|- bgcolor="#dddddd"
| MSI || Wind U100 || Intel Atom N280 1.66Ghz || Intel 945GSE || Intel ICH7-M || ? || ENE KB3310 || SST MX25L8005 || 8 Mb|| no || TSOP40 / SPI || ?
|- bgcolor="#eeeeee"
| One || [http://www.a110wiki.de A110] || VIA C7-M ULV 1.0 GHz || VIA VX800 |||| none || ENE KB3310 || ? || ? || no || ? || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Panasonic || Toughbook CF-25 || P166MMX || FW82439TX (430TX) || FW82371AB || NSC PC87336VJG || Renesas 3886 || SST SST29EE020 || 256 kB || no || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Roda || Rocky III+ RK886EX || Intel® Core 2 Duo Mobile T5500 || Intel 945 || Intel ICH7 || SMSC® LPC47N227 || Renesas M38859 || SST SST49LF080 || 8Mb || yes || PLCC || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#dddddd"
| Roda || Rocky II+ RT686 || Intel Pentium III || Intel 430BX || Intel FW82371EB || SMSC® FDC37N769 || Renesas M38867M8A || SST SST29LE020 || 256KB || yes || PLCC/parallel || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| Sony || Vaio Picturebook PCG-C1XD || P2 400 || 443ZX |||| ? || ? || ST M29W004BT || 512 kB || no || || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Sony || Vaio Picturebook PCG-C1X || P266MMX || 430TX |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Toshiba || Libretto 50M PA1243CM || P133 || custom FPGA |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Toshiba || Satellite A80-117 || Intel Celeron || Intel 915GM || Intel ICH6 || SMSC LPC47N217 || ENE KB910 || ? || 1024 kB || no || TSOP (?) || [[User:Uwe|UH]]

|}


1 According to the vendor BIOS update tool. 
2 Nice thing: EC/Flash is not shared, so you can erase the whole flash during system operation (this was tested). 


Further links:

* [http://tuxmobil.org/mylaptops.html Tuxmobil Laptop Survey]
* [http://mcelrath.org/laptops.html Laptops/Notebooks with Linux Preinstalled]
* [http://www.fsf.org/campaigns/free-bios.html The Free Software Foundation's Campaign for Free BIOS]

== Mailinglist discussion ==

A few earlier coreboot discussions on laptops are linked here, you might get useful information out of them:

* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010985.html Any update on coreboot for laptops]
* [http://comments.gmane.org/gmane.linux.bios/13081 Notebook 340s2 (sis630) 256k Flash]
* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010972.html yet another reason to use coreboot in laptops I guess]
* [http://www.coreboot.org/pipermail/linuxbios/2005-April/011429.html coreboot laptop hunt wiki page]
* [http://www.coreboot.org/pipermail/linuxbios/2005-March/011140.html HP Pavillion ZV5000 (Laptop)]
* [http://www.coreboot.org/pipermail/linuxbios/2005-July/011942.html SA1100]
* [http://www.coreboot.org/pipermail/linuxbios/2003-September/004954.html Laptop with Sis 650 chipset]
* [http://www.coreboot.org/pipermail/linuxbios/2006-September/015551.html coreboot on Laptops]

== Who really makes your laptop? ==

There are several various brands of laptops, but there are only a few actual laptop makers.

Name brand companies like Hewlet Packard, Compaq, IBM, Dell, Gateway, Sony, Micron, Toshiba and others; including Alienware and Voodoo do not make their own laptops. The exceptions are Asus and Apple, and even Apple doesn't make all of their laptops.

Original Design Manufacturers (ODM) make the laptops for Original Equipment Manufacturers (OEM). They in turn, add their preloaded hard drives and sell them to consumers. This is why a laptop is a bit more complicated to support with coreboot. The OEM's may not even have all the specifications for the laptop since the ODM has done all the design and assembly.

Some laptop ODMs are:

* [http://www.quantatw.com Quanta] makes laptops for Sony, Dell, and IBM
* [http://www.inventec.com/ Inventec] and [http://www.arima.com.tw/ Arima] make the Compaq line
* [http://www.compal.com/ Compal] also makes IBM and Dell lines, as well as Hewlett Packard
* [http://www.clevo.com.tw/ Clevo] makes the popular Alienware and Voodoo gaming laptops

Further links:

* [http://www.laptopworldwide.com/laptops.html Makers of Laptops]
* [http://tuxmobil.org/laptop_oem.html Laptop and NoteBook Manufacturer - OEM/ODM Relation Matrix]
* [http://tuxmobil.org/reseller.html Where to Buy a Preinstalled Linux Laptop, Notebook, Mobile Phone or PDA? - Vendor Overview]

== Random product links ==

VIA has a list of many netbooks at [http://via.com.tw/en/products/notebook/notebook.jsp VIA Partner Mobility Devices].

VIA also has information on other mobile platforms at [http://via.com.tw/en/products/notebook/index.jsp VIA Mobility Platform].

The [http://www.a110wiki.de Quanta IL1] vx800 based reference design covers similar models/clones such as:

*[http://www.one.de/shop/one-notebooks-one-mini-notebooks-c-213_214.html One Mini A110/A115/A120/A140/A150/A470]
*[http://preview.tinyurl.com/5zbzl6 Airis Kira 100/350/740]
*[http://www.norhtec.com/products/gecko/index.html Norhtec Gecko]
*[http://www.pioneercomputers.com.au/products/configure.asp?c1=3&c2=12&id=2458 Pioneer DreamBook Light IL1]
*[http://www.ctlcorp.com/v4/p-697-ctl-il1a-89-netbook-with-windows-xp-home.aspx CTL IL1] More [http://www.a110wiki.de/wiki/CTL_IL1 CTL IL1 info] with tear-down pics.
*[http://www.aci-asia.com/html/Ethos_7.html ACi Ethos 7]
*[http://www.ilikeblue.net/products/umpc.htm BDSI Deep Blue H1]

Other vx800 based netbooks:

*[http://www.everex.com/products/cloudbook_max/cloudbook_max.htm Everex CloudBook MAX]
*[http://www.fic.com.tw/product/ce2a1.aspx FIC CE2A1]

There are still a few netbook designs currently on the market that use the VIA vx700 chipset:

*[http://www.sylvaniacomputers.com/products.php?p=g Sylvania G]
*[http://www.everex.com/products/cloudbook/cloudbook.htm Everex Cloudbook]
*[http://www.fic.com.tw/product/ce260.aspx FIC CE260]
*[http://www.fic.com.tw/product/ce268.aspx FIC CE268]

There are also several AMD 690/600 laptops still available that may be candidates as well:

*[http://reviews.cnet.com/laptops/acer-extensa-4420-5963/4505-3121_7-33361062.html Acer Extensa 4420]
*[http://www.raondigital.com EVERUN NOTE]

Intel Atom with i945 chipset netbooks:

*[http://en.wikipedia.org/wiki/Aspire_One Acer Aspire One]
*[http://en.wikipedia.org/wiki/MSI_Wind_PC MSI Wind]
*[http://en.wikipedia.org/wiki/ASUS_Eee_PC ASUS eeePC]

Dell Vostro V13

2010-08-18T06:47:16Z

XVilka:

Dell Vostro V13 - laptop with ICH-9M chipset.

== Hardware ==

'''Overview:'''

* '''Northbridge:''' Mobile Intel GS45 Express GHMC with integrated video
* '''Southbridge:''' Intel I/O Controller Hub 9-ME (ICH9M-E) 82801IEM
* '''Super I/O:''' ITE IT8502E
** The Super I/O also "contains" the embedded controller (EC), which is an 8051 derivate.
* '''Audio controller:'''
* '''ExpressCard controller:'''
* '''ROM/BIOS chip:''' Winbond 25Q16BVSIG (SOIP/PDIP, 2 Mb, SPI, soldered)

'''lspci -tvnn:'''
<pre>
-[0000:00]-+-00.0 Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40]
+-02.0 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42]
+-02.1 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43]
+-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937]
+-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938]
+-1a.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939]
+-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c]
+-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e]
+-1c.0-[01-02]--
+-1c.1-[03-04]--
+-1c.2-[05-06]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
+-1c.3-[07-08]--
+-1c.4-[09-0a]----00.0 Broadcom Corporation BCM4312 802.11b/g [14e4:4315]
+-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934]
+-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935]
+-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936]
+-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a]
+-1e.0-[0b]--
+-1f.0 Intel Corporation ICH9M-E LPC Interface Controller [8086:2917]
+-1f.2 Intel Corporation ICH9M/M-E SATA AHCI Controller [8086:2929]
\-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930]
</pre>

'''cat /proc/cpuinfo:'''
<pre>
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 23
model name : Intel(R) Celeron(R) CPU 743 @ 1.30GHz
stepping : 10
cpu MHz : 1297.056
cache size : 1024 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 13
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl tm2 ssse3 cx16 xtpr pdcm xsave lahf_lm
bogomips : 2594.11
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
</pre>

==Photos==

{{GPL}}

Dell Vostro V13

2010-08-18T06:44:53Z

XVilka: Added Dell Vostro V13 page

Dell Vostro V13 is an older laptop with ICH-9M chipset.

== Hardware ==

'''Overview:'''

* '''Northbridge:''' Mobile Intel GS45 Express GHMC with integrated video
* '''Southbridge:''' Intel I/O Controller Hub 9-ME (ICH9M-E) 82801IEM
* '''Super I/O:''' ITE IT8502E
** The Super I/O also "contains" the embedded controller (EC), which is an 8051 derivate.
* '''Audio controller:'''
* '''ExpressCard controller:'''
* '''ROM/BIOS chip:''' Winbond 25Q16BVSIG (SOIP/PDIP, 2 Mb, SPI, soldered)

'''lspci -tvnn:'''
<pre>
-[0000:00]-+-00.0 Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40]
+-02.0 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42]
+-02.1 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43]
+-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937]
+-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938]
+-1a.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939]
+-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c]
+-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e]
+-1c.0-[01-02]--
+-1c.1-[03-04]--
+-1c.2-[05-06]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
+-1c.3-[07-08]--
+-1c.4-[09-0a]----00.0 Broadcom Corporation BCM4312 802.11b/g [14e4:4315]
+-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934]
+-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935]
+-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936]
+-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a]
+-1e.0-[0b]--
+-1f.0 Intel Corporation ICH9M-E LPC Interface Controller [8086:2917]
+-1f.2 Intel Corporation ICH9M/M-E SATA AHCI Controller [8086:2929]
\-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930]
</pre>

'''cat /proc/cpuinfo:'''
<pre>
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 23
model name : Intel(R) Celeron(R) CPU 743 @ 1.30GHz
stepping : 10
cpu MHz : 1297.056
cache size : 1024 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 13
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl tm2 ssse3 cx16 xtpr pdcm xsave lahf_lm
bogomips : 2594.11
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
</pre>

==Photos==

{{GPL}}

Laptop

2010-08-18T06:20:25Z

XVilka: /* Laptop survey */

== Recent progress of coreboot on laptops ==

* coreboot supports the [http://en.getac.com/products/P470/P470_overview.html Getac P470] semi rugged notebook, based on Intel 82945GM/ICH7.
* coreboot supports the [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda RK886EX (Rocky III+)] laptop, based on Intel 82945GM/ICH7.
* VIA has recently released open documentation for the VX700 and VX800 chipsets at the [http://linux.via.com.tw/support/downloadFiles.action VIA Download Portal].

== Embedded controllers ==

The remaining issue with supporting netbooks may be open firmware support for the [[Embedded controller]] (EC).
These ECs used to support keyboard scan, lid open/closed, battery charging, power management, etc.

coreboot should work with the "stock" EC firmware. This may still be a challenge because "we don't know what we don't know". Behavior at runtime is fairly standardized, but we don't know what we need to do for initialization - do we need to set up registers, put in tables, kick things, or will it all Just Work (TM)?

== HOWTO to find a way ==

* find a model and manufacturer of your laptop
* download these tools:
#superiotool ( svn co svn://coreboot.org/coreboot/trunk/util/superiotool )
#inteltool ( svn co svn://coreboot.org/coreboot/trunk/util/inteltool )
#ectool ( svn co svn://coreboot.org/coreboot/trunk/util/ectool )
#dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )
#msrtool (svn co svn://coreboot.org/coreboot/trunk/util/msrtool )
#nvramtool ( svn co svn://coreboot.org/coreboot/trunk/util/nvramtool )
#flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )
* make and install them (make; sudo make install)
* check that your distro have this tools and install them:
#lspci
#dmesg
#acpitool
#lspnp
* Do this commands:
# lspci -nnvvvxxxx > lscpi.log
# lspnp > lspnp.log
# superiotool -deV > superiotool.log
# inteltool -a > inteltool.log
# ectool > ectool.log
# msrtool > msrtool.log
# dmidecode > dmidecode.log
# biosdecode > biosdecode.log
# nvramtool -x > nvramtool.log
# dmesg > dmesg.log
# flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log
# flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log
* Save all logs in safe place, and also rom.bin file.
* try to find information - what EC or Super I/O chip is used in your laptop (may be some info in Service Manuals or Disassembly guides)
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support
* if you see that ectool return looks like 'right' output - you have a big chances for support
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop
* try to find your Super I/O / EC chip datasheet

== Laptop survey ==

This page attempts to list chipsets, Super I/Os, flash chips, and especially [[embedded controller]]s used in various laptops.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Model
! align="left" | CPU
! align="left" | Chipset NB
! align="left" | Chipset SB
! align="left" | Super I/O
! align="left" | [[Embedded controller|EC]]
! align="left" | Flash Chip
! align="left" | Flash Size
! align="left" | Flash S.
! align="left" | Flash T.
! align="left" | Owner

|- bgcolor="#dddddd"
| ASUS || S96F/Z96F || Intel Core™2 Duo T7400 || Intel i945 || Intel ICH7 || ITE IT8510E || in Super I/O || ? || ? || ? || ? || [http://www.flashrom.org/pipermail/flashrom/2010-January/001986.html macavity]
|- bgcolor="#eeeeee"
| Acer || Aspire One ZG5 || Intel Atom N270 1.6GHz || Intel 82945GME || Intel NH82801GBM ICH7-M || Winbond WPCE775LA0DG || in Super I/O || Winbond 25x80AVSIG || 8Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Acer || Aspire 3613LC || Intel Celeron M 370 1.5GHz L2: 1MB || Intel 82910GML || Intel FW82801FBM SL7W6 ICH6-M || ? || ? || PMC 0537 PM39LV040-70JCE || 1Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#eeeeee"
| Dell || [[Dell Latitude CPi A366XT|Latitude CPi A366XT]] || PII, 360 MHz || Intel 440BX |||| SMSC FDC37N958FR || in Super I/O || AMD AM29F040B || 512KB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Dell || [[Dell Latitude C610|Latitude C610]] || PIII, 1.2 GHz || Intel i830 |||| SMSC LPC47N252 || in Super I/O || SST SST49LF004A || 512KB || no || PLCC || [mailto:coreboot@miradou.com CybFr]
|- bgcolor="#eeeeee"
| Dell || [[Dell Vostro V13]] || Intel Celeron 743 1.2GHz, L2: 1MB (Ultra Low Voltage) || Mobile Intel GS45 Express GHMC ||Intel 82801IEM ICH9M-E|| none || ITE IT8502E || Winbond 25Q16BVSIG || 2Mb || no || SOIP/PDIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Dell || XPS M1530 || Intel Core™2 Duo T7700 || Intel PM965 || Intel ICH8 || none || Winbond WPC8763L || Winbond 25X16VSIG || 16Mb || ?? || SPI || Corey Osgood
|- bgcolor="#eeeeee"
| Fujitsu-S. || Lifebook S-4572 || PIII, 750 MHz || Intel 82440MX |||| SMSC FDC37N769 || ? || Fujitsu MBM29F400T1 || ? || no || TSOP(?) || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Fujitsu-S. || Lifebook S7110 || Intel Core™2 Duo T7200 || Intel i945 || Intel ICH7 || SMSC LPC47N217 || Fujitsu MB90378 || Spansion S25FL008A2 || 1024 kB || no || SO8 / SPI || twice11
|- bgcolor="#eeeeee"
| Gateway || [[Gateway W730-K8X | W730-K8X]] || Socket 754 |||| ?? || ?? || ?? || SST 39VF040 || ?? || yes || PLCC || [[User:Juri|Juri]]
|- bgcolor="#dddddd"
| Gateway || [[Gateway 6020GZ|6020GZ]] || Celeron M 1.4Ghz || Intel 855GME |||| ?? || ?? || ?? || ?? || no || ?? || [[User:Juri|Juri]]
|- bgcolor="#eeeeee"
| Gericom || Webboy 340S2 || PIII || SiS630 |||| NSC PC87393VJG || NSC PC87570 || Winbond 29C020 || 256 kB || yes || PLCC || [http://thread.gmane.org/gmane.linux.bios/13081 NS]
|- bgcolor="#dddddd"
| Getac || P470 || Intel® Core 2 Duo Mobile || Intel 945 || Intel ICH7 || ? || ? || ? || 8Mb || no || SPI / SOIC8 || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#eeeeee"
| Highscreen || XD 14-C1700 || Intel Celeron 1.7 GHz || SiS650 |||| NSC PC87391(?) || ? || EON EN29F040(A) || 512 kB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| HP || Omnibook XE3(L) || PIII, 750 MHz || Intel 82371MB ||Intel PIIX4M || SMSC FDC37N869 || NSC PC87570 || SST 28SF040A || 512 kB || no || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| IBM || Thinkpad T30 || Intel P4 Mobile, 1.8 GHz || Intel i845 || Intel ICH3-M || NSC PC87392 || Renesas H8S 64F3169ATE10 || ST M50FW080N5 || 1024 kB || no || TSOP40 / FWH || edgecase
|- bgcolor="#dddddd"
| MSI || Wind U100 || Intel Atom N280 1.66Ghz || Intel 945GSE || Intel ICH7-M || ? || ENE KB3310 || SST MX25L8005 || 8 Mb|| no || TSOP40 / SPI || ?
|- bgcolor="#eeeeee"
| One || [http://www.a110wiki.de A110] || VIA C7-M ULV 1.0 GHz || VIA VX800 |||| none || ENE KB3310 || ? || ? || no || ? || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Panasonic || Toughbook CF-25 || P166MMX || FW82439TX (430TX) || FW82371AB || NSC PC87336VJG || Renesas 3886 || SST SST29EE020 || 256 kB || no || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Roda || Rocky III+ RK886EX || Intel® Core 2 Duo Mobile T5500 || Intel 945 || Intel ICH7 || SMSC® LPC47N227 || Renesas M38859 || SST SST49LF080 || 8Mb || yes || PLCC || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#dddddd"
| Roda || Rocky II+ RT686 || Intel Pentium III || Intel 430BX || Intel FW82371EB || SMSC® FDC37N769 || Renesas M38867M8A || SST SST29LE020 || 256KB || yes || PLCC/parallel || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| Sony || Vaio Picturebook PCG-C1XD || P2 400 || 443ZX |||| ? || ? || ST M29W004BT || 512 kB || no || || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Sony || Vaio Picturebook PCG-C1X || P266MMX || 430TX |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Toshiba || Libretto 50M PA1243CM || P133 || custom FPGA |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Toshiba || Satellite A80-117 || Intel Celeron || Intel 915GM || Intel ICH6 || SMSC LPC47N217 || ENE KB910 || ? || 1024 kB || no || TSOP (?) || [[User:Uwe|UH]]

|}


1 According to the vendor BIOS update tool. 
2 Nice thing: EC/Flash is not shared, so you can erase the whole flash during system operation (this was tested). 


Further links:

* [http://tuxmobil.org/mylaptops.html Tuxmobil Laptop Survey]
* [http://mcelrath.org/laptops.html Laptops/Notebooks with Linux Preinstalled]
* [http://www.fsf.org/campaigns/free-bios.html The Free Software Foundation's Campaign for Free BIOS]

== Mailinglist discussion ==

A few earlier coreboot discussions on laptops are linked here, you might get useful information out of them:

* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010985.html Any update on coreboot for laptops]
* [http://comments.gmane.org/gmane.linux.bios/13081 Notebook 340s2 (sis630) 256k Flash]
* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010972.html yet another reason to use coreboot in laptops I guess]
* [http://www.coreboot.org/pipermail/linuxbios/2005-April/011429.html coreboot laptop hunt wiki page]
* [http://www.coreboot.org/pipermail/linuxbios/2005-March/011140.html HP Pavillion ZV5000 (Laptop)]
* [http://www.coreboot.org/pipermail/linuxbios/2005-July/011942.html SA1100]
* [http://www.coreboot.org/pipermail/linuxbios/2003-September/004954.html Laptop with Sis 650 chipset]
* [http://www.coreboot.org/pipermail/linuxbios/2006-September/015551.html coreboot on Laptops]

== Who really makes your laptop? ==

There are several various brands of laptops, but there are only a few actual laptop makers.

Name brand companies like Hewlet Packard, Compaq, IBM, Dell, Gateway, Sony, Micron, Toshiba and others; including Alienware and Voodoo do not make their own laptops. The exceptions are Asus and Apple, and even Apple doesn't make all of their laptops.

Original Design Manufacturers (ODM) make the laptops for Original Equipment Manufacturers (OEM). They in turn, add their preloaded hard drives and sell them to consumers. This is why a laptop is a bit more complicated to support with coreboot. The OEM's may not even have all the specifications for the laptop since the ODM has done all the design and assembly.

Some laptop ODMs are:

* [http://www.quantatw.com Quanta] makes laptops for Sony, Dell, and IBM
* [http://www.inventec.com/ Inventec] and [http://www.arima.com.tw/ Arima] make the Compaq line
* [http://www.compal.com/ Compal] also makes IBM and Dell lines, as well as Hewlett Packard
* [http://www.clevo.com.tw/ Clevo] makes the popular Alienware and Voodoo gaming laptops

Further links:

* [http://www.laptopworldwide.com/laptops.html Makers of Laptops]
* [http://tuxmobil.org/laptop_oem.html Laptop and NoteBook Manufacturer - OEM/ODM Relation Matrix]
* [http://tuxmobil.org/reseller.html Where to Buy a Preinstalled Linux Laptop, Notebook, Mobile Phone or PDA? - Vendor Overview]

== Random product links ==

VIA has a list of many netbooks at [http://via.com.tw/en/products/notebook/notebook.jsp VIA Partner Mobility Devices].

VIA also has information on other mobile platforms at [http://via.com.tw/en/products/notebook/index.jsp VIA Mobility Platform].

The [http://www.a110wiki.de Quanta IL1] vx800 based reference design covers similar models/clones such as:

*[http://www.one.de/shop/one-notebooks-one-mini-notebooks-c-213_214.html One Mini A110/A115/A120/A140/A150/A470]
*[http://preview.tinyurl.com/5zbzl6 Airis Kira 100/350/740]
*[http://www.norhtec.com/products/gecko/index.html Norhtec Gecko]
*[http://www.pioneercomputers.com.au/products/configure.asp?c1=3&c2=12&id=2458 Pioneer DreamBook Light IL1]
*[http://www.ctlcorp.com/v4/p-697-ctl-il1a-89-netbook-with-windows-xp-home.aspx CTL IL1] More [http://www.a110wiki.de/wiki/CTL_IL1 CTL IL1 info] with tear-down pics.
*[http://www.aci-asia.com/html/Ethos_7.html ACi Ethos 7]
*[http://www.ilikeblue.net/products/umpc.htm BDSI Deep Blue H1]

Other vx800 based netbooks:

*[http://www.everex.com/products/cloudbook_max/cloudbook_max.htm Everex CloudBook MAX]
*[http://www.fic.com.tw/product/ce2a1.aspx FIC CE2A1]

There are still a few netbook designs currently on the market that use the VIA vx700 chipset:

*[http://www.sylvaniacomputers.com/products.php?p=g Sylvania G]
*[http://www.everex.com/products/cloudbook/cloudbook.htm Everex Cloudbook]
*[http://www.fic.com.tw/product/ce260.aspx FIC CE260]
*[http://www.fic.com.tw/product/ce268.aspx FIC CE268]

There are also several AMD 690/600 laptops still available that may be candidates as well:

*[http://reviews.cnet.com/laptops/acer-extensa-4420-5963/4505-3121_7-33361062.html Acer Extensa 4420]
*[http://www.raondigital.com EVERUN NOTE]

Intel Atom with i945 chipset netbooks:

*[http://en.wikipedia.org/wiki/Aspire_One Acer Aspire One]
*[http://en.wikipedia.org/wiki/MSI_Wind_PC MSI Wind]
*[http://en.wikipedia.org/wiki/ASUS_Eee_PC ASUS eeePC]

Laptop

2010-08-18T05:47:19Z

XVilka:

== Recent progress of coreboot on laptops ==

* coreboot supports the [http://en.getac.com/products/P470/P470_overview.html Getac P470] semi rugged notebook, based on Intel 82945GM/ICH7.
* coreboot supports the [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda RK886EX (Rocky III+)] laptop, based on Intel 82945GM/ICH7.
* VIA has recently released open documentation for the VX700 and VX800 chipsets at the [http://linux.via.com.tw/support/downloadFiles.action VIA Download Portal].

== Embedded controllers ==

The remaining issue with supporting netbooks may be open firmware support for the [[Embedded controller]] (EC).
These ECs used to support keyboard scan, lid open/closed, battery charging, power management, etc.

coreboot should work with the "stock" EC firmware. This may still be a challenge because "we don't know what we don't know". Behavior at runtime is fairly standardized, but we don't know what we need to do for initialization - do we need to set up registers, put in tables, kick things, or will it all Just Work (TM)?

== HOWTO to find a way ==

* find a model and manufacturer of your laptop
* download these tools:
#superiotool ( svn co svn://coreboot.org/coreboot/trunk/util/superiotool )
#inteltool ( svn co svn://coreboot.org/coreboot/trunk/util/inteltool )
#ectool ( svn co svn://coreboot.org/coreboot/trunk/util/ectool )
#dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )
#msrtool (svn co svn://coreboot.org/coreboot/trunk/util/msrtool )
#nvramtool ( svn co svn://coreboot.org/coreboot/trunk/util/nvramtool )
#flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )
* make and install them (make; sudo make install)
* check that your distro have this tools and install them:
#lspci
#dmesg
#acpitool
#lspnp
* Do this commands:
# lspci -nnvvvxxxx > lscpi.log
# lspnp > lspnp.log
# superiotool -deV > superiotool.log
# inteltool -a > inteltool.log
# ectool > ectool.log
# msrtool > msrtool.log
# dmidecode > dmidecode.log
# biosdecode > biosdecode.log
# nvramtool -x > nvramtool.log
# dmesg > dmesg.log
# flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log
# flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log
* Save all logs in safe place, and also rom.bin file.
* try to find information - what EC or Super I/O chip is used in your laptop (may be some info in Service Manuals or Disassembly guides)
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support
* if you see that ectool return looks like 'right' output - you have a big chances for support
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop
* try to find your Super I/O / EC chip datasheet

== Laptop survey ==

This page attempts to list chipsets, Super I/Os, flash chips, and especially [[embedded controller]]s used in various laptops.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Model
! align="left" | CPU
! align="left" | Chipset NB
! align="left" | Chipset SB
! align="left" | Super I/O
! align="left" | [[Embedded controller|EC]]
! align="left" | Flash Chip
! align="left" | Flash Size
! align="left" | Flash S.
! align="left" | Flash T.
! align="left" | Owner

|- bgcolor="#dddddd"
| ASUS || S96F/Z96F || Intel Core™2 Duo T7400 || Intel i945 || Intel ICH7 || ITE IT8510E || in Super I/O || ? || ? || ? || ? || [http://www.flashrom.org/pipermail/flashrom/2010-January/001986.html macavity]
|- bgcolor="#eeeeee"
| Acer || Aspire One ZG5 || Intel Atom N270 1.6GHz || Intel 82945GME || Intel NH82801GBM ICH7-M || Winbond WPCE775LA0DG || in Super I/O || Winbond 25x80AVSIG || 8Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Acer || Aspire 3613LC || Intel Celeron M 370 1.5GHz L2: 1MB || Intel 82910GML || Intel FW82801FBM SL7W6 ICH6-M || ? || ? || PMC 0537 PM39LV040-70JCE || 1Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#eeeeee"
| Dell || [[Dell Latitude CPi A366XT|Latitude CPi A366XT]] || PII, 360 MHz || Intel 440BX |||| SMSC FDC37N958FR || in Super I/O || AMD AM29F040B || 512KB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Dell || [[Dell Latitude C610|Latitude C610]] || PIII, 1.2 GHz || Intel i830 |||| SMSC LPC47N252 || in Super I/O || SST SST49LF004A || 512KB || no || PLCC || [mailto:coreboot@miradou.com CybFr]
|- bgcolor="#eeeeee"
| Dell || Dell Vostro V13 || Intel Celeron 743 1.2GHz, L2: 1MB (Ultra Low Voltage) || Mobile Intel GS45 Express GHMC ||Intel 82801IEM ICH9M-E|| none || ITE IT8502E || Winbond 25Q16BVSIG || 2Mb || no || SOIP/PDIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Dell || XPS M1530 || Intel Core™2 Duo T7700 || Intel PM965 || Intel ICH8 || none || Winbond WPC8763L || Winbond 25X16VSIG || 16Mb || ?? || SPI || Corey Osgood
|- bgcolor="#eeeeee"
| Fujitsu-S. || Lifebook S-4572 || PIII, 750 MHz || Intel 82440MX |||| SMSC FDC37N769 || ? || Fujitsu MBM29F400T1 || ? || no || TSOP(?) || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Fujitsu-S. || Lifebook S7110 || Intel Core™2 Duo T7200 || Intel i945 || Intel ICH7 || SMSC LPC47N217 || Fujitsu MB90378 || Spansion S25FL008A2 || 1024 kB || no || SO8 / SPI || twice11
|- bgcolor="#eeeeee"
| Gateway || [[Gateway W730-K8X | W730-K8X]] || Socket 754 |||| ?? || ?? || ?? || SST 39VF040 || ?? || yes || PLCC || [[User:Juri|Juri]]
|- bgcolor="#dddddd"
| Gateway || [[Gateway 6020GZ|6020GZ]] || Celeron M 1.4Ghz || Intel 855GME |||| ?? || ?? || ?? || ?? || no || ?? || [[User:Juri|Juri]]
|- bgcolor="#eeeeee"
| Gericom || Webboy 340S2 || PIII || SiS630 |||| NSC PC87393VJG || NSC PC87570 || Winbond 29C020 || 256 kB || yes || PLCC || [http://thread.gmane.org/gmane.linux.bios/13081 NS]
|- bgcolor="#dddddd"
| Getac || P470 || Intel® Core 2 Duo Mobile || Intel 945 || Intel ICH7 || ? || ? || ? || 8Mb || no || SPI / SOIC8 || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#eeeeee"
| Highscreen || XD 14-C1700 || Intel Celeron 1.7 GHz || SiS650 |||| NSC PC87391(?) || ? || EON EN29F040(A) || 512 kB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| HP || Omnibook XE3(L) || PIII, 750 MHz || Intel 82371MB ||Intel PIIX4M || SMSC FDC37N869 || NSC PC87570 || SST 28SF040A || 512 kB || no || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| IBM || Thinkpad T30 || Intel P4 Mobile, 1.8 GHz || Intel i845 || Intel ICH3-M || NSC PC87392 || Renesas H8S 64F3169ATE10 || ST M50FW080N5 || 1024 kB || no || TSOP40 / FWH || edgecase
|- bgcolor="#dddddd"
| MSI || Wind U100 || Intel Atom N280 1.66Ghz || Intel 945GSE || Intel ICH7-M || ? || ENE KB3310 || SST MX25L8005 || 8 Mb|| no || TSOP40 / SPI || ?
|- bgcolor="#eeeeee"
| One || [http://www.a110wiki.de A110] || VIA C7-M ULV 1.0 GHz || VIA VX800 |||| none || ENE KB3310 || ? || ? || no || ? || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Panasonic || Toughbook CF-25 || P166MMX || FW82439TX (430TX) || FW82371AB || NSC PC87336VJG || Renesas 3886 || SST SST29EE020 || 256 kB || no || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Roda || Rocky III+ RK886EX || Intel® Core 2 Duo Mobile T5500 || Intel 945 || Intel ICH7 || SMSC® LPC47N227 || Renesas M38859 || SST SST49LF080 || 8Mb || yes || PLCC || [[User:Stepan|Stefan Reinauer]]
|- bgcolor="#dddddd"
| Roda || Rocky II+ RT686 || Intel Pentium III || Intel 430BX || Intel FW82371EB || SMSC® FDC37N769 || Renesas M38867M8A || SST SST29LE020 || 256KB || yes || PLCC/parallel || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| Sony || Vaio Picturebook PCG-C1XD || P2 400 || 443ZX |||| ? || ? || ST M29W004BT || 512 kB || no || || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Sony || Vaio Picturebook PCG-C1X || P266MMX || 430TX |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Toshiba || Libretto 50M PA1243CM || P133 || custom FPGA |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Toshiba || Satellite A80-117 || Intel Celeron || Intel 915GM || Intel ICH6 || SMSC LPC47N217 || ENE KB910 || ? || 1024 kB || no || TSOP (?) || [[User:Uwe|UH]]

|}


1 According to the vendor BIOS update tool. 
2 Nice thing: EC/Flash is not shared, so you can erase the whole flash during system operation (this was tested). 


Further links:

* [http://tuxmobil.org/mylaptops.html Tuxmobil Laptop Survey]
* [http://mcelrath.org/laptops.html Laptops/Notebooks with Linux Preinstalled]
* [http://www.fsf.org/campaigns/free-bios.html The Free Software Foundation's Campaign for Free BIOS]

== Mailinglist discussion ==

A few earlier coreboot discussions on laptops are linked here, you might get useful information out of them:

* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010985.html Any update on coreboot for laptops]
* [http://comments.gmane.org/gmane.linux.bios/13081 Notebook 340s2 (sis630) 256k Flash]
* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010972.html yet another reason to use coreboot in laptops I guess]
* [http://www.coreboot.org/pipermail/linuxbios/2005-April/011429.html coreboot laptop hunt wiki page]
* [http://www.coreboot.org/pipermail/linuxbios/2005-March/011140.html HP Pavillion ZV5000 (Laptop)]
* [http://www.coreboot.org/pipermail/linuxbios/2005-July/011942.html SA1100]
* [http://www.coreboot.org/pipermail/linuxbios/2003-September/004954.html Laptop with Sis 650 chipset]
* [http://www.coreboot.org/pipermail/linuxbios/2006-September/015551.html coreboot on Laptops]

== Who really makes your laptop? ==

There are several various brands of laptops, but there are only a few actual laptop makers.

Name brand companies like Hewlet Packard, Compaq, IBM, Dell, Gateway, Sony, Micron, Toshiba and others; including Alienware and Voodoo do not make their own laptops. The exceptions are Asus and Apple, and even Apple doesn't make all of their laptops.

Original Design Manufacturers (ODM) make the laptops for Original Equipment Manufacturers (OEM). They in turn, add their preloaded hard drives and sell them to consumers. This is why a laptop is a bit more complicated to support with coreboot. The OEM's may not even have all the specifications for the laptop since the ODM has done all the design and assembly.

Some laptop ODMs are:

* [http://www.quantatw.com Quanta] makes laptops for Sony, Dell, and IBM
* [http://www.inventec.com/ Inventec] and [http://www.arima.com.tw/ Arima] make the Compaq line
* [http://www.compal.com/ Compal] also makes IBM and Dell lines, as well as Hewlett Packard
* [http://www.clevo.com.tw/ Clevo] makes the popular Alienware and Voodoo gaming laptops

Further links:

* [http://www.laptopworldwide.com/laptops.html Makers of Laptops]
* [http://tuxmobil.org/laptop_oem.html Laptop and NoteBook Manufacturer - OEM/ODM Relation Matrix]
* [http://tuxmobil.org/reseller.html Where to Buy a Preinstalled Linux Laptop, Notebook, Mobile Phone or PDA? - Vendor Overview]

== Random product links ==

VIA has a list of many netbooks at [http://via.com.tw/en/products/notebook/notebook.jsp VIA Partner Mobility Devices].

VIA also has information on other mobile platforms at [http://via.com.tw/en/products/notebook/index.jsp VIA Mobility Platform].

The [http://www.a110wiki.de Quanta IL1] vx800 based reference design covers similar models/clones such as:

*[http://www.one.de/shop/one-notebooks-one-mini-notebooks-c-213_214.html One Mini A110/A115/A120/A140/A150/A470]
*[http://preview.tinyurl.com/5zbzl6 Airis Kira 100/350/740]
*[http://www.norhtec.com/products/gecko/index.html Norhtec Gecko]
*[http://www.pioneercomputers.com.au/products/configure.asp?c1=3&c2=12&id=2458 Pioneer DreamBook Light IL1]
*[http://www.ctlcorp.com/v4/p-697-ctl-il1a-89-netbook-with-windows-xp-home.aspx CTL IL1] More [http://www.a110wiki.de/wiki/CTL_IL1 CTL IL1 info] with tear-down pics.
*[http://www.aci-asia.com/html/Ethos_7.html ACi Ethos 7]
*[http://www.ilikeblue.net/products/umpc.htm BDSI Deep Blue H1]

Other vx800 based netbooks:

*[http://www.everex.com/products/cloudbook_max/cloudbook_max.htm Everex CloudBook MAX]
*[http://www.fic.com.tw/product/ce2a1.aspx FIC CE2A1]

There are still a few netbook designs currently on the market that use the VIA vx700 chipset:

*[http://www.sylvaniacomputers.com/products.php?p=g Sylvania G]
*[http://www.everex.com/products/cloudbook/cloudbook.htm Everex Cloudbook]
*[http://www.fic.com.tw/product/ce260.aspx FIC CE260]
*[http://www.fic.com.tw/product/ce268.aspx FIC CE268]

There are also several AMD 690/600 laptops still available that may be candidates as well:

*[http://reviews.cnet.com/laptops/acer-extensa-4420-5963/4505-3121_7-33361062.html Acer Extensa 4420]
*[http://www.raondigital.com EVERUN NOTE]

Intel Atom with i945 chipset netbooks:

*[http://en.wikipedia.org/wiki/Aspire_One Acer Aspire One]
*[http://en.wikipedia.org/wiki/MSI_Wind_PC MSI Wind]
*[http://en.wikipedia.org/wiki/ASUS_Eee_PC ASUS eeePC]

Laptop

2010-05-31T21:57:30Z

XVilka: Add short guide to find a difficulty to laptop support

== Recent progress of coreboot on laptops ==

* coreboot supports the [http://en.getac.com/products/P470/P470_overview.html Getac P470] semi rugged notebook, based on Intel 82945GM/ICH7.
* coreboot supports the [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda RK886EX (Rocky III+)] laptop, based on Intel 82945GM/ICH7.
* VIA has recently released open documentation for the VX700 and VX800 chipsets at the [http://linux.via.com.tw/support/downloadFiles.action VIA Download Portal].

== Embedded controllers ==

The remaining issue with supporting netbooks may be open firmware support for the [[Embedded controller]] (EC).
These ECs used to support keyboard scan, lid open/closed, battery charging, power management, etc.

coreboot should work with the "stock" EC firmware. This may still be a challenge because "we don't know what we don't know". Behavior at runtime is fairly standardized, but we don't know what we need to do for initialization - do we need to set up registers, put in tables, kick things, or will it all Just Work (TM)?

== HOWTO to find a way ==

* find a model and manufacturer of your laptop
* download a superiotool (latest svn) and build it
* run as root 'superiotool -deV' and save output
* download a ectool (latest svn) and build it
* run as root 'ectool' and save output
* try to find information - what EC or Super I/O chip is used in your laptop (may be some info in Service Manuals or Disassembly guides)
* if you see that ectool return some fake staff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support
* if you see that ectool return looks like 'right' output - you have a big chances for support
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop
* try to find your Super I/O / EC chip datasheet

== Laptop survey ==

This page attempts to list chipsets, Super I/Os, flash chips, and especially [[embedded controller]]s used in various laptops.

{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Vendor
! align="left" | Model
! align="left" | CPU
! align="left" | Chipset NB
! align="left" | Chipset SB
! align="left" | Super I/O
! align="left" | [[Embedded controller|EC]]
! align="left" | Flash Chip
! align="left" | Flash Size
! align="left" | Flash S.
! align="left" | Flash T.
! align="left" | Owner

|- bgcolor="#dddddd"
| ASUS || S96F/Z96F || Intel Core™2 Duo T7400 || Intel i945 || Intel ICH7 || ITE IT8510E || in Super I/O || ? || ? || ? || ? || [http://www.flashrom.org/pipermail/flashrom/2010-January/001986.html macavity]
|- bgcolor="#eeeeee"
| Acer || Aspire One ZG5 || Intel Atom N270 1.6GHz || Intel 82945GME || Intel NH82801GBM ICH7-M || Winbond WPCE775LA0DG || in Super I/O || Winbond 25x80AVSIG || 8Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Acer || Aspire 3613LC || Intel Celeron M 370 1.5GHz L2: 1MB || Intel 82910GML || Intel FW82801FBM SL7W6 ICH6-M || ? || ? || PMC 0537 PM39LV040-70JCE || 1Mb || no || SOIP/DIP || [[User:XVilka|XVilka]]
|- bgcolor="#eeeeee"
| Dell || [[Dell Latitude CPi A366XT|Latitude CPi A366XT]] || PII, 360 MHz || Intel 440BX |||| SMSC FDC37N958FR || in Super I/O || AMD AM29F040B || 512KB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| Dell || [[Dell Latitude C610|Latitude C610]] || PIII, 1.2 GHz || Intel i830 |||| SMSC LPC47N252 || in Super I/O || SST SST49LF004A || 512KB || no || PLCC || [mailto:coreboot@miradou.com CybFr]
|- bgcolor="#eeeeee"
| Dell || Dell Vostro V13 || Intel Celeron 743 1.2GHz, L2: 1MB (Ultra Low Voltage) || Mobile Intel GS45 Express GHMC ||Intel 82801IEM ICH9M-E|| none || ITE IT8502E || Winbond 25Q16BVSIG || 2Mb || no || SOIP/PDIP || [[User:XVilka|XVilka]]
|- bgcolor="#dddddd"
| Fujitsu-S. || Lifebook S-4572 || PIII, 750 MHz || Intel 82440MX |||| SMSC FDC37N769 || ? || Fujitsu MBM29F400T1 || ? || no || TSOP(?) || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Fujitsu-S. || Lifebook S7110 || Intel Core™2 Duo T7200 || Intel i945 || Intel ICH7 || SMSC LPC47N217 || Fujitsu MB90378 || Spansion S25FL008A2 || 1024 kB || no || SO8 / SPI || twice11
|- bgcolor="#eeeeee"
| Gericom || Webboy 340S2 || PIII || SiS630 |||| NSC PC87393VJG || NSC PC87570 || Winbond 29C020 || 256 kB || yes || PLCC || [http://thread.gmane.org/gmane.linux.bios/13081 NS]
|- bgcolor="#dddddd"
| Gateway || [[Gateway W730-K8X | W730-K8X]] || Socket 754 |||| ?? || ?? || ?? || SST 39VF040 || ?? || yes || PLCC || [[User:Juri|Juri]]
|- bgcolor="#dddddd"
| Gateway || [[Gateway 6020GZ|6020GZ]] || Celeron M 1.4Ghz || Intel 855GME |||| ?? || ?? || ?? || ?? || no || ?? || [[User:Juri|Juri]]
|- bgcolor="#dddddd"
| Highscreen || XD 14-C1700 || Intel Celeron 1.7 GHz || SiS650 |||| NSC PC87391(?) || ? || EON EN29F040(A) || 512 kB || yes || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| HP || Omnibook XE3(L) || PIII, 750 MHz || Intel 82371MB ||Intel PIIX4M || SMSC FDC37N869 || NSC PC87570 || SST 28SF040A || 512 kB || no || PLCC || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| IBM || Thinkpad T30 || Intel P4 Mobile, 1.8 GHz || Intel i845 || Intel ICH3-M || NSC PC87392 || Renesas H8S 64F3169ATE10 || ST M50FW080N5 || 1024 kB || no || TSOP40 / FWH || edgecase
|- bgcolor="#eeeeee"
| MSI || Wind U100 || Intel Atom N280 1.66Ghz || Intel 945GSE || Intel ICH7-M || ? || ENE KB3310 || SST MX25L8005 || 8 Mb|| no || TSOP40 / SPI || ?
|- bgcolor="#dddddd"
| One || [http://www.a110wiki.de A110] || VIA C7-M ULV 1.0 GHz || VIA VX800 |||| none || ENE KB3310 || ? || ? || no || ? || [[User:Uwe|UH]]
|- bgcolor="#eeeeee"
| Panasonic || Toughbook CF-25 || P166MMX || FW82439TX (430TX) || FW82371AB || NSC PC87336VJG || Renesas 3886 || SST SST29EE020 || 256 kB || no || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Roda || Rocky III+ RK886EX || Intel® Core 2 Duo Mobile T5500 || Intel 945 || Intel ICH7 || SMSC® LPC47N227 || Renesas M38859 || ? || ? || ? || ? || ?
|- bgcolor="#eeeeee"
| Roda || Rocky II+ RT686 || Intel Pentium III || Intel 430BX || Intel FW82371EB || SMSC® FDC37N769 || Renesas M38867M8A || SST SST29LE020 || 256KB || yes || PLCC/parallel || [[User:Uwe|UH]]
|- bgcolor="#dddddd"
| Sony || Vaio Picturebook PCG-C1XD || P2 400 || 443ZX |||| ? || ? || ST M29W004BT || 512 kB || no || || [[User:Miernik|Miernik]]
|- bgcolor="#dddddd"
| Sony || Vaio Picturebook PCG-C1X || P266MMX || 430TX |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Toshiba || Libretto 50M PA1243CM || P133 || custom FPGA |||| ? || ? || ? || ? || ? || ? || [[User:Miernik|Miernik]]
|- bgcolor="#eeeeee"
| Toshiba || Satellite A80-117 || Intel Celeron || Intel 915GM || Intel ICH6 || SMSC LPC47N217 || ENE KB910 || ? || 1024 kB || no || TSOP (?) || [[User:Uwe|UH]]

|}


1 According to the vendor BIOS update tool. 
2 Nice thing: EC/Flash is not shared, so you can erase the whole flash during system operation (this was tested). 


Further links:

* [http://tuxmobil.org/mylaptops.html Tuxmobil Laptop Survey]
* [http://mcelrath.org/laptops.html Laptops/Notebooks with Linux Preinstalled]
* [http://www.fsf.org/campaigns/free-bios.html The Free Software Foundation's Campaign for Free BIOS]

== Mailinglist discussion ==

A few earlier coreboot discussions on laptops are linked here, you might get useful information out of them:

* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010985.html Any update on coreboot for laptops]
* [http://comments.gmane.org/gmane.linux.bios/13081 Notebook 340s2 (sis630) 256k Flash]
* [http://www.coreboot.org/pipermail/linuxbios/2005-February/010972.html yet another reason to use coreboot in laptops I guess]
* [http://www.coreboot.org/pipermail/linuxbios/2005-April/011429.html coreboot laptop hunt wiki page]
* [http://www.coreboot.org/pipermail/linuxbios/2005-March/011140.html HP Pavillion ZV5000 (Laptop)]
* [http://www.coreboot.org/pipermail/linuxbios/2005-July/011942.html SA1100]
* [http://www.coreboot.org/pipermail/linuxbios/2003-September/004954.html Laptop with Sis 650 chipset]
* [http://www.coreboot.org/pipermail/linuxbios/2006-September/015551.html coreboot on Laptops]

== Who really makes your laptop? ==

There are several various brands of laptops, but there are only a few actual laptop makers.

Name brand companies like Hewlet Packard, Compaq, IBM, Dell, Gateway, Sony, Micron, Toshiba and others; including Alienware and Voodoo do not make their own laptops. The exceptions are Asus and Apple, and even Apple doesn't make all of their laptops.

Original Design Manufacturers (ODM) make the laptops for Original Equipment Manufacturers (OEM). They in turn, add their preloaded hard drives and sell them to consumers. This is why a laptop is a bit more complicated to support with coreboot. The OEM's may not even have all the specifications for the laptop since the ODM has done all the design and assembly.

Some laptop ODMs are:

* [http://www.quantatw.com Quanta] makes laptops for Sony, Dell, and IBM
* [http://www.inventec.com/ Inventec] and [http://www.arima.com.tw/ Arima] make the Compaq line
* [http://www.compal.com/ Compal] also makes IBM and Dell lines, as well as Hewlett Packard
* [http://www.clevo.com.tw/ Clevo] makes the popular Alienware and Voodoo gaming laptops

Further links:

* [http://www.laptopworldwide.com/laptops.html Makers of Laptops]
* [http://tuxmobil.org/laptop_oem.html Laptop and NoteBook Manufacturer - OEM/ODM Relation Matrix]
* [http://tuxmobil.org/reseller.html Where to Buy a Preinstalled Linux Laptop, Notebook, Mobile Phone or PDA? - Vendor Overview]

== Random product links ==

VIA has a list of many netbooks at [http://via.com.tw/en/products/notebook/notebook.jsp VIA Partner Mobility Devices].

VIA also has information on other mobile platforms at [http://via.com.tw/en/products/notebook/index.jsp VIA Mobility Platform].

The [http://www.a110wiki.de Quanta IL1] vx800 based reference design covers similar models/clones such as:

*[http://www.one.de/shop/one-notebooks-one-mini-notebooks-c-213_214.html One Mini A110/A115/A120/A140/A150/A470]
*[http://preview.tinyurl.com/5zbzl6 Airis Kira 100/350/740]
*[http://www.norhtec.com/products/gecko/index.html Norhtec Gecko]
*[http://www.pioneercomputers.com.au/products/configure.asp?c1=3&c2=12&id=2458 Pioneer DreamBook Light IL1]
*[http://www.ctlcorp.com/v4/p-697-ctl-il1a-89-netbook-with-windows-xp-home.aspx CTL IL1] More [http://www.a110wiki.de/wiki/CTL_IL1 CTL IL1 info] with tear-down pics.
*[http://www.aci-asia.com/html/Ethos_7.html ACi Ethos 7]
*[http://www.ilikeblue.net/products/umpc.htm BDSI Deep Blue H1]

Other vx800 based netbooks:

*[http://www.everex.com/products/cloudbook_max/cloudbook_max.htm Everex CloudBook MAX]
*[http://www.fic.com.tw/product/ce2a1.aspx FIC CE2A1]

There are still a few netbook designs currently on the market that use the VIA vx700 chipset:

*[http://www.sylvaniacomputers.com/products.php?p=g Sylvania G]
*[http://www.everex.com/products/cloudbook/cloudbook.htm Everex Cloudbook]
*[http://www.fic.com.tw/product/ce260.aspx FIC CE260]
*[http://www.fic.com.tw/product/ce268.aspx FIC CE268]

There are also several AMD 690/600 laptops still available that may be candidates as well:

*[http://reviews.cnet.com/laptops/acer-extensa-4420-5963/4505-3121_7-33361062.html Acer Extensa 4420]
*[http://www.raondigital.com EVERUN NOTE]

Intel Atom with i945 chipset netbooks:

*[http://en.wikipedia.org/wiki/Aspire_One Acer Aspire One]
*[http://en.wikipedia.org/wiki/MSI_Wind_PC MSI Wind]
*[http://en.wikipedia.org/wiki/ASUS_Eee_PC ASUS eeePC]