ASUS A8N-E - Revision history

Stepan: /* Building coreboot */

2010-05-05T08:06:49Z

‎Building coreboot

Stepan: /* Building coreboot */ svn paths

2009-10-30T18:26:42Z

‎Building coreboot: svn paths

Uwe at 00:06, 1 June 2009

2009-06-01T00:06:14Z

Uwe: ASUS A8N-E Build Tutorial moved to ASUS A8N-E

2008-11-16T14:04:05Z

ASUS A8N-E Build Tutorial moved to ASUS A8N-E

Uwe: Status updates.

2008-10-03T19:46:02Z

Status updates.

Uwe: Both PCIe x1 slots works fine (tested with a network card).

2008-09-30T17:29:06Z

Both PCIe x1 slots works fine (tested with a network card).

Uwe: /* Status */ PS/2 mouse works.

2008-09-30T16:51:08Z

‎Status: PS/2 mouse works.

Uwe: Update HOWTO and documentation.

2008-09-30T01:48:26Z

Update HOWTO and documentation.

AndyJ at 21:12, 29 September 2008

2008-09-29T21:12:22Z

Uwe: /* Status */ CDROM works fine, HPET can be enabled via "hpet=force".

2008-04-23T20:33:13Z

‎Status: CDROM works fine, HPET can be enabled via "hpet=force".

@@ Line 109: / Line 109: @@
 == Building coreboot ==
- $ svn co svn://coreboot.org/coreboot/trunk coreboot
+See the [[Build HOWTO]] for information on how to build coreboot for this board.
- $ cd coreboot/targets
- $ ./buildtarget asus/a8n_e
- $ cd asus/a8n_e/asus_a8n_e
-−
-Now place your payload in this directory and name it '''payload.elf'''. Complete the build with:
-−
- $ make
-−
-The resulting '''coreboot.rom''' file (512 KB) can now be flashed using e.g. [[flashrom]].
 == Known issues ==

@@ Line 109: / Line 109: @@
 == Building coreboot ==
-  $ svn co svn://coreboot.org/repos/trunk/coreboot-v2
+  $ svn co svn://coreboot.org/coreboot/trunk coreboot
-  $ cd coreboot-v2/targets
+  $ cd coreboot/targets
   $ ./buildtarget asus/a8n_e
   $ cd asus/a8n_e/asus_a8n_e

@@ Line 54: / Line 54: @@
 |PCI_cards_status = OK
 |PCI_cards_comments = Tested: PCI VGA card in all three PCI slots.
 |AGP_cards_status = N/A
 |PCIE_x1_status = OK

@@ Line 22: / Line 22: @@
 |RAM_SODIMM_status = N/A
 |RAM_DDR_status = OK
-|RAM_DDR_comments = Tested with one DIMM in slot DIMM_B1 (see manual).
+|RAM_DDR_comments = Tested with one DIMM in slot DIMM_B1 (see manual). Since [http://tracker.coreboot.org/trac/coreboot/changeset/3614 r3614] it's also possible to use a single DIMM in slot DIMM_B2.
 |RAM_DDR2_status = N/A
 |RAM_DDR3_status = N/A
@@ Line 42: / Line 42: @@
 |Onboard_VGA_status = N/A
 |Onboard_ethernet_status = OK
-|Onboard_audio_status = Untested
+|Onboard_audio_status = WIP
 |Onboard_modem_status = N/A
 |Onboard_firewire_status = N/A
@@ Line 59: / Line 60: @@
 |PCIE_x4_status = Untested
 |PCIE_x8_status = N/A
-|PCIE_x16_status = Untested
+|PCIE_x16_status = WIP
 |PCIE_x32_status = N/A
 |HTX_status = N/A
-|Floppy_status = Untested
+|Floppy_status = WIP
 |COM1_status = OK
 |COM2_status = N/A
@@ Line 72: / Line 74: @@
 |PS2_mouse_status = OK
 |PS2_mouse_comments = Works since [http://tracker.coreboot.org/trac/coreboot/changeset/3610 r3610],
-|Game_port_status = Untested
+|Game_port_status = WIP
 |IR_status = N/A
 |Speaker_status = OK
@@ Line 118: / Line 120: @@
 == Known issues ==
 * The MAC address is stored in flash for almost all CK804/MCP55 boards. All of these boards flashed with coreboot probably have the same MAC address. See '''src/southbridge/nvidia/ck804/romstrap.inc''' and '''src/southbridge/nvidia/mcp55/romstrap.inc''' for details. On some of these boards, the MAC address is stored in a separate EEPROM, but you can't count on that.
 If you can help out with this, please join the [[Mailinglist|mailing list]] and let us know!
 {{GPL}}

@@ Line 54: / Line 54: @@
 |PCI_cards_comments = Tested: PCI VGA card in all three PCI slots.
 |AGP_cards_status = N/A
-|PCIE_x1_status = Untested
+|PCIE_x1_status = OK
 |PCIE_x2_status = N/A
 |PCIE_x4_status = Untested

@@ Line 69: / Line 69: @@
 |PS2_keyboard_status = OK
 |PS2_keyboard_comments = Works since [http://tracker.coreboot.org/trac/coreboot/changeset/3610 r3610],
-|PS2_mouse_status = WIP
+|PS2_mouse_status = OK
-|PS2_mouse_comments = Doesn't seem to work yet, this is being investigated.
+|PS2_mouse_comments = Works since [http://tracker.coreboot.org/trac/coreboot/changeset/3610 r3610],
 |Game_port_status = Untested
 |IR_status = N/A

@@ Line 68: / Line 68: @@
 |PP_comments = Tested: '''modprobe ppdev''', further tests were not performed.
 |PS2_keyboard_status = OK
-|PS2_keyboard_comments = use Rev. >=3610
+|PS2_keyboard_comments = Works since [http://tracker.coreboot.org/trac/coreboot/changeset/3610 r3610],
 |PS2_mouse_status = WIP
 |PS2_mouse_comments = Doesn't seem to work yet, this is being investigated.
@@ Line 102: / Line 102: @@
 }}
-== Before you begin ==
+== Building coreboot ==
-The '''ASUS A8N-E''' is an Athlon64 Socket 939 board (nforce 4 ultra) with socketed BIOS sold around €120 (mostly out of stock in 8/2007; used items at eBay ~ €20-35). It already boots coreboot. Latest legacy BIOS is from May 2006 v.1013. Socket 939 Athlons do not have Pacifica Virtualization.
+ $ svn co svn://coreboot.org/repos/trunk/coreboot-v2
-The '''ASUS A8N-SLI Deluxe''', an "nforce 4 sli" board probably shares the same PCB design with more solder pads populated (please confirm), and is also out of stock mostly.
+Now place your payload in this directory and name it '''payload.elf'''. Complete the build with:
-The '''ASUS A8NE-FM/S''' has initial support in the form of [http://www.coreboot.org/pipermail/linuxbios/2007-July/023029.html a patch].
+ $ make
-Hot plugging a BIOS chip was successfully done (pull out chip with glued-on handle while running Linux), so you don't necessarily need an external EPROM programmer, just a spare working 49LF004 chip. 8 MBit SST 49LF080A was also successfully flashed and booted with legacy BIOS (two images concatenated).
+The resulting '''coreboot.rom''' file (512 KB) can now be flashed using e.g. [[flashrom]].
-The PLCC32 BIOS chip is of type SST 49LF004B of which you need a spare programmed piece. You might reflash an empty or used one plugged into your A8N.
-−
-Enable Serial Console for debugging. It will come up at 115200,8n1 option SERIAL_CONSOLE
-The revisions 3000 and up work, but don't expect anything to see on the POST card. The serial Terminal will show whether LB manages with your RAM.
-−
-run targets/buildtarget
-then run make in the A8N-E directory. you get a 512KB image.
-abuild may come up with a 508KB image, which is not working.
-−
-−
-in bash you may type
-svn co svn://coreboot.org/buildrom
-then type "make menuconfig" but the A8NE is not supported there yet.
 == Known issues ==
-* this tutorial is not as complete as the one for Gigabyte M57-SLI, so please look there for info on building the image.
+* Single DIMM support only: the blue DIMM_B1 socket should be populated only (for now).
+* The MAC address is stored in flash for almost all CK804/MCP55 boards. All of these boards flashed with coreboot probably have the same MAC address. See '''src/southbridge/nvidia/ck804/romstrap.inc''' and '''src/southbridge/nvidia/mcp55/romstrap.inc''' for details. On some of these boards, the MAC address is stored in a separate EEPROM, but you can't count on that.
-* Currently PS/2 keyboards do not work, but USB keyboards do. --> this was fixed with Rev.3610
 * Single DIMM support only : the blue DIMM_B1 socket should be populated only.
-* The MAC address is stored in flash for almost all CK804/MCP55 boards. All of these boards flashed with LB probably have the same MAC address. See src/southbridge/nvidia/ck804/romstrap.inc and src/southbridge/nvidia/mcp55/romstrap.inc for details. On some of these boards, the MAC address is stored in a separate EEPROM, but you can't count on that.
 == TODO ==

@@ Line 34: / Line 34: @@
 |IDE_CF_status = OK
 |IDE_CF_comments = Tested: Primary IDE (master and slave) and secondary IDE (master and slave).
-|CDROM_DVD_status = Untested
+|CDROM_DVD_status = OK
 |SATA_status = WIP
-|SATA_comments = Port 3 (''hde'' in FILO) and 4 (''hdg'' in FILO) on the board work fine. Port 1 and 2 don't seem to work, this is being investigated.
+|SATA_comments = Port 3 ('''hde''' in FILO) and 4 ('''hdg''' in FILO) on the board work fine. Port 1 and 2 don't seem to work, this is being investigated.
 |USB_status = OK
 |USB_comments = Tested: USB keyboard (on each of the 10 possible USB ports).
@@ Line 88: / Line 89: @@
 |LEDs_status = OK
 |LEDs_comments = There's a green LED on the board which is enabled when the board is powered-on. Works out of the box, no special coreboot support required.
-|HPET_status = Untested
+|HPET_status = OK
-|HPET_comments = Doesn't seem to be enabled right now, but [http://lkml.org/lkml/2007/10/19/226 the hardware seems to support it].
+|HPET_comments = The hardware [http://lkml.org/lkml/2007/10/19/226 supports it], but you currently need the '''hpet=force''' Linux kernel parameter. Reduces the number of wakeups in powertop ''drastically''.
 |RNG_status = N/A
 |WakeOnModem_status = Untested