Difference between revisions of "Board:asus/a8n sli"
Revision as of 00:31, 1 June 2009
This HOWTO explains how to use coreboot on the A8N-SLI board.
|CPU works||OK||Tested: TODO|
|L1 cache enabled||OK||CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)|
|L2 cache enabled||OK||CPU: L2 Cache: 512K (64 bytes/line)|
|L3 cache enabled||N/A|
|Multiple CPU support||N/A|
|DDR||WIP||See known Issues, only DIMMs A2_B2 or B2 will allow boot.|
|Dual channel support||Untested|
|On-board IDE 3.5"|
|On-board IDE 2.5"||N/A|
|On-board SATA||WIP||See known Issues, Only SATA port 3 is tested as working|
|On-board audio||WIP||This is being worked on.|
|On-board smartcard reader||N/A|
|ISA add-on cards||N/A|
|Audio/Modem-Riser (AMR/CNR) cards||N/A|
|PCI add-on cards||No||see known issues|
|Mini-PCI add-on cards||N/A|
|PCI-X add-on cards||N/A|
|AGP graphics cards||N/A|
|PCI Express x1 add-on cards|
|PCI Express x2 add-on cards||N/A|
|PCI Express x4 add-on cards||Untested|
|PCI Express x8 add-on cards||N/A|
|PCI Express x16 add-on cards||WIP||Will boot with a card in PCIEX16_1, if card outputs to screen is untested|
|PCI Express x32 add-on cards||N/A|
|HTX add-on cards||N/A|
|Legacy / Super I/O|
|Serial port 1 (COM1)||OK|
|Serial port 2 (COM2)||N/A|
|Sensors / fan control|
|CPU frequency scaling||No||Needs (at least partial) ACPI support.|
|Other powersaving features||N/A|
|ACPI||No||There's no ACPI implementation for this board.|
|High precision event timers (HPET)|
|Random number generator (RNG)||N/A|
|Wake on modem ring||Untested|
|Wake on LAN|
|Wake on keyboard||Untested|
|Wake on mouse||Untested|
Note: you can use the same target as for the ASUS A8N-E board. At the time of writing there's no specific target for the ASUS A8N-SLI Standard.
$ svn co svn://coreboot.org/repos/trunk/coreboot-v2 $ cd coreboot-v2/targets $ ./buildtarget asus/a8n_e $ cd asus/a8n_e/asus_a8n_e
Now place your payload in this directory and name it payload.elf. Complete the build with:
The resulting coreboot.rom file (512 KB) can now be flashed using e.g. flashrom.
- The MAC address is stored in flash for almost all CK804/MCP55 boards. All of these boards flashed with coreboot probably have the same MAC address. See src/southbridge/nvidia/ck804/romstrap.inc and src/southbridge/nvidia/mcp55/romstrap.inc for details. On some of these boards, the MAC address is stored in a separate EEPROM, but you can't count on that.
- halt -p / shutdown -P fails due to no acpi
- possible issue if PCI card in PCI_1 causing hang
- SATA ports 1 and 2 will not allow disk to be found SATA port 3 works and 4 is untested.
- 512mb ram, DIMM A1 ( 1x512mb ) - Boots
- 512mb ram, DIMM A2 ( 1x512mb ) - Hangs
- 512mb ram, DIMM B1 ( 1x512mb ) - Hangs
- 512mb ram, DIMM B2 ( 1x512mb ) - Hangs
- 1gb ram, DIMMs A2_B2 ( 2x512mb ) - Boots
- 1.5Gb Ram, DIMMS A2_B2_B1 (3x512Mb) - Hangs on Ram2.00
- 1.5Gb Ram, DIMMS A2_B2_A1 (3x512Mb) - Hangs on Ram2.00
- 1.5Gb Ram, DIMMS A2_B2_B1_A1 (4x512Mb) - Hangs on Ram2.00
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