Difference between revisions of "ASUS M4A785T-M"

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(→‎PCIe)
Line 207: Line 207:
  
 
== PCIe ==
 
== PCIe ==
 +
From 53a89c25ce07fe70d2ec60098049714e3f483db2 Mon Sep 17 00:00:00 2001
 +
From: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
 +
Date: Tue, 18 Sep 2012 19:35:44 +0200
 +
Subject: [PATCH] IRQ tables for getting the PCIe graphic card working
 +
 +
Change-Id: Ie99ee5adaf997cb94c96eb1942d1089ab2528f85
 +
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
 +
---
 +
  src/mainboard/asus/m4a785-m/irq_tables.c  |    6 +++---
 +
  src/mainboard/asus/m4a785t-m/devicetree.cb |    6 +++---
 +
  2 files changed, 6 insertions(+), 6 deletions(-)
 +
 +
diff --git a/src/mainboard/asus/m4a785-m/irq_tables.c b/src/mainboard/asus/m4a785-m/irq_tables.c
 +
index 4edeec1..e02cd28 100644
 +
--- a/src/mainboard/asus/m4a785-m/irq_tables.c
 +
+++ b/src/mainboard/asus/m4a785-m/irq_tables.c
 +
@@ -23,7 +23,7 @@
 +
  const struct irq_routing_table intel_irq_routing_table = {
 +
  PIRQ_SIGNATURE, /* u32 signature */
 +
  PIRQ_VERSION, /* u16 version */
 +
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
 +
+ 32 + 16 * 19, /* Max. number of devices on the bus */
 +
  0x00, /* Interrupt router bus */
 +
  (0x14 << 3) | 0x3, /* Interrupt router dev */
 +
  0, /* IRQs devoted exclusively to PCI usage */
 +
@@ -31,14 +31,14 @@ const struct irq_routing_table intel_irq_routing_table = {
 +
  0x439d, /* Device */
 +
  0, /* Miniport */
 +
  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 +
- 0x8, /* Checksum (has to be set to some value that
 +
+ 0x2e, /* Checksum (has to be set to some value that
 +
  * would give 0 after the sum of all bytes
 +
  * for this structure (including checksum).
 +
                                  */
 +
  {
 +
  /* bus,        dev | fn,  {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
 +
- {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
 +
  {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
 +
+ {0x01, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x2, 0x0},
 +
  {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
 +
  {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
 +
  {0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
 +
diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb
 +
index e8764b1..7095afd 100644
 +
--- a/src/mainboard/asus/m4a785t-m/devicetree.cb
 +
+++ b/src/mainboard/asus/m4a785t-m/devicetree.cb
 +
@@ -10,8 +10,8 @@ chip northbridge/amd/amdfam10/root_complex
 +
  device pci 18.0 on #  northbridge
 +
  chip southbridge/amd/rs780
 +
  device pci 0.0 on end # HT  0x9600
 +
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
 +
- device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
 +
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9602
 +
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
 +
  device pci 3.0 off end # PCIE P2P bridge 0x960b
 +
  device pci 4.0 off end # PCIE P2P bridge 0x9604
 +
  device pci 5.0 off end # PCIE P2P bridge 0x9605
 +
@@ -24,7 +24,7 @@ chip northbridge/amd/amdfam10/root_complex
 +
  register "gpp_configuration" = "3"  # Configuration D default
 +
  register "port_enable" = "0x6fc"
 +
  register "gfx_dev2_dev3" = "1"
 +
- register "gfx_dual_slot" = "2"
 +
+ register "gfx_dual_slot" = "0"
 +
 
 +
  register "gfx_lane_reversal" = "0"
 +
  register "gfx_tmds" = "0"
 +
--
 +
1.7.5.4
  
 
== SerialICE ==
 
== SerialICE ==
 
* Selecting the ASUS M4A77TD-PRO mainboard makes the serialICE shell appear once flashed.
 
* Selecting the ASUS M4A77TD-PRO mainboard makes the serialICE shell appear once flashed.

Revision as of 14:06, 25 September 2012

Contents

Status

Device/functionality Status Comments
CPU
CPU works OK Tested: AMD Athlon64 X2 250.
L1 cache enabled Untested Not tested yet
L2 cache enabled Untested Not tested yet
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support OK
Hardware virtualization Untested Not tested yet
RAM
EDO N/A
SDRAM N/A
SO-DIMM N/A
DDR N/A N/A
DDR2 Untested
DDR3 OK 2G works, 4G(2 * 2G) works with lastest coreboot
Dual channel support Untested
ECC support Untested
On-board Hardware
On-board IDE 3.5" OK Tested: 500GB HDD
On-board IDE 2.5" N/A
On-board SATA OK Tested some ports, works fine
On-board SCSI N/A
On-board USB OK USB keyboard works
On-board VGA OK Tested:analog VGA and HDMI,dual screen.
On-board ethernet OK
On-board audio No Linux driver crashes.
On-board modem N/A
On-board FireWire N/A
On-board smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards OK I've an ath9k wifi PCI card and it works.
Mini-PCI add-on cards N/A
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards Untested
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards No I'll investigate soon
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A There is no floppy connector at all.
Serial port 1 (COM1) OK COM1 is only pin header on board. DB-9 serial connector is available, but not included with board.
Serial port 2 (COM2) N/A
Parallel port Untested No connector, pins on board only
PS/2 keyboard OK
PS/2 mouse Untested
Game port N/A
Infrared N/A
PC speaker Untested
DiskOnChip N/A
Miscellaneous
Sensors / fan control Untested
Hardware watchdog N/A
SMBus Unknown
CAN bus N/A
CPU frequency scaling Untested
Other powersaving features Untested
ACPI Untested
Reboot OK
Poweroff OK
Suspend Unknown
Nonstandard LEDs
High precision event timers (HPET)
Random number generator (RNG) Untested
Wake on modem ring Untested
Wake on LAN
Wake on keyboard Untested
Wake on mouse Untested
Flashrom OK The chip is SPI

Introduction

This pages is about the port to the M4A785T-M, this mainboard is very similar to the M4A785-M, but:

  • it has DDR3 instead of DDR2

The port is in the very early stages...(it will be ok when screen will not flickers at resolutions > 800x600)

Building the serial port adapter

You'll need to build a serial port adapter to get the coreboot logs during. Here's a picture of the serial port connector on the mainboard:
ASUS M4A785T-M serial connector witout serial adapter.jpeg
And here's the kind of cable you will need:
ASUS M4A785T-M serial connector with serial adapter.jpeg
And you'll need to build a cable similar to this one(on the picture the DB9 is connector is a male connector):
ASUS M4A785T-M serial cable.jpeg
Here's how it looks like on the mainboard: 

_____________________
|
|NC|09|
|08|07|
|06|05|
|04|03|
|02|01|
|
|

Here's a table of corresponding pins:

Mainboard connector pin Mainboard pin Function Standard DE9 pin connector Standard DE9 pin Function Mandatory for coreboot
1 ? ? ? No
2 RX 3 TX Yes (you could do without but it's advised to get it, to be able to use certain functions of coreboot)
3 TX 2 RX Yes
4 4 DTR No
5 Ground 5 Ground Yes
6 ? ? ? No
7 7 RTS No
8 8 CTS No
9 ? ? ? No

Adapting GNU/Linux

Before booting with coreboot, do the following:

  • blacklist the snd-hda* modules (refer to the usual way to get help for the GNU/Linux distribution you want to run for doing that)
  • 32bit GNU/Linux trisquel distribution tested
  • 64bit GNU/Linux trisquel distribution failed to initialize the USB.

Building Coreboot

To build coreboot for this mainboard:

  • checkout coreboot revision 1b1309f289d6fc9f6ec348686665d25218535030
  • Configure and Build it as usual(for having graphics you need to extract your VGA BIOS ROM from your BIOS)

PCIe 

From 53a89c25ce07fe70d2ec60098049714e3f483db2 Mon Sep 17 00:00:00 2001
From: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date: Tue, 18 Sep 2012 19:35:44 +0200
Subject: [PATCH] IRQ tables for getting the PCIe graphic card working

Change-Id: Ie99ee5adaf997cb94c96eb1942d1089ab2528f85
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
---
 src/mainboard/asus/m4a785-m/irq_tables.c   |    6 +++---
 src/mainboard/asus/m4a785t-m/devicetree.cb |    6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/asus/m4a785-m/irq_tables.c b/src/mainboard/asus/m4a785-m/irq_tables.c
index 4edeec1..e02cd28 100644
--- a/src/mainboard/asus/m4a785-m/irq_tables.c
+++ b/src/mainboard/asus/m4a785-m/irq_tables.c
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
+	32 + 16 * 19,		/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x14 << 3) | 0x3,	/* Interrupt router dev */
 	0,			/* IRQs devoted exclusively to PCI usage */
@@ -31,14 +31,14 @@ const struct irq_routing_table intel_irq_routing_table = {
 	0x439d,			/* Device */
 	0,			/* Miniport */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x8,			/* Checksum (has to be set to some value that
+	0x2e,			/* Checksum (has to be set to some value that
 				 * would give 0 after the sum of all bytes
 				 * for this structure (including checksum).
                                  */
 	{
 		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
 		{0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x2, 0x0},
 		{0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
 		{0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
 		{0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb
index e8764b1..7095afd 100644
--- a/src/mainboard/asus/m4a785t-m/devicetree.cb
+++ b/src/mainboard/asus/m4a785t-m/devicetree.cb
@@ -10,8 +10,8 @@ chip northbridge/amd/amdfam10/root_complex
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
 					device pci 0.0 on end # HT  	0x9600
-					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
-					device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 1.0 off end # Internal Graphics P2P bridge 0x9602
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
 					device pci 3.0 off end # PCIE P2P bridge	0x960b
 					device pci 4.0 off end # PCIE P2P bridge 0x9604
 					device pci 5.0 off end # PCIE P2P bridge 0x9605
@@ -24,7 +24,7 @@ chip northbridge/amd/amdfam10/root_complex
 					register "gpp_configuration" = "3"   # Configuration D default
 					register "port_enable" = "0x6fc"
 					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "2"
+					register "gfx_dual_slot" = "0"
 
 					register "gfx_lane_reversal" = "0"
 					register "gfx_tmds" = "0"
-- 
1.7.5.4

SerialICE

  • Selecting the ASUS M4A77TD-PRO mainboard makes the serialICE shell appear once flashed.
Retrieved from "http://www.coreboot.org/index.php?title=ASUS_M4A785T-M&oldid=11231"
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