Difference between revisions of "Coreboot Options"

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Until recently, coreboot was using a proprietary config system. For some time you can look at the [[Coreboot Options(old)|old list of options]].
+
This is an automatically generated list of '''coreboot compile-time options''' (using coreboot/util/optionlist utility).
  
This is an automatically generated list of '''coreboot compile-time options'''.
+
Last update: 2013/01/12 17:40:48. (runknown)
 
+
Last update: 2010/02/09 15:05:25. (r5100)
+
 
{| border="0" style="font-size: smaller"
 
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
Line 29: Line 27:
 
the coreboot version number, so that you can easily distinguish
 
the coreboot version number, so that you can easily distinguish
 
boot logs of different boards from each other.
 
boot logs of different boards from each other.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
 +
Select the prefix to all files put into the image. It's "fallback"
 +
by default, "normal" is a common alternative.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_PREFIX || toplevel || string || Compiler to use ||
 +
This option allows you to select the compiler used for building
 +
coreboot.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COMPILER_GCC || toplevel || bool || GCC ||
 +
Use the GNU Compiler Collection (GCC) to build coreboot.
 +
 +
For details see http://gcc.gnu.org.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang ||
 +
Use LLVM/clang to build coreboot.
 +
 +
For details see http://clang.llvm.org.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static code analysis ||
 +
Changes the build process to use scan-build (a utility for
 +
running the clang static code analyzer from the command line).
 +
 +
Requires the scan-build utility in your system $PATH.
 +
 +
For details see http://clang-analyzer.llvm.org/scan-build.html.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory for the scan-build report(s) ||
 +
Directory where the scan-build reports should be stored in. The
 +
reports are stored in subdirectories of the form 'yyyy-mm-dd-*'
 +
in the specified directory.
 +
 +
If this setting is left empty, the coreboot top-level directory
 +
will be used to store the report subdirectories.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||
 +
Enables the use of ccache for faster builds.
 +
 +
Requires the ccache utility in your system $PATH.
 +
 +
For details see https://ccache.samba.org.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||
 +
Enable this option if you are working on the sconfig device tree
 +
parser and made changes to sconfig.l and sconfig.y.
 +
 +
Otherwise, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
 +
Enable this option if coreboot shall read options from the "CMOS"
 +
NVRAM instead of using hard-coded values.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
 +
Compress ramstage to save memory in the flash image. Note
 +
that decompression might slow down booting if the boot flash
 +
is connected through a slow link (i.e. SPI).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||
 +
Include the .config file that was used to compile coreboot
 +
in the (CBFS) ROM image. This is useful if you want to know which
 +
options were used to build a specific coreboot.rom image.
 +
 +
Saying Y here will increase the image size by 2-3kB.
 +
 +
You can use the following command to easily list the options:
 +
 +
grep -a CONFIG_ coreboot.rom
 +
 +
Alternatively, you can also use cbfstool to print the image
 +
contents (including the raw 'config' item we're looking for).
 +
 +
Example:
 +
 +
$ cbfstool coreboot.rom print
 +
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
 +
offset 0x0
 +
Alignment: 64 bytes
 +
 +
Name                          Offset    Type        Size
 +
cmos_layout.bin                0x0        cmos layout  1159
 +
fallback/romstage              0x4c0      stage        339756
 +
fallback/coreboot_ram          0x53440    stage        186664
 +
fallback/payload              0x80dc0    payload      51526
 +
config                        0x8d740    raw          3324
 +
(empty)                        0x8e480    null        3610440
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EARLY_CBMEM_INIT || toplevel || bool || Initialize CBMEM while in ROM stage ||
 +
Make coreboot initialize the cbmem structures while running in ROM
 +
stage. This could be useful when the ROM stage wants to communicate
 +
some, for instance, execution timestamps.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
 +
Make coreboot create a table of timer-ID/timer-value pairs to
 +
allow measuring time spent at different phases of the boot process.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
 +
This draws in the blobs repository, which contains binary files that
 +
might be required for some chipsets or boards.
 +
This flag ensures that a "Free" option remains available for users.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REQUIRES_BLOB || toplevel || bool ||  ||
 +
This option can be configured by boards that require the blobs
 +
repository for the default configuration. It will make the build
 +
fail if USE_BLOBS is disabled. Users that still desire to do a
 +
coreboot build for such a board can override this manually, but
 +
this option serves as warning that it might fail.
  
 
||
 
||
Line 35: Line 169:
 
! align="left" | Menu: Mainboard || || || ||
 
! align="left" | Menu: Mainboard || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_4096 || mainboard || bool || ROM chip size ||  
+
| SPL_TEXT_BASE || mainboard/google/snow || hex ||  ||
 +
Location of SPL. Default location is within iRAM region.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPL_MAX_SIZE || mainboard/google/snow || hex ||  ||
 +
Max size of SPL. Let's say 32KB for now...
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_UART0 || mainboard/google/snow || bool || UART0 ||
 +
Serial console on UART0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_UART1 || mainboard/google/snow || bool || UART1 ||
 +
Serial console on UART1
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_UART2 || mainboard/google/snow || bool || UART2 ||
 +
Serial console on UART2
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_UART3 || mainboard/google/snow || bool || UART3 ||
 +
Serial console on UART3
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_UART_ADDRESS || mainboard/google/snow || hex ||  ||
 +
Map the UART names to the respective MMIO address.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||
 +
The following X60 series ThinkPad machines have been verified to
 +
work correctly:
 +
 
 +
ThinkPad X60s (Model 1702, 1703)
 +
ThinkPad X60  (Model 1709)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||
 +
The following T60 series ThinkPad machines have been verified to
 +
work correctly:
 +
 
 +
Thinkpad T60p (Model 2007)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
 +
Look on the bottom side for a number like 406-0001-30.  The last 2
 +
digits state the PCB revision (3.0 in this example).  For 2.0 or older
 +
boards choose Y, for 3.0 and newer say N.
 +
 
 +
Old revision boards need a jumper shorting the power button to
 +
power on automatically.  You may enable the button only after this
 +
jumper has been removed.  New revision boards are not restricted
 +
in this way, and always have the power button enabled.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
 +
If selected, both on-board serial ports will operate in RS485 mode
 +
instead of RS232.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
 +
If selected, the first two on-board serial ports will operate in RS485
 +
mode instead of RS232.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
 +
If selected, the on-board Compact Flash card socket will act as IDE
 +
Slave instead of Master.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
 +
If selected, both on-board serial ports will operate in RS485 mode
 +
instead of RS232.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
 +
If selected, both on-board serial ports will operate in RS485 mode
 +
instead of RS232.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
 +
If selected, the on-board SSD will act as IDE Slave instead of Master.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SIO_PORT || mainboard/supermicro/h8scm || hex ||  ||
 +
though UARTs are on the NUVOTON BMC, port 0x164E
 +
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SIO_PORT || mainboard/supermicro/h8qgi || hex ||  ||
 +
though UARTs are on the NUVOTON BMC, port 0x164E
 +
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SIO_PORT || mainboard/tyan/s8226 || hex ||  ||
 +
though UARTs are on the NUVOTON BMC, port 0x164E
 +
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||  
 
Select the size of the ROM chip you intend to flash coreboot on.
 
Select the size of the ROM chip you intend to flash coreboot on.
  
 
The build system will take care of creating a coreboot.rom file
 
The build system will take care of creating a coreboot.rom file
 
of the matching size.
 
of the matching size.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||
 +
Choose this option if you have a 64 KB ROM chip.
  
 
||
 
||
Line 70: Line 326:
 
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||  
 
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||  
 
Choose this option if you have a 4096 KB (4 MB) ROM chip.
 
Choose this option if you have a 4096 KB (4 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
 +
Choose this option if you have a 8192 KB (8 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
 +
Choose this option if you have a 16384 KB (16 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
 +
The selected mainboard can optionally have the power button tied
 +
to ground with a jumper so that the button appears to be
 +
constantly depressed. If this option is enabled and the jumper is
 +
installed then the board will turn on, but turn off again after a
 +
short timeout, usually 4 seconds.
 +
 +
Select Y here if you have removed the jumper and want to use an
 +
actual power button. Select N if you have the jumper installed.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SERIAL_NUMBER || mainboard || string || Serial number ||
 +
Define the used serial number which will be used by SMBIOS tables.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_VERSION || mainboard || string || Version number ||
 +
Define the used version number which will be used by SMBIOS tables.
 +
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Architecture (x86) || || || ||
 +
|- bgcolor="#eeeeee"
 +
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||
 +
If this option is enabled, no new coreboot.rom file
 +
is created. Instead it is expected that there already
 +
is a suitable file for further processing.
 +
The bootblock will not be modified.
 +
 +
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Architecture (armv7) || || || ||
 +
|- bgcolor="#eeeeee"
 +
| UPDATE_IMAGE || arch/armv7 || bool || Update existing coreboot.rom image ||
 +
If this option is enabled, no new coreboot.rom file
 +
is created. Instead it is expected that there already
 +
is a suitable file for further processing.
 +
The bootblock will not be modified.
  
 
||
 
||
Line 77: Line 386:
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || CPU ||
 
| || || (comment) || || CPU ||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_LOWLEVEL_INIT || cpu/samsung || bool || Skip low-level init ||
 +
Certain functions (ie PLL init) and processor features may already be
 +
handled by masked ROM code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_OFFSET || cpu/samsung/exynos5250 || hex || Bootblock offset ||
 +
This is where the Coreboot bootblock resides. For Exynos5250,
 +
this value is pre-determined by the vendor-provided BL1.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||
 +
Select this to apply patches to the CPU microcode provided by
 +
AMD without source, and distributed with coreboot, to address
 +
issues in the CPU post production.
 +
 +
Microcode updates distributed with coreboot are not necessarily
 +
the latest version available from AMD. Updates are only applied
 +
if they are newer than the microcode already in your CPU.
 +
 +
Unselect this to let Fam10h CPUs run with microcode as shipped
 +
from factory. No binary microcode patches will be included in the
 +
coreboot image in that case, which can help with creating an image
 +
for which complete source code is available, which in turn might
 +
simplify license compliance.
 +
 +
Microcode updates intend to solve issues that have been discovered
 +
after CPU production. The common case is that systems work as
 +
intended with updated microcode, but we have also seen cases where
 +
issues were solved by not applying the microcode updates.
 +
 +
Note that some operating system include these same microcode
 +
patches, so you may need to also disable microcode updates in
 +
your operating system in order for this option to matter.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GEODE_VSA_FILE || cpu/amd/geode_gx2 || bool || Add a VSA image ||
 +
Select this option if you have an AMD Geode GX2 vsa that you would
 +
like to add to your ROM.
 +
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VSA_FILENAME || cpu/amd/geode_gx2 || string || AMD Geode GX2 VSA path and filename ||
 +
The path and filename of the file to use as VSA.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||
 +
Select this option if you have an AMD Geode LX vsa that you would
 +
like to add to your ROM.
 +
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||
 +
The path and filename of the file to use as VSA.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/agesa || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD paltform, one socket support 2 or more kinds of
 +
processor family, compiling several cpu families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash rom,
 +
more space is required to be set as write through caching.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
 +
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
 +
 +
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_G34 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD G34 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_C32 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD C32 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_AM3R2 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD AM3r2 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family15 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
 +
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
 +
 +
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an lfence instruction in order to synchronize
 +
rdtsc. This is true for all modern AMD CPUs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an mfence instruction in order to synchronize
 +
rdtsc. This is true for all modern Intel CPUs.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SMP || cpu || bool ||  ||  
 
| SMP || cpu || bool ||  ||  
Line 84: Line 512:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool ||  ||  
+
| AP_SIPI_VECTOR || cpu || hex ||  ||  
Unset this if you don't want the MTRR code to use
+
This must equal address of ap_sipi_vector from bootblock build.
subtractive MTRRs
+
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| MMX || cpu || bool ||  ||
 +
Select MMX in your socket or model Kconfig if your CPU has MMX
 +
streaming SIMD instructions. ROMCC can build more efficient
 +
code if it can spill to MMX registers.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SSE || cpu || bool ||  ||
 +
Select SSE in your socket or model Kconfig if your CPU has SSE
 +
streaming SIMD instructions. ROMCC can build more efficient
 +
code if it can spill to SSE (aka XMM) registers.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SSE2 || cpu || bool ||  ||
 +
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
 +
streaming SIMD instructions. Some parts of coreboot can be built
 +
with more efficient code if SSE2 instructions are available.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||
 +
Select this option if you want microcode updates to be assembled when
 +
building coreboot and included in the final image as a separate CBFS
 +
file. Microcode will not be hard-coded into ramstage.
 +
 +
The microcode file and may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 +
If unsure, select this option.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_EXTERNAL || cpu || bool || Include external microcode file ||
 +
Select this option if you want to include an external file containing
 +
the CPU microcode. This will be included as a separate file in CBFS.
 +
A word of caution: only select this option if you are sure the
 +
microcode that you have is newer than the microcode shipping with
 +
coreboot.
 +
 +
The microcode file and may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 +
If unsure, select "Generate from tree"
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_FILE || cpu || string || Path and filename of CPU microcode ||
 +
The path and filename of the file containing the CPU microcode.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||
 +
Select this option if you do not want CPU microcode included in CBFS.
 +
Note that for some CPUs, the microcode is hard-coded into the source
 +
tree and is not loaded from CBFS. In this case, microcode will still
 +
be updated. There is a push to move all microcode to CBFS, but this
 +
change is not implemented for all CPUs.
 +
 +
This option currently applies to:
 +
- Intel SandyBridge/IvyBridge
 +
- VIA Nano
 +
 +
Microcode may be added to the ROM image at a later time with cbfstool,
 +
if desired.
 +
 +
If unsure, select "Generate from tree"
 +
 +
The GOOD:
 +
Microcode updates intend to solve issues that have been discovered
 +
after CPU production. The expected effect is that systems work as
 +
intended with the updated microcode, but we have also seen cases where
 +
issues were solved by not applying microcode updates.
 +
 +
The BAD:
 +
Note that some operating system include these same microcode patches,
 +
so you may need to also disable microcode updates in your operating
 +
system for this option to have an effect.
 +
 +
The UGLY:
 +
A word of CAUTION: some CPUs depend on microcode updates to function
 +
correctly. Not updating the microcode may leave the CPU operating at
 +
less than optimal performance, or may cause outright hangups.
 +
There are CPUs where coreboot cannot properly initialize the CPU
 +
without microcode updates
 +
For example, if running with the factory microcode, some Intel
 +
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
 +
will hang when changing the frequency.
 +
 +
Make sure you have a way of flashing the ROM externally before
 +
selecting this option.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Northbridge ||
 
| || || (comment) || || Northbridge ||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool ||  ||
 +
Select this for boards with a Voltage Regulator able to operate
 +
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Northbridge CIMX
 +
Trace debug information to the serial console.
 +
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 +
 +
||
 +
 +
||
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: HyperTransport setup || || || ||
 +
|- bgcolor="#eeeeee"
 +
| None || northbridge/amd || None || HyperTransport frequency ||
 +
This option sets the maximum permissible HyperTransport link
 +
frequency.
 +
 +
Use of this option will only limit the autodetected HT frequency.
 +
It will not (and cannot) increase the frequency beyond the
 +
autodetected limits.
 +
 +
This is primarily used to work around poorly designed or laid out
 +
HT traces on certain motherboards.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||
 +
This option sets the maximum permissible HyperTransport
 +
downlink width.
 +
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||
 +
This option sets the maximum permissible HyperTransport
 +
uplink width.
 +
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
 +
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||
 +
This option affects how the SDRAMC register is programmed.
 +
Memory clock signals will not be routed properly if this option
 +
is set wrong.
 +
 +
If your board has 4 DIMM slots, you must use select this option, in
 +
your Kconfig file of the board. On boards with 3 DIMM slots,
 +
do _not_ select this option.
 +
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool ||  ||
 +
Usually system firmware turns off system memory clock
 +
signals to unused SO-DIMM slots to reduce EMI and power
 +
consumption.
 +
However, some boards do not like unused clock signals to
 +
be disabled.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int ||  ||
 +
If non-zero, this designates the maximum DDR frequency
 +
the board supports, despite what the chipset should be
 +
capable of.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||
 +
On some boards it may be neccessary to hard reset early
 +
during resume from S3 if the SLFRCS register indicates that
 +
a memory channel is not guaranteed to be in self-refresh.
 +
On other boards the check always creates a false positive,
 +
effectively making it impossible to resume.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || northbridge/intel/sandybridge || bool || Add a System Agent binary ||
 +
Select this option to add a System Agent binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || northbridge/intel/sandybridge || hex || Size of CBFS filesystem in ROM ||
 +
On Sandybridge and Ivybridge systems the firmware image has to
 +
store a lot more than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
- MRC cache information
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Southbridge ||
 
| || || (comment) || || Southbridge ||
Line 97: Line 739:
 
! align="left" | Menu: AMD Geode GX1 video support || || || ||
 
! align="left" | Menu: AMD Geode GX1 video support || || || ||
  
 +
|- bgcolor="#eeeeee"
 +
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool ||  ||
 +
Select if RS690 should be setup to support MMCONF.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. IDE or AHCI.
 +
The default is IDE.
 +
 +
config SATA_MODE_IDE
 +
bool "IDE"
 +
 +
config SATA_MODE_AHCI
 +
bool "AHCI"
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb700 || hex ||  ||
 +
0x0 = Native IDE mode.
 +
0x1 = RAID mode.
 +
0x2 = AHCI mode.
 +
0x3 = Legacy IDE mode.
 +
0x4 = IDE->AHCI mode.
 +
0x5 = AHCI mode as 7804 ID (AMD driver).
 +
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIB_ENABLE || southbridge/amd/cimx/sb700 || bool ||  ||
 +
n = Disable PCI Bridge Device 14 Function 4.
 +
y = Enable PCI Bridge Device 14 Function 4.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb700 || hex ||  ||
 +
Set SCI IRQ to 9.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_SBCIMX_TRACE_TO_SERIAL || southbridge/amd/cimx/sb700 || bool || Redirect AMD Southbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Southbridge CIMX Trace
 +
debug information to the serial console.
 +
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VOLATILE_POS || southbridge/amd/cimx/sb700 || hex || S3 volatile storage position ||
 +
For a system with S3 feature, the BIOS needs to save some data to
 +
non-volitile storage at cold boot stage.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
 +
If Combined Mode is enabled. IDE controller is exposed and
 +
SATA controller has control over Port0 through Port3,
 +
IDE controller has control over Port4 and Port5.
 +
 +
If Combined Mode is disabled, IDE controller is hidden and
 +
SATA controller has full control of all 6 Ports when operating in non-IDE mode.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
 +
NATIVE is the default mode and does not require a ROM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
 +
AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
 +
sb800 RAID mode must have the two required ROM files.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
 +
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must larger than 0x100000.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VOLATILE_POS || southbridge/amd/cimx/sb800 || hex || S3 volatile storage position ||
 +
For a system with S3 feature, the BIOS needs to save some data to
 +
non-volitile storage at cold boot stage.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
 +
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_POSITION || southbridge/amd/cimx/sb800 || hex || Fan Control ||
 +
Select the method of SB800 fan control to be used.  None would be
 +
for either fixed maximum speed fans connected to the SB800 or for
 +
an external chip controlling the fan speeds.  Manual control sets
 +
up the SB800 fan control registers.  IMC fan control uses the SB800
 +
IMC to actively control the fan speeds.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
 +
No SB800 Fan control - Do not set up the SB800 fan control registers.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
 +
Configure the SB800 fan control registers in devicetree.cb.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
 +
Set up the SB800 to use the IMC based Fan controller.  This requires
 +
the IMC rom from AMD.  Configure the registers in devicetree.cb.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex ||  ||
 +
0x0 = Native IDE mode.
 +
0x1 = RAID mode.
 +
0x2 = AHCI mode.
 +
0x3 = Legacy IDE mode.
 +
0x4 = IDE->AHCI mode.
 +
0x5 = AHCI mode as 7804 ID (AMD driver).
 +
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool ||  ||
 +
n = Disable PCI Bridge Device 14 Function 4.
 +
y = Enable PCI Bridge Device 14 Function 4.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex ||  ||
 +
Set SCI IRQ to 9.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VOLATILE_POS || southbridge/amd/cimx/sb900 || hex || S3 volatile storage position ||
 +
For a system with S3 feature, the BIOS needs to save some data to
 +
non-volitile storage at cold boot stage.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool || Add gec firmware ||
 +
Add Hudson 2/3/4 GEC Firmware
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || Hudson Firmware rom Position ||
 +
Hudson requires the firmware MUST be located at
 +
a specific address (ROM start address + 0x20000), otherwise
 +
xhci host Controller can not find or load the xhci firmware.
 +
 +
The firmware start address is dependent on the ROM chip size.
 +
The default offset is 0x20000 from the ROM start address, namely
 +
0xFFF20000 if flash chip size is 1M
 +
0xFFE20000 if flash chip size is 2M
 +
0xFFC20000 if flash chip size is 4M
 +
0xFF820000 if flash chip size is 8M
 +
0xFF020000 if flash chip size is 16M
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_IDE || southbridge/amd/agesa/hudson || bool || NATIVE ||
 +
NATIVE is the default mode and does not require a ROM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_RAID || southbridge/amd/agesa/hudson || bool || RAID ||
 +
HUDSON RAID mode must have the two required ROM files.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_AHCI || southbridge/amd/agesa/hudson || bool || AHCI ||
 +
AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_LEGACY_IDE || southbridge/amd/agesa/hudson || bool || LEGACY IDE ||
 +
TODO
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_IDE2AHCI || southbridge/amd/agesa/hudson || bool || IDE to AHCI ||
 +
TODO
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_AHCI7804 || southbridge/amd/agesa/hudson || bool || AHCI7804 ||
 +
AHCI ROM Required, and AMD driver required in the OS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_IDE2AHCI7804 || southbridge/amd/agesa/hudson || bool || IDE to AHCI7804 ||
 +
AHCI ROM Required, and AMD driver required in the OS.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must larger than 0x100000.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VOLATILE_POS || southbridge/amd/agesa/hudson || hex || S3 volatile storage position ||
 +
For a system with S3 feature, the BIOS needs to save some data to
 +
non-volitile storage at cold boot stage.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
 +
Select this option to add a CMC state machine binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
 +
The path and filename of the file to use as CMC state machine
 +
binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/bd82x6x || bool || Lock Management Engine section ||
 +
The Intel Management Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 +
If unsure, say N.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Super I/O ||
 
| || || (comment) || || Super I/O ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
+
| || || (comment) || || Embedded Controllers ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||  
+
| EC_ACPI || ec/acpi || bool || ||  
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
+
ACPI Embedded Controller interface. Mostly found in laptops.
this unless you're sure you don't want the briges setup for VGA.
+
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||  
+
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool || ||  
Execute VGA option ROMs, if found. This is required to enable
+
Interface to COMPAL ENE932 Embedded Controller.
PCI/AGP/PCI-E video cards.
+
  
 +
||
 +
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||  
+
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool || ||  
Execute non-VGA PCI option ROMs, if found.
+
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
  
Examples include IDE/SATA controller option ROMs and option ROMs
+
||
 +
 
 +
||
 +
 
 +
||
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Devices || || || ||
 +
|- bgcolor="#eeeeee"
 +
| VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||
 +
Execute VGA Option ROMs in coreboot if found. This is required
 +
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
 +
payload.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||
 +
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCI_ROM_RUN || device || bool || Run non-VGA Option ROMs ||
 +
Execute non-VGA PCI Option ROMs in coreboot if found.
 +
 
 +
Examples include IDE/SATA controller Option ROMs and Option ROMs
 
for network cards (NICs).
 
for network cards (NICs).
 +
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ON_DEVICE_ROM_RUN || device || bool || Run Option ROMs on PCI devices ||
 +
Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
 +
 +
If disabled, only Option ROMs stored in CBFS will be executed by
 +
coreboot. If you are concerned about security, you might want to
 +
disable this option, but it might leave your system in a state of
 +
degraded functionality.
 +
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Real mode ||  
+
| PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||  
If you select this option, PCI option ROMs will be executed
+
If you select this option, PCI Option ROMs will be executed
 
natively on the CPU in real mode. No CPU emulation is involved,
 
natively on the CPU in real mode. No CPU emulation is involved,
 
so this is the fastest, but also the least secure option.
 
so this is the fastest, but also the least secure option.
Line 130: Line 1,147:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_X86EMU || devices || bool || x86emu ||  
+
| PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||  
 
If you select this option, the x86emu CPU emulator will be used to
 
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.
+
execute PCI Option ROMs.
 +
 
 +
This option prevents Option ROMs from doing dirty tricks with the
 +
system (such as installing SMM modules or hypervisors), but it is
 +
also significantly slower than the native Option ROM initialization
 +
method.
 +
 
 +
This is the default choice for non-x86 systems.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||
 +
Per default, YABEL only allows Option ROMs to access the PCI device
 +
that they are associated with. However, this causes trouble for some
 +
onboard graphics chips whose Option ROM needs to reconfigure the
 +
north bridge.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||
 +
By default, YABEL aborts when the Option ROM tries to write to other
 +
devices' config spaces. With this option enabled, the write doesn't
 +
follow through, but the Option ROM is allowed to go on.
 +
This can create issues such as hanging Option ROMs (if it depends on
 +
that other register changing to the written value), so test for
 +
impact before using this option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||
 +
YABEL requires 1MB memory for its CPU emulation. This memory is
 +
normally located at 16MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_DIRECTHW || device || bool || Direct hardware access ||
 +
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 +
additionally provides a PC system emulation that filters bad device
 +
and memory access (such as PCI config space access to other devices
 +
than the initialized one).
 +
 
 
When choosing this option, x86emu will pass through all hardware
 
When choosing this option, x86emu will pass through all hardware
accesses to memory and IO devices to the underlying memory and IO
+
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
+
addresses. While this option prevents Option ROMs from doing dirty
 
tricks with the CPU (such as installing SMM modules or hypervisors),
 
tricks with the CPU (such as installing SMM modules or hypervisors),
 
they can still access all devices in the system.
 
they can still access all devices in the system.
Choosing x86emu, option ROM execution is slower than native execution
+
Enable this option for a good compromise between security and speed.
in real mode, but faster than the full system emulation YABEL
+
This is the default choice for non-x86 systems.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || YABEL ||  
+
| PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||  
If you select this option, the YABEL system emulator will be used to
+
Detect and enable Common Clock on PCIe links.
execute PCI option ROMs.
+
YABEL consists of two parts: It uses x86emu for the CPU emulation and
+
additionally provides a PC system emulation that filters bad device and
+
memory access (such as PCI config space access to other devices than the
+
initialized one).
+
This option best prevents option ROMs from doing dirty tricks with the
+
system (such as installing SMM modules or hypervisors), but it is also
+
significantly slower than the other option ROM initialization methods.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_DEBUG_FLAGS || devices || hex || Hex value for YABEL debug flags ||  
+
| PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||  
See debug.h for values 0 is no debug output, 0x31ff is _verbose_.
+
Detect and enable ASPM on PCIe links.
  
 
||
 
||
  
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: Console options || || || ||
+
! align="left" | Menu: VGA BIOS || || || ||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS || device || bool || Add a VGA BIOS image ||
 +
Select this option if you have a VGA BIOS image that you would
 +
like to add to your ROM.
 +
 
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || device || string || VGA device PCI IDs ||
 +
The comma-separated PCI vendor and device ID that would associate
 +
your VGA BIOS to your video card.
 +
 
 +
Example: 1106,3230
 +
 
 +
In the above example 1106 is the PCI vendor ID (in hex, but without
 +
the "0x" prefix) and 3230 specifies the PCI device ID of the
 +
video card (also in hex, without "0x" prefix).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_MBI || device || bool || Add an MBI image ||
 +
Select this option if you have an Intel MBI image that you would
 +
like to add to your ROM.
 +
 
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MBI_FILE || device || string || Intel MBI path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Display || || || ||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_SET_VESA_MODE || device || bool || Set VESA framebuffer mode ||
 +
Set VESA framebuffer mode (needed for bootsplash)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_SET_VESA_MODE || device || bool || VESA framebuffer video mode ||
 +
This option sets the resolution used for the coreboot framebuffer (and
 +
bootsplash screen).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_KEEP_VESA_MODE || device || bool || Keep VESA framebuffer ||
 +
This option keeps the framebuffer mode set after coreboot finishes
 +
execution. If this option is enabled, coreboot will pass a
 +
framebuffer entry in its coreboot table and the payload will need a
 +
framebuffer driver. If this option is disabled, coreboot will switch
 +
back to text mode before handing control to a payload.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTSPLASH || device || bool || Show graphical bootsplash ||
 +
This option shows a graphical bootsplash screen. The grapics are
 +
loaded from the CBFS file bootsplash.jpg.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTSPLASH_FILE || device || string || Bootsplash path and filename ||
 +
The path and filename of the file to use as graphical bootsplash
 +
screen. The file format has to be jpg.
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Generic Drivers || || || ||
 +
|- bgcolor="#eeeeee"
 +
| ELOG || drivers/elog || bool || Support for flash based event log ||
 +
Enable support for flash based event logging.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_FLASH_BASE || drivers/elog || hex || Event log offset into flash ||
 +
Offset into the flash chip for the ELOG block.
 +
This should be allocated in the FMAP.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_AREA_SIZE || drivers/elog || hex || Size of Event Log area in flash ||
 +
This should be a multiple of flash block size.
 +
 
 +
Default is 4K.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_FULL_THRESHOLD || drivers/elog || hex || Threshold at which flash is considered full ||
 +
When the Event Log size is larger than this it will be shrunk
 +
to ELOG_SHRINK_SIZE.  Must be greater than ELOG_AREA_SIZE, and
 +
ELOG_AREA_SIZE - ELOG_FULL_THRESHOLD must be greater than the
 +
maximum event size of 128.
 +
 
 +
Default is 75% of the log, or 3K.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_SHRINK_SIZE || drivers/elog || hex || Resulting size when the event log is shrunk ||
 +
When the Event Log is shrunk it will go to this size.
 +
ELOG_AREA_SIZE - ELOG_SHRINK_SIZE must be less than
 +
CONFIG_ELOG_FULL_THRESHOLD.
 +
 
 +
Default is 1K.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||
 +
This option will have ELOG store a copy of the flash event log
 +
in a CBMEM region and export that address in SMBIOS to the OS.
 +
This is useful if the ELOG location is not in memory mapped flash,
 +
but it means that events added at runtime via the SMI handler
 +
will not be reflected in the CBMEM copy of the log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||
 +
This interface is compatible with the linux kernel driver
 +
available with CONFIG_GOOGLE_GSMI and can be used to write
 +
kernel reset/shutdown messages to the event log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||
 +
Store a monotonic boot number in CMOS and provide an interface
 +
to read the current value and increment the counter.  This boot
 +
counter will be logged as part of the System Boot event.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||
 +
This value must be greater than 16 bytes so as not to interfere
 +
with the standard RTC region.  Requires 8 bytes.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_MAXIM_MAX77686 || drivers/maxim/max77686 || bool ||  ||
 +
Maxim MAX77686 power regulator
 +
 
 +
||
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||
 +
Support for Oxford OXPCIe952 serial port PCIe cards.
 +
Currently only devices with the vendor ID 0x1415 and device ID
 +
0xc158 will work.
 +
NOTE: Right now you have to set the base address of your OXPCIe952
 +
card to exactly the value that the device allocator would set them
 +
later on, or serial console functionality will stop as soon as the
 +
resource allocator assigns a new base address to the device.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system. In order to use an
 +
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 +
that controls the OXPCIe952 controller first.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system. In order to use an
 +
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 +
that controls the OXPCIe952 controller first.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system. In order to use an
 +
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 +
that controls the OXPCIe952 controller first.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system. In order to use an
 +
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 +
that controls the OXPCIe952 controller first.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system. In order to use an
 +
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
 +
for the OXPCIe952 controller.
 +
 
 +
 
 +
||
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_PS2_KEYBOARD || drivers/pc80 || bool || PS/2 keyboard init ||
 +
Enable this option to initialize PS/2 keyboards found connected
 +
to the PS/2 port.
 +
 
 +
Some payloads (eg, filo) require this option.  Other payloads
 +
(eg, SeaBIOS, Linux) do not require it.
 +
Initializing a PS/2 keyboard can take several hundred milliseconds.
 +
 
 +
If you know you will only use a payload which does not require
 +
this option, then you can say N here to speed up boot time.
 +
Otherwise say Y.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM || drivers/pc80 || bool ||  ||
 +
Enable this option to enable TPM support in coreboot.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RTL8168_ROM_DISABLE || drivers/realtek || bool || Disable RTL8168 ROM ||
 +
Just enough of a driver to make coreboot not look for an Option ROM.
 +
No configuration is necessary for the OS to pick up the device.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||
 +
It sets PCI class to IDE compatible native mode, allowing
 +
SeaBIOS, FILO etc... to boot from it.
 +
 
 +
 
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SMM || drivers/spi || bool || SPI flash driver support in SMM ||
 +
Select this option if you want SPI flash support in SMM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_EON || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by EON.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_MACRONIX || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Macronix.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SPANSION || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Spansion.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SST || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by SST.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_STMICRO || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by ST MICRO.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_WINBOND || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Winbond.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_NO_FAST_READ || drivers/spi || bool || Disable Fast Read command ||
 +
Select this option if your setup requires to avoid "fast read"s
 +
from the SPI flash parts.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_GIGADEVICE || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Gigadevice.
 +
 
 +
||
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Console || || || ||
 +
|- bgcolor="#eeeeee"
 +
| SERIAL_CONSOLE || console || bool || Serial port console output ||
 +
Send coreboot debug output to a serial port
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EARLY_SERIAL_CONSOLE || console || bool ||  ||
 +
Use serial console during early (pre-RAM) boot stages
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL8250 || console || bool || Serial port console output (I/O mapped, 8250-compatible) ||
 +
Send coreboot debug output to an I/O mapped serial port console.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped, 8250-compatible) ||
 +
Send coreboot debug output to a memory mapped serial port console.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||  
+
| CONSOLE_SERIAL_NONSTANDARD_MEM || console || bool || Serial port console output (memory-mapped, device-specific) ||  
Send coreboot debug output to a serial port console.
+
Send coreboot debug output to a memory mapped serial port console
 +
on a device-specific UART.
  
 
||
 
||
Line 218: Line 1,599:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIAL_POST || console || bool || Show POST codes on the serial port console ||
+
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||  
If enabled, coreboot will additionally print POST codes (which are
+
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
+
device) on the serial console.
+
 
+
||
+
|- bgcolor="#eeeeee"
+
| USBDEBUG_DIRECT || console || bool || USB 2.0 EHCI debug dongle support ||  
+
 
This option allows you to use a so-called USB EHCI Debug device
 
This option allows you to use a so-called USB EHCI Debug device
 +
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
 +
Linux "EHCI Debug Device gadget" driver found in recent kernel)
 
to retrieve the coreboot debug messages (instead, or in addition
 
to retrieve the coreboot debug messages (instead, or in addition
 
to, a serial port).
 
to, a serial port).
Line 233: Line 1,609:
  
 
It also requires a USB2 controller which supports the EHCI
 
It also requires a USB2 controller which supports the EHCI
Debug Port capability. Controllers which are known to work:
+
Debug Port capability.
  
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
+
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
* 8086:24cd Intel ICH4/ICH4-M
+
of supported controllers.
* 8086:24dd Intel ICH5
+
* 8086:265c Intel ICH6
+
* 8086:268c Intel 631xESB/632xESB/3100
+
* 8086:27cc Intel ICH7
+
* 8086:2836 Intel ICH8
+
* 8086:283a Intel ICH8
+
* 8086:293a Intel ICH9
+
* 10de:0088 NVIDIA MCP2A
+
* 10de:005b NVIDIA CK804
+
* 10de:026e NVIDIA MCP51
+
* 10de:036d NVIDIA MCP55
+
* 10de:03f2 NVIDIA MCP61
+
* 1002:4386 ATI/AMD SB600
+
* 1106:3104 VIA VX800
+
  
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
+
If unsure, say N.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_VGA_ONBOARD_AT_FIRST || console || bool || Use onboard VGA as primary video device ||  
+
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||
 +
This option selects which physical USB port coreboot will try to
 +
use as EHCI Debug Port first (valid values are: 1-15).
 +
 
 +
If coreboot doesn't detect an EHCI Debug Port dongle on this port,
 +
it will try all the other ports one after the other. This will take
 +
a few seconds of time though, and thus slow down the booting process.
 +
 
 +
Hence, if you select the correct port here, you can speed up
 +
your boot time. Which USB port number (1-15) refers to which
 +
actual port on your mainboard (potentially also USB pin headers
 +
on your mainboard) is highly board-specific, and you'll likely
 +
have to find out by trial-and-error.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||  
 
If not selected, the last adapter found will be used.
 
If not selected, the last adapter found will be used.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
 +
Send coreboot debug output to a Ethernet console, it works
 +
same way as Linux netconsole, packets are received to UDP
 +
port 6666 on IP/MAC specified with options bellow.
 +
Use following netcat command: nc -u -l -p 6666
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
 +
Type in either MAC address of logging system or MAC address
 +
of the router.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
 +
This is IP adress of the system running for example
 +
netcat command to dump the packets.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
 +
This is the IP of the coreboot system
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
 +
This is the IO port address for the IO port
 +
on the card, please select some non-conflicting region,
 +
32 bytes of IO spaces will be used (and align on 32 bytes
 +
boundary, qemu needs broader align)
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_CBMEM || console || bool || Send console output to a CBMEM buffer ||
 +
Enable this to save the console output in a CBMEM buffer. This would
 +
allow to see coreboot console output from Linux space.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_CBMEM_BUFFER_SIZE || console || hex || Room allocated for console output in CBMEM ||
 +
Space allocated for console output storage in CBMEM. The default
 +
value (64K or 0x10000 bytes) is large enough to accommodate
 +
even the BIOS_SPEW level.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_CAR_BUFFER_SIZE || console || hex || Room allocated for console output in Cache as RAM ||
 +
Console is used before RAM is initialized. This is the room reserved
 +
in the DCACHE based RAM to keep console output before it can be
 +
saved in a CBMEM buffer. 3K bytes should be enough even for the
 +
BIOS_SPEW level.
 +
  
 
||
 
||
Line 344: Line 1,777:
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||
 +
If enabled, coreboot will additionally print POST codes (which are
 +
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
 +
device) on the debug console.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST || console || bool || Store post codes in CMOS for debugging ||
 +
If enabled, coreboot will store post codes in CMOS and switch between
 +
two offsets on each boot so the last post code in the previous boot
 +
can be retrieved.  This uses 3 bytes of CMOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST_OFFSET || console || hex || Offset into CMOS to store POST codes ||
 +
If CMOS_POST is enabled then an offset into CMOS must be provided.
 +
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
 +
defined in the mainboard option table.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IO_POST || console || bool || Send POST codes to an IO port ||
 +
If enabled, POST codes will be written to an IO port.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IO_POST_PORT || console || hex || IO port for POST codes ||
 +
POST codes on x86 are typically written to the LPC bus on port
 +
0x80. However, it may be desireable to change the port number
 +
depending on the presence of coprocessors/microcontrollers or if the
 +
platform does not support IO in the conventional x86 manner.
 +
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| HAVE_HARD_RESET || toplevel || bool ||  ||
 +
This variable specifies whether a given board has a hard_reset
 +
function, no matter if it's provided by board code or chipset code.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| HAVE_OPTION_TABLE || toplevel || bool ||  ||  
 
| HAVE_OPTION_TABLE || toplevel || bool ||  ||  
 
This variable specifies whether a given board has a cmos.layout
 
This variable specifies whether a given board has a cmos.layout
 
file containing NVRAM/CMOS bit definitions.
 
file containing NVRAM/CMOS bit definitions.
It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
+
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
  
 
||
 
||
Line 360: Line 1,833:
 
| GFXUMA || toplevel || bool ||  ||  
 
| GFXUMA || toplevel || bool ||  ||  
 
Enable Unified Memory Architecture for graphics.
 
Enable Unified Memory Architecture for graphics.
 
||
 
|- bgcolor="#eeeeee"
 
| HAVE_LOW_TABLES || toplevel || bool ||  ||
 
This Option is unused in the code.  Since two boards try to set it to
 
'n', they may be broken.  We either need to make the option useful or
 
get rid of it.  The broken boards are:
 
asus/m2v-mx_se
 
supermicro/h8dme
 
 
||
 
|- bgcolor="#eeeeee"
 
| HAVE_HIGH_TABLES || toplevel || bool ||  ||
 
This variable specifies whether a given northbridge has high table
 
support.
 
It is set in northbridge/*/Kconfig.
 
Whether or not the high tables are actually written by coreboot is
 
configurable by the user via WRITE_HIGH_TABLES.
 
  
 
||
 
||
Line 402: Line 1,857:
 
Whether or not the PIRQ table is actually generated by coreboot
 
Whether or not the PIRQ table is actually generated by coreboot
 
is configurable by the user via GENERATE_PIRQ_TABLE.
 
is configurable by the user via GENERATE_PIRQ_TABLE.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAX_PIRQ_LINKS || toplevel || int ||  ||
 +
This variable specifies the number of PIRQ interrupt links which are
 +
routable. On most chipsets, this is 4, INTA through INTD. Some
 +
chipsets offer more than four links, commonly up to INTH. They may
 +
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
 +
table specifies links greater than 4, pirq_route_irqs will not
 +
function properly, unless this variable is correctly set.
  
 
||
 
||
Line 424: Line 1,889:
 
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||  
 
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||  
 
Generate a PIRQ table for this board.
 
Generate a PIRQ table for this board.
 +
 +
If unsure, say Y.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||
 +
Generate SMBIOS tables for this board.
  
 
If unsure, say Y.
 
If unsure, say Y.
Line 452: Line 1,924:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FALLBACK_PAYLOAD_FILE || toplevel || string || Payload path and filename ||  
+
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||
 +
Select this option if you want to build a coreboot image
 +
with a SeaBIOS payload. If you don't know what this is
 +
about, just leave it enabled.
 +
 
 +
See http://coreboot.org/Payloads for more information.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_FILO || toplevel || bool || FILO ||
 +
Select this option if you want to build a coreboot image
 +
with a FILO payload. If you don't know what this is
 +
about, just leave it enabled.
 +
 
 +
See http://coreboot.org/Payloads for more information.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SEABIOS_STABLE || toplevel || bool || 1.7.1 ||
 +
Stable SeaBIOS version
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SEABIOS_MASTER || toplevel || bool || master ||
 +
Newest SeaBIOS version
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FILO_STABLE || toplevel || bool || 0.6.0 ||
 +
Stable FILO version
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FILO_MASTER || toplevel || bool || HEAD ||
 +
Newest FILO version
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||  
 
The path and filename of the ELF executable file to use as payload.
 
The path and filename of the ELF executable file to use as payload.
  
Line 464: Line 1,970:
  
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
+
! align="left" | Menu: Debugging || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||  
+
| GDB_STUB || toplevel || bool || GDB debugging support ||  
Select this option if you have a VGA BIOS image that you would
+
If enabled, you will be able to set breakpoints for gdb debugging.
like to add to your ROM.
+
See src/arch/x86/lib/c_start.S for details.
  
You will be able to specify the location and file name of the
+
||
image later.
+
|- bgcolor="#eeeeee"
 +
| GDB_WAIT || toplevel || bool || Wait for a GDB connection ||
 +
If enabled, coreboot will wait for a GDB connection.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FALLBACK_VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||  
+
| DEBUG_CBFS || toplevel || bool || Output verbose CBFS debug messages ||  
The path and filename of the file to use as VGA BIOS.
+
This option enables additional CBFS related debug messages.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FALLBACK_VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||  
+
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||  
The comma-separated PCI vendor and device ID that would associate
+
This option enables additional RAM init related debug messages.
your VGA BIOS to your video card.
+
It is recommended to enable this when debugging issues on your
 +
board which might be RAM init related.
  
Example: 1106,3230
+
Note: This option will increase the size of the coreboot image.
  
In the above example 1106 is the PCI vendor ID (in hex, but without
+
If unsure, say N.
the "0x" prefix) and 3230 specifies the PCI device ID of the
+
video card (also in hex, without "0x" prefix).
+
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
 +
This option enables additional CAR related debug messages.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
 +
If unsure, say N.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
 +
This option enables additional SMBus (and SPD) debug messages.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
 +
This option enables additional SMI related debug messages.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
 +
This option enables additional SMM handler relocation related
 +
debug messages.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
 +
This option enables additional malloc related debug messages.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||
 +
This option enables additional ACPI related debug messages.
 +
 +
Note: This option will slightly increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
 +
This option enables additional x86emu related debug messages.
 +
 +
Note: This option will increase the time to emulate a ROM.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
 +
This option enables additional x86emu related debug messages.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
 +
Print information about JMP and RETF opcodes from x86emu.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
 +
Print _all_ opcodes that are executed by x86emu.
 +
 +
WARNING: This will produce a LOT of output and take a long time.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
 +
Print Plug And Play accesses made by option ROMs.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
 +
Print Disk I/O related messages.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
 +
Print messages related to POST Memory Manager (PMM).
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
 +
Print messages related to VESA BIOS Extension (VBE) functions.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
 +
Let INT10 (i.e. character output) calls print messages to debug output.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
 +
Print messages related to interrupt handling.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
 +
Print messages related to accesses to certain areas of the virtual
 +
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
 +
Print memory accesses made by option ROM.
 +
Note: This also includes accesses to fetch instructions.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
 +
Print I/O accesses made by option ROM.
 +
 +
Note: This option will increase the size of the coreboot image.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_TPM || toplevel || bool || Output verbose TPM debug messages ||
 +
This option enables additional TPM related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SPI_FLASH || toplevel || bool || Output verbose SPI flash debug messages ||
 +
This option enables additional SPI flash related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_INTEL_ME || toplevel || bool || Verbose logging for Intel Management Engine ||
 +
Enable verbose logging for Intel Management Engine driver that
 +
is present on Intel 6-series chipsets.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LLSHELL || toplevel || bool || Built-in low-level shell ||
 +
If enabled, you will have a low level shell to examine your machine.
 +
Put llshell() in your (romstage) code to start the shell.
 +
See src/arch/x86/llshell/llshell.inc for details.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TRACE || toplevel || bool || Trace function calls ||
 +
If enabled, every function will print information to console once
 +
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
 +
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
 +
of calling function. Please note some printk releated functions
 +
are omitted from trace to have good looking console dumps.
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || bool ||  ||
 +
Select when the board has a power button which can optionally be
 +
disabled by the user.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || bool ||  ||
 +
Select when the board has a power button which can optionally be
 +
enabled by the user, e.g. when the board ships with a jumper over
 +
the power switch contacts.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_BUTTON_FORCE_ENABLE || toplevel || bool ||  ||
 +
Select when the board requires that the power button is always
 +
enabled.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_BUTTON_FORCE_DISABLE || toplevel || bool ||  ||
 +
Select when the board requires that the power button is always
 +
disabled, e.g. when it has been hardwired to ground.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool ||  ||
 +
Internal option that controls ENABLE_POWER_BUTTON visibility.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS || vendorcode/google/chromeos || bool ||  ||
 +
Enable ChromeOS specific features like the GPIO sub table in
 +
the coreboot table. NOTE: Enabling this option on an unsupported
 +
board will most likely break your build.
 +
 +
||
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
+
! align="left" | Menu: ChromeOS || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||  
+
| VBNV_OFFSET || vendorcode/google/chromeos || hex || ||  
If enabled, you will be able to set breakpoints for gdb debugging.
+
CMOS offset for VbNv data. This value must match cmos.layout
See src/arch/i386/lib/c_start.S for details.
+
in the mainboard directory, minus 14 bytes for the RTC.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| VBNV_SIZE || vendorcode/google/chromeos || hex ||  ||
 +
CMOS storage size for VbNv data. This value must match cmos.layout
 +
in the mainboard directory.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FLASHMAP_OFFSET || vendorcode/google/chromeos || hex || Flash Map Offset ||
 +
Offset of flash map in firmware image
 +
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| NO_TPM_RESUME || vendorcode/google/chromeos || bool ||  ||
 +
On some boards the TPM stays powered up in S3. On those
 +
boards, booting Windows will break if the TPM resume command
 +
is sent during an S3 resume.
 +
 +
||
 +
 +
 +
||
 +
 +
||
 +
 +
||
 
|}
 
|}

Latest revision as of 13:44, 12 January 2013

This is an automatically generated list of coreboot compile-time options (using coreboot/util/optionlist utility).

Last update: 2013/01/12 17:40:48. (runknown)

Option Source Format Short Description Description
Menu: General setup
EXPERT toplevel bool Expert mode

This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are doing! You have been warned!

LOCALVERSION toplevel string Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.

CBFS_PREFIX toplevel string CBFS prefix to use

Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative.

CBFS_PREFIX toplevel string Compiler to use

This option allows you to select the compiler used for building coreboot.

COMPILER_GCC toplevel bool GCC

Use the GNU Compiler Collection (GCC) to build coreboot.

For details see http://gcc.gnu.org.

COMPILER_LLVM_CLANG toplevel bool LLVM/clang

Use LLVM/clang to build coreboot.

For details see http://clang.llvm.org.

SCANBUILD_ENABLE toplevel bool Build with scan-build for static code analysis

Changes the build process to use scan-build (a utility for running the clang static code analyzer from the command line).

Requires the scan-build utility in your system $PATH.

For details see http://clang-analyzer.llvm.org/scan-build.html.

SCANBUILD_REPORT_LOCATION toplevel string Directory for the scan-build report(s)

Directory where the scan-build reports should be stored in. The reports are stored in subdirectories of the form 'yyyy-mm-dd-*' in the specified directory.

If this setting is left empty, the coreboot top-level directory will be used to store the report subdirectories.

CCACHE toplevel bool Use ccache to speed up (re)compilation

Enables the use of ccache for faster builds.

Requires the ccache utility in your system $PATH.

For details see https://ccache.samba.org.

SCONFIG_GENPARSER toplevel bool Generate SCONFIG parser using flex and bison

Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and sconfig.y.

Otherwise, say N.

USE_OPTION_TABLE toplevel bool Use CMOS for configuration values

Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values.

COMPRESS_RAMSTAGE toplevel bool Compress ramstage with LZMA

Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI).

INCLUDE_CONFIG_FILE toplevel bool Include the coreboot .config file into the ROM image

Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which options were used to build a specific coreboot.rom image.

Saying Y here will increase the image size by 2-3kB.

You can use the following command to easily list the options:

grep -a CONFIG_ coreboot.rom

Alternatively, you can also use cbfstool to print the image contents (including the raw 'config' item we're looking for).

Example:

$ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes

Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 fallback/coreboot_ram 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440

EARLY_CBMEM_INIT toplevel bool Initialize CBMEM while in ROM stage

Make coreboot initialize the cbmem structures while running in ROM stage. This could be useful when the ROM stage wants to communicate some, for instance, execution timestamps.

COLLECT_TIMESTAMPS toplevel bool Create a table of timestamps collected during boot

Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.

USE_BLOBS toplevel bool Allow use of binary-only repository

This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users.

REQUIRES_BLOB toplevel bool

This option can be configured by boards that require the blobs repository for the default configuration. It will make the build fail if USE_BLOBS is disabled. Users that still desire to do a coreboot build for such a board can override this manually, but this option serves as warning that it might fail.

Menu: Mainboard
SPL_TEXT_BASE mainboard/google/snow hex

Location of SPL. Default location is within iRAM region.

SPL_MAX_SIZE mainboard/google/snow hex

Max size of SPL. Let's say 32KB for now...

CONSOLE_SERIAL_UART0 mainboard/google/snow bool UART0

Serial console on UART0

CONSOLE_SERIAL_UART1 mainboard/google/snow bool UART1

Serial console on UART1

CONSOLE_SERIAL_UART2 mainboard/google/snow bool UART2

Serial console on UART2

CONSOLE_SERIAL_UART3 mainboard/google/snow bool UART3

Serial console on UART3

CONSOLE_SERIAL_UART_ADDRESS mainboard/google/snow hex

Map the UART names to the respective MMIO address.

BOARD_LENOVO_X60 mainboard/lenovo bool ThinkPad X60 / X60s

The following X60 series ThinkPad machines have been verified to work correctly:

ThinkPad X60s (Model 1702, 1703) ThinkPad X60 (Model 1709)

BOARD_LENOVO_T60 mainboard/lenovo bool ThinkPad T60 / T60p

The following T60 series ThinkPad machines have been verified to work correctly:

Thinkpad T60p (Model 2007)

BOARD_OLD_REVISION mainboard/lippert/hurricane-lx bool Board is old pre-3.0 revision

Look on the bottom side for a number like 406-0001-30. The last 2 digits state the PCB revision (3.0 in this example). For 2.0 or older boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to power on automatically. You may enable the button only after this jumper has been removed. New revision boards are not restricted in this way, and always have the power button enabled.

ONBOARD_UARTS_RS485 mainboard/lippert/hurricane-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_UARTS_RS485 mainboard/lippert/literunner-lx bool Switch on-board serial ports 1 & 2 to RS485

If selected, the first two on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/literunner-lx bool Make on-board CF socket act as Slave

If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master.

ONBOARD_UARTS_RS485 mainboard/lippert/roadrunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_UARTS_RS485 mainboard/lippert/spacerunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/spacerunner-lx bool Make on-board SSD act as Slave

If selected, the on-board SSD will act as IDE Slave instead of Master.

SIO_PORT mainboard/supermicro/h8scm hex

though UARTs are on the NUVOTON BMC, port 0x164E PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

SIO_PORT mainboard/supermicro/h8qgi hex

though UARTs are on the NUVOTON BMC, port 0x164E PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

SIO_PORT mainboard/tyan/s8226 hex

though UARTs are on the NUVOTON BMC, port 0x164E PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E

BOARD_ROMSIZE_KB_16384 mainboard bool ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file of the matching size.

COREBOOT_ROMSIZE_KB_64 mainboard bool 64 KB

Choose this option if you have a 64 KB ROM chip.

COREBOOT_ROMSIZE_KB_128 mainboard bool 128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256 mainboard bool 256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512 mainboard bool 512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024 mainboard bool 1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048 mainboard bool 2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096 mainboard bool 4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

COREBOOT_ROMSIZE_KB_8192 mainboard bool 8192 KB (8 MB)

Choose this option if you have a 8192 KB (8 MB) ROM chip.

COREBOOT_ROMSIZE_KB_16384 mainboard bool 16384 KB (16 MB)

Choose this option if you have a 16384 KB (16 MB) ROM chip.

ENABLE_POWER_BUTTON mainboard bool Enable the power button

The selected mainboard can optionally have the power button tied to ground with a jumper so that the button appears to be constantly depressed. If this option is enabled and the jumper is installed then the board will turn on, but turn off again after a short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an actual power button. Select N if you have the jumper installed.

MAINBOARD_SERIAL_NUMBER mainboard string Serial number

Define the used serial number which will be used by SMBIOS tables.

MAINBOARD_VERSION mainboard string Version number

Define the used version number which will be used by SMBIOS tables.

Menu: Architecture (x86)
UPDATE_IMAGE arch/x86 bool Update existing coreboot.rom image

If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified.

Menu: Architecture (armv7)
UPDATE_IMAGE arch/armv7 bool Update existing coreboot.rom image

If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified.

Menu: Chipset
(comment) CPU
SKIP_LOWLEVEL_INIT cpu/samsung bool Skip low-level init

Certain functions (ie PLL init) and processor features may already be handled by masked ROM code.

BOOTBLOCK_OFFSET cpu/samsung/exynos5250 hex Bootblock offset

This is where the Coreboot bootblock resides. For Exynos5250, this value is pre-determined by the vendor-provided BL1.

UPDATE_CPU_MICROCODE cpu/amd/model_10xxx bool Update CPU microcode

Select this to apply patches to the CPU microcode provided by AMD without source, and distributed with coreboot, to address issues in the CPU post production.

Microcode updates distributed with coreboot are not necessarily the latest version available from AMD. Updates are only applied if they are newer than the microcode already in your CPU.

Unselect this to let Fam10h CPUs run with microcode as shipped from factory. No binary microcode patches will be included in the coreboot image in that case, which can help with creating an image for which complete source code is available, which in turn might simplify license compliance.

Microcode updates intend to solve issues that have been discovered after CPU production. The common case is that systems work as intended with updated microcode, but we have also seen cases where issues were solved by not applying the microcode updates.

Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system in order for this option to matter.

GEODE_VSA_FILE cpu/amd/geode_gx2 bool Add a VSA image

Select this option if you have an AMD Geode GX2 vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_gx2 string AMD Geode GX2 VSA path and filename

The path and filename of the file to use as VSA.

GEODE_VSA_FILE cpu/amd/geode_lx bool Add a VSA image

Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_lx string AMD Geode LX VSA path and filename

The path and filename of the file to use as VSA.

XIP_ROM_SIZE cpu/amd/agesa hex

Overwride the default write through caching size as 1M Bytes. On some AMD paltform, one socket support 2 or more kinds of processor family, compiling several cpu families agesa code will increase the romstage size. In order to execute romstage in place on the flash rom, more space is required to be set as write through caching.

REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL cpu/amd/agesa/family10 bool Redirect AGESA IDS_HDT_CONSOLE to serial console

This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

CPU_AMD_SOCKET_G34 cpu/amd/agesa/family15 bool

AMD G34 Socket

CPU_AMD_SOCKET_C32 cpu/amd/agesa/family15 bool

AMD C32 Socket

CPU_AMD_SOCKET_AM3R2 cpu/amd/agesa/family15 bool

AMD AM3r2 Socket

REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL cpu/amd/agesa/family15 bool Redirect AGESA IDS_HDT_CONSOLE to serial console

This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

TSC_SYNC_LFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an lfence instruction in order to synchronize rdtsc. This is true for all modern AMD CPUs.

TSC_SYNC_MFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs.

SMP cpu bool

This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.

AP_SIPI_VECTOR cpu hex

This must equal address of ap_sipi_vector from bootblock build.

MMX cpu bool

Select MMX in your socket or model Kconfig if your CPU has MMX streaming SIMD instructions. ROMCC can build more efficient code if it can spill to MMX registers.

SSE cpu bool

Select SSE in your socket or model Kconfig if your CPU has SSE streaming SIMD instructions. ROMCC can build more efficient code if it can spill to SSE (aka XMM) registers.

SSE2 cpu bool

Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available.

CPU_MICROCODE_CBFS_GENERATE cpu bool Generate from tree

Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS file. Microcode will not be hard-coded into ramstage.

The microcode file and may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select this option.

CPU_MICROCODE_CBFS_EXTERNAL cpu bool Include external microcode file

Select this option if you want to include an external file containing the CPU microcode. This will be included as a separate file in CBFS. A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot.

The microcode file and may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

CPU_MICROCODE_FILE cpu string Path and filename of CPU microcode

The path and filename of the file containing the CPU microcode.

CPU_MICROCODE_CBFS_NONE cpu bool Do not include microcode updates

Select this option if you do not want CPU microcode included in CBFS. Note that for some CPUs, the microcode is hard-coded into the source tree and is not loaded from CBFS. In this case, microcode will still be updated. There is a push to move all microcode to CBFS, but this change is not implemented for all CPUs.

This option currently applies to: - Intel SandyBridge/IvyBridge - VIA Nano

Microcode may be added to the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

The GOOD: Microcode updates intend to solve issues that have been discovered after CPU production. The expected effect is that systems work as intended with the updated microcode, but we have also seen cases where issues were solved by not applying microcode updates.

The BAD: Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system for this option to have an effect.

The UGLY: A word of CAUTION: some CPUs depend on microcode updates to function correctly. Not updating the microcode may leave the CPU operating at less than optimal performance, or may cause outright hangups. There are CPUs where coreboot cannot properly initialize the CPU without microcode updates For example, if running with the factory microcode, some Intel SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs will hang when changing the frequency.

Make sure you have a way of flashing the ROM externally before selecting this option.

(comment) Northbridge
SVI_HIGH_FREQ northbridge/amd/amdfam10 bool

Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

REDIRECT_NBCIMX_TRACE_TO_SERIAL northbridge/amd/cimx/rd890 bool Redirect AMD Northbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Northbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

Menu: HyperTransport setup
None northbridge/amd None HyperTransport frequency

This option sets the maximum permissible HyperTransport link frequency.

Use of this option will only limit the autodetected HT frequency. It will not (and cannot) increase the frequency beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

LIMIT_HT_SPEED_AUTO northbridge/amd bool HyperTransport downlink width

This option sets the maximum permissible HyperTransport downlink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

LIMIT_HT_DOWN_WIDTH_16 northbridge/amd bool HyperTransport uplink width

This option sets the maximum permissible HyperTransport uplink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

SDRAMPWR_4DIMM northbridge/intel/i440bx bool

This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong.

If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option.


OVERRIDE_CLOCK_DISABLE northbridge/intel/i945 bool

Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power consumption. However, some boards do not like unused clock signals to be disabled.

MAXIMUM_SUPPORTED_FREQUENCY northbridge/intel/i945 int

If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of.

CHECK_SLFRCS_ON_RESUME northbridge/intel/i945 int

On some boards it may be neccessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, effectively making it impossible to resume.

HAVE_MRC northbridge/intel/sandybridge bool Add a System Agent binary

Select this option to add a System Agent binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE northbridge/intel/sandybridge string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

CBFS_SIZE northbridge/intel/sandybridge hex Size of CBFS filesystem in ROM

On Sandybridge and Ivybridge systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image.

(comment) Southbridge
Menu: AMD Geode GX1 video support
EXT_CONF_SUPPORT southbridge/amd/rs690 bool

Select if RS690 should be setup to support MMCONF.

USBDEBUG_DEFAULT_PORT southbridge/amd/sb600 int SATA Mode

Select the mode in which SATA should be driven. IDE or AHCI. The default is IDE.

config SATA_MODE_IDE bool "IDE"

config SATA_MODE_AHCI bool "AHCI"

SATA_CONTROLLER_MODE southbridge/amd/cimx/sb700 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb700 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb700 hex

Set SCI IRQ to 9.

REDIRECT_SBCIMX_TRACE_TO_SERIAL southbridge/amd/cimx/sb700 bool Redirect AMD Southbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Southbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

S3_VOLATILE_POS southbridge/amd/cimx/sb700 hex S3 volatile storage position

For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage.

ENABLE_IDE_COMBINED_MODE southbridge/amd/cimx/sb800 bool Enable SATA IDE combined mode

If Combined Mode is enabled. IDE controller is exposed and SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and SATA controller has full control of all 6 Ports when operating in non-IDE mode.

IDE_COMBINED_MODE southbridge/amd/cimx/sb800 hex SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE.

SB800_SATA_IDE southbridge/amd/cimx/sb800 bool NATIVE

NATIVE is the default mode and does not require a ROM.

SB800_SATA_AHCI southbridge/amd/cimx/sb800 bool AHCI

AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM.

SB800_SATA_RAID southbridge/amd/cimx/sb800 bool RAID

sb800 RAID mode must have the two required ROM files.

RAID_ROM_ID southbridge/amd/cimx/sb800 string RAID device PCI IDs

1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/cimx/sb800 hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000.

S3_VOLATILE_POS southbridge/amd/cimx/sb800 hex S3 volatile storage position

For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage.

SB800_IMC_FWM southbridge/amd/cimx/sb800 bool Add IMC firmware

Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

SB800_FWM_AT_FFFA0000 southbridge/amd/cimx/sb800 bool 0xFFFA0000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFF20000 southbridge/amd/cimx/sb800 bool 0xFFF20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFE20000 southbridge/amd/cimx/sb800 bool 0xFFE20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFC20000 southbridge/amd/cimx/sb800 bool 0xFFC20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FF820000 southbridge/amd/cimx/sb800 bool 0xFF820000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_POSITION southbridge/amd/cimx/sb800 hex Fan Control

Select the method of SB800 fan control to be used. None would be for either fixed maximum speed fans connected to the SB800 or for an external chip controlling the fan speeds. Manual control sets up the SB800 fan control registers. IMC fan control uses the SB800 IMC to actively control the fan speeds.

SB800_NO_FAN_CONTROL southbridge/amd/cimx/sb800 bool None

No SB800 Fan control - Do not set up the SB800 fan control registers.

SB800_MANUAL_FAN_CONTROL southbridge/amd/cimx/sb800 bool Manual

Configure the SB800 fan control registers in devicetree.cb.

SB800_IMC_FAN_CONTROL southbridge/amd/cimx/sb800 bool IMC Based

Set up the SB800 to use the IMC based Fan controller. This requires the IMC rom from AMD. Configure the registers in devicetree.cb.

SATA_CONTROLLER_MODE southbridge/amd/cimx/sb900 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb900 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb900 hex

Set SCI IRQ to 9.

S3_VOLATILE_POS southbridge/amd/cimx/sb900 hex S3 volatile storage position

For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage.

HUDSON_XHCI_FWM southbridge/amd/agesa/hudson bool Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard usb3.0

HUDSON_IMC_FWM southbridge/amd/agesa/hudson bool Add imc firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM southbridge/amd/agesa/hudson bool Add gec firmware

Add Hudson 2/3/4 GEC Firmware

HUDSON_FWM_POSITION southbridge/amd/agesa/hudson hex Hudson Firmware rom Position

Hudson requires the firmware MUST be located at a specific address (ROM start address + 0x20000), otherwise xhci host Controller can not find or load the xhci firmware.

The firmware start address is dependent on the ROM chip size. The default offset is 0x20000 from the ROM start address, namely 0xFFF20000 if flash chip size is 1M 0xFFE20000 if flash chip size is 2M 0xFFC20000 if flash chip size is 4M 0xFF820000 if flash chip size is 8M 0xFF020000 if flash chip size is 16M

HUDSON_FWM_POSITION southbridge/amd/agesa/hudson hex SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE.

HUDSON_SATA_IDE southbridge/amd/agesa/hudson bool NATIVE

NATIVE is the default mode and does not require a ROM.

HUDSON_SATA_RAID southbridge/amd/agesa/hudson bool RAID

HUDSON RAID mode must have the two required ROM files.

HUDSON_SATA_AHCI southbridge/amd/agesa/hudson bool AHCI

AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM.

HUDSON_SATA_LEGACY_IDE southbridge/amd/agesa/hudson bool LEGACY IDE

TODO

HUDSON_SATA_IDE2AHCI southbridge/amd/agesa/hudson bool IDE to AHCI

TODO

HUDSON_SATA_AHCI7804 southbridge/amd/agesa/hudson bool AHCI7804

AHCI ROM Required, and AMD driver required in the OS.

HUDSON_SATA_IDE2AHCI7804 southbridge/amd/agesa/hudson bool IDE to AHCI7804

AHCI ROM Required, and AMD driver required in the OS.

RAID_ROM_ID southbridge/amd/agesa/hudson string RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/agesa/hudson hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000.

S3_VOLATILE_POS southbridge/amd/agesa/hudson hex S3 volatile storage position

For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage.

HAVE_CMC southbridge/intel/sch bool Add a CMC state machine binary

Select this option to add a CMC state machine binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

CMC_FILE southbridge/intel/sch string Intel CMC path and filename

The path and filename of the file to use as CMC state machine binary.

SERIRQ_CONTINUOUS_MODE southbridge/intel/bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

LOCK_MANAGEMENT_ENGINE southbridge/intel/bd82x6x bool Lock Management Engine section

The Intel Management Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

(comment) Super I/O
(comment) Embedded Controllers
EC_ACPI ec/acpi bool

ACPI Embedded Controller interface. Mostly found in laptops.

EC_COMPAL_ENE932 ec/compal/ene932 bool

Interface to COMPAL ENE932 Embedded Controller.

EC_SMSC_MEC1308 ec/smsc/mec1308 bool

Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.

Menu: Devices
VGA_ROM_RUN device bool Run VGA Option ROMs

Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS payload.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

S3_VGA_ROM_RUN device bool Re-run VGA Option ROMs on S3 resume

Execute VGA Option ROMs in coreboot when resuming from S3 suspend.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

PCI_ROM_RUN device bool Run non-VGA Option ROMs

Execute non-VGA PCI Option ROMs in coreboot if found.

Examples include IDE/SATA controller Option ROMs and Option ROMs for network cards (NICs).

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

ON_DEVICE_ROM_RUN device bool Run Option ROMs on PCI devices

Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.

If disabled, only Option ROMs stored in CBFS will be executed by coreboot. If you are concerned about security, you might want to disable this option, but it might leave your system in a state of degraded functionality.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

PCI_OPTION_ROM_RUN_REALMODE device bool Native mode

If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)

PCI_OPTION_ROM_RUN_YABEL device bool Secure mode

If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs.

This option prevents Option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the native Option ROM initialization method.

This is the default choice for non-x86 systems.

YABEL_PCI_ACCESS_OTHER_DEVICES device bool Allow Option ROMs to access other devices

Per default, YABEL only allows Option ROMs to access the PCI device that they are associated with. However, this causes trouble for some onboard graphics chips whose Option ROM needs to reconfigure the north bridge.

YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG device bool Fake success on writing other device's config space

By default, YABEL aborts when the Option ROM tries to write to other devices' config spaces. With this option enabled, the write doesn't follow through, but the Option ROM is allowed to go on. This can create issues such as hanging Option ROMs (if it depends on that other register changing to the written value), so test for impact before using this option.

YABEL_VIRTMEM_LOCATION device hex Location of YABEL's virtual memory

YABEL requires 1MB memory for its CPU emulation. This memory is normally located at 16MB.

YABEL_DIRECTHW device bool Direct hardware access

YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one).

When choosing this option, x86emu will pass through all hardware accesses to memory and I/O devices to the underlying memory and I/O addresses. While this option prevents Option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Enable this option for a good compromise between security and speed.

PCIEXP_COMMON_CLOCK device bool Enable PCIe Common Clock

Detect and enable Common Clock on PCIe links.

PCIEXP_ASPM device bool Enable PCIe ASPM

Detect and enable ASPM on PCIe links.

Menu: VGA BIOS
VGA_BIOS device bool Add a VGA BIOS image

Select this option if you have a VGA BIOS image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VGA_BIOS_FILE device string VGA BIOS path and filename

The path and filename of the file to use as VGA BIOS.

VGA_BIOS_ID device string VGA device PCI IDs

The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix).

INTEL_MBI device bool Add an MBI image

Select this option if you have an Intel MBI image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

MBI_FILE device string Intel MBI path and filename

The path and filename of the file to use as VGA BIOS.

Menu: Display
FRAMEBUFFER_SET_VESA_MODE device bool Set VESA framebuffer mode

Set VESA framebuffer mode (needed for bootsplash)

FRAMEBUFFER_SET_VESA_MODE device bool VESA framebuffer video mode

This option sets the resolution used for the coreboot framebuffer (and bootsplash screen).

FRAMEBUFFER_KEEP_VESA_MODE device bool Keep VESA framebuffer

This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a framebuffer driver. If this option is disabled, coreboot will switch back to text mode before handing control to a payload.

BOOTSPLASH device bool Show graphical bootsplash

This option shows a graphical bootsplash screen. The grapics are loaded from the CBFS file bootsplash.jpg.

BOOTSPLASH_FILE device string Bootsplash path and filename

The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg.

Menu: Generic Drivers
ELOG drivers/elog bool Support for flash based event log

Enable support for flash based event logging.

ELOG_FLASH_BASE drivers/elog hex Event log offset into flash

Offset into the flash chip for the ELOG block. This should be allocated in the FMAP.

ELOG_AREA_SIZE drivers/elog hex Size of Event Log area in flash

This should be a multiple of flash block size.

Default is 4K.

ELOG_FULL_THRESHOLD drivers/elog hex Threshold at which flash is considered full

When the Event Log size is larger than this it will be shrunk to ELOG_SHRINK_SIZE. Must be greater than ELOG_AREA_SIZE, and ELOG_AREA_SIZE - ELOG_FULL_THRESHOLD must be greater than the maximum event size of 128.

Default is 75% of the log, or 3K.

ELOG_SHRINK_SIZE drivers/elog hex Resulting size when the event log is shrunk

When the Event Log is shrunk it will go to this size. ELOG_AREA_SIZE - ELOG_SHRINK_SIZE must be less than CONFIG_ELOG_FULL_THRESHOLD.

Default is 1K.

ELOG_CBMEM drivers/elog bool Store a copy of ELOG in CBMEM

This option will have ELOG store a copy of the flash event log in a CBMEM region and export that address in SMBIOS to the OS. This is useful if the ELOG location is not in memory mapped flash, but it means that events added at runtime via the SMI handler will not be reflected in the CBMEM copy of the log.

ELOG_GSMI drivers/elog bool SMI interface to write and clear event log

This interface is compatible with the linux kernel driver available with CONFIG_GOOGLE_GSMI and can be used to write kernel reset/shutdown messages to the event log.

ELOG_BOOT_COUNT drivers/elog bool Maintain a monotonic boot number in CMOS

Store a monotonic boot number in CMOS and provide an interface to read the current value and increment the counter. This boot counter will be logged as part of the System Boot event.

ELOG_BOOT_COUNT_CMOS_OFFSET drivers/elog int Offset in CMOS to store the boot count

This value must be greater than 16 bytes so as not to interfere with the standard RTC region. Requires 8 bytes.

DRIVER_MAXIM_MAX77686 drivers/maxim/max77686 bool

Maxim MAX77686 power regulator

DRIVERS_OXFORD_OXPCIE drivers/oxford/oxpcie bool Oxford OXPCIe952

Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID 0xc158 will work. NOTE: Right now you have to set the base address of your OXPCIe952 card to exactly the value that the device allocator would set them later on, or serial console functionality will stop as soon as the resource allocator assigns a new base address to the device.

OXFORD_OXPCIE_BRIDGE_BUS drivers/oxford/oxpcie hex OXPCIe's PCIe bridge bus number

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system. In order to use an OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge that controls the OXPCIe952 controller first.

OXFORD_OXPCIE_BRIDGE_DEVICE drivers/oxford/oxpcie hex OXPCIe's PCIe bridge device number

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system. In order to use an OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge that controls the OXPCIe952 controller first.

OXFORD_OXPCIE_BRIDGE_FUNCTION drivers/oxford/oxpcie hex OXPCIe's PCIe bridge function number

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system. In order to use an OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge that controls the OXPCIe952 controller first.

OXFORD_OXPCIE_BRIDGE_SUBORDINATE drivers/oxford/oxpcie hex OXPCIe's PCIe bridge subordinate bus

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system. In order to use an OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge that controls the OXPCIe952 controller first.

OXFORD_OXPCIE_BASE_ADDRESS drivers/oxford/oxpcie hex Base address for rom stage console

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system. In order to use an OXPCIe952 based PCIe card, coreboot has to set up a temporary address for the OXPCIe952 controller.


DRIVERS_PS2_KEYBOARD drivers/pc80 bool PS/2 keyboard init

Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads (eg, SeaBIOS, Linux) do not require it. Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y.

TPM drivers/pc80 bool

Enable this option to enable TPM support in coreboot.

If unsure, say N.

RTL8168_ROM_DISABLE drivers/realtek bool Disable RTL8168 ROM

Just enough of a driver to make coreboot not look for an Option ROM. No configuration is necessary for the OS to pick up the device.

DRIVERS_SIL_3114 drivers/sil bool Silicon Image SIL3114

It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it.


SPI_FLASH drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash.

SPI_FLASH_SMM drivers/spi bool SPI flash driver support in SMM

Select this option if you want SPI flash support in SMM.

SPI_FLASH_EON drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON.

SPI_FLASH_MACRONIX drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix.

SPI_FLASH_SPANSION drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion.

SPI_FLASH_SST drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST.

SPI_FLASH_STMICRO drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO.

SPI_FLASH_WINBOND drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond.

SPI_FLASH_NO_FAST_READ drivers/spi bool Disable Fast Read command

Select this option if your setup requires to avoid "fast read"s from the SPI flash parts.

SPI_FLASH_GIGADEVICE drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice.

Menu: Console
SERIAL_CONSOLE console bool Serial port console output

Send coreboot debug output to a serial port

EARLY_SERIAL_CONSOLE console bool

Use serial console during early (pre-RAM) boot stages

CONSOLE_SERIAL8250 console bool Serial port console output (I/O mapped, 8250-compatible)

Send coreboot debug output to an I/O mapped serial port console.

CONSOLE_SERIAL8250MEM console bool Serial port console output (memory mapped, 8250-compatible)

Send coreboot debug output to a memory mapped serial port console.

CONSOLE_SERIAL_NONSTANDARD_MEM console bool Serial port console output (memory-mapped, device-specific)

Send coreboot debug output to a memory mapped serial port console on a device-specific UART.

CONSOLE_SERIAL_COM1 console bool COM1/ttyS0, I/O port 0x3f8

Serial console on COM1/ttyS0 at I/O port 0x3f8.

CONSOLE_SERIAL_COM2 console bool COM2/ttyS1, I/O port 0x2f8

Serial console on COM2/ttyS1 at I/O port 0x2f8.

CONSOLE_SERIAL_COM3 console bool COM3/ttyS2, I/O port 0x3e8

Serial console on COM3/ttyS2 at I/O port 0x3e8.

CONSOLE_SERIAL_COM4 console bool COM4/ttyS3, I/O port 0x2e8

Serial console on COM4/ttyS3 at I/O port 0x2e8.

TTYS0_BASE console hex

Map the COM port names to the respective I/O port.

CONSOLE_SERIAL_115200 console bool 115200

Set serial port Baud rate to 115200.

CONSOLE_SERIAL_57600 console bool 57600

Set serial port Baud rate to 57600.

CONSOLE_SERIAL_38400 console bool 38400

Set serial port Baud rate to 38400.

CONSOLE_SERIAL_19200 console bool 19200

Set serial port Baud rate to 19200.

CONSOLE_SERIAL_9600 console bool 9600

Set serial port Baud rate to 9600.

TTYS0_BAUD console int

Map the Baud rates to an integer.

USBDEBUG console bool USB 2.0 EHCI debug dongle support

This option allows you to use a so-called USB EHCI Debug device (such as the Ajays NET20DC, AMIDebug RX, or a system using the Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI Debug Port capability.

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list of supported controllers.

If unsure, say N.

USBDEBUG_DEFAULT_PORT console int Default USB port to use as Debug Port

This option selects which physical USB port coreboot will try to use as EHCI Debug Port first (valid values are: 1-15).

If coreboot doesn't detect an EHCI Debug Port dongle on this port, it will try all the other ports one after the other. This will take a few seconds of time though, and thus slow down the booting process.

Hence, if you select the correct port here, you can speed up your boot time. Which USB port number (1-15) refers to which actual port on your mainboard (potentially also USB pin headers on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error.

ONBOARD_VGA_IS_PRIMARY console bool Use onboard VGA as primary video device

If not selected, the last adapter found will be used.

CONSOLE_NE2K console bool Network console over NE2000 compatible Ethernet adapter

Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP port 6666 on IP/MAC specified with options bellow. Use following netcat command: nc -u -l -p 6666

CONSOLE_NE2K_DST_MAC console string Destination MAC address of remote system

Type in either MAC address of logging system or MAC address of the router.

CONSOLE_NE2K_DST_IP console string Destination IP of logging system

This is IP adress of the system running for example netcat command to dump the packets.

CONSOLE_NE2K_SRC_IP console string IP address of coreboot system

This is the IP of the coreboot system

CONSOLE_NE2K_IO_PORT console hex NE2000 adapter fixed IO port address

This is the IO port address for the IO port on the card, please select some non-conflicting region, 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align)

CONSOLE_CBMEM console bool Send console output to a CBMEM buffer

Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.

CONSOLE_CBMEM_BUFFER_SIZE console hex Room allocated for console output in CBMEM

Space allocated for console output storage in CBMEM. The default value (64K or 0x10000 bytes) is large enough to accommodate even the BIOS_SPEW level.

CONSOLE_CAR_BUFFER_SIZE console hex Room allocated for console output in Cache as RAM

Console is used before RAM is initialized. This is the room reserved in the DCACHE based RAM to keep console output before it can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level.


MAXIMUM_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

MAXIMUM_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

MAXIMUM_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

MAXIMUM_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

MAXIMUM_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

MAXIMUM_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

MAXIMUM_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

MAXIMUM_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

MAXIMUM_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

MAXIMUM_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

DEFAULT_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

DEFAULT_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

DEFAULT_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

DEFAULT_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

DEFAULT_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

DEFAULT_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

DEFAULT_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

DEFAULT_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

DEFAULT_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

DEFAULT_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

CONSOLE_POST console bool Show POST codes on the debug console

If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the debug console.

CMOS_POST console bool Store post codes in CMOS for debugging

If enabled, coreboot will store post codes in CMOS and switch between two offsets on each boot so the last post code in the previous boot can be retrieved. This uses 3 bytes of CMOS.

CMOS_POST_OFFSET console hex Offset into CMOS to store POST codes

If CMOS_POST is enabled then an offset into CMOS must be provided. If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table.

IO_POST console bool Send POST codes to an IO port

If enabled, POST codes will be written to an IO port.

IO_POST_PORT console hex IO port for POST codes

POST codes on x86 are typically written to the LPC bus on port 0x80. However, it may be desireable to change the port number depending on the presence of coprocessors/microcontrollers or if the platform does not support IO in the conventional x86 manner.

HAVE_HARD_RESET toplevel bool

This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code.

HAVE_OPTION_TABLE toplevel bool

This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig.

VGA toplevel bool

Build board-specific VGA code.

GFXUMA toplevel bool

Enable Unified Memory Architecture for graphics.

HAVE_ACPI_TABLES toplevel bool

This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. Whether or not the ACPI tables are actually generated by coreboot is configurable by the user via GENERATE_ACPI_TABLES.

HAVE_MP_TABLE toplevel bool

This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.

HAVE_PIRQ_TABLE toplevel bool

This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.

MAX_PIRQ_LINKS toplevel int

This variable specifies the number of PIRQ interrupt links which are routable. On most chipsets, this is 4, INTA through INTD. Some chipsets offer more than four links, commonly up to INTH. They may also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set.

Menu: System tables
GENERATE_ACPI_TABLES toplevel bool Generate ACPI tables

Generate ACPI tables for this board.

If unsure, say Y.

GENERATE_MP_TABLE toplevel bool Generate an MP table

Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board.

If unsure, say Y.

GENERATE_PIRQ_TABLE toplevel bool Generate a PIRQ table

Generate a PIRQ table for this board.

If unsure, say Y.

GENERATE_SMBIOS_TABLES toplevel bool Generate SMBIOS tables

Generate SMBIOS tables for this board.

If unsure, say Y.

Menu: Payload
PAYLOAD_NONE toplevel bool None

Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.

PAYLOAD_ELF toplevel bool An ELF executable payload

Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

PAYLOAD_SEABIOS toplevel bool SeaBIOS

Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

PAYLOAD_FILO toplevel bool FILO

Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

SEABIOS_STABLE toplevel bool 1.7.1

Stable SeaBIOS version

SEABIOS_MASTER toplevel bool master

Newest SeaBIOS version

FILO_STABLE toplevel bool 0.6.0

Stable FILO version

FILO_MASTER toplevel bool HEAD

Newest FILO version

PAYLOAD_FILE toplevel string Payload path and filename

The path and filename of the ELF executable file to use as payload.

COMPRESSED_PAYLOAD_LZMA toplevel bool Use LZMA compression for payloads

In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.

Menu: Debugging
GDB_STUB toplevel bool GDB debugging support

If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details.

GDB_WAIT toplevel bool Wait for a GDB connection

If enabled, coreboot will wait for a GDB connection.

DEBUG_CBFS toplevel bool Output verbose CBFS debug messages

This option enables additional CBFS related debug messages.

DEBUG_RAM_SETUP toplevel bool Output verbose RAM init debug messages

This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_CAR toplevel bool Output verbose Cache-as-RAM debug messages

This option enables additional CAR related debug messages.

DEBUG_PIRQ toplevel bool Check PIRQ table consistency

If unsure, say N.

DEBUG_SMBUS toplevel bool Output verbose SMBus debug messages

This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_SMI toplevel bool Output verbose SMI debug messages

This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_SMM_RELOCATION toplevel bool Debug SMM relocation code

This option enables additional SMM handler relocation related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_MALLOC toplevel bool Output verbose malloc debug messages

This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_ACPI toplevel bool Output verbose ACPI debug messages

This option enables additional ACPI related debug messages.

Note: This option will slightly increase the size of the coreboot image.

If unsure, say N.

REALMODE_DEBUG toplevel bool Enable debug messages for option ROM execution

This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.

X86EMU_DEBUG toplevel bool Output verbose x86emu debug messages

This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_JMP toplevel bool Trace JMP/RETF

Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_TRACE toplevel bool Trace all opcodes

Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_PNP toplevel bool Log Plug&Play accesses

Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_DISK toplevel bool Log Disk I/O

Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_PMM toplevel bool Log PMM

Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.


X86EMU_DEBUG_VBE toplevel bool Debug VESA BIOS Extensions

Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_INT10 toplevel bool Redirect INT10 output to console

Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_INTERRUPTS toplevel bool Log intXX calls

Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_CHECK_VMEM_ACCESS toplevel bool Log special memory accesses

Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_MEM toplevel bool Log all memory accesses

Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_IO toplevel bool Log IO accesses

Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_TPM toplevel bool Output verbose TPM debug messages

This option enables additional TPM related debug messages.

DEBUG_SPI_FLASH toplevel bool Output verbose SPI flash debug messages

This option enables additional SPI flash related debug messages.

DEBUG_INTEL_ME toplevel bool Verbose logging for Intel Management Engine

Enable verbose logging for Intel Management Engine driver that is present on Intel 6-series chipsets.

LLSHELL toplevel bool Built-in low-level shell

If enabled, you will have a low level shell to examine your machine. Put llshell() in your (romstage) code to start the shell. See src/arch/x86/llshell/llshell.inc for details.

TRACE toplevel bool Trace function calls

If enabled, every function will print information to console once the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) the 0xaaaabbbb is the actual function and 0xccccdddd is EIP of calling function. Please note some printk releated functions are omitted from trace to have good looking console dumps.

POWER_BUTTON_DEFAULT_ENABLE toplevel bool

Select when the board has a power button which can optionally be disabled by the user.

POWER_BUTTON_DEFAULT_DISABLE toplevel bool

Select when the board has a power button which can optionally be enabled by the user, e.g. when the board ships with a jumper over the power switch contacts.

POWER_BUTTON_FORCE_ENABLE toplevel bool

Select when the board requires that the power button is always enabled.

POWER_BUTTON_FORCE_DISABLE toplevel bool

Select when the board requires that the power button is always disabled, e.g. when it has been hardwired to ground.

POWER_BUTTON_IS_OPTIONAL toplevel bool

Internal option that controls ENABLE_POWER_BUTTON visibility.

CHROMEOS vendorcode/google/chromeos bool

Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build.

Menu: ChromeOS
VBNV_OFFSET vendorcode/google/chromeos hex

CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC.

VBNV_SIZE vendorcode/google/chromeos hex

CMOS storage size for VbNv data. This value must match cmos.layout in the mainboard directory.

FLASHMAP_OFFSET vendorcode/google/chromeos hex Flash Map Offset

Offset of flash map in firmware image

NO_TPM_RESUME vendorcode/google/chromeos bool

On some boards the TPM stays powered up in S3. On those boards, booting Windows will break if the TPM resume command is sent during an S3 resume.