Difference between revisions of "Coreboot Options"

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(Most options now have a CONFIG_ prefix.)
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This is an automatically generated list of '''coreboot v2 compile-time options'''.
+
This is an automatically generated list of '''coreboot compile-time options'''.
 
+
Last update: 2009/07/01 00:10:41.
+
  
 +
Last update: 2010/02/09 15:05:25. (r5100)
 
{| border="0" style="font-size: smaller"
 
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
 
! align="left" | Option
 
! align="left" | Option
! align="left" | Comment
+
! align="left" | Source
! align="left" | Default
+
! align="left" | Export
+
 
! align="left" | Format
 
! align="left" | Format
 +
! align="left" | Short Description
 +
! align="left" | Description
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: General setup || || || ||
 +
|- bgcolor="#eeeeee"
 +
| EXPERT || toplevel || bool || Expert mode ||
 +
This allows you to select certain advanced configuration options.
 +
 +
Warning: Only enable this option if you really know what you are
 +
doing! You have been warned!
  
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ARCH_X86 || "X86 is the default" || 1 || always ||  
+
| LOCALVERSION || toplevel || string || Local version string ||
 +
Append an extra string to the end of the coreboot version.
 +
 
 +
This can be useful if, for instance, you want to append the
 +
respective board's hostname or some other identifying string to
 +
the coreboot version number, so that you can easily distinguish
 +
boot logs of different boards from each other.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Mainboard || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ARCH || "Default architecture is i386, options are alpha and ppc" || "i386" || always ||  
+
| BOARD_ROMSIZE_KB_4096 || mainboard || bool || ROM chip size ||
 +
Select the size of the ROM chip you intend to flash coreboot on.
 +
 
 +
The build system will take care of creating a coreboot.rom file
 +
of the matching size.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_HAVE_MOVNTI || "This cpu supports the MOVNTI directive" || 0 || always ||  
+
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
 +
Choose this option if you have a 128 KB ROM chip.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CROSS_COMPILE || "Cross compiler prefix" || "" || always ||  
+
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
 +
Choose this option if you have a 256 KB ROM chip.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CC || "Target C Compiler" || "$(CONFIG_CROSS_COMPILE)gcc" || always ||  
+
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
 +
Choose this option if you have a 512 KB ROM chip.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HOSTCC || "Host C Compiler" || "gcc" || always ||  
+
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
 +
Choose this option if you have a 1024 KB (1 MB) ROM chip.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CPU_OPT || "Additional per-cpu CFLAGS" || none || used ||  
+
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
 +
Choose this option if you have a 2048 KB (2 MB) ROM chip.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_OBJCOPY || "Objcopy command" || "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff" || always ||  
+
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
 +
Choose this option if you have a 4096 KB (4 MB) ROM chip.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Chipset || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_VERSION || "coreboot version" || "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)" || always || "\"%s\""
+
| || || (comment) || || CPU ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_EXTRA_VERSION || || ||  || "\"%s\""
+
| SMP || cpu || bool ||  ||  
 +
This option is used to enable certain functions to make coreboot
 +
work correctly on symmetric multi processor (SMP) systems.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_BUILD || "Build date" || "$(shell date)" || always || "\"%s\""
+
| VAR_MTRR_HOLE || cpu || bool || ||
 +
Unset this if you don't want the MTRR code to use
 +
subtractive MTRRs
 +
 
 +
||
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_COMPILE_TIME || "Build time" || "$(shell date +%T)" || always || "\"%s\""
+
| || || (comment) || || Northbridge ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_COMPILE_BY || "Who build this image" || "$(shell whoami)" || always || "\"%s\""
+
| || || (comment) || || Southbridge ||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: AMD Geode GX1 video support || || || ||
 +
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_COMPILE_HOST || "Build host" || "$(shell hostname)" || always || "\"%s\""
+
| || || (comment) || || Super I/O ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_COMPILE_DOMAIN || "Build domain name" || "$(shell dnsdomainname)" || always || "\"%s\""
+
| || || (comment) || || Devices ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_COMPILER || "Build compiler" || "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -1)" || always || "\"%s\""
+
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
 +
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
 +
this unless you're sure you don't want the briges setup for VGA.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_LINKER || "Build linker" || "$(shell  $(CC) -Wl,--version 2>&1 | grep \" ld\")" || always || "\"%s\""
+
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
 +
Execute VGA option ROMs, if found. This is required to enable
 +
PCI/AGP/PCI-E video cards.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ASSEMBLER || "Build assembler" || "$(shell  touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )" || always || "\"%s\""
+
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
 +
Execute non-VGA PCI option ROMs, if found.
 +
 
 +
Examples include IDE/SATA controller option ROMs and option ROMs
 +
for network cards (NICs).
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CHIP_CONFIGURE || "Use new chip_configure method for configuring (non-pci) devices" || 0 || used ||  
+
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Real mode ||
 +
If you select this option, PCI option ROMs will be executed
 +
natively on the CPU in real mode. No CPU emulation is involved,
 +
so this is the fastest, but also the least secure option.
 +
(only works on x86/x64 systems)
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_USE_INIT || "Use stage 1 initialization code" || 0 || always ||  
+
| PCI_OPTION_ROM_RUN_X86EMU || devices || bool || x86emu ||
 +
If you select this option, the x86emu CPU emulator will be used to
 +
execute PCI option ROMs.
 +
When choosing this option, x86emu will pass through all hardware
 +
accesses to memory and IO devices to the underlying memory and IO
 +
addresses. While this option prevents option ROMs from doing dirty
 +
tricks with the CPU (such as installing SMM modules or hypervisors),
 +
they can still access all devices in the system.
 +
Choosing x86emu, option ROM execution is slower than native execution
 +
in real mode, but faster than the full system emulation YABEL
 +
This is the default choice for non-x86 systems.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_V2 || "This is used by code to determine v2 vs v3" || 1 || always ||  
+
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || YABEL ||
 +
If you select this option, the YABEL system emulator will be used to
 +
execute PCI option ROMs.
 +
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 +
additionally provides a PC system emulation that filters bad device and
 +
memory access (such as PCI config space access to other devices than the
 +
initialized one).
 +
This option best prevents option ROMs from doing dirty tricks with the
 +
system (such as installing SMM modules or hypervisors), but it is also
 +
significantly slower than the other option ROM initialization methods.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_HAVE_FALLBACK_BOOT || "Set if fallback booting required" || 0 || always || "%d"
+
| YABEL_DEBUG_FLAGS || devices || hex || Hex value for YABEL debug flags ||  
 +
See debug.h for values 0 is no debug output, 0x31ff is _verbose_.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Console options || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_HAVE_FAILOVER_BOOT || "Set if failover booting required" || 0 || always || "%d"
+
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
 +
Send coreboot debug output to a serial port console.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_USE_FALLBACK_IMAGE || "Set to build a fallback image" || 0 || used || "%d"
+
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
 +
Serial console on COM1/ttyS0 at I/O port 0x3f8.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_USE_FAILOVER_IMAGE || || || ||  
+
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
 +
Serial console on COM2/ttyS1 at I/O port 0x2f8.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_FALLBACK_SIZE || "Default fallback image size" || 65536 || used || "0x%x"
+
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
 +
Serial console on COM3/ttyS2 at I/O port 0x3e8.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_FAILOVER_SIZE || || || ||  
+
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
 +
Serial console on COM4/ttyS3 at I/O port 0x2e8.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ROM_SIZE || "Size of your ROM" || none || used || "0x%x"
+
| TTYS0_BASE || console || hex || ||
 +
Map the COM port names to the respective I/O port.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ROM_IMAGE_SIZE || "Default image size" || 65535 || always || "0x%x"
+
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
 +
Set serial port Baud rate to 115200.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ROM_SECTION_SIZE || "Default rom section size" || {CONFIG_FALLBACK_SIZE} || used || "0x%x"
+
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
 +
Set serial port Baud rate to 57600.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ROM_SECTION_OFFSET || "Default rom section offset" || {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE} || used || "0x%x"
+
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
 +
Set serial port Baud rate to 38400.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_PAYLOAD_SIZE || "Default payload size" || {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE} || always || "0x%x"
+
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
 +
Set serial port Baud rate to 19200.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ROMBASE || "Base address of coreboot in ROM" || {CONFIG_PAYLOAD_SIZE} || always || "0x%x"
+
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
 +
Set serial port Baud rate to 9600.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_ROMSTART || "Start address of coreboot in ROM" || none || used || "0x%x"
+
| TTYS0_BAUD || console || int || ||
 +
Map the Baud rates to an integer.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_RESET || "Hardware reset vector address" || {CONFIG_ROMBASE} || always || "0x%x"
+
| SERIAL_POST || console || bool || Show POST codes on the serial port console ||  
 +
If enabled, coreboot will additionally print POST codes (which are
 +
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
 +
device) on the serial console.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_EXCEPTION_VECTORS || "Address of exception vector table" || {CONFIG_ROMBASE+0x100} || always || "0x%x"
+
| USBDEBUG_DIRECT || console || bool || USB 2.0 EHCI debug dongle support ||
 +
This option allows you to use a so-called USB EHCI Debug device
 +
to retrieve the coreboot debug messages (instead, or in addition
 +
to, a serial port).
 +
 
 +
This feature is NOT supported on all chipsets in coreboot!
 +
 
 +
It also requires a USB2 controller which supports the EHCI
 +
Debug Port capability. Controllers which are known to work:
 +
 
 +
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
 +
* 8086:24cd Intel ICH4/ICH4-M
 +
* 8086:24dd Intel ICH5
 +
* 8086:265c Intel ICH6
 +
* 8086:268c Intel 631xESB/632xESB/3100
 +
* 8086:27cc Intel ICH7
 +
* 8086:2836 Intel ICH8
 +
* 8086:283a Intel ICH8
 +
* 8086:293a Intel ICH9
 +
* 10de:0088 NVIDIA MCP2A
 +
* 10de:005b NVIDIA CK804
 +
* 10de:026e NVIDIA MCP51
 +
* 10de:036d NVIDIA MCP55
 +
* 10de:03f2 NVIDIA MCP61
 +
* 1002:4386 ATI/AMD SB600
 +
* 1106:3104 VIA VX800
 +
 
 +
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_STACK_SIZE || "Default stack size" || 0x2000 || always || "0x%x"
+
| CONSOLE_VGA_ONBOARD_AT_FIRST || console || bool || Use onboard VGA as primary video device ||
 +
If not selected, the last adapter found will be used.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_HEAP_SIZE || "Default heap size" || 0x2000 || always || "0x%x"
+
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
 +
Way too many details.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_RAMBASE || "Base address of coreboot in RAM" || none || always || "0x%x"
+
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
 +
Debug-level messages.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_RAMSTART || "Start address of coreboot in RAM" || none || used || "0x%x"
+
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
 +
Informational messages.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_USE_DCACHE_RAM || "Use data cache as temporary RAM if possible" || 0 || always ||  
+
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
 +
Normal but significant conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CAR_FAM10 || "AMD family 10 CAR requires additional setup" || 0 || always ||  
+
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
 +
Warning conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_DCACHE_RAM_BASE || "Base address of data cache when using it for temporary RAM" || 0xc0000 || always || "0x%x"
+
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
 +
Error conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_DCACHE_RAM_SIZE || "Size of data cache when using it for temporary RAM" || 0x1000 || always || "0x%x"
+
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
 +
Critical conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE || "Size of region that for global variable of cache as ram stage" || 0 || always || "0x%x"
+
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
 +
Action must be taken immediately.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_AP_CODE_IN_CAR || || || ||  
+
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
 +
System is unusable.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_MEM_TRAIN_SEQ || || ||  ||  
+
| MAXIMUM_CONSOLE_LOGLEVEL || console || int ||  ||
 +
Map the log level config names to an integer.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_WAIT_BEFORE_CPUS_INIT || || || ||  
+
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
 +
Way too many details.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_XIP_ROM_BASE || "Start address of area to cache during coreboot execution directly from ROM" || 0 || used || "0x%x"
+
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
 +
Debug-level messages.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_XIP_ROM_SIZE || "Size of area to cache during coreboot execution directly from ROM" || 0 || used || "0x%x"
+
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
 +
Informational messages.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_COMPRESS || "Set for compressed image" || 1 || always ||  
+
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
 +
Normal but significant conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_UNCOMPRESSED || "Set for uncompressed image" || {!CONFIG_COMPRESS} || always || "%d"
+
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
 +
Warning conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_LB_MEM_TOPK || "Kilobytes of memory to initialized before executing code from RAM" || 2048 || always || "%d"
+
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
 +
Error conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_HAVE_OPTION_TABLE || "Export CMOS option table" || 0 || always ||  
+
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
 +
Critical conditions.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_USE_OPTION_TABLE || "Use option table" || {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE} || always || "%d"
+
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
 +
Action must be taken immediately.
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_LB_CKS_RANGE_START || "First CMOS byte to use for coreboot options" || 49 || always || "%d"
+
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
 +
System is unusable.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_LB_CKS_RANGE_END || "Last CMOS byte to use for coreboot options" || 125 || always || "%d"
+
| DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
 +
Map the log level config names to an integer.
 +
 
 +
||
 +
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_LB_CKS_LOC || "Pair of bytes to use for CMOS checksum" || 126 || always || "%d"
+
| HAVE_OPTION_TABLE || toplevel || bool || ||
 +
This variable specifies whether a given board has a cmos.layout
 +
file containing NVRAM/CMOS bit definitions.
 +
It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CRT0 || "Main initialization target" || "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb" || always ||  
+
| VGA || toplevel || bool || ||
 +
Build board-specific VGA code.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_DEBUG || "Enable x86emu debugging code" || 0 || always ||  
+
| GFXUMA || toplevel || bool || ||
 +
Enable Unified Memory Architecture for graphics.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_VGA || "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)" || 0 || always ||  
+
| HAVE_LOW_TABLES || toplevel || bool || ||
 +
This Option is unused in the code.  Since two boards try to set it to
 +
'n', they may be broken.  We either need to make the option useful or
 +
get rid of it.  The broken boards are:
 +
asus/m2v-mx_se
 +
supermicro/h8dme
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_VGA_MULTI || || ||  ||  
+
| HAVE_HIGH_TABLES || toplevel || bool ||  ||
 +
This variable specifies whether a given northbridge has high table
 +
support.
 +
It is set in northbridge/*/Kconfig.
 +
Whether or not the high tables are actually written by coreboot is
 +
configurable by the user via WRITE_HIGH_TABLES.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST || || ||  ||  
+
| HAVE_ACPI_TABLES || toplevel || bool ||  ||
 +
This variable specifies whether a given board has ACPI table support.
 +
It is usually set in mainboard/*/Kconfig.
 +
Whether or not the ACPI tables are actually generated by coreboot
 +
is configurable by the user via GENERATE_ACPI_TABLES.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_BTEXT || || ||  ||  
+
| HAVE_MP_TABLE || toplevel || bool ||  ||
 +
This variable specifies whether a given board has MP table support.
 +
It is usually set in mainboard/*/Kconfig.
 +
Whether or not the MP table is actually generated by coreboot
 +
is configurable by the user via GENERATE_MP_TABLE.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_LOGBUF || "Log messages to buffer" || 0 || always ||  
+
| HAVE_PIRQ_TABLE || toplevel || bool ||  ||
 +
This variable specifies whether a given board has PIRQ table support.
 +
It is usually set in mainboard/*/Kconfig.
 +
Whether or not the PIRQ table is actually generated by coreboot
 +
is configurable by the user via GENERATE_PIRQ_TABLE.
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: System tables || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_SROM || "Log messages to SROM console" || 0 || always ||  
+
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
 +
Generate ACPI tables for this board.
 +
 
 +
If unsure, say Y.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_CONSOLE_SERIAL8250 || "Log messages to 8250 uart based serial console" || 0 || always ||  
+
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
 +
Generate an MP table (conforming to the Intel MultiProcessor
 +
specification 1.4) for this board.
 +
 
 +
If unsure, say Y.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_USBDEBUG_DIRECT || "Log messages to ehci debug port console" || 0 || always ||  
+
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
 +
Generate a PIRQ table for this board.
 +
 
 +
If unsure, say Y.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Payload || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_DEFAULT_CONSOLE_LOGLEVEL || "Console will log at this level unless changed" || 7 || always ||  
+
| PAYLOAD_NONE || toplevel || bool || None ||
 +
Select this option if you want to create an "empty" coreboot
 +
ROM image for a certain mainboard, i.e. a coreboot ROM image
 +
which does not yet contain a payload.
 +
 
 +
For such an image to be useful, you have to use 'cbfstool'
 +
to add a payload to the ROM image later.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_MAXIMUM_CONSOLE_LOGLEVEL || || 8 || always ||  
+
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
 +
Select this option if you have a payload image (an ELF file)
 +
which coreboot should run as soon as the basic hardware
 +
initialization is completed.
 +
 
 +
You will be able to specify the location and file name of the
 +
payload image later.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_SERIAL_POST || "Enable SERIAL POST codes" || 0 || always ||  
+
| FALLBACK_PAYLOAD_FILE || toplevel || string || Payload path and filename ||
 +
The path and filename of the ELF executable file to use as payload.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_NO_POST || "Disable POST codes" || none || used ||  
+
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
 +
In order to reduce the size payloads take up in the ROM chip
 +
coreboot can compress them using the LZMA algorithm.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: VGA BIOS || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_TTYS0_BASE || "Base address for 8250 uart for the serial console" || 0x3f8 || always || "0x%x"
+
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
 +
Select this option if you have a VGA BIOS image that you would
 +
like to add to your ROM.
 +
 
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_TTYS0_BAUD || "Default baud rate for serial console" || 115200 || always ||  
+
| FALLBACK_VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_TTYS0_DIV || "Allow UART divisor to be set explicitly" || none || used || "%d"
+
| FALLBACK_VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||  
 +
The comma-separated PCI vendor and device ID that would associate
 +
your VGA BIOS to your video card.
 +
 
 +
Example: 1106,3230
 +
 
 +
In the above example 1106 is the PCI vendor ID (in hex, but without
 +
the "0x" prefix) and 3230 specifies the PCI device ID of the
 +
video card (also in hex, without "0x" prefix).
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Debugging || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONFIG_TTYS0_LCS || "Default flow control settings for the 8250 serial console uart" || 0x3 || always || "0x%x"
+
| GDB_STUB || toplevel || bool || GDB debugging support ||  
|- bgcolor="#eeeeee"
+
If enabled, you will be able to set breakpoints for gdb debugging.
| CONFIG_USE_PRINTK_IN_CAR || "use printk instead of print in CAR stage code" || 0 || always ||
+
See src/arch/i386/lib/c_start.S for details.
|- bgcolor="#eeeeee"
+
 
| CONFIG_ASSEMBLER_DEBUG || "Create disassembly files for debugging" || 0 || always ||
+
||
|- bgcolor="#eeeeee"
+
| CONFIG_MAINBOARD || "Mainboard name" || "Mainboard_not_set" || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAINBOARD_PART_NUMBER || "Part number of mainboard" || "Part_number_not_set" || always || "\"%s\""
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAINBOARD_VENDOR || "Vendor of mainboard" || "Vendor_not_set" || always || "\"%s\""
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID || "PCI Vendor ID of mainboard manufacturer" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID || "PCI susbsystem device id assigned my mainboard manufacturer" || 0 || always || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL || "Default power on after power fail setting" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SYS_CLK_FREQ || "System clock frequency in MHz" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAX_PCI_BUSES || "Maximum number of PCI buses to search for devices" || 255 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SMP || "Define if we support SMP" || 0 || always ||  
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAX_CPUS ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAX_PHYSICAL_CPUS ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_LOGICAL_CPUS || "Should multiple cpus per die be enabled?" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AP_IN_SIPI_WAIT || "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_MP_TABLE || "Define to build an MP table" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SERIAL_CPU_INIT ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_APIC_ID_OFFSET || "We need to share this value between cache_as_ram_auto.c and northbridge.c" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_ENABLE_APIC_EXT_ID || "Enable APIC ext id mode 8 bit" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_LIFT_BSP_APIC_ID || "decide if we lift bsp apic id while ap apic id" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MULTIBOOT || "Use Multiboot (rather than ELF boot notes) to boot the payload" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IDE_PAYLOAD || "Boot from IDE device" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_ROM_PAYLOAD || "Boot image is located in ROM"  || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_ROM_PAYLOAD_START || "ROM stream start location" || {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1} || always || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_COMPRESSED_PAYLOAD_NRV2B || "NRV2B compressed boot image is located in ROM"  || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_COMPRESSED_PAYLOAD_LZMA || "LZMA compressed boot image is located in ROM"  || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PRECOMPRESSED_PAYLOAD || "boot image is already compressed"  || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SERIAL_PAYLOAD || "Download boot image from serial port" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_FS_PAYLOAD || "Boot from a filesystem" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_FS_EXT2 || "Enable ext2 filesystem support" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_FS_ISO9660 || "Enable ISO9660 filesystem support" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_FS_FAT || "Enable FAT filesystem support" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_CBFS || "The new CBFS file system" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AUTOBOOT_DELAY || "Delay (in seconds) before autobooting" || 2 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AUTOBOOT_CMDLINE || "Default command line when autobooting" || "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200" || always || "\"%s\""
+
|- bgcolor="#eeeeee"
+
| CONFIG_USE_WATCHDOG_ON_BOOT || "Use the watchdog on booting" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT || "Enable support for plugin Hypertransport busses" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AGP_PLUGIN_SUPPORT || "Enable support for plugin AGP busses" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_CARDBUS_PLUGIN_SUPPORT || "Enable support cardbus plugin cards" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCIX_PLUGIN_SUPPORT || "Enable support for plugin PCI-X busses" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCIEXP_PLUGIN_SUPPORT || "Enable support for plugin PCI-E busses" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_PIRQ_TABLE || "Define if we have a PIRQ table" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PIRQ_ROUTE || "Define if we have a PIRQ table and want routing IRQs" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IRQ_SLOT_COUNT || "Number of IRQ slots" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCIBIOS_IRQ || "PCIBIOS IRQ support" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IOAPIC || "IOAPIC support" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IDE || "Define to include IDE support" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IDE_BOOT_DRIVE || "Disk number of boot drive" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IDE_SWAB || "Swap bytes when reading from IDE device" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_IDE_OFFSET || "Sector at which to start searching for boot image" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCI_IO_CFG_EXT || "allow 4K register space via io CFG port" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCIC0_CFGADDR || "Address of PCI Configuration Address Register" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCIC0_CFGDATA || "Address of PCI Configuration Data Register" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_ISA_IO_BASE || "Base address of PCI/ISA I/O address range" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_ISA_MEM_BASE || "Base address of PCI/ISA memory address range" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_PNP_CFGADDR || "PNP Configuration Address Register offset" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_PNP_CFGDATA || "PNP Configuration Data Register offset" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_IO_BASE || "Base address of memory mapped I/O operations" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_EMBEDDED_RAM_SIZE || "Embedded boards generally have fixed RAM size" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_GDB_STUB || "Compile in gdb stub support?" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_INIT_TIMER || "Have a init_timer function" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_HARD_RESET || "Have hard reset" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_SMI_HANDLER || "Set, if the board needs an SMI handler" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MEMORY_HOLE || "Set to deal with memory hole" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MAX_REBOOT_CNT || "Set maximum reboots" || 3 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_FANCTL || "Include board specific FAN control initialization" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 || "Use timer2 to callibrate the x86 time stamp counter" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_INTEL_PPRO_MTRR || "" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_UDELAY_TSC || "Implement udelay with the x86 time stamp counter" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_UDELAY_IO || "Implement udelay with x86 io registers" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_FAKE_SPDROM || "Use this to fake spd rom values" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_ACPI_TABLES || "Define to build ACPI tables" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_ACPI_RESUME || "Define to build ACPI with resume support" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_ACPI_SSDTX_NUM || "extra ssdt num for PCI Device" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AGP_APERTURE_SIZE || "AGP graphics virtual memory aperture size" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_HT_CHAIN_UNITID_BASE || "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HT_CHAIN_END_UNITID_BASE ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SB_HT_CHAIN_ON_BUS0 ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCI_BUS_SEGN_BITS ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MMCONF_SUPPORT || "enable mmconfig for pci conf" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MMCONF_SUPPORT_DEFAULT || "enable mmconfig for pci conf" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_MMCONF_BASE_ADDRESS || "enable mmconfig base address" || none || used || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_HW_MEM_HOLE_SIZEK ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_VAR_MTRR_HOLE || "using hole in MTRR instead of increasing method" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_K8_HT_FREQ_1G_SUPPORT || "Optern E0 later could support 1G HT, but still depends MB design" || 0  || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_K8_REV_F_SUPPORT ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_CBB || "Opteron cpu bus num base" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_CDB || "Opteron cpu device num base" || 0x18 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HT3_SUPPORT || "Hypertransport 3 support, include ac HT and unganged sublink feature" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_EXT_RT_TBL_SUPPORT || "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_EXT_CONF_SUPPORT || "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_DIMM_SUPPORT ||  ||  ||  || "0x%x"
+
|- bgcolor="#eeeeee"
+
| CONFIG_CPU_SOCKET_TYPE || "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3" || 0x10 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_CPU_ADDR_BITS || "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48" || 36 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_VGA || "Include VGA initialisation code" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_VGA_ROM_RUN || "Init x86 ROMs on VGA-class PCI devices" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCI_ROM_RUN || "Init x86 ROMs on all PCI devices" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCI_OPTION_ROM_RUN_YABEL || "Use Yabel instead of old bios emulator" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_YABEL_DEBUG_FLAGS || "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES || "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs." || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCI_OPTION_ROM_RUN_REALMODE || "Use Yabel instead of old bios emulator" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCI_64BIT_PREF_MEM ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AMDMCT || "use AMD MCT to init RAM instead of native code" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_AMD_UCODE_PATCH_FILE || "name of the microcode patch file" || none || used || "\"%s\""
+
|- bgcolor="#eeeeee"
+
| CONFIG_K8_MEM_BANK_B_ONLY || "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert." || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_VIDEO_MB ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_GFXUMA ||  ||  ||  ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_MAINBOARD_RESOURCES || "Enable if the mainboard/chipset requires extra entries in the memory map" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_LOW_TABLES || "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte" || 1 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_HAVE_HIGH_TABLES || "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SPLASH_GRAPHIC || "Paint a splash screen" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_GX1_VIDEO || "Build in GX1's graphic support" || 0 || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_GX1_VIDEOMODE || "Define video mode after reset" || none || used ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_PCIE_CONFIGSPACE_HOLE || "Leave a hole for PCIe config space in the device allocator" || 0 || always ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SANDPOINT_ALTIMUS || "Configure Sandpoint with Altimus PMC" || 0 || never ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SANDPOINT_TALUS || "Configure Sandpoint with Talus PMC" || 0 || never ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SANDPOINT_UNITY || "Configure Sandpoint with Unity PMC" || 0 || never ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SANDPOINT_VALIS || "Configure Sandpoint with Valis PMC" || 0 || never ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_SANDPOINT_GYRUS || "Configure Sandpoint with Gyrus PMC" || 0 || never ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_BRIQ_750FX || "Configure briQ with PowerPC 750FX" || 0 || never ||
+
|- bgcolor="#eeeeee"
+
| CONFIG_BRIQ_7400 || "Configure briQ with PowerPC G4" || 0 || never ||  
+
  
 
|}
 
|}

Revision as of 14:06, 9 February 2010

This is an automatically generated list of coreboot compile-time options.

Last update: 2010/02/09 15:05:25. (r5100)

Option Source Format Short Description Description
Menu: General setup
EXPERT toplevel bool Expert mode

This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are doing! You have been warned!

LOCALVERSION toplevel string Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.

Menu: Mainboard
BOARD_ROMSIZE_KB_4096 mainboard bool ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file of the matching size.

COREBOOT_ROMSIZE_KB_128 mainboard bool 128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256 mainboard bool 256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512 mainboard bool 512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024 mainboard bool 1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048 mainboard bool 2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096 mainboard bool 4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

Menu: Chipset
(comment) CPU
SMP cpu bool

This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.

VAR_MTRR_HOLE cpu bool

Unset this if you don't want the MTRR code to use subtractive MTRRs

(comment) Northbridge
(comment) Southbridge
Menu: AMD Geode GX1 video support
(comment) Super I/O
(comment) Devices
VGA_BRIDGE_SETUP devices bool Setup bridges on path to VGA adapter

Allow bridges to set up legacy decoding ranges for VGA. Don't disable this unless you're sure you don't want the briges setup for VGA.

VGA_ROM_RUN devices bool Run VGA option ROMs

Execute VGA option ROMs, if found. This is required to enable PCI/AGP/PCI-E video cards.

PCI_ROM_RUN devices bool Run non-VGA option ROMs

Execute non-VGA PCI option ROMs, if found.

Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs).

PCI_OPTION_ROM_RUN_REALMODE devices bool Real mode

If you select this option, PCI option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)

PCI_OPTION_ROM_RUN_X86EMU devices bool x86emu

If you select this option, the x86emu CPU emulator will be used to execute PCI option ROMs. When choosing this option, x86emu will pass through all hardware accesses to memory and IO devices to the underlying memory and IO addresses. While this option prevents option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Choosing x86emu, option ROM execution is slower than native execution in real mode, but faster than the full system emulation YABEL This is the default choice for non-x86 systems.

PCI_OPTION_ROM_RUN_YABEL devices bool YABEL

If you select this option, the YABEL system emulator will be used to execute PCI option ROMs. YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one). This option best prevents option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the other option ROM initialization methods.

YABEL_DEBUG_FLAGS devices hex Hex value for YABEL debug flags

See debug.h for values 0 is no debug output, 0x31ff is _verbose_.

Menu: Console options
CONSOLE_SERIAL8250 console bool Serial port console output

Send coreboot debug output to a serial port console.

CONSOLE_SERIAL_COM1 console bool COM1/ttyS0, I/O port 0x3f8

Serial console on COM1/ttyS0 at I/O port 0x3f8.

CONSOLE_SERIAL_COM2 console bool COM2/ttyS1, I/O port 0x2f8

Serial console on COM2/ttyS1 at I/O port 0x2f8.

CONSOLE_SERIAL_COM3 console bool COM3/ttyS2, I/O port 0x3e8

Serial console on COM3/ttyS2 at I/O port 0x3e8.

CONSOLE_SERIAL_COM4 console bool COM4/ttyS3, I/O port 0x2e8

Serial console on COM4/ttyS3 at I/O port 0x2e8.

TTYS0_BASE console hex

Map the COM port names to the respective I/O port.

CONSOLE_SERIAL_115200 console bool 115200

Set serial port Baud rate to 115200.

CONSOLE_SERIAL_57600 console bool 57600

Set serial port Baud rate to 57600.

CONSOLE_SERIAL_38400 console bool 38400

Set serial port Baud rate to 38400.

CONSOLE_SERIAL_19200 console bool 19200

Set serial port Baud rate to 19200.

CONSOLE_SERIAL_9600 console bool 9600

Set serial port Baud rate to 9600.

TTYS0_BAUD console int

Map the Baud rates to an integer.

SERIAL_POST console bool Show POST codes on the serial port console

If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the serial console.

USBDEBUG_DIRECT console bool USB 2.0 EHCI debug dongle support

This option allows you to use a so-called USB EHCI Debug device to retrieve the coreboot debug messages (instead, or in addition to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI Debug Port capability. Controllers which are known to work:

  • 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
  • 8086:24cd Intel ICH4/ICH4-M
  • 8086:24dd Intel ICH5
  • 8086:265c Intel ICH6
  • 8086:268c Intel 631xESB/632xESB/3100
  • 8086:27cc Intel ICH7
  • 8086:2836 Intel ICH8
  • 8086:283a Intel ICH8
  • 8086:293a Intel ICH9
  • 10de:0088 NVIDIA MCP2A
  • 10de:005b NVIDIA CK804
  • 10de:026e NVIDIA MCP51
  • 10de:036d NVIDIA MCP55
  • 10de:03f2 NVIDIA MCP61
  • 1002:4386 ATI/AMD SB600
  • 1106:3104 VIA VX800

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.

CONSOLE_VGA_ONBOARD_AT_FIRST console bool Use onboard VGA as primary video device

If not selected, the last adapter found will be used.

MAXIMUM_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

MAXIMUM_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

MAXIMUM_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

MAXIMUM_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

MAXIMUM_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

MAXIMUM_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

MAXIMUM_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

MAXIMUM_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

MAXIMUM_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

MAXIMUM_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

DEFAULT_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

DEFAULT_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

DEFAULT_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

DEFAULT_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

DEFAULT_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

DEFAULT_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

DEFAULT_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

DEFAULT_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

DEFAULT_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

DEFAULT_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

HAVE_OPTION_TABLE toplevel bool

This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.

VGA toplevel bool

Build board-specific VGA code.

GFXUMA toplevel bool

Enable Unified Memory Architecture for graphics.

HAVE_LOW_TABLES toplevel bool

This Option is unused in the code. Since two boards try to set it to 'n', they may be broken. We either need to make the option useful or get rid of it. The broken boards are: asus/m2v-mx_se supermicro/h8dme

HAVE_HIGH_TABLES toplevel bool

This variable specifies whether a given northbridge has high table support. It is set in northbridge/*/Kconfig. Whether or not the high tables are actually written by coreboot is configurable by the user via WRITE_HIGH_TABLES.

HAVE_ACPI_TABLES toplevel bool

This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. Whether or not the ACPI tables are actually generated by coreboot is configurable by the user via GENERATE_ACPI_TABLES.

HAVE_MP_TABLE toplevel bool

This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.

HAVE_PIRQ_TABLE toplevel bool

This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.

Menu: System tables
GENERATE_ACPI_TABLES toplevel bool Generate ACPI tables

Generate ACPI tables for this board.

If unsure, say Y.

GENERATE_MP_TABLE toplevel bool Generate an MP table

Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board.

If unsure, say Y.

GENERATE_PIRQ_TABLE toplevel bool Generate a PIRQ table

Generate a PIRQ table for this board.

If unsure, say Y.

Menu: Payload
PAYLOAD_NONE toplevel bool None

Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.

PAYLOAD_ELF toplevel bool An ELF executable payload

Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

FALLBACK_PAYLOAD_FILE toplevel string Payload path and filename

The path and filename of the ELF executable file to use as payload.

COMPRESSED_PAYLOAD_LZMA toplevel bool Use LZMA compression for payloads

In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.

Menu: VGA BIOS
VGA_BIOS toplevel bool Add a VGA BIOS image

Select this option if you have a VGA BIOS image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

FALLBACK_VGA_BIOS_FILE toplevel string VGA BIOS path and filename

The path and filename of the file to use as VGA BIOS.

FALLBACK_VGA_BIOS_ID toplevel string VGA device PCI IDs

The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix).

Menu: Debugging
GDB_STUB toplevel bool GDB debugging support

If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/i386/lib/c_start.S for details.