Difference between revisions of "Coreboot Options"

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This is an automatically generated list of '''coreboot compile-time options'''.
 
This is an automatically generated list of '''coreboot compile-time options'''.
  
Last update: 2011/10/14 00:44:39. (runknown)
+
Last update: 2015/05/05 16:17:26. (r4.0-9599-g40c26df-dirty)
 
{| border="0" style="font-size: smaller"
 
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
Line 36: Line 36:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler ||  
+
| COMMON_CBFS_SPI_WRAPPER || toplevel || bool ||  ||
 +
Use common wrapper to interface CBFS to SPI bootrom.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MULTIPLE_CBFS_INSTANCES || toplevel || bool || Multiple CBFS instances in the bootrom ||
 +
Account for the firmware image containing more than one CBFS
 +
instance. Locations of instances are known at build time and are
 +
communicated between coreboot stages to make sure the next stage is
 +
loaded from the appropriate instance.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MULTIPLE_CBFS_INSTANCES || toplevel || bool || Compiler to use ||  
 
This option allows you to select the compiler used for building
 
This option allows you to select the compiler used for building
 
coreboot.
 
coreboot.
Line 42: Line 55:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||  
+
| COMPILER_GCC || toplevel || bool || GCC ||  
Changes the build process to scan-build is used.
+
Use the GNU Compiler Collection (GCC) to build coreboot.
Requires scan-build in path.
+
 
 +
For details see http://gcc.gnu.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||  
+
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang ||  
Where the scan-build report should be stored
+
Use LLVM/clang to build coreboot.
 +
 
 +
For details see http://clang.llvm.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || ccache ||  
+
| ANY_TOOLCHAIN || toplevel || bool || Allow building with any toolchain ||
 +
Many toolchains break when building coreboot since it uses quite
 +
unusual linker features. Unless developers explicitely request it,
 +
we'll have to assume that they use their distro compiler by mistake.
 +
Make sure that using patched compilers is a conscious decision.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||  
 
Enables the use of ccache for faster builds.
 
Enables the use of ccache for faster builds.
Requires ccache in path.
+
 
 +
Requires the ccache utility in your system $PATH.
 +
 
 +
For details see https://ccache.samba.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||  
 
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||  
Enable this option if you are working on the sconfig
+
Enable this option if you are working on the sconfig device tree
device tree parser and made changes to sconfig.l and
+
parser and made changes to sconfig.l and sconfig.y.
sconfig.y.
+
 
 
Otherwise, say N.
 
Otherwise, say N.
  
Line 69: Line 96:
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||  
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||  
 
Enable this option if coreboot shall read options from the "CMOS"
 
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.
+
NVRAM instead of using hard-coded values.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STATIC_OPTION_TABLE || toplevel || bool || Load default configuration values into CMOS on each boot ||
 +
Enable this option to reset "CMOS" NVRAM values to default on
 +
every boot.  Use this if you want the NVRAM configuration to
 +
never be modified from its default values.
  
 
||
 
||
Line 76: Line 110:
 
Compress ramstage to save memory in the flash image. Note
 
Compress ramstage to save memory in the flash image. Note
 
that decompression might slow down booting if the boot flash
 
that decompression might slow down booting if the boot flash
is connected through a slow Link (i.e. SPI)
+
is connected through a slow link (i.e. SPI).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||  
+
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||  
Include in CBFS the coreboot config file that was used to compile the ROM image
+
Include the .config file that was used to compile coreboot
 +
in the (CBFS) ROM image. This is useful if you want to know which
 +
options were used to build a specific coreboot.rom image.
 +
 
 +
Saying Y here will increase the image size by 2-3KB.
 +
 
 +
You can use the following command to easily list the options:
 +
 
 +
grep -a CONFIG_ coreboot.rom
 +
 
 +
Alternatively, you can also use cbfstool to print the image
 +
contents (including the raw 'config' item we're looking for).
 +
 
 +
Example:
 +
 
 +
$ cbfstool coreboot.rom print
 +
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
 +
offset 0x0
 +
Alignment: 64 bytes
 +
 
 +
Name                          Offset    Type        Size
 +
cmos_layout.bin                0x0        cmos layout  1159
 +
fallback/romstage              0x4c0      stage        339756
 +
fallback/ramstage              0x53440    stage        186664
 +
fallback/payload              0x80dc0    payload      51526
 +
config                        0x8d740    raw          3324
 +
(empty)                        0x8e480    null        3610440
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
 +
Make coreboot create a table of timer-ID/timer-value pairs to
 +
allow measuring time spent at different phases of the boot process.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
 +
This draws in the blobs repository, which contains binary files that
 +
might be required for some chipsets or boards.
 +
This flag ensures that a "Free" option remains available for users.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COVERAGE || toplevel || bool || Code coverage support ||
 +
Add code coverage support for coreboot. This will store code
 +
coverage information in CBMEM for extraction from user space.
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RELOCATABLE_MODULES || toplevel || bool || Relocatable Modules ||
 +
If RELOCATABLE_MODULES is selected then support is enabled for
 +
building relocatable modules in the RAM stage. Those modules can be
 +
loaded anywhere and all the relocations are handled automatically.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RELOCATABLE_RAMSTAGE || toplevel || bool || Build the ramstage to be relocatable in 32-bit address space. ||
 +
The reloctable ramstage support allows for the ramstage to be built
 +
as a relocatable module. The stage loader can identify a place
 +
out of the OS way so that copying memory is unnecessary during an S3
 +
wake. When selecting this option the romstage is responsible for
 +
determing a stack location to use for loading the ramstage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM || toplevel || bool || Cache the relocated ramstage outside of cbmem. ||
 +
The relocated ramstage is saved in an area specified by the
 +
by the board and/or chipset.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_MAX_REBOOT_CNT_CLEAR || toplevel || bool || Do not clear reboot count after successful boot ||
 +
Do not clear the reboot count immediately after successful boot.
 +
Set to allow the payload to control normal/fallback image recovery.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UPDATE_IMAGE || toplevel || bool || Update existing coreboot.rom image ||
 +
If this option is enabled, no new coreboot.rom file
 +
is created. Instead it is expected that there already
 +
is a suitable file for further processing.
 +
The bootblock will not be modified.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GENERIC_GPIO_LIB || toplevel || bool ||  ||
 +
If enabled, compile the generic GPIO library. A "generic" GPIO
 +
implies configurability usually found on SoCs, particularly the
 +
ability to control internal pull resistors.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ID_AUTO || toplevel || bool ||  ||
 +
Mainboards that can read a board ID from the hardware straps
 +
(ie. GPIO) select this configuration option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ID_MANUAL || toplevel || bool || Add board ID file to CBFS ||
 +
If you want to maintain a board ID, but the hardware does not
 +
have straps to automatically determine the ID, you can say Y
 +
here and add a file named 'board_id' to CBFS. If you don't know
 +
what this is about, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ID_STRING || toplevel || string || Board ID ||
 +
This string is placed in the 'board_id' CBFS file for indicating
 +
board type.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAM_CODE_SUPPORT || toplevel || bool || Discover RAM configuration code and store it in coreboot table ||
 +
If enabled, coreboot discovers RAM configuration (value obtained by
 +
reading board straps) and stores it in coreboot table.
  
 
||
 
||
Line 88: Line 237:
 
! align="left" | Menu: Mainboard || || || ||
 
! align="left" | Menu: Mainboard || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||  
+
| || || (comment) || || see under vendor LiPPERT ||
The following X60 series ThinkPad machines have been verified to
+
|- bgcolor="#eeeeee"
work correctly:
+
| BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V ||
 +
Set DRR3 memory voltage to 1.35V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V ||  
 +
Set DRR3 memory voltage to 1.50V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V ||
 +
Set DRR3 memory voltage to 1.65V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135 || mainboard/asus/f2a85-m_le || bool || 1.35V ||
 +
Set DRR3 memory voltage to 1.35V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150 || mainboard/asus/f2a85-m_le || bool || 1.50V ||
 +
Set DRR3 memory voltage to 1.50V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165 || mainboard/asus/f2a85-m_le || bool || 1.65V ||
 +
Set DRR3 memory voltage to 1.65V
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: On-Chip Device Power Down Control || || || ||
  
ThinkPad X60s (Model 1702, 1703)
+
|- bgcolor="#6699dd"
ThinkPad X60  (Model 1709)
+
! align="left" | Menu: Watchdog Timer setting || || || ||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: IDE controller setting || || || ||
 +
|- bgcolor="#eeeeee"
 +
| IDE_STANDARD_COMPATIBLE || mainboard/dmp/vortex86ex || bool || Standard IDE Compatible ||
 +
Built-in IDE controller PCI vendor/device ID is 17F3:1012, which
 +
is not recognized by some OSes.
 +
 
 +
This option can change IDE controller PCI vendor/device ID to
 +
other value for software compatibility.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||  
+
| IDE_COMPATIBLE_SELECTION || mainboard/dmp/vortex86ex || hex || IDE Compatible Selection ||  
The following T60 series ThinkPad machines have been verified to
+
IDE controller PCI vendor/device ID value setting.
work correctly:
+
  
Thinkpad T60p (Model 2007)
+
Higher 16-bit is vendor ID, lower 16-bit is device ID.
  
 
||
 
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: GPIO setting || || || ||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: UART setting || || || ||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: LPT setting || || || ||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||  
+
| UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int || ||  
Look on the bottom side for a number like 406-0001-30.  The last 2
+
The Mohon Peak board uses COM2 (2f8) for the serial console.
digits state the PCB revision (3.0 in this example).  For 2.0 or older
+
boards choose Y, for 3.0 and newer say N.
+
  
Old revision boards need a jumper shorting the power button to
+
||
power on automatically. You may enable the button only after this
+
|- bgcolor="#eeeeee"
jumper has been removedNew revision boards are not restricted
+
| SEABIOS_MALLOC_UPPERMEMORY || mainboard/intel/mohonpeak || bool || ||
in this way, and always have the power button enabled.
+
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segmentThis means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||  
+
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_blaze || string || BCT boot media ||  
If selected, both on-board serial ports will operate in RS485 mode
+
Which boot media to configure the BCT for.
instead of RS232.
+
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BLAZE_BCT_CFG_SPI || mainboard/google/nyan_blaze || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BLAZE_BCT_CFG_EMMC || mainboard/google/nyan_blaze || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/nyan_blaze || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan_blaze || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/rush_ryu || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_RYU_BCT_CFG_SPI || mainboard/google/rush_ryu || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_RYU_BCT_CFG_EMMC || mainboard/google/rush_ryu || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/rush_ryu || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/rush_ryu || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan_big || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRAM_SIZE_MB || mainboard/google/rush || int || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_BCT_CFG_SPI || mainboard/google/rush || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_BCT_CFG_EMMC || mainboard/google/rush || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/rush || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/rush || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port ||
 +
The PCI Express slot at J120 can be configured as an additional
 +
DisplayPort connector using an adapter card from AMD or as a normal
 +
PCI Express (x4) slot.
 +
 +
By default, the connector is configured as a PCI Express (x4) slot.
 +
 +
Select this option to enable the slot for use with one of AMD's
 +
passive graphics port expander cards (only available from AMD).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || was acquired by ADLINK ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||  
 
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||  
Line 135: Line 460:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||  
+
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
 +
Look on the bottom side for a number like 406-0001-30.  The last 2
 +
digits state the PCB revision (3.0 in this example).  For 2.0 or older
 +
boards choose Y, for 3.0 and newer say N.
 +
 
 +
Old revision boards need a jumper shorting the power button to
 +
power on automatically.  You may enable the button only after this
 +
jumper has been removed.  New revision boards are not restricted
 +
in this way, and always have the power button enabled.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||  
 
If selected, both on-board serial ports will operate in RS485 mode
 
If selected, both on-board serial ports will operate in RS485 mode
 
instead of RS232.
 
instead of RS232.
Line 152: Line 489:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8qgi || hex || ||  
+
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||  
though UARTs are on the NUVOTON BMC, port 0x164E
+
If selected, both on-board serial ports will operate in RS485 mode
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+
instead of RS232.
  
 
||
 
||
Line 163: Line 500:
 
The build system will take care of creating a coreboot.rom file
 
The build system will take care of creating a coreboot.rom file
 
of the matching size.
 
of the matching size.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||
 +
Choose this option if you have a 64 KB ROM chip.
  
 
||
 
||
Line 198: Line 540:
 
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
 
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
 
Choose this option if you have a 8192 KB (8 MB) ROM chip.
 
Choose this option if you have a 8192 KB (8 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) ||
 +
Choose this option if you have a 12288 KB (12 MB) ROM chip.
  
 
||
 
||
Line 218: Line 565:
 
||
 
||
  
 +
|- bgcolor="#eeeeee"
 +
| LATE_CBMEM_INIT || arch/x86 || bool ||  ||
 +
Enable this in chipset's Kconfig if northbridge does not implement
 +
early get_top_of_ram() call for romstage. CBMEM tables will be
 +
allocated late in ramstage, after PCI devices resources are known.
 +
 +
||
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: Architecture (x86) || || || ||
+
! align="left" | Menu: ChromeOS || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||  
+
| CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS ||
If this option is enabled, no new coreboot.rom file
+
Enable ChromeOS specific features like the GPIO sub table in
is created. Instead it is expected that there already
+
the coreboot table. NOTE: Enabling this option on an unsupported
is a suitable file for further processing.
+
board will most likely break your build.
The bootblock will not be modified.
+
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBNV_OFFSET || vendorcode/google/chromeos || hex ||  ||
 +
CMOS offset for VbNv data. This value must match cmos.layout
 +
in the mainboard directory, minus 14 bytes for the RTC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBNV_SIZE || vendorcode/google/chromeos || hex ||  ||
 +
CMOS storage size for VbNv data. This value must match cmos.layout
 +
in the mainboard directory.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_CMOS || vendorcode/google/chromeos || bool || Vboot non-volatile storage in CMOS. ||
 +
VBNV is stored in CMOS
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_EC || vendorcode/google/chromeos || bool || Vboot non-volatile storage in EC. ||
 +
VBNV is stored in EC
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_FLASH || vendorcode/google/chromeos || bool ||  ||
 +
VBNV is stored in flash storage
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FLASHMAP_OFFSET || vendorcode/google/chromeos || hex || Flash Map Offset ||
 +
Offset of flash map in firmware image
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_SOFTWARE_SYNC || vendorcode/google/chromeos || bool || Enable EC software sync ||
 +
EC software sync is a mechanism where the AP helps the EC verify its
 +
firmware similar to how vboot verifies the main system firmware. This
 +
option selects whether depthcharge should support EC software sync.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_EC_SLOW_UPDATE || vendorcode/google/chromeos || bool || EC is slow to update ||
 +
Whether the EC (or PD) is slow to update and needs to display a
 +
screen that informs the user the update is happening.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_OPROM_MATTERS || vendorcode/google/chromeos || bool || Video option ROM matters ||
 +
Whether the video option ROM has run matters on this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_DEV_SWITCH || vendorcode/google/chromeos || bool || Virtual developer switch support ||
 +
Whether this platform has a virtual developer switch.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_VERIFY_FIRMWARE || vendorcode/google/chromeos || bool || Verify firmware with vboot. ||
 +
Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components
 +
of the firmware (stages, payload, etc).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_TPM_RESUME || vendorcode/google/chromeos || bool ||  ||
 +
On some boards the TPM stays powered up in S3. On those
 +
boards, booting Windows will break if the TPM resume command
 +
is sent during an S3 resume.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PHYSICAL_REC_SWITCH || vendorcode/google/chromeos || bool || Physical recovery switch is present ||
 +
Whether this platform has a physical recovery switch
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| WIPEOUT_SUPPORTED || vendorcode/google/chromeos || bool || User is able to request factory reset ||
 +
When this option is enabled, the firmware provides the ability to
 +
signal the application the need for factory reset (a.k.a. wipe
 +
out) of the device
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_STARTS_IN_BOOTBLOCK || vendorcode/google/chromeos/vboot2 || bool ||  ||
 +
Firmware verification happens during or at the end of bootblock.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_STARTS_IN_ROMSTAGE || vendorcode/google/chromeos/vboot2 || bool ||  ||
 +
Firmware verification happens during or at the end of romstage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT2_MOCK_SECDATA || vendorcode/google/chromeos/vboot2 || bool || Mock secdata for firmware verification ||
 +
Enabling VBOOT2_MOCK_SECDATA will mock secdata for the firmware
 +
verification to avoid access to a secdata storage (typically TPM).
 +
All operations for a secdata storage will be successful. This option
 +
can be used during development when a TPM is not present or broken.
 +
THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_DISABLE_DEV_ON_RECOVERY || vendorcode/google/chromeos/vboot2 || bool || Disable dev mode on recovery requests ||
 +
When this option is enabled, the Chrome OS device leaves the
 +
developer mode as soon as recovery request is detected. This is
 +
handy on embedded devices with limited input capabilities.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RETURN_FROM_VERSTAGE || vendorcode/google/chromeos/vboot2 || bool ||  ||
 +
If this is set, the verstage returns back to the calling stage instead
 +
of exiting to the succeeding stage so that the verstage space can be
 +
reused by the succeeding stage. This is useful if a ram space is too
 +
small to fit both the verstage and the succeeding stage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_ROMSTAGE_INDEX || vendorcode/google/chromeos/vboot2 || hex || Romstage component index ||
 +
This is the index of the romstage component in the verified
 +
firmware block.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_RAMSTAGE_INDEX || vendorcode/google/chromeos/vboot2 || hex || Ramstage component index ||
 +
This is the index of the ramstage component in the verified
 +
firmware block.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_REFCODE_INDEX || vendorcode/google/chromeos/vboot2 || hex || Reference code firmware index ||
 +
This is the index of the reference code component in the verified
 +
firmware block.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_BOOT_LOADER_INDEX || vendorcode/google/chromeos/vboot2 || hex || Bootloader component index ||
 +
This is the index of the bootloader component in the verified
 +
firmware block.
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_DEV_SWITCH || vendorcode/google/chromeos || bool ||  ||
 +
Whether this platform has a virtual developer switch.
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: AMD Platform Initialization || || || ||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_PATH_DEFAULT || vendorcode/amd/pi/00630F01 || string ||  ||
 +
The default binary file name to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_FILE_DEFAULT || vendorcode/amd/pi/00630F01 || string ||  ||
 +
The default binary file name to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_LOCATION_DEFAULT || vendorcode/amd/pi/00630F01 || hex ||  ||
 +
The default ROM address at which to store the binary Platform
 +
Initialization code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_PATH_DEFAULT || vendorcode/amd/pi/00730F01 || string ||  ||
 +
The default binary file name to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_FILE_DEFAULT || vendorcode/amd/pi/00730F01 || string ||  ||
 +
The default binary file name to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_LOCATION_DEFAULT || vendorcode/amd/pi/00730F01 || hex ||  ||
 +
The default ROM address at which to store the binary Platform
 +
Initialization code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| None || vendorcode/amd || None || AGESA source ||
 +
Select the method for including the AMD Platform Initialization
 +
code into coreboot.  Platform Initialization code is required for
 +
all AMD processors.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI ||
 +
Use a binary PI package.  Generally, these will be stored in the
 +
"3rdparty" directory.  For some processors, these must be obtained
 +
directly from AMD Embedded Processors Group
 +
(http://www.amdcom/embedded).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA ||
 +
Build the PI package ("AGESA") from source code in the "vendorcode"
 +
directory.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_PATH || vendorcode/amd || string || AGESA PI directory path ||
 +
Specify where to find the AGESA headers and binary file
 +
for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_FILE || vendorcode/amd || string || AGESA PI binary file name ||
 +
Specify the binary file to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_LOCATION || vendorcode/amd || string || AGESA PI binary address in ROM ||
 +
Specify the ROM address at which to store the binary Platform
 +
Initialization code.
  
 
||
 
||
Line 234: Line 804:
 
| || || (comment) || || CPU ||
 
| || || (comment) || || CPU ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||  
+
| LAPIC_MONOTONIC_TIMER || cpu/x86 || bool || ||  
Select this to apply patches to the CPU microcode provided by
+
Expose monotonic time using the local apic.
AMD without source, and distributed with coreboot, to address
+
issues in the CPU post production.
+
  
Microcode updates distributed with coreboot are not necessarily
+
||
the latest version available from AMD. Updates are only applied
+
|- bgcolor="#eeeeee"
if they are newer than the microcode already in your CPU.
+
| TSC_CONSTANT_RATE || cpu/x86 || bool ||  ||
 +
This option asserts that the TSC ticks at a known constant rate.
 +
Therefore, no TSC calibration is required.
  
Unselect this to let Fam10h CPUs run with microcode as shipped
+
||
from factory. No binary microcode patches will be included in the
+
|- bgcolor="#eeeeee"
coreboot image in that case, which can help with creating an image
+
| TSC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
for which complete source code is available, which in turn might
+
Expose monotonic time using the TSC.
simplify license compliance.
+
  
Microcode updates intend to solve issues that have been discovered
+
||
after CPU production. The common case is that systems work as
+
|- bgcolor="#eeeeee"
intended with updated microcode, but we have also seen cases where
+
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||
issues were solved by not applying the microcode updates.
+
The CPU driver should select this if the CPU needs
 +
to execute an lfence instruction in order to synchronize
 +
rdtsc. This is true for all modern AMD CPUs.
  
Note that some operating system include these same microcode
+
||
patches, so you may need to also disable microcode updates in
+
|- bgcolor="#eeeeee"
your operating system in order for this option to matter.
+
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an mfence instruction in order to synchronize
 +
rdtsc. This is true for all modern Intel CPUs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMM_MODULES || cpu/x86 || bool ||  ||
 +
If SMM_MODULES is selected then SMM handlers are built as modules.
 +
A SMM stub along with a SMM loader/relocator. All the handlers are
 +
written in C with stub being the only assembly.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMM_MODULE_HEAP_SIZE || cpu/x86 || hex ||  ||
 +
This option determines the size of the heap within the SMM handler
 +
modules.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86_AMD_FIXED_MTRRS || cpu/x86 || bool ||  ||
 +
This option informs the MTRR code to use the RdMem and WrMem fields
 +
in the fixed MTRR MSRs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PLATFORM_USES_FSP1_0 || cpu/x86 || bool ||  ||
 +
Selected for Intel processors/platform combinations that use the
 +
Intel Firmware Support Package (FSP) 1.0 for initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PARALLEL_MP || cpu/x86 || bool ||  ||
 +
This option uses common MP infrastructure for bringing up APs
 +
in parallel. It additionally provides a more flexible mechanism
 +
for sequencing the steps of bringing up the APs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BACKUP_DEFAULT_SMM_REGION || cpu/x86 || bool ||  ||
 +
The CPU support will select this option if the default SMM region
 +
needs to be backed up for suspend/resume purposes.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool ||  ||
 +
On certain platforms a boot speed gain can be realized if mirroring
 +
the payload data stored in non-volatile storage. On x86 systems the
 +
payload would typically live in a memory-mapped SPI part. Copying
 +
the SPI contents to RAM before performing the load can speed up
 +
the boot process.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || cpu/x86 || int ||  ||
 +
Most x86 systems which boot from SPI flash boot using bus 0.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
 +
The haswell romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MONOTONIC_TIMER_MSR || cpu/intel/haswell || bool ||  ||
 +
Provide a monotonic timer using the 24MHz MSR counter.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None ||  ||
 +
This option selects building a Firmware Interface Table (FIT).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int ||  ||
 +
This option selects the number of empty entries in the FIT table.
 +
 
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None ||  ||
 +
This option indicates that the turbo mode setting is not package
 +
scoped. i.e. enable_turbo() needs to be called on not just the bsp
 +
 
 +
||
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||  
+
| GEODE_VSA_FILE || cpu/amd/geode_gx2 || bool || Add a VSA image ||  
 
Select this option if you have an AMD Geode GX2 vsa that you would
 
Select this option if you have an AMD Geode GX2 vsa that you would
 
like to add to your ROM.
 
like to add to your ROM.
Line 270: Line 932:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||  
+
| VSA_FILENAME || cpu/amd/geode_gx2 || string || AMD Geode GX2 VSA path and filename ||  
 
The path and filename of the file to use as VSA.
 
The path and filename of the file to use as VSA.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||  
+
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||  
 
Select this option if you have an AMD Geode LX vsa that you would
 
Select this option if you have an AMD Geode LX vsa that you would
 
like to add to your ROM.
 
like to add to your ROM.
Line 284: Line 946:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||  
+
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||  
 
The path and filename of the file to use as VSA.
 
The path and filename of the file to use as VSA.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/agesa || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
  
 
||
 
||
Line 293: Line 965:
  
 
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_G34 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD G34 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_C32 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD C32 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_AM3R2 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD AM3r2 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family15 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
 +
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
 +
 +
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool ||  ||
 +
Force AGESA to ignore package type mismatch between CPU and northbridge
 +
in memory code. This enables Socket AM1 support with current AGESA
 +
version for Kabini platform.
 +
Enable this option only if you have Socket AM1 board.
 +
Note that the AGESA release shipped with coreboot does not officially
 +
support the AM1 socket. Selecting this option might damage your hardware.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/pi || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
  
 
||
 
||
Line 299: Line 1,013:
 
This option is used to enable certain functions to make coreboot
 
This option is used to enable certain functions to make coreboot
 
work correctly on symmetric multi processor (SMP) systems.
 
work correctly on symmetric multi processor (SMP) systems.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AP_SIPI_VECTOR || cpu || hex ||  ||
 +
This must equal address of ap_sipi_vector from bootblock build.
  
 
||
 
||
Line 323: Line 1,042:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool || ||  
+
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||  
Unset this if you don't want the MTRR code to use
+
Select this option if you want microcode updates to be assembled when
subtractive MTRRs
+
building coreboot and included in the final image as a separate CBFS
 +
file. Microcode will not be hard-coded into ramstage.
 +
 
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 
 +
If unsure, select this option.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
+
| CPU_MICROCODE_CBFS_EXTERNAL || cpu || bool || Include external microcode file ||  
|- bgcolor="#eeeeee"
+
Select this option if you want to include an external file containing
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||  
+
the CPU microcode. This will be included as a separate file in CBFS.
Select this for boards with a Voltage Regulator able to operate
+
A word of caution: only select this option if you are sure the
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
+
microcode that you have is newer than the microcode shipping with
 +
coreboot.
 +
 
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 
 +
If unsure, select "Generate from tree"
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: HyperTransport setup || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||  
+
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||  
This option sets the maximum permissible HyperTransport link
+
Select this option if you do not want CPU microcode included in CBFS.
frequency.
+
Note that for some CPUs, the microcode is hard-coded into the source
 +
tree and is not loaded from CBFS. In this case, microcode will still
 +
be updated. There is a push to move all microcode to CBFS, but this
 +
change is not implemented for all CPUs.
  
Use of this option will only limit the autodetected HT frequency.
+
This option currently applies to:
It will not (and cannot) increase the frequency beyond the
+
- Intel SandyBridge/IvyBridge
autodetected limits.
+
- VIA Nano
  
This is primarily used to work around poorly designed or laid out
+
Microcode may be added to the ROM image at a later time with cbfstool,
HT traces on certain motherboards.
+
if desired.
 +
 
 +
If unsure, select "Generate from tree"
 +
 
 +
The GOOD:
 +
Microcode updates intend to solve issues that have been discovered
 +
after CPU production. The expected effect is that systems work as
 +
intended with the updated microcode, but we have also seen cases where
 +
issues were solved by not applying microcode updates.
 +
 
 +
The BAD:
 +
Note that some operating system include these same microcode patches,
 +
so you may need to also disable microcode updates in your operating
 +
system for this option to have an effect.
 +
 
 +
The UGLY:
 +
A word of CAUTION: some CPUs depend on microcode updates to function
 +
correctly. Not updating the microcode may leave the CPU operating at
 +
less than optimal performance, or may cause outright hangups.
 +
There are CPUs where coreboot cannot properly initialize the CPU
 +
without microcode updates
 +
For example, if running with the factory microcode, some Intel
 +
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
 +
will hang when changing the frequency.
 +
 
 +
Make sure you have a way of flashing the ROM externally before
 +
selecting this option.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||  
+
| CPU_MICROCODE_FILE || cpu || string || Path and filename of CPU microcode ||  
This option sets the maximum permissible HyperTransport
+
The path and filename of the file containing the CPU microcode.
downlink width.
+
  
Use of this option will only limit the autodetected HT width.
+
||
It will not (and cannot) increase the width beyond the autodetected
+
||
limits.
+
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Northbridge ||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string ||  ||
 +
This is the default PCI ID for the sandybridge/ivybridge graphics
 +
devices. This string names the vbios ROM in cbfs.  The following
 +
PCI IDs will be remapped to load this ROM:
 +
0x80860102, 0x8086010a, 0x80860112, 0x80860116
 +
0x80860122, 0x80860126, 0x80860166
  
This is primarily used to work around poorly designed or laid out HT
+
||
traces on certain motherboards.
+
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || northbridge/intel/fsp_sandybridge || hex || Size of CBFS filesystem in ROM ||
 +
On Sandybridge and Ivybridge systems the firmware image may
 +
have to store a lot more than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
This option specifies the maximum size of the CBFS portion in the
 +
firmware image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||  
+
| FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string || ||  
This option sets the maximum permissible HyperTransport
+
The path and filename of the Intel FSP binary for this platform.
uplink width.
+
  
Use of this option will only limit the autodetected HT width.
+
||
It will not (and cannot) increase the width beyond the autodetected
+
|- bgcolor="#eeeeee"
limits.
+
| FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with the Intel's BCT (tool).
  
This is primarily used to work around poorly designed or laid out HT
+
The Ivy Bridge Processor/Panther Point FSP is built with a preferred
traces on certain motherboards.
+
base address of 0xFFF80000
  
 
||
 
||
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || northbridge/intel/nehalem || hex || Size of CBFS filesystem in ROM ||
 +
On Nehalem systems the firmware image has to
 +
store a lot more than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || northbridge/intel/gm45 || hex || Size of CBFS filesystem in ROM ||
 +
On GM45 systems the firmware image may
 +
store a lot more than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||  
 
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||  
Line 390: Line 1,185:
  
 
||
 
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-ram rom stage execution.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||
 +
Select this option to add a System Agent binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || northbridge/intel/haswell || hex || Size of CBFS filesystem in ROM ||
 +
On Haswell systems the firmware image has to store a lot more
 +
than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
- MRC cache information
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||
 +
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || northbridge/intel/sandybridge || bool || Add a System Agent binary ||
 +
Select this option to add a System Agent binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || northbridge/intel/sandybridge || hex || Size of CBFS filesystem in ROM ||
 +
On Sandybridge and Ivybridge systems the firmware image has to
 +
store a lot more than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
- MRC cache information
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 408: Line 1,279:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
+
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||
 +
On some boards it may be neccessary to hard reset early
 +
during resume from S3 if the SLFRCS register indicates that
 +
a memory channel is not guaranteed to be in self-refresh.
 +
On other boards the check always creates a false positive,
 +
effectively making it impossible to resume.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||
 +
Set the TSEG area to 1 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||
 +
Set the TSEG area to 2 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||
 +
Set the TSEG area to 4 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||
 +
Set the TSEG area to 8 MB.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
The Rangeley FSP is built with a preferred base address of 0xFFF80000
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Northbridge CIMX
 +
Trace debug information to the serial console.
 +
 
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||  
 +
Select this for boards with a Voltage Regulator able to operate
 +
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
 +
 
 +
||
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Geode GX1 video support || || || ||
+
! align="left" | Menu: HyperTransport setup || || || ||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||
 +
This option sets the maximum permissible HyperTransport
 +
downlink width.
  
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||  
+
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||  
Select if RS690 should be setup to support MMCONF.
+
This option sets the maximum permissible HyperTransport
 +
uplink width.
 +
 
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
  
 
||
 
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||  
+
| || || (comment) || || Southbridge ||
Select the mode in which SATA should be driven. IDE or AHCI.
+
|- bgcolor="#eeeeee"
The default is IDE.
+
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||  
 +
Select this option to add a CMC state machine binary to
 +
the resulting coreboot image.
  
config SATA_MODE_IDE
+
Note: Without this binary coreboot will not work
bool "IDE"
+
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
 +
The path and filename of the file to use as CMC state machine
 +
binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BUILD_WITH_FAKE_IFD || southbridge/intel/bd82x6x || bool || Build with a fake IFD ||
 +
If you don't have an Intel Firmware Descriptor (ifd.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
Though, the resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_GBE_BIN || southbridge/intel/bd82x6x || bool || Add gigabit ethernet firmware ||
 +
The integrated gigabit ethernet controller needs a firmware file.
 +
Select this if you are going to use the PCH integrated controller
 +
and have the firmware.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || southbridge/intel/bd82x6x || bool || Add Intel Management Engine firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller called Management Engine (ME). The ME
 +
firmware might be provided in coreboot's 3rdparty repository. If
 +
not and if you don't have the firmware elsewhere, you can still
 +
build coreboot without it. In this case however, you'll have to make
 +
sure that you don't overwrite your ME firmware on your flash ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/bd82x6x || bool || Lock Management Engine section ||
 +
The Intel Management Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_SPI_ON_RESUME || southbridge/intel/bd82x6x || bool || Lock all flash ROM sections on S3 resume ||
 +
If the flash ROM shall be protected against write accesses from the
 +
operating system (OS), the locking procedure has to be repeated after
 +
each resume from S3. Select this if you never want to update the flash
 +
ROM from within your OS. Notice: Even with this option, the write lock
 +
has still to be enabled on the normal boot path (e.g. by the payload).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool ||  ||
 +
Set this option to y for Lynxpont LP (Haswell ULT).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BUILD_WITH_FAKE_IFD || southbridge/intel/lynxpoint || bool || Build with a fake IFD ||
 +
If you don't have an Intel Firmware Descriptor (ifd.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
Though, the resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || southbridge/intel/lynxpoint || bool || Add Intel Management Engine firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller called Management Engine (ME). The ME
 +
firmware might be provided in coreboot's 3rdparty repository. If
 +
not and if you don't have the firmware elsewhere, you can still
 +
build coreboot without it. In this case however, you'll have to make
 +
sure that you don't overwrite your ME firmware on your flash ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||
 +
If you set this option to y, the Management Engine driver
 +
will defer waiting for the MBP Cleared indicator until the
 +
finalize step.  This can speed up boot time if the ME takes
 +
a long time to indicate this status.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||
 +
If you set this option to y, the USB ports will be routed
 +
to the XHCI controller during the finalize SMM callback.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/lynxpoint || bool || Lock Management Engine section ||
 +
The Intel Management Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INCLUDE_ME || southbridge/intel/fsp_bd82x6x || bool ||  ||
 +
Include the me.bin and descriptor.bin for Intel PCH.
 +
This is usually required for the PCH.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ME_PATH || southbridge/intel/fsp_bd82x6x || string ||  ||
 +
The path of the ME and Descriptor files.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/fsp_bd82x6x || bool || Lock Management Engine section ||
 +
The Intel Management Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BUILD_WITH_FAKE_IFD || southbridge/intel/ibexpeak || bool || Build with a fake IFD ||
 +
If you don't have an Intel Firmware Descriptor (ifd.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
Though, the resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || southbridge/intel/ibexpeak || bool || Add Intel Management Engine firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller called Management Engine (ME). The ME
 +
firmware might be provided in coreboot's 3rdparty repository. If
 +
not and if you don't have the firmware elsewhere, you can still
 +
build coreboot without it. In this case however, you'll have to make
 +
sure that you don't overwrite your ME firmware on your flash ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/ibexpeak || bool || Lock Management Engine section ||
 +
The Intel Management Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INCLUDE_ME || southbridge/intel/fsp_rangeley || bool || Add Intel descriptor.bin file ||
 +
Include the descriptor.bin for rangeley.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ME_PATH || southbridge/intel/fsp_rangeley || string || Path to descriptor.bin file ||
 +
The path of the descriptor.bin file.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb700 || hex ||  ||
 +
0x0 = Native IDE mode.
 +
0x1 = RAID mode.
 +
0x2 = AHCI mode.
 +
0x3 = Legacy IDE mode.
 +
0x4 = IDE->AHCI mode.
 +
0x5 = AHCI mode as 7804 ID (AMD driver).
 +
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIB_ENABLE || southbridge/amd/cimx/sb700 || bool ||  ||
 +
n = Disable PCI Bridge Device 14 Function 4.
 +
y = Enable PCI Bridge Device 14 Function 4.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb700 || hex ||  ||
 +
Set SCI IRQ to 9.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_SBCIMX_TRACE_TO_SERIAL || southbridge/amd/cimx/sb700 || bool || Redirect AMD Southbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Southbridge CIMX Trace
 +
debug information to the serial console.
 +
 
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
  
config SATA_MODE_AHCI
 
bool "AHCI"
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 441: Line 1,653:
 
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
 
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
 
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.
+
The default is AHCI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
 
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
NATIVE is the default mode and does not require a ROM.
+
NATIVE does not require a ROM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
 
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
AHCI may work with or without AHCI ROM. It depends on the payload support.
+
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
 
For example, seabios does not require the AHCI ROM.
 
For example, seabios does not require the AHCI ROM.
  
Line 470: Line 1,682:
 
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 
The CONFIG_ROM_SIZE must larger than 0x100000.
 
The CONFIG_ROM_SIZE must larger than 0x100000.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
 +
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||
 +
Select the method of SB800 fan control to be used.  None would be
 +
for either fixed maximum speed fans connected to the SB800 or for
 +
an external chip controlling the fan speeds.  Manual control sets
 +
up the SB800 fan control registers.  IMC fan control uses the SB800
 +
IMC to actively control the fan speeds.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
 +
No SB800 Fan control - Do not set up the SB800 fan control registers.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
 +
Configure the SB800 fan control registers in devicetree.cb.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
 +
Set up the SB800 to use the IMC based Fan controller.  This requires
 +
the IMC rom from AMD.  Configure the registers in devicetree.cb.
  
 
||
 
||
Line 495: Line 1,772:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||  
+
| HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||
Select this option to add a CMC state machine binary to
+
The XHCI controller must be enabled and the XHCI firmware
 +
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool ||  ||
 +
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_FWM_POSITION || southbridge/amd/pi/hudson || hex || Hudson Firmware ROM Position ||
 +
Hudson requires the firmware MUST be located at
 +
a specific address (ROM start address + 0x20000), otherwise
 +
xhci host Controller can not find or load the xhci firmware.
 +
 
 +
The firmware start address is dependent on the ROM chip size.
 +
The default offset is 0x20000 from the ROM start address, namely
 +
0xFFF20000 if flash chip size is 1M
 +
0xFFE20000 if flash chip size is 2M
 +
0xFFC20000 if flash chip size is 4M
 +
0xFF820000 if flash chip size is 8M
 +
0xFF020000 if flash chip size is 16M
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || RAID ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AZ_PIN || southbridge/amd/pi/hudson || hex ||  ||
 +
bit 1,0 - pin 0
 +
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool ||  ||
 +
Select if RS690 should be setup to support MMCONF.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||
 +
The XHCI controller must be enabled and the XHCI firmware
 +
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool ||  ||
 +
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || Hudson Firmware ROM Position ||
 +
Hudson requires the firmware MUST be located at
 +
a specific address (ROM start address + 0x20000), otherwise
 +
xhci host Controller can not find or load the xhci firmware.
 +
 
 +
The firmware start address is dependent on the ROM chip size.
 +
The default offset is 0x20000 from the ROM start address, namely
 +
0xFFF20000 if flash chip size is 1M
 +
0xFFE20000 if flash chip size is 2M
 +
0xFFC20000 if flash chip size is 4M
 +
0xFF820000 if flash chip size is 8M
 +
0xFF020000 if flash chip size is 16M
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || RAID ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AZ_PIN || southbridge/amd/agesa/hudson || hex ||  ||
 +
bit 1,0 - pin 0
 +
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||
 +
Select the mode in which SATA should be driven. IDE or AHCI.
 +
The default is IDE.
 +
 
 +
config SATA_MODE_IDE
 +
bool "IDE"
 +
 
 +
config SATA_MODE_AHCI
 +
bool "AHCI"
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Super I/O ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Embedded Controllers ||
 +
|- bgcolor="#eeeeee"
 +
| EC_ACPI || ec/acpi || bool ||  ||
 +
ACPI Embedded Controller interface. Mostly found in laptops.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_QUANTA_IT8518 || ec/quanta/it8518 || bool ||  ||
 +
Interface to QUANTA IT8518 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool ||  ||
 +
Interface to QUANTA ENE KB3940Q Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool ||  ||
 +
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool ||  ||
 +
When defined, ACPI accesses EC memmap data on ports 66h/62h. When
 +
not defined, the memmap data is instead accessed on 900h-9ffh via
 +
the LPC bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC via I2C bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool ||  ||
 +
Use only proto3 for i2c EC communication.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool ||  ||
 +
Google Chrome EC via LPC bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool ||  ||
 +
Microchip EC variant for LPC register access.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC via SPI bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int ||  ||
 +
Force delay after asserting /CS to allow EC to wakeup.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool ||  ||
 +
Interface to COMPAL ENE932 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_KONTRON_IT8516E || ec/kontron/it8516e || bool ||  ||
 +
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
 +
come from Fintek (mentioned as Finte*c* somewhere in their Linux
 +
driver).
 +
The KTQM77 is an embedded board and the IT8516E seems to be
 +
only used for fan control and GPIO.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || SoC ||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_CPU_INIT || soc/nvidia/tegra124 || string ||  ||
 +
CPU/SoC-specific bootblock code. This is useful if the
 +
bootblock must load microcode or copy data from ROM before
 +
searching for the bootblock.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra132 || bool || Use dsi graphics interface ||
 +
Initialize dsi display
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra132 || bool || Use dp graphics interface ||
 +
Initialize dp display
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_CPU_INIT || soc/nvidia/tegra132 || string ||  ||
 +
CPU/SoC-specific bootblock code. This is useful if the
 +
bootblock must load microcode or copy data from ROM before
 +
searching for the bootblock.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MTS_DIRECTORY || soc/nvidia/tegra132 || string || Directory where MTS microcode files are located ||
 +
Path to directory where MTS microcode files are located.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra132 || hex || Size of Trust Zone region ||
 +
Size of Trust Zone area in MiB to reserve in memory map.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra132 || bool || SoC BootROM does SDRAM init with full BCT ||
 +
Use during Ryu LPDDR3 bringup
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||
 +
Warning: M0 expects that auto self-refresh is enabled. Modify
 +
with caution.
 +
 
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool ||  ||
 +
Bay Trail M/D part support.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||
 +
Select this option to add a blob containing
 +
memory reference code.
 +
Note: Without this binary coreboot will not work
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary. Note that this points to the sandybridge binary file
 +
which is will not work, but it serves its purpose to do builds.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/baytrail || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-RAM ROM stage execution.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||
 +
The baytrail romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || soc/intel/baytrail || hex || Size of CBFS filesystem in ROM ||
 +
On Bay Trail systems the firmware image has to store a lot more
 +
than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
- MRC cache information
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||
 +
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || soc/intel/baytrail || bool || Add Intel Management Engine firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller called Management Engine (ME). The ME
 +
firmware might be provided in coreboot's 3rdparty repository. If
 +
not and if you don't have the firmware elsewhere, you can still
 +
build coreboot without it. In this case however, you'll have to make
 +
sure that you don't overwrite your ME firmware on your flash ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BUILD_WITH_FAKE_IFD || soc/intel/baytrail || bool || Build with a fake IFD ||
 +
If you don't have an Intel Firmware Descriptor (ifd.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
Though, the resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||
 +
The reference code blob will be placed into cbfs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||
 +
The path and filename to the file to be added to cbfs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON || soc/intel/common || bool ||  ||
 +
common code for Intel SOCs
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool ||  ||
 +
Intel Broadwell and Haswell ULT support.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/broadwell || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-ram rom stage execution.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||  
 +
Select this option to add a Memory Reference Code binary to
 
the resulting coreboot image.
 
the resulting coreboot image.
  
Line 503: Line 2,243:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||  
+
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||  
The path and filename of the file to use as CMC state machine
+
The filename of the file to use as Memory Reference Code binary.
binary.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
+
| CBFS_SIZE || soc/intel/broadwell || hex || Size of CBFS filesystem in ROM ||  
 +
The firmware image has to store more than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Management Engine firmware
 +
- MRC cache information
 +
This option allows to limit the size of the CBFS portion in the
 +
firmware image.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
+
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||  
 +
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
+
The romstage code caches the loaded ramstage program in SMM space.
this unless you're sure you don't want the briges setup for VGA.
+
On S3 wake the romstage will copy over a fresh ramstage that was
 +
cached in the SMM space. This option determines the action to take
 +
when the ramstage cache is invalid. If selected the system will
 +
reset otherwise the ramstage will be reloaded from cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||  
+
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool || ||  
Execute VGA option ROMs, if found. This is required to enable
+
If you set this option to y, the serial IRQ machine will be
PCI/AGP/PCI-E video cards.
+
operated in continuous mode.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || soc/intel/broadwell || bool || Add Intel Management Engine firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller called Management Engine (ME). The ME
 +
firmware might be provided in coreboot's 3rdparty repository. If
 +
not and if you don't have the firmware elsewhere, you can still
 +
build coreboot without it. In this case however, you'll have to make
 +
sure that you don't overwrite your ME firmware on your flash ROM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||  
+
| BUILD_WITH_FAKE_IFD || soc/intel/broadwell || bool || Build with a fake IFD ||
Execute non-VGA PCI option ROMs, if found.
+
If you don't have an Intel Firmware Descriptor (ifd.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
Though, the resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || soc/intel/broadwell || bool || Lock Management Engine section ||
 +
The Intel Management Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool ||  ||
 +
Bay Trail I part support using the Intel FSP.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex ||  ||
 +
This is set by the FSP
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string ||  ||
 +
This is the default PCI ID for the Bay Trail graphics
 +
devices.  This string names the vbios ROM in cbfs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || soc/intel/fsp_baytrail || hex ||  ||
 +
On Bay Trail systems the firmware image has to store a lot more
 +
than just coreboot, including:
 +
- a firmware descriptor
 +
- Intel Trusted Execution Engine firmware
 +
This option specifies the maximum size of the CBFS portion in the
 +
firmware image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INCLUDE_ME || soc/intel/fsp_baytrail || bool || Include the TXE ||
 +
Build the TXE and descriptor.bin into the ROM image.  If you want to use a
 +
descriptor.bin and TXE file from the previous ROM image, you may not want
 +
to build it in here.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ME_PATH || soc/intel/fsp_baytrail || string || Path to ME ||
 +
The path of the TXE and Descriptor files.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || soc/intel/fsp_baytrail || bool || Lock TXE section ||
 +
The Intel Trusted Execution Engine supports preventing write accesses
 +
from the host to the Management Engine section in the firmware
 +
descriptor. If the ME section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||
 +
The Baytrail SOC has one legacy serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
The Bay Trail FSP is built with a preferred base address of
 +
0xFFFC0000.
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || soc/qualcomm/ipq806x || hex || Size of CBFS filesystem in ROM ||
 +
CBFS size needs to match the size of memory allocated to the
 +
coreboot blob elsewhere in the system. Make sure this config option
 +
is fine tuned in the board config file.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||
 +
The path and filename of the binary blob containing
 +
ipq806x early initialization code, as supplied by the
 +
vendor.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel FSP ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
 +
Enabling this feature will force the MRC data to be cached in NV
 +
storage to be used for speeding up boot time on future reboots
 +
and/or power cycles.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool ||  ||
 +
Enabling this feature will cause MRC data to be cached in NV storage.
 +
This can either be used for fast boot, or just because the FSP wants
 +
it to be saved.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
 +
This is the amount of space in NV storage that is reserved for the
 +
fast boot data cache storage.
 +
 
 +
WARNING: Because this area will be erased and re-written, the size
 +
should be a full sector of the flash ROM chip and nothing else should
 +
be included in CBFS in any sector that the fast boot cache data is in.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OVERRIDE_CACHE_CACHE_LOC || drivers/intel/fsp1_0 || bool ||  ||
 +
Selected by the platform to set a new default location for the
 +
MRC/fast boot cache.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_LOC_OVERRIDE || drivers/intel/fsp1_0 || hex ||  ||
 +
Sets the override CBFS location of the MRC/fast boot cache.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_LOC || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache location in CBFS ||
 +
The location in CBFS for the MRC data to be cached.
 +
 
 +
WARNING: This should be on a sector boundary of the BIOS ROM chip
 +
and nothing else should be included in that sector, or IT WILL BE
 +
ERASED.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
 +
This is used to calculate the offset of the MRC data cache in NV
 +
Storage for fast boot.  If in doubt, leave this set to the default
 +
which sets the virtual size equal to the ROM size.
 +
 
 +
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
 +
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
 +
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
 +
size is 16 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
 +
This is the size of the cachable area that is passed into the FSP in
 +
the early initialization.  Typically this should be the size of the CBFS
 +
area, but the size must be a power of 2 whereas the CBFS size does not
 +
have this limitation.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||
 +
The chipset can select this to use a generic cache_as_ram.inc file
 +
that should be good for all FSP based platforms.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
 +
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Devices || || || ||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_NATIVE_VGA_INIT || device || bool || Use native graphics initialization ||
 +
Some mainboards, such as the Google Link, allow initializing the display
 +
without the need of a binary only VGA OPROM. Enabling this option may be
 +
faster, but also lacks flexibility in setting modes.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||  
 +
Execute VGA Option ROMs in coreboot if found. This is required
 +
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
 +
payload.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||
 +
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ALWAYS_LOAD_OPROM || device || bool ||  ||
 +
Always load option ROMs if any are found. The decision to run
 +
the ROM is still determined at runtime, but the distinction
 +
between loading and not running comes into play for CHROMEOS.
 +
 
 +
An example where this is required is that VBT (Video BIOS Tables)
 +
are needed for the kernel's display driver to know how a piece of
 +
hardware is configured to be used.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ON_DEVICE_ROM_RUN || device || bool || Run Option ROMs on PCI devices ||
 +
Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
 +
 
 +
If disabled, only Option ROMs stored in CBFS will be executed by
 +
coreboot. If you are concerned about security, you might want to
 +
disable this option, but it might leave your system in a state of
 +
degraded functionality.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
  
Examples include IDE/SATA controller option ROMs and option ROMs
+
If unsure, say N when using SeaBIOS as payload, Y otherwise.
for network cards (NICs).
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||  
+
| PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||  
If you select this option, PCI option ROMs will be executed
+
If you select this option, PCI Option ROMs will be executed
 
natively on the CPU in real mode. No CPU emulation is involved,
 
natively on the CPU in real mode. No CPU emulation is involved,
 
so this is the fastest, but also the least secure option.
 
so this is the fastest, but also the least secure option.
Line 541: Line 2,574:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||  
+
| PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||  
 
If you select this option, the x86emu CPU emulator will be used to
 
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.
+
execute PCI Option ROMs.
  
This option prevents option ROMs from doing dirty tricks with the
+
This option prevents Option ROMs from doing dirty tricks with the
 
system (such as installing SMM modules or hypervisors), but it is
 
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native option ROM initialization
+
also significantly slower than the native Option ROM initialization
 
method.
 
method.
  
Line 554: Line 2,587:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||  
+
| YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||  
Per default, YABEL only allows option ROMs to access the PCI device
+
Per default, YABEL only allows Option ROMs to access the PCI device
 
that they are associated with. However, this causes trouble for some
 
that they are associated with. However, this causes trouble for some
onboard graphics chips whose option ROM needs to reconfigure the
+
onboard graphics chips whose Option ROM needs to reconfigure the
 
north bridge.
 
north bridge.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||  
+
| YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||
 +
By default, YABEL aborts when the Option ROM tries to write to other
 +
devices' config spaces. With this option enabled, the write doesn't
 +
follow through, but the Option ROM is allowed to go on.
 +
This can create issues such as hanging Option ROMs (if it depends on
 +
that other register changing to the written value), so test for
 +
impact before using this option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||  
 
YABEL requires 1MB memory for its CPU emulation. This memory is
 
YABEL requires 1MB memory for its CPU emulation. This memory is
 
normally located at 16MB.
 
normally located at 16MB.
Line 568: Line 2,611:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||  
+
| YABEL_DIRECTHW || device || bool || Direct hardware access ||  
 
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 
additionally provides a PC system emulation that filters bad device
 
additionally provides a PC system emulation that filters bad device
Line 576: Line 2,619:
 
When choosing this option, x86emu will pass through all hardware
 
When choosing this option, x86emu will pass through all hardware
 
accesses to memory and I/O devices to the underlying memory and I/O
 
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
+
addresses. While this option prevents Option ROMs from doing dirty
 
tricks with the CPU (such as installing SMM modules or hypervisors),
 
tricks with the CPU (such as installing SMM modules or hypervisors),
 
they can still access all devices in the system.
 
they can still access all devices in the system.
Line 583: Line 2,626:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
+
| PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||  
 +
Detect and enable Common Clock on PCIe links.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||  
+
| PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||  
ACPI Embedded Controller interface. Mostly found in laptops.
+
Detect and enable ASPM on PCIe links.
  
 
||
 
||
||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Generic Drivers || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||  
+
| PCIEXP_CLK_PM || device || bool || Enable PCIe Clock Power Management ||  
Support for Oxford OXPCIe952 serial port PCIe cards.
+
Detect and enable Clock Power Management on PCIe.
Currently only devices with the vendor ID 0x1415 and device ID
+
0xc158 will work.
+
NOTE: Right now you have to set the base address of your OXPCIe952
+
card to exactly the value that the device allocator would set them
+
later on, or serial console functionality will stop as soon as the
+
resource allocator assigns a new base address to the device.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||  
+
| EARLY_PCI_BRIDGE || device || bool || Early PCI bridge ||  
 
While coreboot is executing code from ROM, the coreboot resource
 
While coreboot is executing code from ROM, the coreboot resource
 
allocator has not been running yet. Hence PCI devices living behind
 
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system. In order to use an
+
a bridge are not yet visible to the system.
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
 
that controls the OXPCIe952 controller first.
+
This option enables static configuration for a single pre-defined
 +
PCI bridge function on bus 0.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||  
+
| PCIEXP_L1_SUB_STATE || device || bool || Enable PCIe ASPM L1 SubState ||  
While coreboot is executing code from ROM, the coreboot resource
+
Detect and enable ASPM on PCIe links.
allocator has not been running yet. Hence PCI devices living behind
+
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
that controls the OXPCIe952 controller first.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||  
+
| SUBSYSTEM_VENDOR_ID || device || hex || Override PCI Subsystem Vendor ID ||  
While coreboot is executing code from ROM, the coreboot resource
+
This config option will override the devicetree settings for
allocator has not been running yet. Hence PCI devices living behind
+
PCI Subsystem Vendor ID.
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
that controls the OXPCIe952 controller first.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||  
+
| SUBSYSTEM_DEVICE_ID || device || hex || Override PCI Subsystem Device ID ||  
While coreboot is executing code from ROM, the coreboot resource
+
This config option will override the devicetree settings for
allocator has not been running yet. Hence PCI devices living behind
+
PCI Subsystem Device ID.
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
that controls the OXPCIe952 controller first.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||  
+
| VGA_BIOS || device || bool || Add a VGA BIOS image ||  
While coreboot is executing code from ROM, the coreboot resource
+
Select this option if you have a VGA BIOS image that you would
allocator has not been running yet. Hence PCI devices living behind
+
like to add to your ROM.
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
+
for the OXPCIe952 controller.
+
  
 +
You will be able to specify the location and file name of the
 +
image later.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || device || string || VGA device PCI IDs ||
 +
The comma-separated PCI vendor and device ID that would associate
 +
your VGA BIOS to your video card.
 +
 +
Example: 1106,3230
 +
 +
In the above example 1106 is the PCI vendor ID (in hex, but without
 +
the "0x" prefix) and 3230 specifies the PCI device ID of the
 +
video card (also in hex, without "0x" prefix).
 +
 +
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||  
+
| INTEL_MBI || device || bool || Add an MBI image ||  
It sets PCI class to IDE compatible native mode, allowing
+
Select this option if you have an Intel MBI image that you would
SeaBIOS, FILO etc... to boot from it.
+
like to add to your ROM.
  
 +
You will be able to specify the location and file name of the
 +
image later.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MBI_FILE || device || string || Intel MBI path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| PXE_ROM || device || bool || Add a PXE ROM image ||
 +
Select this option if you have a PXE ROM image that you would
 +
like to add to your ROM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PXE_ROM_FILE || device || string || PXE ROM filename ||
 +
The path and filename of the file to use as PXE ROM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PXE_ROM_ID || device || string || network card PCI IDs ||
 +
The comma-separated PCI vendor and device ID that would associate
 +
your PXE ROM to your network card.
 +
 +
Example: 10ec,8168
 +
 +
In the above example 10ec is the PCI vendor ID (in hex, but without
 +
the "0x" prefix) and 8168 specifies the PCI device ID of the
 +
network card (also in hex, without "0x" prefix).
 +
 +
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOFTWARE_I2C || device || bool || Enable I2C controller emulation in software ||
 +
This config option will enable code to override the i2c_transfer
 +
routine with a (simple) software emulation of the protocol. This may
 +
be useful for debugging or on platforms where a driver for the real
 +
I2C controller is not (yet) available. The platform code needs to
 +
provide bindings to manually toggle I2C lines.
 +
 
||
 
||
  
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: Console || || || ||
+
! align="left" | Menu: Display || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||  
+
| FRAMEBUFFER_SET_VESA_MODE || device || bool || Set framebuffer graphics resolution ||  
Send coreboot debug output to an I/O mapped serial port console.
+
Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||  
+
| FRAMEBUFFER_SET_VESA_MODE || device || bool || framebuffer graphics resolution ||  
Send coreboot debug output to a memory mapped serial port console.
+
This option sets the resolution used for the coreboot framebuffer (and
 +
bootsplash screen).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||  
+
| FRAMEBUFFER_KEEP_VESA_MODE || device || bool || Keep VESA framebuffer ||  
Serial console on COM1/ttyS0 at I/O port 0x3f8.
+
This option keeps the framebuffer mode set after coreboot finishes
 +
execution. If this option is enabled, coreboot will pass a
 +
framebuffer entry in its coreboot table and the payload will need a
 +
framebuffer driver. If this option is disabled, coreboot will switch
 +
back to text mode before handing control to a payload.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||  
+
| BOOTSPLASH || device || bool || Show graphical bootsplash ||  
Serial console on COM2/ttyS1 at I/O port 0x2f8.
+
This option shows a graphical bootsplash screen. The graphics are
 +
loaded from the CBFS file bootsplash.jpg.
 +
 
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||  
+
| BOOTSPLASH_FILE || device || string || Bootsplash path and filename ||  
Serial console on COM3/ttyS2 at I/O port 0x3e8.
+
The path and filename of the file to use as graphical bootsplash
 +
screen. The file format has to be jpg.
 +
 
 
||
 
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Generic Drivers || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||  
+
| SPI_FLASH || drivers/spi || bool || ||  
Serial console on COM4/ttyS3 at I/O port 0x2e8.
+
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex ||  ||  
+
| SPI_ATOMIC_SEQUENCING || drivers/spi || bool ||  ||  
Map the COM port names to the respective I/O port.
+
Select this option if the SPI controller uses "atomic sequencing."
 +
Atomic sequencing is when the sequence of commands is pre-programmed
 +
in the SPI controller. Hardware manages the transaction instead of
 +
software. This is common on x86 platforms.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||  
+
| SPI_FLASH_MEMORY_MAPPED || drivers/spi || bool || ||  
Set serial port Baud rate to 115200.
+
Inform system if SPI is memory-mapped or not.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||  
+
| SPI_FLASH_SMM || drivers/spi || bool || SPI flash driver support in SMM ||  
Set serial port Baud rate to 57600.
+
Select this option if you want SPI flash support in SMM.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||  
+
| SPI_FLASH_NO_FAST_READ || drivers/spi || bool || Disable Fast Read command ||  
Set serial port Baud rate to 38400.
+
Select this option if your setup requires to avoid "fast read"s
 +
from the SPI flash parts.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||  
+
| SPI_FLASH_ADESTO || drivers/spi || bool || ||  
Set serial port Baud rate to 19200.
+
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Adesto Technologies.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||  
+
| SPI_FLASH_AMIC || drivers/spi || bool || ||  
Set serial port Baud rate to 9600.
+
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by AMIC.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int ||  ||  
+
| SPI_FLASH_ATMEL || drivers/spi || bool ||  ||  
Map the Baud rates to an integer.
+
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Atmel.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||  
+
| SPI_FLASH_EON || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by EON.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_GIGADEVICE || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Gigadevice.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_MACRONIX || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Macronix.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SPANSION || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Spansion.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SST || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by SST.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_STMICRO || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by ST MICRO.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_WINBOND || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Winbond.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B || drivers/spi || bool ||  ||
 +
Select this option if your SPI flash supports the fast read dual-
 +
output command (opcode 0x3b) where the opcode and address are sent
 +
to the chip on MOSI and data is received on both MOSI and MISO.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG || drivers/elog || bool || Support for flash based event log ||
 +
Enable support for flash based event logging.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_FLASH_BASE || drivers/elog || hex || Event log offset into flash ||
 +
Offset into the flash chip for the ELOG block.
 +
This should be allocated in the FMAP.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_AREA_SIZE || drivers/elog || hex || Size of Event Log area in flash ||
 +
This should be a multiple of flash block size.
 +
 
 +
Default is 4K.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||
 +
This option will have ELOG store a copy of the flash event log
 +
in a CBMEM region and export that address in SMBIOS to the OS.
 +
This is useful if the ELOG location is not in memory mapped flash,
 +
but it means that events added at runtime via the SMI handler
 +
will not be reflected in the CBMEM copy of the log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||
 +
This interface is compatible with the linux kernel driver
 +
available with CONFIG_GOOGLE_GSMI and can be used to write
 +
kernel reset/shutdown messages to the event log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||
 +
Store a monotonic boot number in CMOS and provide an interface
 +
to read the current value and increment the counter.  This boot
 +
counter will be logged as part of the System Boot event.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||
 +
This value must be greater than 16 bytes so as not to interfere
 +
with the standard RTC region.  Requires 8 bytes.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG || drivers/usb || bool || USB 2.0 EHCI debug dongle support ||  
 
This option allows you to use a so-called USB EHCI Debug device
 
This option allows you to use a so-called USB EHCI Debug device
 
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
 
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Line 743: Line 2,949:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||  
+
| USBDEBUG_IN_ROMSTAGE || drivers/usb || bool || Enable early (pre-RAM) usbdebug ||
This option selects which physical USB port coreboot will try to
+
Configuring USB controllers in system-agent binary may cause
use as EHCI Debug Port first (valid values are: 1-15).
+
problems to usbdebug. Disabling this option delays usbdebug to
 +
be setup on entry to ramstage.
 +
 
 +
If unsure, say Y.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_HCD_INDEX || drivers/usb || int || Index for EHCI controller to use with usbdebug ||
 +
Some boards have multiple EHCI controllers with possibly only
 +
one having the Debug Port capability on an external USB port.
 +
 
 +
Mapping of this index to PCI device functions is southbridge
 +
specific and mainboard level Kconfig should already provide
 +
a working default value here.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DEFAULT_PORT || drivers/usb || int || Default USB port to use as Debug Port ||  
 +
Selects which physical USB port usbdebug dongle is connected to.
 +
Setting of 0 means to scan possible ports starting from 1.
  
If coreboot doesn't detect an EHCI Debug Port dongle on this port,
+
Intel platforms have hardwired the debug port location and this
it will try all the other ports one after the other. This will take
+
setting makes no difference there.
a few seconds of time though, and thus slow down the booting process.
+
  
 
Hence, if you select the correct port here, you can speed up
 
Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
+
your boot time. Which USB port number refers to which actual
actual port on your mainboard (potentially also USB pin headers
+
port on your mainboard (potentially also USB pin headers on
on your mainboard) is highly board-specific, and you'll likely
+
your mainboard) is highly board-specific, and you'll likely
 
have to find out by trial-and-error.
 
have to find out by trial-and-error.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DONGLE_BEAGLEBONE || drivers/usb || bool || BeagleBone ||
 +
Use this to configure the USB hub on BeagleBone board.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DONGLE_BEAGLEBONE_BLACK || drivers/usb || bool || BeagleBone Black ||
 +
Use this with BeagleBone Black.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GIC || drivers/gic || None ||  ||
 +
This option enables GIC support, the ARM generic interrupt controller.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_UART_OXPCIE || drivers/uart || bool || Oxford OXPCIe952 ||
 +
Support for Oxford OXPCIe952 serial port PCIe cards.
 +
Currently only devices with the vendor ID 0x1415 and device ID
 +
0xc158 or 0xc11b will work.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_PS2_KEYBOARD || drivers/pc80 || bool || PS/2 keyboard init ||
 +
Enable this option to initialize PS/2 keyboards found connected
 +
to the PS/2 port.
 +
 +
Some payloads (eg, filo) require this option.  Other payloads
 +
(eg, GRUB 2, SeaBIOS, Linux) do not require it.
 +
Initializing a PS/2 keyboard can take several hundred milliseconds.
 +
 +
If you know you will only use a payload which does not require
 +
this option, then you can say N here to speed up boot time.
 +
Otherwise say Y.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LPC_TPM || drivers/pc80/tpm || bool ||  ||
 +
Enable this option to enable LPC TPM support in coreboot.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_TIS_BASE_ADDRESS || drivers/pc80/tpm || hex || TPM Base Address ||
 +
This can be used to adjust the TPM memory base address.
 +
The default is specified by the TCG PC Client Specific TPM
 +
Interface Specification 1.2 and should not be changed unless
 +
the TPM being used does not conform to TPM TIS 1.2.
 +
 +
||
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_EMULATION_QEMU_BOCHS || drivers/emulation/qemu || bool || bochs dispi interface vga driver ||
 +
VGA driver for qemu emulated vga cards supporting
 +
the bochs dispi interface.  This includes
 +
standard vga, vmware svga and qxl.  The default
 +
vga (cirrus) is *not* supported, so you have to
 +
pick another one explicitly via 'qemu -vga $card'.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_XPOWERS_AXP209 || drivers/xpowers/axp209 || bool ||  ||
 +
X-Powers AXP902 Power Management Unit
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_XPOWERS_AXP209_BOOTBLOCK || drivers/xpowers/axp209 || bool ||  ||
 +
Make AXP209 functionality available in he bootblock.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_DP || drivers/intel/gma || bool ||  ||
 +
helper functions for intel display port operations
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_DDI || drivers/intel/gma || bool ||  ||
 +
helper functions for intel DDI operations
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_TI_TPS65090 || drivers/ti/tps65090 || bool ||  ||
 +
TI TPS65090
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_PARADE_PS8625 || drivers/parade/ps8625 || bool ||  ||
 +
Parade ps8625 display port to lvds bridge
 +
 +
||
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_I2C_RTD2132 || drivers/i2c/rtd2132 || bool ||  ||
 +
Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_SIL_3114 || drivers/sil/3114 || bool || Silicon Image SIL3114 ||
 +
It sets PCI class to IDE compatible native mode, allowing
 +
SeaBIOS, FILO etc... to boot from it.
 +
 +
||
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DIGITIZER_AUTODETECT || drivers/lenovo || bool || Autodetect ||
 +
The presence of digitizer is inferred from model number stored in
 +
AT24RF chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DIGITIZER_PRESENT || drivers/lenovo || bool || Present ||
 +
The digitizer is assumed to be present.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DIGITIZER_ABSENT || drivers/lenovo || bool || Absent ||
 +
The digitizer is assumed to be absent.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_MAXIM_MAX77686 || drivers/maxim/max77686 || bool ||  ||
 +
Maxim MAX77686 power regulator
 +
 +
||
 +
 +
||
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| TPM || toplevel || bool ||  ||
 +
Enable this option to enable TPM support in coreboot.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Console || || || ||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_CONSOLE || console || bool || Enable early (bootblock) console output. ||
 +
Use console during the bootblock if supported
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SQUELCH_EARLY_SMP || console || bool || Squelch AP CPUs from early console. ||
 +
When selected only the BSP CPU will output to early console.
 +
 +
Console drivers have unpredictable behaviour if multiple threads
 +
attempt to share the same resources without a spinlock.
 +
 +
If unsure, say Y.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL || console || bool || Serial port console output ||
 +
Send coreboot debug output to a serial port.
 +
 +
The type of serial port driver selected based on your configuration is
 +
shown on the following menu line. Supporting multiple different types
 +
of UARTs in one build is not supported.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || I/O mapped, 8250-compatible ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || memory mapped, 8250-compatible ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || device-specific UART ||
 +
|- bgcolor="#eeeeee"
 +
| TTYS0_BASE || console || hex ||  ||
 +
Map the COM port number to the respective I/O port.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
 +
Set serial port Baud rate to 115200.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
 +
Set serial port Baud rate to 57600.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
 +
Set serial port Baud rate to 38400.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
 +
Set serial port Baud rate to 19200.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
 +
Set serial port Baud rate to 9600.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TTYS0_BAUD || console || int ||  ||
 +
Map the Baud rates to an integer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPKMODEM || console || bool || spkmodem (console on speaker) console output ||
 +
Send coreboot debug output through speaker
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_USB || console || bool || USB dongle console output ||
 +
Send coreboot debug output to USB.
 +
 +
Configuration for USB hardware is under menu Generic Drivers.
  
 
||
 
||
Line 779: Line 3,222:
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||  
 
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||  
This is IP adress of the system running for example
+
This is IP address of the system running for example
 
netcat command to dump the packets.
 
netcat command to dump the packets.
  
Line 794: Line 3,237:
 
32 bytes of IO spaces will be used (and align on 32 bytes
 
32 bytes of IO spaces will be used (and align on 32 bytes
 
boundary, qemu needs broader align)
 
boundary, qemu needs broader align)
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||  
+
| CONSOLE_CBMEM || console || bool || Send console output to a CBMEM buffer ||  
Way too many details.
+
Enable this to save the console output in a CBMEM buffer. This would
 +
allow to see coreboot console output from Linux space.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||  
+
| CONSOLE_CBMEM_BUFFER_SIZE || console || hex || Room allocated for console output in CBMEM ||  
Debug-level messages.
+
Space allocated for console output storage in CBMEM. The default
 +
value (128K or 0x20000 bytes) is large enough to accommodate
 +
even the BIOS_SPEW level.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
+
| CONSOLE_CBMEM_DUMP_TO_UART || console || bool || Dump CBMEM console on resets ||  
Informational messages.
+
Enable this to have CBMEM console buffer contents dumped on the
||
+
serial output in case serial console is disabled and the device
|- bgcolor="#eeeeee"
+
resets itself while trying to boot the payload.
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||  
+
Normal but significant conditions.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
+
Warning conditions.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
+
Error conditions.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
+
Critical conditions.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
+
Action must be taken immediately.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
+
System is unusable.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||  
+
| CONSOLE_QEMU_DEBUGCON || console || bool || QEMU debug console output ||  
Map the log level config names to an integer.
+
Send coreboot debug output to QEMU's isa-debugcon device:
 +
 
 +
qemu-system-x86_64 \
 +
-chardev file,id=debugcon,path=/dir/file.log \
 +
-device isa-debugcon,iobase=0x402,chardev=debugcon
  
 
||
 
||
Line 879: Line 3,308:
 
| DEFAULT_CONSOLE_LOGLEVEL || console || int ||  ||  
 
| DEFAULT_CONSOLE_LOGLEVEL || console || int ||  ||  
 
Map the log level config names to an integer.
 
Map the log level config names to an integer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST || console || bool || Store post codes in CMOS for debugging ||
 +
If enabled, coreboot will store post codes in CMOS and switch between
 +
two offsets on each boot so the last post code in the previous boot
 +
can be retrieved.  This uses 3 bytes of CMOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST_OFFSET || console || hex || Offset into CMOS to store POST codes ||
 +
If CMOS_POST is enabled then an offset into CMOS must be provided.
 +
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
 +
defined in the mainboard option table.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST_EXTRA || console || bool || Store extra logging info into CMOS ||
 +
This will enable extra logging of work that happens between post
 +
codes into CMOS for debug.  This uses an additional 8 bytes of CMOS.
  
 
||
 
||
Line 886: Line 3,335:
 
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
 
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
 
device) on the debug console.
 
device) on the debug console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POST_IO || console || bool || Send POST codes to an IO port ||
 +
If enabled, POST codes will be written to an IO port.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POST_IO_PORT || console || hex || IO port for POST codes ||
 +
POST codes on x86 are typically written to the LPC bus on port
 +
0x80. However, it may be desirable to change the port number
 +
depending on the presence of coprocessors/microcontrollers or if the
 +
platform does not support IO in the conventional x86 manner.
  
 
||
 
||
Line 893: Line 3,355:
 
This variable specifies whether a given board has a hard_reset
 
This variable specifies whether a given board has a hard_reset
 
function, no matter if it's provided by board code or chipset code.
 
function, no matter if it's provided by board code or chipset code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MONOTONIC_TIMER || toplevel || bool ||  ||
 +
The board/chipset provides a monotonic timer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GENERIC_UDELAY || toplevel || bool ||  ||
 +
The board/chipset uses a generic udelay function utilizing the
 +
monotonic timer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TIMER_QUEUE || toplevel || bool ||  ||
 +
Provide a timer queue for performing time-based callbacks.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COOP_MULTITASKING || toplevel || bool ||  ||
 +
Cooperative multitasking allows callbacks to be multiplexed on the
 +
main thread of ramstage. With this enabled it allows for multiple
 +
execution paths to take place when they have udelay() calls within
 +
their code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NUM_THREADS || toplevel || int ||  ||
 +
How many execution threads to cooperatively multitask with.
  
 
||
 
||
Line 900: Line 3,391:
 
file containing NVRAM/CMOS bit definitions.
 
file containing NVRAM/CMOS bit definitions.
 
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
 
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM ||
 +
This is the part of the ROM actually managed by CBFS, located at the
 +
end of the ROM (passed through cbfstool -o) on x86 and at at the start
 +
of the ROM (passed through cbfstool -s) everywhere else. Defaults to
 +
span the whole ROM but can be overwritten to make coreboot live
 +
alongside other components (like ChromeOS's vboot/FMAP).
  
 
||
 
||
Line 916: Line 3,416:
 
This variable specifies whether a given board has ACPI table support.
 
This variable specifies whether a given board has ACPI table support.
 
It is usually set in mainboard/*/Kconfig.
 
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
 
is configurable by the user via GENERATE_ACPI_TABLES.
 
  
 
||
 
||
Line 936: Line 3,434:
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: System tables || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||  
+
| MAX_PIRQ_LINKS || toplevel || int || ||  
Generate ACPI tables for this board.
+
This variable specifies the number of PIRQ interrupt links which are
 
+
routable. On most chipsets, this is 4, INTA through INTD. Some
If unsure, say Y.
+
chipsets offer more than four links, commonly up to INTH. They may
 +
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
 +
table specifies links greater than 4, pirq_route_irqs will not
 +
function properly, unless this variable is correctly set.
  
 
||
 
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: System tables || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||  
 
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||  
Line 965: Line 3,466:
  
 
If unsure, say Y.
 
If unsure, say Y.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SERIAL_NUMBER || toplevel || string || SMBIOS Serial Number ||
 +
The Serial Number to store in SMBIOS structures.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_VERSION || toplevel || string || SMBIOS Version Number ||
 +
The Version Number to store in SMBIOS structures.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SMBIOS_MANUFACTURER || toplevel || string || SMBIOS Manufacturer ||
 +
Override the default Manufacturer stored in SMBIOS structures.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SMBIOS_PRODUCT_NAME || toplevel || string || SMBIOS Product name ||
 +
Override the default Product name stored in SMBIOS structures.
  
 
||
 
||
Line 985: Line 3,506:
 
which coreboot should run as soon as the basic hardware
 
which coreboot should run as soon as the basic hardware
 
initialization is completed.
 
initialization is completed.
 +
 +
You will be able to specify the location and file name of the
 +
payload image later.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_LINUX || toplevel || bool || A Linux payload ||
 +
Select this option if you have a Linux bzImage which coreboot
 +
should run as soon as the basic hardware initialization
 +
is completed.
  
 
You will be able to specify the location and file name of the
 
You will be able to specify the location and file name of the
Line 1,009: Line 3,540:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || stable ||  
+
| PAYLOAD_GRUB2 || toplevel || bool || GRUB2 ||  
Stable SeaBIOS version
+
Select this option if you want to build a coreboot image
 +
with a GRUB2 payload. If you don't know what this is
 +
about, just leave it enabled.
 +
 
 +
See http://coreboot.org/Payloads for more information.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||  
+
| PAYLOAD_TIANOCORE || toplevel || bool || Tiano Core ||  
Newest SeaBIOS version
+
Select this option if you want to build a coreboot image
 +
with a Tiano Core payload. If you don't know what this is
 +
about, just leave it enabled.
 +
 
 +
See http://coreboot.org/Payloads for more information.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||  
+
| SEABIOS_STABLE || toplevel || bool || 1.7.5 ||  
Stable FILO version
+
Stable SeaBIOS version
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||  
+
| SEABIOS_MASTER || toplevel || bool || master ||  
Newest FILO version
+
Newest SeaBIOS version
||
+
|- bgcolor="#eeeeee"
+
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||
+
The path and filename of the ELF executable file to use as payload.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||  
+
| SEABIOS_PS2_TIMEOUT || toplevel || int || PS/2 keyboard controller initialization timeout (milliseconds) ||  
In order to reduce the size payloads take up in the ROM chip
+
Some PS/2 keyboard controllers don't respond to commands immediately
coreboot can compress them using the LZMA algorithm.
+
after powering on. This specifies how long SeaBIOS will wait for the
 +
keyboard controller to become ready before giving up.
  
 
||
 
||
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: VGA BIOS || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||  
+
| SEABIOS_THREAD_OPTIONROMS || toplevel || bool || Hardware init during option ROM execution ||  
Select this option if you have a VGA BIOS image that you would
+
Allow hardware init to run in parallel with optionrom execution.
like to add to your ROM.
+
  
You will be able to specify the location and file name of the
+
This can reduce boot time, but can cause some timing
image later.
+
variations during option ROM code execution. It is not
 +
known if all option ROMs will behave properly with this option.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||  
+
| SEABIOS_MALLOC_UPPERMEMORY || toplevel || bool || ||  
The path and filename of the file to use as VGA BIOS.
+
Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
 +
"low memory" allocations.  If this is not selected, the memory is
 +
instead allocated from the "9-segment" (0x90000-0xa0000).
 +
This is not typically needed, but may be required on some platforms
 +
to allow USB and SATA buffers to be written correctly by the
 +
hardware.  In general, if this is desired, the option will be
 +
set to 'N' by the chipset Kconfig.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||  
+
| SEABIOS_VGA_COREBOOT || toplevel || bool || Include generated option rom that implements legacy VGA BIOS compatibility ||  
The comma-separated PCI vendor and device ID that would associate
+
Coreboot can initialize the GPU of some mainboards.
your VGA BIOS to your video card.
+
  
Example: 1106,3230
+
After initializing the GPU, the information about it can be passed to the payload.
 +
Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
  
In the above example 1106 is the PCI vendor ID (in hex, but without
+
||
the "0x" prefix) and 3230 specifies the PCI device ID of the
+
|- bgcolor="#eeeeee"
video card (also in hex, without "0x" prefix).
+
| GRUB2_MASTER || toplevel || bool || HEAD ||
 +
Newest GRUB2 version
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||  
+
| FILO_STABLE || toplevel || bool || 0.6.0 ||  
Select this option if you have an Intel MBI image that you would
+
Stable FILO version
like to add to your ROM.
+
 
+
You will be able to specify the location and file name of the
+
image later.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MBI_FILE || toplevel || string || Intel MBI path and filename ||  
+
| FILO_MASTER || toplevel || bool || HEAD ||  
The path and filename of the file to use as VGA BIOS.
+
Newest FILO version
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||
 +
The path and filename of the ELF executable file to use as payload.
  
|- bgcolor="#6699dd"
+
||
! align="left" | Menu: Display || || || ||
+
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || toplevel || bool || Set VESA framebuffer mode ||  
+
| PAYLOAD_FILE || toplevel || string || Linux path and filename ||  
Set VESA framebuffer mode (needed for bootsplash)
+
The path and filename of the bzImage kernel to use as payload.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||  
+
| PAYLOAD_FILE || toplevel || string || Tianocore firmware volume ||  
This option sets the resolution used for the coreboot framebuffer (and
+
The result of a corebootPkg build
bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
+
some day make this a "choice".
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_KEEP_VESA_MODE || toplevel || bool || Keep VESA framebuffer ||  
+
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||  
This option keeps the framebuffer mode set after coreboot finishes
+
In order to reduce the size payloads take up in the ROM chip
execution. If this option is enabled, coreboot will pass a
+
coreboot can compress them using the LZMA algorithm.
framebuffer entry in its coreboot table and the payload will need a
+
framebuffer driver. If this option is disabled, coreboot will switch
+
back to text mode before handing control to a payload.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||  
+
| LINUX_COMMAND_LINE || toplevel || string || Linux command line ||  
This option shows a graphical bootsplash screen. The grapics are
+
A command line to add to the Linux kernel.
loaded from the CBFS file bootsplash.jpg.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||  
+
| LINUX_INITRD || toplevel || string || Linux initrd ||  
The path and filename of the file to use as graphical bootsplash
+
An initrd image to add to the Linux kernel.
screen. The file format has to be jpg.
+
 
 
||
 
||
  
Line 1,120: Line 3,654:
 
If enabled, you will be able to set breakpoints for gdb debugging.
 
If enabled, you will be able to set breakpoints for gdb debugging.
 
See src/arch/x86/lib/c_start.S for details.
 
See src/arch/x86/lib/c_start.S for details.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GDB_WAIT || toplevel || bool || Wait for a GDB connection ||
 +
If enabled, coreboot will wait for a GDB connection.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FATAL_ASSERTS || toplevel || bool || Halt when hitting a BUG() or assertion error ||
 +
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_CBFS || toplevel || bool || Output verbose CBFS debug messages ||
 +
This option enables additional CBFS related debug messages.
  
 
||
 
||
Line 1,177: Line 3,726:
  
 
If unsure, say N.
 
If unsure, say N.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,185: Line 3,735:
  
 
If unsure, say N.
 
If unsure, say N.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,193: Line 3,744:
  
 
If unsure, say N.
 
If unsure, say N.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,308: Line 3,860:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LLSHELL || toplevel || bool || Built-in low-level shell ||  
+
| X86EMU_DEBUG_TIMINGS || toplevel || bool || Output timing information ||  
If enabled, you will have a low level shell to examine your machine.
+
Print timing information needed by i915tool.
Put llshell() in your (romstage) code to start the shell.
+
 
See src/arch/x86/llshell/llshell.inc for details.
+
If unsure, say N.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_TPM || toplevel || bool || Output verbose TPM debug messages ||
 +
This option enables additional TPM related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SPI_FLASH || toplevel || bool || Output verbose SPI flash debug messages ||
 +
This option enables additional SPI flash related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_USBDEBUG || toplevel || bool || Output verbose USB 2.0 EHCI debug dongle messages ||
 +
This option enables additional USB 2.0 debug dongle related messages.
 +
 +
Select this to debug the connection of usbdebug dongle. Note that
 +
you need some other working console to receive the messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_INTEL_ME || toplevel || bool || Verbose logging for Intel Management Engine ||
 +
Enable verbose logging for Intel Management Engine driver that
 +
is present on Intel 6-series chipsets.
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,321: Line 3,896:
 
of calling function. Please note some printk releated functions
 
of calling function. Please note some printk releated functions
 
are omitted from trace to have good looking console dumps.
 
are omitted from trace to have good looking console dumps.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_COVERAGE || toplevel || bool || Debug code coverage ||
 +
If enabled, the code coverage hooks in coreboot will output some
 +
information about the coverage data that is dumped.
 +
 
||
 
||
  
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || bool ||  ||  
 
Select when the board has a power button which can optionally be
 
Select when the board has a power button which can optionally be
 
disabled by the user.
 
disabled by the user.
Line 1,330: Line 3,912:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || bool ||  ||  
 
Select when the board has a power button which can optionally be
 
Select when the board has a power button which can optionally be
 
enabled by the user, e.g. when the board ships with a jumper over
 
enabled by the user, e.g. when the board ships with a jumper over
Line 1,337: Line 3,919:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_FORCE_ENABLE || toplevel || bool ||  ||  
 
Select when the board requires that the power button is always
 
Select when the board requires that the power button is always
 
enabled.
 
enabled.
Line 1,343: Line 3,925:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_FORCE_DISABLE || toplevel || bool ||  ||  
 
Select when the board requires that the power button is always
 
Select when the board requires that the power button is always
 
disabled, e.g. when it has been hardwired to ground.
 
disabled, e.g. when it has been hardwired to ground.
Line 1,353: Line 3,935:
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: Deprecated || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool ||  ||  
+
| REG_SCRIPT || toplevel || bool ||  ||  
This variable specifies whether a given board has a reset.c
+
Internal option that controls whether we compile in register scripts.
file containing a hard_reset() function.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_HAS_FADT || toplevel.deprecated_options || bool ||  ||  
+
| MAX_REBOOT_CNT || toplevel || int ||  ||  
This variable specifies whether a given board has a board-local
+
Internal option that sets the maximum number of bootblock executions allowed
FADT in fadt.c. Long-term, those should be moved to appropriate
+
with the normal image enabled before assuming the normal image is defective
chipset components (eg. southbridge).
+
and switching to the fallback image.
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool ||  ||
 
This variable specifies whether a given board has a get_bus_conf.c
 
file containing information about bus routing.
 
 
||
 
|- bgcolor="#eeeeee"
 
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init ||
 
Enable this option to initialize PS/2 keyboards found connected
 
to the PS/2 port.
 
 
Some payloads (eg, filo) require this option.  Other payloads
 
(eg, SeaBIOS, Linux) do not require it.
 
Initializing a PS/2 keyboard can take several hundred milliseconds.
 
 
If you know you will only use a payload which does not require
 
this option, then you can say N here to speed up boot time.
 
Otherwise say Y.
 
 
||
 
|- bgcolor="#eeeeee"
 
| PCIE_TUNING || toplevel.deprecated_options || bool ||  ||
 
This variable enables certain PCIe optimizations. Right now it's
 
only ASPM and it's untested.
 
 
||
 
 
 
|}
 
|}

Latest revision as of 23:24, 5 May 2015

This is an automatically generated list of coreboot compile-time options.

Last update: 2015/05/05 16:17:26. (r4.0-9599-g40c26df-dirty)

Option Source Format Short Description Description
Menu: General setup
EXPERT toplevel bool Expert mode

This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are doing! You have been warned!

LOCALVERSION toplevel string Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.

CBFS_PREFIX toplevel string CBFS prefix to use

Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative.

COMMON_CBFS_SPI_WRAPPER toplevel bool

Use common wrapper to interface CBFS to SPI bootrom.

MULTIPLE_CBFS_INSTANCES toplevel bool Multiple CBFS instances in the bootrom

Account for the firmware image containing more than one CBFS instance. Locations of instances are known at build time and are communicated between coreboot stages to make sure the next stage is loaded from the appropriate instance.

MULTIPLE_CBFS_INSTANCES toplevel bool Compiler to use

This option allows you to select the compiler used for building coreboot.

COMPILER_GCC toplevel bool GCC

Use the GNU Compiler Collection (GCC) to build coreboot.

For details see http://gcc.gnu.org.

COMPILER_LLVM_CLANG toplevel bool LLVM/clang

Use LLVM/clang to build coreboot.

For details see http://clang.llvm.org.

ANY_TOOLCHAIN toplevel bool Allow building with any toolchain

Many toolchains break when building coreboot since it uses quite unusual linker features. Unless developers explicitely request it, we'll have to assume that they use their distro compiler by mistake. Make sure that using patched compilers is a conscious decision.

CCACHE toplevel bool Use ccache to speed up (re)compilation

Enables the use of ccache for faster builds.

Requires the ccache utility in your system $PATH.

For details see https://ccache.samba.org.

SCONFIG_GENPARSER toplevel bool Generate SCONFIG parser using flex and bison

Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and sconfig.y.

Otherwise, say N.

USE_OPTION_TABLE toplevel bool Use CMOS for configuration values

Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values.

STATIC_OPTION_TABLE toplevel bool Load default configuration values into CMOS on each boot

Enable this option to reset "CMOS" NVRAM values to default on every boot. Use this if you want the NVRAM configuration to never be modified from its default values.

COMPRESS_RAMSTAGE toplevel bool Compress ramstage with LZMA

Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI).

INCLUDE_CONFIG_FILE toplevel bool Include the coreboot .config file into the ROM image

Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which options were used to build a specific coreboot.rom image.

Saying Y here will increase the image size by 2-3KB.

You can use the following command to easily list the options:

grep -a CONFIG_ coreboot.rom

Alternatively, you can also use cbfstool to print the image contents (including the raw 'config' item we're looking for).

Example:

$ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes

Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 fallback/ramstage 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440

COLLECT_TIMESTAMPS toplevel bool Create a table of timestamps collected during boot

Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.

USE_BLOBS toplevel bool Allow use of binary-only repository

This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users.

COVERAGE toplevel bool Code coverage support

Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. If unsure, say N.

RELOCATABLE_MODULES toplevel bool Relocatable Modules

If RELOCATABLE_MODULES is selected then support is enabled for building relocatable modules in the RAM stage. Those modules can be loaded anywhere and all the relocations are handled automatically.

RELOCATABLE_RAMSTAGE toplevel bool Build the ramstage to be relocatable in 32-bit address space.

The reloctable ramstage support allows for the ramstage to be built as a relocatable module. The stage loader can identify a place out of the OS way so that copying memory is unnecessary during an S3 wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage.

CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM toplevel bool Cache the relocated ramstage outside of cbmem.

The relocated ramstage is saved in an area specified by the by the board and/or chipset.

SKIP_MAX_REBOOT_CNT_CLEAR toplevel bool Do not clear reboot count after successful boot

Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery.

UPDATE_IMAGE toplevel bool Update existing coreboot.rom image

If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified.

GENERIC_GPIO_LIB toplevel bool

If enabled, compile the generic GPIO library. A "generic" GPIO implies configurability usually found on SoCs, particularly the ability to control internal pull resistors.

BOARD_ID_AUTO toplevel bool

Mainboards that can read a board ID from the hardware straps (ie. GPIO) select this configuration option.

BOARD_ID_MANUAL toplevel bool Add board ID file to CBFS

If you want to maintain a board ID, but the hardware does not have straps to automatically determine the ID, you can say Y here and add a file named 'board_id' to CBFS. If you don't know what this is about, say N.

BOARD_ID_STRING toplevel string Board ID

This string is placed in the 'board_id' CBFS file for indicating board type.

RAM_CODE_SUPPORT toplevel bool Discover RAM configuration code and store it in coreboot table

If enabled, coreboot discovers RAM configuration (value obtained by reading board straps) and stores it in coreboot table.

Menu: Mainboard
(comment) see under vendor LiPPERT
BOARD_ASUS_F2A85_M_DDR3_VOLT_135 mainboard/asus/f2a85-m bool 1.35V

Set DRR3 memory voltage to 1.35V

BOARD_ASUS_F2A85_M_DDR3_VOLT_150 mainboard/asus/f2a85-m bool 1.50V

Set DRR3 memory voltage to 1.50V

BOARD_ASUS_F2A85_M_DDR3_VOLT_165 mainboard/asus/f2a85-m bool 1.65V

Set DRR3 memory voltage to 1.65V

BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135 mainboard/asus/f2a85-m_le bool 1.35V

Set DRR3 memory voltage to 1.35V

BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150 mainboard/asus/f2a85-m_le bool 1.50V

Set DRR3 memory voltage to 1.50V

BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165 mainboard/asus/f2a85-m_le bool 1.65V

Set DRR3 memory voltage to 1.65V

Menu: On-Chip Device Power Down Control
Menu: Watchdog Timer setting
Menu: IDE controller setting
IDE_STANDARD_COMPATIBLE mainboard/dmp/vortex86ex bool Standard IDE Compatible

Built-in IDE controller PCI vendor/device ID is 17F3:1012, which is not recognized by some OSes.

This option can change IDE controller PCI vendor/device ID to other value for software compatibility.

IDE_COMPATIBLE_SELECTION mainboard/dmp/vortex86ex hex IDE Compatible Selection

IDE controller PCI vendor/device ID value setting.

Higher 16-bit is vendor ID, lower 16-bit is device ID.

Menu: GPIO setting
Menu: UART setting
Menu: LPT setting
UART_FOR_CONSOLE mainboard/intel/mohonpeak int

The Mohon Peak board uses COM2 (2f8) for the serial console.

SEABIOS_MALLOC_UPPERMEMORY mainboard/intel/mohonpeak bool

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

MAINBOARD_PART_NUMBER mainboard/google/nyan_blaze string BCT boot media

Which boot media to configure the BCT for.

NYAN_BLAZE_BCT_CFG_SPI mainboard/google/nyan_blaze bool SPI

Configure the BCT for booting from SPI.

NYAN_BLAZE_BCT_CFG_EMMC mainboard/google/nyan_blaze bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/nyan_blaze int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/nyan_blaze int Chip select for SPI boot media

Which chip select to use for boot media.

MAINBOARD_PART_NUMBER mainboard/google/nyan string BCT boot media

Which boot media to configure the BCT for.

NYAN_BCT_CFG_SPI mainboard/google/nyan bool SPI

Configure the BCT for booting from SPI.

NYAN_BCT_CFG_EMMC mainboard/google/nyan bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/nyan int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/nyan int Chip select for SPI boot media

Which chip select to use for boot media.

MAINBOARD_PART_NUMBER mainboard/google/rush_ryu string BCT boot media

Which boot media to configure the BCT for.

RUSH_RYU_BCT_CFG_SPI mainboard/google/rush_ryu bool SPI

Configure the BCT for booting from SPI.

RUSH_RYU_BCT_CFG_EMMC mainboard/google/rush_ryu bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/rush_ryu int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/rush_ryu int Chip select for SPI boot media

Which chip select to use for boot media.

MAINBOARD_PART_NUMBER mainboard/google/nyan_big string BCT boot media

Which boot media to configure the BCT for.

NYAN_BIG_BCT_CFG_SPI mainboard/google/nyan_big bool SPI

Configure the BCT for booting from SPI.

NYAN_BIG_BCT_CFG_EMMC mainboard/google/nyan_big bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/nyan_big int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/nyan_big int Chip select for SPI boot media

Which chip select to use for boot media.

DRAM_SIZE_MB mainboard/google/rush int BCT boot media

Which boot media to configure the BCT for.

RUSH_BCT_CFG_SPI mainboard/google/rush bool SPI

Configure the BCT for booting from SPI.

RUSH_BCT_CFG_EMMC mainboard/google/rush bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/rush int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/rush int Chip select for SPI boot media

Which chip select to use for boot media.

ENABLE_DP3_DAUGHTER_CARD_IN_J120 mainboard/amd/lamar bool Use J120 as an additional graphics port

The PCI Express slot at J120 can be configured as an additional DisplayPort connector using an adapter card from AMD or as a normal PCI Express (x4) slot.

By default, the connector is configured as a PCI Express (x4) slot.

Select this option to enable the slot for use with one of AMD's passive graphics port expander cards (only available from AMD).

(comment) was acquired by ADLINK
ONBOARD_UARTS_RS485 mainboard/lippert/literunner-lx bool Switch on-board serial ports 1 & 2 to RS485

If selected, the first two on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/literunner-lx bool Make on-board CF socket act as Slave

If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master.

BOARD_OLD_REVISION mainboard/lippert/hurricane-lx bool Board is old pre-3.0 revision

Look on the bottom side for a number like 406-0001-30. The last 2 digits state the PCB revision (3.0 in this example). For 2.0 or older boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to power on automatically. You may enable the button only after this jumper has been removed. New revision boards are not restricted in this way, and always have the power button enabled.

ONBOARD_UARTS_RS485 mainboard/lippert/hurricane-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_UARTS_RS485 mainboard/lippert/spacerunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/spacerunner-lx bool Make on-board SSD act as Slave

If selected, the on-board SSD will act as IDE Slave instead of Master.

ONBOARD_UARTS_RS485 mainboard/lippert/roadrunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

BOARD_ROMSIZE_KB_16384 mainboard bool ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file of the matching size.

COREBOOT_ROMSIZE_KB_64 mainboard bool 64 KB

Choose this option if you have a 64 KB ROM chip.

COREBOOT_ROMSIZE_KB_128 mainboard bool 128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256 mainboard bool 256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512 mainboard bool 512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024 mainboard bool 1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048 mainboard bool 2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096 mainboard bool 4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

COREBOOT_ROMSIZE_KB_8192 mainboard bool 8192 KB (8 MB)

Choose this option if you have a 8192 KB (8 MB) ROM chip.

COREBOOT_ROMSIZE_KB_12288 mainboard bool 12288 KB (12 MB)

Choose this option if you have a 12288 KB (12 MB) ROM chip.

COREBOOT_ROMSIZE_KB_16384 mainboard bool 16384 KB (16 MB)

Choose this option if you have a 16384 KB (16 MB) ROM chip.

ENABLE_POWER_BUTTON mainboard bool Enable the power button

The selected mainboard can optionally have the power button tied to ground with a jumper so that the button appears to be constantly depressed. If this option is enabled and the jumper is installed then the board will turn on, but turn off again after a short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an actual power button. Select N if you have the jumper installed.

LATE_CBMEM_INIT arch/x86 bool

Enable this in chipset's Kconfig if northbridge does not implement early get_top_of_ram() call for romstage. CBMEM tables will be allocated late in ramstage, after PCI devices resources are known.

Menu: ChromeOS
CHROMEOS vendorcode/google/chromeos bool Build for ChromeOS

Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build.

VBNV_OFFSET vendorcode/google/chromeos hex

CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC.

VBNV_SIZE vendorcode/google/chromeos hex

CMOS storage size for VbNv data. This value must match cmos.layout in the mainboard directory.

CHROMEOS_VBNV_CMOS vendorcode/google/chromeos bool Vboot non-volatile storage in CMOS.

VBNV is stored in CMOS

CHROMEOS_VBNV_EC vendorcode/google/chromeos bool Vboot non-volatile storage in EC.

VBNV is stored in EC

CHROMEOS_VBNV_FLASH vendorcode/google/chromeos bool

VBNV is stored in flash storage

FLASHMAP_OFFSET vendorcode/google/chromeos hex Flash Map Offset

Offset of flash map in firmware image

EC_SOFTWARE_SYNC vendorcode/google/chromeos bool Enable EC software sync

EC software sync is a mechanism where the AP helps the EC verify its firmware similar to how vboot verifies the main system firmware. This option selects whether depthcharge should support EC software sync.

VBOOT_EC_SLOW_UPDATE vendorcode/google/chromeos bool EC is slow to update

Whether the EC (or PD) is slow to update and needs to display a screen that informs the user the update is happening.

VBOOT_OPROM_MATTERS vendorcode/google/chromeos bool Video option ROM matters

Whether the video option ROM has run matters on this platform.

VIRTUAL_DEV_SWITCH vendorcode/google/chromeos bool Virtual developer switch support

Whether this platform has a virtual developer switch.

VBOOT_VERIFY_FIRMWARE vendorcode/google/chromeos bool Verify firmware with vboot.

Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components of the firmware (stages, payload, etc).

NO_TPM_RESUME vendorcode/google/chromeos bool

On some boards the TPM stays powered up in S3. On those boards, booting Windows will break if the TPM resume command is sent during an S3 resume.

PHYSICAL_REC_SWITCH vendorcode/google/chromeos bool Physical recovery switch is present

Whether this platform has a physical recovery switch

WIPEOUT_SUPPORTED vendorcode/google/chromeos bool User is able to request factory reset

When this option is enabled, the firmware provides the ability to signal the application the need for factory reset (a.k.a. wipe out) of the device

VBOOT_STARTS_IN_BOOTBLOCK vendorcode/google/chromeos/vboot2 bool

Firmware verification happens during or at the end of bootblock.

VBOOT_STARTS_IN_ROMSTAGE vendorcode/google/chromeos/vboot2 bool

Firmware verification happens during or at the end of romstage.

VBOOT2_MOCK_SECDATA vendorcode/google/chromeos/vboot2 bool Mock secdata for firmware verification

Enabling VBOOT2_MOCK_SECDATA will mock secdata for the firmware verification to avoid access to a secdata storage (typically TPM). All operations for a secdata storage will be successful. This option can be used during development when a TPM is not present or broken. THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.

VBOOT_DISABLE_DEV_ON_RECOVERY vendorcode/google/chromeos/vboot2 bool Disable dev mode on recovery requests

When this option is enabled, the Chrome OS device leaves the developer mode as soon as recovery request is detected. This is handy on embedded devices with limited input capabilities.

RETURN_FROM_VERSTAGE vendorcode/google/chromeos/vboot2 bool

If this is set, the verstage returns back to the calling stage instead of exiting to the succeeding stage so that the verstage space can be reused by the succeeding stage. This is useful if a ram space is too small to fit both the verstage and the succeeding stage.

VBOOT_ROMSTAGE_INDEX vendorcode/google/chromeos/vboot2 hex Romstage component index

This is the index of the romstage component in the verified firmware block.

VBOOT_RAMSTAGE_INDEX vendorcode/google/chromeos/vboot2 hex Ramstage component index

This is the index of the ramstage component in the verified firmware block.

VBOOT_REFCODE_INDEX vendorcode/google/chromeos/vboot2 hex Reference code firmware index

This is the index of the reference code component in the verified firmware block.

VBOOT_BOOT_LOADER_INDEX vendorcode/google/chromeos/vboot2 hex Bootloader component index

This is the index of the bootloader component in the verified firmware block.

VIRTUAL_DEV_SWITCH vendorcode/google/chromeos bool

Whether this platform has a virtual developer switch.

Menu: AMD Platform Initialization
AGESA_BINARY_PI_PATH_DEFAULT vendorcode/amd/pi/00630F01 string

The default binary file name to use for AMD platform initialization.

AGESA_BINARY_PI_FILE_DEFAULT vendorcode/amd/pi/00630F01 string

The default binary file name to use for AMD platform initialization.

AGESA_BINARY_PI_LOCATION_DEFAULT vendorcode/amd/pi/00630F01 hex

The default ROM address at which to store the binary Platform Initialization code.

AGESA_BINARY_PI_PATH_DEFAULT vendorcode/amd/pi/00730F01 string

The default binary file name to use for AMD platform initialization.

AGESA_BINARY_PI_FILE_DEFAULT vendorcode/amd/pi/00730F01 string

The default binary file name to use for AMD platform initialization.

AGESA_BINARY_PI_LOCATION_DEFAULT vendorcode/amd/pi/00730F01 hex

The default ROM address at which to store the binary Platform Initialization code.

None vendorcode/amd None AGESA source

Select the method for including the AMD Platform Initialization code into coreboot. Platform Initialization code is required for all AMD processors.

CPU_AMD_AGESA_BINARY_PI vendorcode/amd bool binary PI

Use a binary PI package. Generally, these will be stored in the "3rdparty" directory. For some processors, these must be obtained directly from AMD Embedded Processors Group (http://www.amdcom/embedded).

CPU_AMD_AGESA_OPENSOURCE vendorcode/amd bool open-source AGESA

Build the PI package ("AGESA") from source code in the "vendorcode" directory.

AGESA_BINARY_PI_PATH vendorcode/amd string AGESA PI directory path

Specify where to find the AGESA headers and binary file for AMD platform initialization.

AGESA_BINARY_PI_FILE vendorcode/amd string AGESA PI binary file name

Specify the binary file to use for AMD platform initialization.

AGESA_BINARY_PI_LOCATION vendorcode/amd string AGESA PI binary address in ROM

Specify the ROM address at which to store the binary Platform Initialization code.

Menu: Chipset
(comment) CPU
LAPIC_MONOTONIC_TIMER cpu/x86 bool

Expose monotonic time using the local apic.

TSC_CONSTANT_RATE cpu/x86 bool

This option asserts that the TSC ticks at a known constant rate. Therefore, no TSC calibration is required.

TSC_MONOTONIC_TIMER cpu/x86 bool

Expose monotonic time using the TSC.

TSC_SYNC_LFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an lfence instruction in order to synchronize rdtsc. This is true for all modern AMD CPUs.

TSC_SYNC_MFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs.

SMM_MODULES cpu/x86 bool

If SMM_MODULES is selected then SMM handlers are built as modules. A SMM stub along with a SMM loader/relocator. All the handlers are written in C with stub being the only assembly.

SMM_MODULE_HEAP_SIZE cpu/x86 hex

This option determines the size of the heap within the SMM handler modules.

X86_AMD_FIXED_MTRRS cpu/x86 bool

This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs.

PLATFORM_USES_FSP1_0 cpu/x86 bool

Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization.

PARALLEL_MP cpu/x86 bool

This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs.

BACKUP_DEFAULT_SMM_REGION cpu/x86 bool

The CPU support will select this option if the default SMM region needs to be backed up for suspend/resume purposes.

MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING cpu/x86 bool

On certain platforms a boot speed gain can be realized if mirroring the payload data stored in non-volatile storage. On x86 systems the payload would typically live in a memory-mapped SPI part. Copying the SPI contents to RAM before performing the load can speed up the boot process.

BOOT_MEDIA_SPI_BUS cpu/x86 int

Most x86 systems which boot from SPI flash boot using bus 0.

RESET_ON_INVALID_RAMSTAGE_CACHE cpu/intel/haswell bool Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

MONOTONIC_TIMER_MSR cpu/intel/haswell bool

Provide a monotonic timer using the 24MHz MSR counter.

CPU_INTEL_FIRMWARE_INTERFACE_TABLE cpu/intel/fit None

This option selects building a Firmware Interface Table (FIT).

CPU_INTEL_NUM_FIT_ENTRIES cpu/intel/fit int

This option selects the number of empty entries in the FIT table.


CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED cpu/intel/turbo None

This option indicates that the turbo mode setting is not package scoped. i.e. enable_turbo() needs to be called on not just the bsp

GEODE_VSA_FILE cpu/amd/geode_gx2 bool Add a VSA image

Select this option if you have an AMD Geode GX2 vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_gx2 string AMD Geode GX2 VSA path and filename

The path and filename of the file to use as VSA.

GEODE_VSA_FILE cpu/amd/geode_lx bool Add a VSA image

Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_lx string AMD Geode LX VSA path and filename

The path and filename of the file to use as VSA.

XIP_ROM_SIZE cpu/amd/agesa hex

Overwride the default write through caching size as 1M Bytes. On some AMD platforms, one socket supports 2 or more kinds of processor family, compiling several CPU families agesa code will increase the romstage size. In order to execute romstage in place on the flash ROM, more space is required to be set as write through caching.

REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL cpu/amd/agesa/family10 bool Redirect AGESA IDS_HDT_CONSOLE to serial console

This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

CPU_AMD_SOCKET_G34 cpu/amd/agesa/family15 bool

AMD G34 Socket

CPU_AMD_SOCKET_C32 cpu/amd/agesa/family15 bool

AMD C32 Socket

CPU_AMD_SOCKET_AM3R2 cpu/amd/agesa/family15 bool

AMD AM3r2 Socket

REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL cpu/amd/agesa/family15 bool Redirect AGESA IDS_HDT_CONSOLE to serial console

This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

FORCE_AM1_SOCKET_SUPPORT cpu/amd/agesa/family16kb bool

Force AGESA to ignore package type mismatch between CPU and northbridge in memory code. This enables Socket AM1 support with current AGESA version for Kabini platform. Enable this option only if you have Socket AM1 board. Note that the AGESA release shipped with coreboot does not officially support the AM1 socket. Selecting this option might damage your hardware.

XIP_ROM_SIZE cpu/amd/pi hex

Overwride the default write through caching size as 1M Bytes. On some AMD platforms, one socket supports 2 or more kinds of processor family, compiling several CPU families agesa code will increase the romstage size. In order to execute romstage in place on the flash ROM, more space is required to be set as write through caching.

SMP cpu bool

This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.

AP_SIPI_VECTOR cpu hex

This must equal address of ap_sipi_vector from bootblock build.

MMX cpu bool

Select MMX in your socket or model Kconfig if your CPU has MMX streaming SIMD instructions. ROMCC can build more efficient code if it can spill to MMX registers.

SSE cpu bool

Select SSE in your socket or model Kconfig if your CPU has SSE streaming SIMD instructions. ROMCC can build more efficient code if it can spill to SSE (aka XMM) registers.

SSE2 cpu bool

Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available.

CPU_MICROCODE_CBFS_GENERATE cpu bool Generate from tree

Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS file. Microcode will not be hard-coded into ramstage.

The microcode file may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select this option.

CPU_MICROCODE_CBFS_EXTERNAL cpu bool Include external microcode file

Select this option if you want to include an external file containing the CPU microcode. This will be included as a separate file in CBFS. A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot.

The microcode file may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

CPU_MICROCODE_CBFS_NONE cpu bool Do not include microcode updates

Select this option if you do not want CPU microcode included in CBFS. Note that for some CPUs, the microcode is hard-coded into the source tree and is not loaded from CBFS. In this case, microcode will still be updated. There is a push to move all microcode to CBFS, but this change is not implemented for all CPUs.

This option currently applies to: - Intel SandyBridge/IvyBridge - VIA Nano

Microcode may be added to the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

The GOOD: Microcode updates intend to solve issues that have been discovered after CPU production. The expected effect is that systems work as intended with the updated microcode, but we have also seen cases where issues were solved by not applying microcode updates.

The BAD: Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system for this option to have an effect.

The UGLY: A word of CAUTION: some CPUs depend on microcode updates to function correctly. Not updating the microcode may leave the CPU operating at less than optimal performance, or may cause outright hangups. There are CPUs where coreboot cannot properly initialize the CPU without microcode updates For example, if running with the factory microcode, some Intel SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs will hang when changing the frequency.

Make sure you have a way of flashing the ROM externally before selecting this option.

CPU_MICROCODE_FILE cpu string Path and filename of CPU microcode

The path and filename of the file containing the CPU microcode.

(comment) Northbridge
VGA_BIOS_ID northbridge/intel/fsp_sandybridge string

This is the default PCI ID for the sandybridge/ivybridge graphics devices. This string names the vbios ROM in cbfs. The following PCI IDs will be remapped to load this ROM: 0x80860102, 0x8086010a, 0x80860112, 0x80860116 0x80860122, 0x80860126, 0x80860166

CBFS_SIZE northbridge/intel/fsp_sandybridge hex Size of CBFS filesystem in ROM

On Sandybridge and Ivybridge systems the firmware image may have to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware This option specifies the maximum size of the CBFS portion in the firmware image.

FSP_FILE northbridge/intel/fsp_sandybridge/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC northbridge/intel/fsp_sandybridge/fsp hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with the Intel's BCT (tool).

The Ivy Bridge Processor/Panther Point FSP is built with a preferred base address of 0xFFF80000

CBFS_SIZE northbridge/intel/nehalem hex Size of CBFS filesystem in ROM

On Nehalem systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware This option allows to limit the size of the CBFS portion in the firmware image.

CBFS_SIZE northbridge/intel/gm45 hex Size of CBFS filesystem in ROM

On GM45 systems the firmware image may store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware This option allows to limit the size of the CBFS portion in the firmware image.

SDRAMPWR_4DIMM northbridge/intel/i440bx bool

This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong.

If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option.


DCACHE_RAM_SIZE northbridge/intel/haswell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE northbridge/intel/haswell hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE northbridge/intel/haswell hex

The amount of anticipated stack usage from the data cache during pre-ram rom stage execution.

HAVE_MRC northbridge/intel/haswell bool Add a System Agent binary

Select this option to add a System Agent binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE northbridge/intel/haswell string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

CBFS_SIZE northbridge/intel/haswell hex Size of CBFS filesystem in ROM

On Haswell systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image.

PRE_GRAPHICS_DELAY northbridge/intel/haswell int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

HAVE_MRC northbridge/intel/sandybridge bool Add a System Agent binary

Select this option to add a System Agent binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE northbridge/intel/sandybridge string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

CBFS_SIZE northbridge/intel/sandybridge hex Size of CBFS filesystem in ROM

On Sandybridge and Ivybridge systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image.

OVERRIDE_CLOCK_DISABLE northbridge/intel/i945 bool

Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power consumption. However, some boards do not like unused clock signals to be disabled.

MAXIMUM_SUPPORTED_FREQUENCY northbridge/intel/i945 int

If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of.

CHECK_SLFRCS_ON_RESUME northbridge/intel/i945 int

On some boards it may be neccessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, effectively making it impossible to resume.

SET_TSEG_1MB northbridge/intel/fsp_rangeley bool 1 MB

Set the TSEG area to 1 MB.

SET_TSEG_2MB northbridge/intel/fsp_rangeley bool 2 MB

Set the TSEG area to 2 MB.

SET_TSEG_4MB northbridge/intel/fsp_rangeley bool 4 MB

Set the TSEG area to 4 MB.

SET_TSEG_8MB northbridge/intel/fsp_rangeley bool 8 MB

Set the TSEG area to 8 MB.

FSP_FILE northbridge/intel/fsp_rangeley/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC northbridge/intel/fsp_rangeley/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Rangeley FSP is built with a preferred base address of 0xFFF80000

REDIRECT_NBCIMX_TRACE_TO_SERIAL northbridge/amd/cimx/rd890 bool Redirect AMD Northbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Northbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

VGA_BIOS_ID northbridge/amd/pi/00630F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID northbridge/amd/pi/00730F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID northbridge/amd/agesa/family16kb string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

SVI_HIGH_FREQ northbridge/amd/amdfam10 bool

Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

Menu: HyperTransport setup
SVI_HIGH_FREQ northbridge/amd/amdfam10 bool HyperTransport downlink width

This option sets the maximum permissible HyperTransport downlink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

LIMIT_HT_DOWN_WIDTH_16 northbridge/amd/amdfam10 bool HyperTransport uplink width

This option sets the maximum permissible HyperTransport uplink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

(comment) Southbridge
HAVE_CMC southbridge/intel/sch bool Add a CMC state machine binary

Select this option to add a CMC state machine binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

CMC_FILE southbridge/intel/sch string Intel CMC path and filename

The path and filename of the file to use as CMC state machine binary.

SERIRQ_CONTINUOUS_MODE southbridge/intel/bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

BUILD_WITH_FAKE_IFD southbridge/intel/bd82x6x bool Build with a fake IFD

If you don't have an Intel Firmware Descriptor (ifd.bin) for your board, you can select this option and coreboot will build without it. Though, the resulting coreboot.rom will not contain all parts required to get coreboot running on your board. You can however write only the BIOS section to your board's flash ROM and keep the other sections untouched. Unfortunately the current version of flashrom doesn't support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

HAVE_GBE_BIN southbridge/intel/bd82x6x bool Add gigabit ethernet firmware

The integrated gigabit ethernet controller needs a firmware file. Select this if you are going to use the PCH integrated controller and have the firmware.

HAVE_ME_BIN southbridge/intel/bd82x6x bool Add Intel Management Engine firmware

The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME firmware might be provided in coreboot's 3rdparty repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM.

LOCK_MANAGEMENT_ENGINE southbridge/intel/bd82x6x bool Lock Management Engine section

The Intel Management Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

LOCK_SPI_ON_RESUME southbridge/intel/bd82x6x bool Lock all flash ROM sections on S3 resume

If the flash ROM shall be protected against write accesses from the operating system (OS), the locking procedure has to be repeated after each resume from S3. Select this if you never want to update the flash ROM from within your OS. Notice: Even with this option, the write lock has still to be enabled on the normal boot path (e.g. by the payload).

INTEL_LYNXPOINT_LP southbridge/intel/lynxpoint bool

Set this option to y for Lynxpont LP (Haswell ULT).

SERIRQ_CONTINUOUS_MODE southbridge/intel/lynxpoint bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

BUILD_WITH_FAKE_IFD southbridge/intel/lynxpoint bool Build with a fake IFD

If you don't have an Intel Firmware Descriptor (ifd.bin) for your board, you can select this option and coreboot will build without it. Though, the resulting coreboot.rom will not contain all parts required to get coreboot running on your board. You can however write only the BIOS section to your board's flash ROM and keep the other sections untouched. Unfortunately the current version of flashrom doesn't support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

HAVE_ME_BIN southbridge/intel/lynxpoint bool Add Intel Management Engine firmware

The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME firmware might be provided in coreboot's 3rdparty repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM.

ME_MBP_CLEAR_LATE southbridge/intel/lynxpoint bool Defer wait for ME MBP Cleared

If you set this option to y, the Management Engine driver will defer waiting for the MBP Cleared indicator until the finalize step. This can speed up boot time if the ME takes a long time to indicate this status.

FINALIZE_USB_ROUTE_XHCI southbridge/intel/lynxpoint bool Route all ports to XHCI controller in finalize step

If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback.

LOCK_MANAGEMENT_ENGINE southbridge/intel/lynxpoint bool Lock Management Engine section

The Intel Management Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

INCLUDE_ME southbridge/intel/fsp_bd82x6x bool

Include the me.bin and descriptor.bin for Intel PCH. This is usually required for the PCH.

ME_PATH southbridge/intel/fsp_bd82x6x string

The path of the ME and Descriptor files.

LOCK_MANAGEMENT_ENGINE southbridge/intel/fsp_bd82x6x bool Lock Management Engine section

The Intel Management Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

SERIRQ_CONTINUOUS_MODE southbridge/intel/ibexpeak bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

BUILD_WITH_FAKE_IFD southbridge/intel/ibexpeak bool Build with a fake IFD

If you don't have an Intel Firmware Descriptor (ifd.bin) for your board, you can select this option and coreboot will build without it. Though, the resulting coreboot.rom will not contain all parts required to get coreboot running on your board. You can however write only the BIOS section to your board's flash ROM and keep the other sections untouched. Unfortunately the current version of flashrom doesn't support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html


HAVE_ME_BIN southbridge/intel/ibexpeak bool Add Intel Management Engine firmware

The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME firmware might be provided in coreboot's 3rdparty repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM.

LOCK_MANAGEMENT_ENGINE southbridge/intel/ibexpeak bool Lock Management Engine section

The Intel Management Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_rangeley bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

INCLUDE_ME southbridge/intel/fsp_rangeley bool Add Intel descriptor.bin file

Include the descriptor.bin for rangeley.

ME_PATH southbridge/intel/fsp_rangeley string Path to descriptor.bin file

The path of the descriptor.bin file.

SATA_CONTROLLER_MODE southbridge/amd/cimx/sb700 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb700 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb700 hex

Set SCI IRQ to 9.

REDIRECT_SBCIMX_TRACE_TO_SERIAL southbridge/amd/cimx/sb700 bool Redirect AMD Southbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Southbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

ENABLE_IDE_COMBINED_MODE southbridge/amd/cimx/sb800 bool Enable SATA IDE combined mode

If Combined Mode is enabled. IDE controller is exposed and SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and SATA controller has full control of all 6 Ports when operating in non-IDE mode.

IDE_COMBINED_MODE southbridge/amd/cimx/sb800 hex SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is AHCI.

SB800_SATA_IDE southbridge/amd/cimx/sb800 bool NATIVE

NATIVE does not require a ROM.

SB800_SATA_AHCI southbridge/amd/cimx/sb800 bool AHCI

AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM.

SB800_SATA_RAID southbridge/amd/cimx/sb800 bool RAID

sb800 RAID mode must have the two required ROM files.

RAID_ROM_ID southbridge/amd/cimx/sb800 string RAID device PCI IDs

1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/cimx/sb800 hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000.

SB800_IMC_FWM southbridge/amd/cimx/sb800 bool Add IMC firmware

Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

SB800_FWM_AT_FFFA0000 southbridge/amd/cimx/sb800 bool 0xFFFA0000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFF20000 southbridge/amd/cimx/sb800 bool 0xFFF20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFE20000 southbridge/amd/cimx/sb800 bool 0xFFE20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFC20000 southbridge/amd/cimx/sb800 bool 0xFFC20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FF820000 southbridge/amd/cimx/sb800 bool 0xFF820000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

EHCI_BAR southbridge/amd/cimx/sb800 hex Fan Control

Select the method of SB800 fan control to be used. None would be for either fixed maximum speed fans connected to the SB800 or for an external chip controlling the fan speeds. Manual control sets up the SB800 fan control registers. IMC fan control uses the SB800 IMC to actively control the fan speeds.

SB800_NO_FAN_CONTROL southbridge/amd/cimx/sb800 bool None

No SB800 Fan control - Do not set up the SB800 fan control registers.

SB800_MANUAL_FAN_CONTROL southbridge/amd/cimx/sb800 bool Manual

Configure the SB800 fan control registers in devicetree.cb.

SB800_IMC_FAN_CONTROL southbridge/amd/cimx/sb800 bool IMC Based

Set up the SB800 to use the IMC based Fan controller. This requires the IMC rom from AMD. Configure the registers in devicetree.cb.

SATA_CONTROLLER_MODE southbridge/amd/cimx/sb900 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb900 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb900 hex

Set SCI IRQ to 9.

HUDSON_XHCI_ENABLE southbridge/amd/pi/hudson bool Enable Hudson XHCI Controller

The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the the XHCI firmware is available but the XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM southbridge/amd/pi/hudson bool Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM southbridge/amd/pi/hudson bool Add IMC firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM southbridge/amd/pi/hudson bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_FWM_POSITION southbridge/amd/pi/hudson hex Hudson Firmware ROM Position

Hudson requires the firmware MUST be located at a specific address (ROM start address + 0x20000), otherwise xhci host Controller can not find or load the xhci firmware.

The firmware start address is dependent on the ROM chip size. The default offset is 0x20000 from the ROM start address, namely 0xFFF20000 if flash chip size is 1M 0xFFE20000 if flash chip size is 2M 0xFFC20000 if flash chip size is 4M 0xFF820000 if flash chip size is 8M 0xFF020000 if flash chip size is 16M

HUDSON_SATA_MODE southbridge/amd/pi/hudson int SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment) NATIVE
(comment) RAID
(comment) AHCI
(comment) LEGACY IDE
(comment) IDE to AHCI
(comment) AHCI7804
(comment) IDE to AHCI7804
RAID_ROM_ID southbridge/amd/pi/hudson string RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/pi/hudson hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE southbridge/amd/pi/hudson bool System is legacy free

Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.

AZ_PIN southbridge/amd/pi/hudson hex

bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3

EXT_CONF_SUPPORT southbridge/amd/rs690 bool

Select if RS690 should be setup to support MMCONF.

HUDSON_XHCI_ENABLE southbridge/amd/agesa/hudson bool Enable Hudson XHCI Controller

The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the the XHCI firmware is available but the XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM southbridge/amd/agesa/hudson bool Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM southbridge/amd/agesa/hudson bool Add imc firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM southbridge/amd/agesa/hudson bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_FWM_POSITION southbridge/amd/agesa/hudson hex Hudson Firmware ROM Position

Hudson requires the firmware MUST be located at a specific address (ROM start address + 0x20000), otherwise xhci host Controller can not find or load the xhci firmware.

The firmware start address is dependent on the ROM chip size. The default offset is 0x20000 from the ROM start address, namely 0xFFF20000 if flash chip size is 1M 0xFFE20000 if flash chip size is 2M 0xFFC20000 if flash chip size is 4M 0xFF820000 if flash chip size is 8M 0xFF020000 if flash chip size is 16M

HUDSON_SATA_MODE southbridge/amd/agesa/hudson int SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment) NATIVE
(comment) RAID
(comment) AHCI
(comment) LEGACY IDE
(comment) IDE to AHCI
(comment) AHCI7804
(comment) IDE to AHCI7804
RAID_ROM_ID southbridge/amd/agesa/hudson string RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/agesa/hudson hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE southbridge/amd/agesa/hudson bool System is legacy free

Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.

AZ_PIN southbridge/amd/agesa/hudson hex

bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3

EHCI_BAR southbridge/amd/sb600 hex SATA Mode

Select the mode in which SATA should be driven. IDE or AHCI. The default is IDE.

config SATA_MODE_IDE bool "IDE"

config SATA_MODE_AHCI bool "AHCI"

(comment) Super I/O
(comment) Embedded Controllers
EC_ACPI ec/acpi bool

ACPI Embedded Controller interface. Mostly found in laptops.

EC_QUANTA_IT8518 ec/quanta/it8518 bool

Interface to QUANTA IT8518 Embedded Controller.

EC_QUANTA_ENE_KB3940Q ec/quanta/ene_kb3940q bool

Interface to QUANTA ENE KB3940Q Embedded Controller.

EC_SMSC_MEC1308 ec/smsc/mec1308 bool

Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.

EC_GOOGLE_CHROMEEC ec/google/chromeec bool

Google's Chrome EC

EC_GOOGLE_CHROMEEC_ACPI_MEMMAP ec/google/chromeec bool

When defined, ACPI accesses EC memmap data on ports 66h/62h. When not defined, the memmap data is instead accessed on 900h-9ffh via the LPC bus.

EC_GOOGLE_CHROMEEC_I2C ec/google/chromeec bool

Google's Chrome EC via I2C bus.

EC_GOOGLE_CHROMEEC_I2C_PROTO3 ec/google/chromeec bool

Use only proto3 for i2c EC communication.

EC_GOOGLE_CHROMEEC_LPC ec/google/chromeec bool

Google Chrome EC via LPC bus.

EC_GOOGLE_CHROMEEC_MEC ec/google/chromeec bool

Microchip EC variant for LPC register access.

EC_GOOGLE_CHROMEEC_SPI ec/google/chromeec bool

Google's Chrome EC via SPI bus.

EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US ec/google/chromeec int

Force delay after asserting /CS to allow EC to wakeup.

EC_COMPAL_ENE932 ec/compal/ene932 bool

Interface to COMPAL ENE932 Embedded Controller.

EC_KONTRON_IT8516E ec/kontron/it8516e bool

Kontron uses an ITE IT8516E on the KTQM77. Its firmware might come from Fintek (mentioned as Finte*c* somewhere in their Linux driver). The KTQM77 is an embedded board and the IT8516E seems to be only used for fan control and GPIO.

(comment) SoC
BOOTBLOCK_CPU_INIT soc/nvidia/tegra124 string

CPU/SoC-specific bootblock code. This is useful if the bootblock must load microcode or copy data from ROM before searching for the bootblock.

MAINBOARD_DO_DSI_INIT soc/nvidia/tegra132 bool Use dsi graphics interface

Initialize dsi display

MAINBOARD_DO_SOR_INIT soc/nvidia/tegra132 bool Use dp graphics interface

Initialize dp display

BOOTBLOCK_CPU_INIT soc/nvidia/tegra132 string

CPU/SoC-specific bootblock code. This is useful if the bootblock must load microcode or copy data from ROM before searching for the bootblock.

MTS_DIRECTORY soc/nvidia/tegra132 string Directory where MTS microcode files are located

Path to directory where MTS microcode files are located.

TRUSTZONE_CARVEOUT_SIZE_MB soc/nvidia/tegra132 hex Size of Trust Zone region

Size of Trust Zone area in MiB to reserve in memory map.

BOOTROM_SDRAM_INIT soc/nvidia/tegra132 bool SoC BootROM does SDRAM init with full BCT

Use during Ryu LPDDR3 bringup

CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE soc/broadcom/cygnus bool Enable DDR auto self-refresh

Warning: M0 expects that auto self-refresh is enabled. Modify with caution.


SOC_INTEL_BAYTRAIL soc/intel/baytrail bool

Bay Trail M/D part support.

HAVE_MRC soc/intel/baytrail bool Add a Memory Reference Code binary

Select this option to add a blob containing memory reference code. Note: Without this binary coreboot will not work

MRC_FILE soc/intel/baytrail string Intel memory refeference code path and filename

The path and filename of the file to use as System Agent binary. Note that this points to the sandybridge binary file which is will not work, but it serves its purpose to do builds.

DCACHE_RAM_SIZE soc/intel/baytrail hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE soc/intel/baytrail hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE soc/intel/baytrail hex

The amount of anticipated stack usage from the data cache during pre-RAM ROM stage execution.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/baytrail bool Reset the system on S3 wake when ramstage cache invalid.

The baytrail romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

CBFS_SIZE soc/intel/baytrail hex Size of CBFS filesystem in ROM

On Bay Trail systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image.

ENABLE_BUILTIN_COM1 soc/intel/baytrail bool Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

HAVE_ME_BIN soc/intel/baytrail bool Add Intel Management Engine firmware

The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME firmware might be provided in coreboot's 3rdparty repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM.

BUILD_WITH_FAKE_IFD soc/intel/baytrail bool Build with a fake IFD

If you don't have an Intel Firmware Descriptor (ifd.bin) for your board, you can select this option and coreboot will build without it. Though, the resulting coreboot.rom will not contain all parts required to get coreboot running on your board. You can however write only the BIOS section to your board's flash ROM and keep the other sections untouched. Unfortunately the current version of flashrom doesn't support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

HAVE_REFCODE_BLOB soc/intel/baytrail bool An external reference code blob should be put into cbfs.

The reference code blob will be placed into cbfs.

REFCODE_BLOB_FILE soc/intel/baytrail string Path and filename to reference code blob.

The path and filename to the file to be added to cbfs.

SOC_INTEL_COMMON soc/intel/common bool

common code for Intel SOCs

SOC_INTEL_BROADWELL soc/intel/broadwell bool

Intel Broadwell and Haswell ULT support.

DCACHE_RAM_SIZE soc/intel/broadwell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE soc/intel/broadwell hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE soc/intel/broadwell hex

The amount of anticipated stack usage from the data cache during pre-ram rom stage execution.

HAVE_MRC soc/intel/broadwell bool Add a Memory Reference Code binary

Select this option to add a Memory Reference Code binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE soc/intel/broadwell string Intel Memory Reference Code path and filename

The filename of the file to use as Memory Reference Code binary.

CBFS_SIZE soc/intel/broadwell hex Size of CBFS filesystem in ROM

The firmware image has to store more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image.

PRE_GRAPHICS_DELAY soc/intel/broadwell int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/broadwell bool Reset the system on S3 wake when ramstage cache invalid.

The romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

SERIRQ_CONTINUOUS_MODE soc/intel/broadwell bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

HAVE_ME_BIN soc/intel/broadwell bool Add Intel Management Engine firmware

The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME firmware might be provided in coreboot's 3rdparty repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM.

BUILD_WITH_FAKE_IFD soc/intel/broadwell bool Build with a fake IFD

If you don't have an Intel Firmware Descriptor (ifd.bin) for your board, you can select this option and coreboot will build without it. Though, the resulting coreboot.rom will not contain all parts required to get coreboot running on your board. You can however write only the BIOS section to your board's flash ROM and keep the other sections untouched. Unfortunately the current version of flashrom doesn't support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

LOCK_MANAGEMENT_ENGINE soc/intel/broadwell bool Lock Management Engine section

The Intel Management Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

SOC_INTEL_FSP_BAYTRAIL soc/intel/fsp_baytrail bool

Bay Trail I part support using the Intel FSP.

SMM_TSEG_SIZE soc/intel/fsp_baytrail hex

This is set by the FSP

VGA_BIOS_ID soc/intel/fsp_baytrail string

This is the default PCI ID for the Bay Trail graphics devices. This string names the vbios ROM in cbfs.

CBFS_SIZE soc/intel/fsp_baytrail hex

On Bay Trail systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Trusted Execution Engine firmware This option specifies the maximum size of the CBFS portion in the firmware image.

INCLUDE_ME soc/intel/fsp_baytrail bool Include the TXE

Build the TXE and descriptor.bin into the ROM image. If you want to use a descriptor.bin and TXE file from the previous ROM image, you may not want to build it in here.

ME_PATH soc/intel/fsp_baytrail string Path to ME

The path of the TXE and Descriptor files.

LOCK_MANAGEMENT_ENGINE soc/intel/fsp_baytrail bool Lock TXE section

The Intel Trusted Execution Engine supports preventing write accesses from the host to the Management Engine section in the firmware descriptor. If the ME section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME firmware is no longer going to change.

If unsure, say N.

ENABLE_BUILTIN_COM1 soc/intel/fsp_baytrail bool Enable built-in legacy Serial Port

The Baytrail SOC has one legacy serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

FSP_FILE soc/intel/fsp_baytrail/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC soc/intel/fsp_baytrail/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Bay Trail FSP is built with a preferred base address of 0xFFFC0000.

CBFS_SIZE soc/qualcomm/ipq806x hex Size of CBFS filesystem in ROM

CBFS size needs to match the size of memory allocated to the coreboot blob elsewhere in the system. Make sure this config option is fine tuned in the board config file.

SBL_BLOB soc/qualcomm/ipq806x string file name of the Qualcomm SBL blob

The path and filename of the binary blob containing ipq806x early initialization code, as supplied by the vendor.

(comment) Intel FSP
HAVE_FSP_BIN drivers/intel/fsp1_0 bool Use Intel Firmware Support Package

Select this option to add an Intel FSP binary to the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP will not boot

FSP_FILE drivers/intel/fsp1_0 string Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC drivers/intel/fsp1_0 hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

ENABLE_FSP_FAST_BOOT drivers/intel/fsp1_0 bool Enable Fast Boot

Enabling this feature will force the MRC data to be cached in NV storage to be used for speeding up boot time on future reboots and/or power cycles.

ENABLE_MRC_CACHE drivers/intel/fsp1_0 bool

Enabling this feature will cause MRC data to be cached in NV storage. This can either be used for fast boot, or just because the FSP wants it to be saved.

MRC_CACHE_SIZE drivers/intel/fsp1_0 hex Fast Boot Data Cache Size

This is the amount of space in NV storage that is reserved for the fast boot data cache storage.

WARNING: Because this area will be erased and re-written, the size should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in.

OVERRIDE_CACHE_CACHE_LOC drivers/intel/fsp1_0 bool

Selected by the platform to set a new default location for the MRC/fast boot cache.

MRC_CACHE_LOC_OVERRIDE drivers/intel/fsp1_0 hex

Sets the override CBFS location of the MRC/fast boot cache.

MRC_CACHE_LOC drivers/intel/fsp1_0 hex Fast Boot Data Cache location in CBFS

The location in CBFS for the MRC data to be cached.

WARNING: This should be on a sector boundary of the BIOS ROM chip and nothing else should be included in that sector, or IT WILL BE ERASED.

VIRTUAL_ROM_SIZE drivers/intel/fsp1_0 hex Virtual ROM Size

This is used to calculate the offset of the MRC data cache in NV Storage for fast boot. If in doubt, leave this set to the default which sets the virtual size equal to the ROM size.

Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB.

CACHE_ROM_SIZE_OVERRIDE drivers/intel/fsp1_0 hex Cache ROM Size

This is the size of the cachable area that is passed into the FSP in the early initialization. Typically this should be the size of the CBFS area, but the size must be a power of 2 whereas the CBFS size does not have this limitation.

USE_GENERIC_FSP_CAR_INC drivers/intel/fsp1_0 bool

The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.

FSP_USES_UPD drivers/intel/fsp1_0 bool

If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.

Menu: Devices
MAINBOARD_DO_NATIVE_VGA_INIT device bool Use native graphics initialization

Some mainboards, such as the Google Link, allow initializing the display without the need of a binary only VGA OPROM. Enabling this option may be faster, but also lacks flexibility in setting modes.

If unsure, say N.

VGA_ROM_RUN device bool Run VGA Option ROMs

Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS payload.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

S3_VGA_ROM_RUN device bool Re-run VGA Option ROMs on S3 resume

Execute VGA Option ROMs in coreboot when resuming from S3 suspend.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

ALWAYS_LOAD_OPROM device bool

Always load option ROMs if any are found. The decision to run the ROM is still determined at runtime, but the distinction between loading and not running comes into play for CHROMEOS.

An example where this is required is that VBT (Video BIOS Tables) are needed for the kernel's display driver to know how a piece of hardware is configured to be used.

ON_DEVICE_ROM_RUN device bool Run Option ROMs on PCI devices

Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.

If disabled, only Option ROMs stored in CBFS will be executed by coreboot. If you are concerned about security, you might want to disable this option, but it might leave your system in a state of degraded functionality.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

PCI_OPTION_ROM_RUN_REALMODE device bool Native mode

If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)

PCI_OPTION_ROM_RUN_YABEL device bool Secure mode

If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs.

This option prevents Option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the native Option ROM initialization method.

This is the default choice for non-x86 systems.

YABEL_PCI_ACCESS_OTHER_DEVICES device bool Allow Option ROMs to access other devices

Per default, YABEL only allows Option ROMs to access the PCI device that they are associated with. However, this causes trouble for some onboard graphics chips whose Option ROM needs to reconfigure the north bridge.

YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG device bool Fake success on writing other device's config space

By default, YABEL aborts when the Option ROM tries to write to other devices' config spaces. With this option enabled, the write doesn't follow through, but the Option ROM is allowed to go on. This can create issues such as hanging Option ROMs (if it depends on that other register changing to the written value), so test for impact before using this option.

YABEL_VIRTMEM_LOCATION device hex Location of YABEL's virtual memory

YABEL requires 1MB memory for its CPU emulation. This memory is normally located at 16MB.

YABEL_DIRECTHW device bool Direct hardware access

YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one).

When choosing this option, x86emu will pass through all hardware accesses to memory and I/O devices to the underlying memory and I/O addresses. While this option prevents Option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Enable this option for a good compromise between security and speed.

PCIEXP_COMMON_CLOCK device bool Enable PCIe Common Clock

Detect and enable Common Clock on PCIe links.

PCIEXP_ASPM device bool Enable PCIe ASPM

Detect and enable ASPM on PCIe links.

PCIEXP_CLK_PM device bool Enable PCIe Clock Power Management

Detect and enable Clock Power Management on PCIe.

EARLY_PCI_BRIDGE device bool Early PCI bridge

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system.

This option enables static configuration for a single pre-defined PCI bridge function on bus 0.

PCIEXP_L1_SUB_STATE device bool Enable PCIe ASPM L1 SubState

Detect and enable ASPM on PCIe links.

SUBSYSTEM_VENDOR_ID device hex Override PCI Subsystem Vendor ID

This config option will override the devicetree settings for PCI Subsystem Vendor ID.

SUBSYSTEM_DEVICE_ID device hex Override PCI Subsystem Device ID

This config option will override the devicetree settings for PCI Subsystem Device ID.

VGA_BIOS device bool Add a VGA BIOS image

Select this option if you have a VGA BIOS image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VGA_BIOS_FILE device string VGA BIOS path and filename

The path and filename of the file to use as VGA BIOS.

VGA_BIOS_ID device string VGA device PCI IDs

The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

INTEL_MBI device bool Add an MBI image

Select this option if you have an Intel MBI image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

MBI_FILE device string Intel MBI path and filename

The path and filename of the file to use as VGA BIOS.

PXE_ROM device bool Add a PXE ROM image

Select this option if you have a PXE ROM image that you would like to add to your ROM.

PXE_ROM_FILE device string PXE ROM filename

The path and filename of the file to use as PXE ROM.

PXE_ROM_ID device string network card PCI IDs

The comma-separated PCI vendor and device ID that would associate your PXE ROM to your network card.

Example: 10ec,8168

In the above example 10ec is the PCI vendor ID (in hex, but without the "0x" prefix) and 8168 specifies the PCI device ID of the network card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

SOFTWARE_I2C device bool Enable I2C controller emulation in software

This config option will enable code to override the i2c_transfer routine with a (simple) software emulation of the protocol. This may be useful for debugging or on platforms where a driver for the real I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines.

Menu: Display
FRAMEBUFFER_SET_VESA_MODE device bool Set framebuffer graphics resolution

Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)

FRAMEBUFFER_SET_VESA_MODE device bool framebuffer graphics resolution

This option sets the resolution used for the coreboot framebuffer (and bootsplash screen).

FRAMEBUFFER_KEEP_VESA_MODE device bool Keep VESA framebuffer

This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a framebuffer driver. If this option is disabled, coreboot will switch back to text mode before handing control to a payload.

BOOTSPLASH device bool Show graphical bootsplash

This option shows a graphical bootsplash screen. The graphics are loaded from the CBFS file bootsplash.jpg.

You will be able to specify the location and file name of the image later.

BOOTSPLASH_FILE device string Bootsplash path and filename

The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg.

Menu: Generic Drivers
SPI_FLASH drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash.

SPI_ATOMIC_SEQUENCING drivers/spi bool

Select this option if the SPI controller uses "atomic sequencing." Atomic sequencing is when the sequence of commands is pre-programmed in the SPI controller. Hardware manages the transaction instead of software. This is common on x86 platforms.

SPI_FLASH_MEMORY_MAPPED drivers/spi bool

Inform system if SPI is memory-mapped or not.

SPI_FLASH_SMM drivers/spi bool SPI flash driver support in SMM

Select this option if you want SPI flash support in SMM.

SPI_FLASH_NO_FAST_READ drivers/spi bool Disable Fast Read command

Select this option if your setup requires to avoid "fast read"s from the SPI flash parts.

SPI_FLASH_ADESTO drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Adesto Technologies.

SPI_FLASH_AMIC drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by AMIC.

SPI_FLASH_ATMEL drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Atmel.

SPI_FLASH_EON drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON.

SPI_FLASH_GIGADEVICE drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice.

SPI_FLASH_MACRONIX drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix.

SPI_FLASH_SPANSION drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion.

SPI_FLASH_SST drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST.

SPI_FLASH_STMICRO drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO.

SPI_FLASH_WINBOND drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond.

SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B drivers/spi bool

Select this option if your SPI flash supports the fast read dual- output command (opcode 0x3b) where the opcode and address are sent to the chip on MOSI and data is received on both MOSI and MISO.

ELOG drivers/elog bool Support for flash based event log

Enable support for flash based event logging.

ELOG_FLASH_BASE drivers/elog hex Event log offset into flash

Offset into the flash chip for the ELOG block. This should be allocated in the FMAP.

ELOG_AREA_SIZE drivers/elog hex Size of Event Log area in flash

This should be a multiple of flash block size.

Default is 4K.

ELOG_CBMEM drivers/elog bool Store a copy of ELOG in CBMEM

This option will have ELOG store a copy of the flash event log in a CBMEM region and export that address in SMBIOS to the OS. This is useful if the ELOG location is not in memory mapped flash, but it means that events added at runtime via the SMI handler will not be reflected in the CBMEM copy of the log.

ELOG_GSMI drivers/elog bool SMI interface to write and clear event log

This interface is compatible with the linux kernel driver available with CONFIG_GOOGLE_GSMI and can be used to write kernel reset/shutdown messages to the event log.

ELOG_BOOT_COUNT drivers/elog bool Maintain a monotonic boot number in CMOS

Store a monotonic boot number in CMOS and provide an interface to read the current value and increment the counter. This boot counter will be logged as part of the System Boot event.

ELOG_BOOT_COUNT_CMOS_OFFSET drivers/elog int Offset in CMOS to store the boot count

This value must be greater than 16 bytes so as not to interfere with the standard RTC region. Requires 8 bytes.

USBDEBUG drivers/usb bool USB 2.0 EHCI debug dongle support

This option allows you to use a so-called USB EHCI Debug device (such as the Ajays NET20DC, AMIDebug RX, or a system using the Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI Debug Port capability.

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list of supported controllers.

If unsure, say N.

USBDEBUG_IN_ROMSTAGE drivers/usb bool Enable early (pre-RAM) usbdebug

Configuring USB controllers in system-agent binary may cause problems to usbdebug. Disabling this option delays usbdebug to be setup on entry to ramstage.

If unsure, say Y.

USBDEBUG_HCD_INDEX drivers/usb int Index for EHCI controller to use with usbdebug

Some boards have multiple EHCI controllers with possibly only one having the Debug Port capability on an external USB port.

Mapping of this index to PCI device functions is southbridge specific and mainboard level Kconfig should already provide a working default value here.

USBDEBUG_DEFAULT_PORT drivers/usb int Default USB port to use as Debug Port

Selects which physical USB port usbdebug dongle is connected to. Setting of 0 means to scan possible ports starting from 1.

Intel platforms have hardwired the debug port location and this setting makes no difference there.

Hence, if you select the correct port here, you can speed up your boot time. Which USB port number refers to which actual port on your mainboard (potentially also USB pin headers on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error.

USBDEBUG_DONGLE_BEAGLEBONE drivers/usb bool BeagleBone

Use this to configure the USB hub on BeagleBone board.

USBDEBUG_DONGLE_BEAGLEBONE_BLACK drivers/usb bool BeagleBone Black

Use this with BeagleBone Black.

GIC drivers/gic None

This option enables GIC support, the ARM generic interrupt controller.

DRIVERS_UART_OXPCIE drivers/uart bool Oxford OXPCIe952

Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID 0xc158 or 0xc11b will work.

DRIVERS_PS2_KEYBOARD drivers/pc80 bool PS/2 keyboard init

Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads (eg, GRUB 2, SeaBIOS, Linux) do not require it. Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y.

LPC_TPM drivers/pc80/tpm bool

Enable this option to enable LPC TPM support in coreboot.

If unsure, say N.

TPM_TIS_BASE_ADDRESS drivers/pc80/tpm hex TPM Base Address

This can be used to adjust the TPM memory base address. The default is specified by the TCG PC Client Specific TPM Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2.

DRIVERS_EMULATION_QEMU_BOCHS drivers/emulation/qemu bool bochs dispi interface vga driver

VGA driver for qemu emulated vga cards supporting the bochs dispi interface. This includes standard vga, vmware svga and qxl. The default vga (cirrus) is *not* supported, so you have to pick another one explicitly via 'qemu -vga $card'.

DRIVER_XPOWERS_AXP209 drivers/xpowers/axp209 bool

X-Powers AXP902 Power Management Unit

DRIVER_XPOWERS_AXP209_BOOTBLOCK drivers/xpowers/axp209 bool

Make AXP209 functionality available in he bootblock.

INTEL_DP drivers/intel/gma bool

helper functions for intel display port operations

INTEL_DDI drivers/intel/gma bool

helper functions for intel DDI operations

DRIVER_TI_TPS65090 drivers/ti/tps65090 bool

TI TPS65090

DRIVER_PARADE_PS8625 drivers/parade/ps8625 bool

Parade ps8625 display port to lvds bridge

DRIVERS_I2C_RTD2132 drivers/i2c/rtd2132 bool

Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.

DRIVERS_SIL_3114 drivers/sil/3114 bool Silicon Image SIL3114

It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it.

DIGITIZER_AUTODETECT drivers/lenovo bool Autodetect

The presence of digitizer is inferred from model number stored in AT24RF chip.

DIGITIZER_PRESENT drivers/lenovo bool Present

The digitizer is assumed to be present.

DIGITIZER_ABSENT drivers/lenovo bool Absent

The digitizer is assumed to be absent.

DRIVER_MAXIM_MAX77686 drivers/maxim/max77686 bool

Maxim MAX77686 power regulator

TPM toplevel bool

Enable this option to enable TPM support in coreboot.

If unsure, say N.

Menu: Console
BOOTBLOCK_CONSOLE console bool Enable early (bootblock) console output.

Use console during the bootblock if supported

SQUELCH_EARLY_SMP console bool Squelch AP CPUs from early console.

When selected only the BSP CPU will output to early console.

Console drivers have unpredictable behaviour if multiple threads attempt to share the same resources without a spinlock.

If unsure, say Y.

CONSOLE_SERIAL console bool Serial port console output

Send coreboot debug output to a serial port.

The type of serial port driver selected based on your configuration is shown on the following menu line. Supporting multiple different types of UARTs in one build is not supported.

(comment) I/O mapped, 8250-compatible
(comment) memory mapped, 8250-compatible
(comment) device-specific UART
TTYS0_BASE console hex

Map the COM port number to the respective I/O port.

CONSOLE_SERIAL_115200 console bool 115200

Set serial port Baud rate to 115200.

CONSOLE_SERIAL_57600 console bool 57600

Set serial port Baud rate to 57600.

CONSOLE_SERIAL_38400 console bool 38400

Set serial port Baud rate to 38400.

CONSOLE_SERIAL_19200 console bool 19200

Set serial port Baud rate to 19200.

CONSOLE_SERIAL_9600 console bool 9600

Set serial port Baud rate to 9600.

TTYS0_BAUD console int

Map the Baud rates to an integer.

SPKMODEM console bool spkmodem (console on speaker) console output

Send coreboot debug output through speaker

CONSOLE_USB console bool USB dongle console output

Send coreboot debug output to USB.

Configuration for USB hardware is under menu Generic Drivers.

ONBOARD_VGA_IS_PRIMARY console bool Use onboard VGA as primary video device

If not selected, the last adapter found will be used.

CONSOLE_NE2K console bool Network console over NE2000 compatible Ethernet adapter

Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP port 6666 on IP/MAC specified with options bellow. Use following netcat command: nc -u -l -p 6666

CONSOLE_NE2K_DST_MAC console string Destination MAC address of remote system

Type in either MAC address of logging system or MAC address of the router.

CONSOLE_NE2K_DST_IP console string Destination IP of logging system

This is IP address of the system running for example netcat command to dump the packets.

CONSOLE_NE2K_SRC_IP console string IP address of coreboot system

This is the IP of the coreboot system

CONSOLE_NE2K_IO_PORT console hex NE2000 adapter fixed IO port address

This is the IO port address for the IO port on the card, please select some non-conflicting region, 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align)

CONSOLE_CBMEM console bool Send console output to a CBMEM buffer

Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.

CONSOLE_CBMEM_BUFFER_SIZE console hex Room allocated for console output in CBMEM

Space allocated for console output storage in CBMEM. The default value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level.

CONSOLE_CBMEM_DUMP_TO_UART console bool Dump CBMEM console on resets

Enable this to have CBMEM console buffer contents dumped on the serial output in case serial console is disabled and the device resets itself while trying to boot the payload.

CONSOLE_QEMU_DEBUGCON console bool QEMU debug console output

Send coreboot debug output to QEMU's isa-debugcon device:

qemu-system-x86_64 \ -chardev file,id=debugcon,path=/dir/file.log \ -device isa-debugcon,iobase=0x402,chardev=debugcon

DEFAULT_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

DEFAULT_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

DEFAULT_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

DEFAULT_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

DEFAULT_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

DEFAULT_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

DEFAULT_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

DEFAULT_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

DEFAULT_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

DEFAULT_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

CMOS_POST console bool Store post codes in CMOS for debugging

If enabled, coreboot will store post codes in CMOS and switch between two offsets on each boot so the last post code in the previous boot can be retrieved. This uses 3 bytes of CMOS.

CMOS_POST_OFFSET console hex Offset into CMOS to store POST codes

If CMOS_POST is enabled then an offset into CMOS must be provided. If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table.

CMOS_POST_EXTRA console bool Store extra logging info into CMOS

This will enable extra logging of work that happens between post codes into CMOS for debug. This uses an additional 8 bytes of CMOS.

CONSOLE_POST console bool Show POST codes on the debug console

If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the debug console.

POST_IO console bool Send POST codes to an IO port

If enabled, POST codes will be written to an IO port.

POST_IO_PORT console hex IO port for POST codes

POST codes on x86 are typically written to the LPC bus on port 0x80. However, it may be desirable to change the port number depending on the presence of coprocessors/microcontrollers or if the platform does not support IO in the conventional x86 manner.

HAVE_HARD_RESET toplevel bool

This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code.

HAVE_MONOTONIC_TIMER toplevel bool

The board/chipset provides a monotonic timer.

GENERIC_UDELAY toplevel bool

The board/chipset uses a generic udelay function utilizing the monotonic timer.

TIMER_QUEUE toplevel bool

Provide a timer queue for performing time-based callbacks.

COOP_MULTITASKING toplevel bool

Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple execution paths to take place when they have udelay() calls within their code.

NUM_THREADS toplevel int

How many execution threads to cooperatively multitask with.

HAVE_OPTION_TABLE toplevel bool

This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig.

CBFS_SIZE toplevel hex Size of CBFS filesystem in ROM

This is the part of the ROM actually managed by CBFS, located at the end of the ROM (passed through cbfstool -o) on x86 and at at the start of the ROM (passed through cbfstool -s) everywhere else. Defaults to span the whole ROM but can be overwritten to make coreboot live alongside other components (like ChromeOS's vboot/FMAP).

VGA toplevel bool

Build board-specific VGA code.

GFXUMA toplevel bool

Enable Unified Memory Architecture for graphics.

HAVE_ACPI_TABLES toplevel bool

This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig.

HAVE_MP_TABLE toplevel bool

This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.

HAVE_PIRQ_TABLE toplevel bool

This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.

MAX_PIRQ_LINKS toplevel int

This variable specifies the number of PIRQ interrupt links which are routable. On most chipsets, this is 4, INTA through INTD. Some chipsets offer more than four links, commonly up to INTH. They may also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set.

Menu: System tables
GENERATE_MP_TABLE toplevel bool Generate an MP table

Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board.

If unsure, say Y.

GENERATE_PIRQ_TABLE toplevel bool Generate a PIRQ table

Generate a PIRQ table for this board.

If unsure, say Y.

GENERATE_SMBIOS_TABLES toplevel bool Generate SMBIOS tables

Generate SMBIOS tables for this board.

If unsure, say Y.

MAINBOARD_SERIAL_NUMBER toplevel string SMBIOS Serial Number

The Serial Number to store in SMBIOS structures.

MAINBOARD_VERSION toplevel string SMBIOS Version Number

The Version Number to store in SMBIOS structures.

MAINBOARD_SMBIOS_MANUFACTURER toplevel string SMBIOS Manufacturer

Override the default Manufacturer stored in SMBIOS structures.

MAINBOARD_SMBIOS_PRODUCT_NAME toplevel string SMBIOS Product name

Override the default Product name stored in SMBIOS structures.

Menu: Payload
PAYLOAD_NONE toplevel bool None

Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.

PAYLOAD_ELF toplevel bool An ELF executable payload

Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

PAYLOAD_LINUX toplevel bool A Linux payload

Select this option if you have a Linux bzImage which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

PAYLOAD_SEABIOS toplevel bool SeaBIOS

Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

PAYLOAD_FILO toplevel bool FILO

Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

PAYLOAD_GRUB2 toplevel bool GRUB2

Select this option if you want to build a coreboot image with a GRUB2 payload. If you don't know what this is about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

PAYLOAD_TIANOCORE toplevel bool Tiano Core

Select this option if you want to build a coreboot image with a Tiano Core payload. If you don't know what this is about, just leave it enabled.

See http://coreboot.org/Payloads for more information.

SEABIOS_STABLE toplevel bool 1.7.5

Stable SeaBIOS version

SEABIOS_MASTER toplevel bool master

Newest SeaBIOS version

SEABIOS_PS2_TIMEOUT toplevel int PS/2 keyboard controller initialization timeout (milliseconds)

Some PS/2 keyboard controllers don't respond to commands immediately after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up.

SEABIOS_THREAD_OPTIONROMS toplevel bool Hardware init during option ROM execution

Allow hardware init to run in parallel with optionrom execution.

This can reduce boot time, but can cause some timing variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option.

SEABIOS_MALLOC_UPPERMEMORY toplevel bool

Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal "low memory" allocations. If this is not selected, the memory is instead allocated from the "9-segment" (0x90000-0xa0000). This is not typically needed, but may be required on some platforms to allow USB and SATA buffers to be written correctly by the hardware. In general, if this is desired, the option will be set to 'N' by the chipset Kconfig.

SEABIOS_VGA_COREBOOT toplevel bool Include generated option rom that implements legacy VGA BIOS compatibility

Coreboot can initialize the GPU of some mainboards.

After initializing the GPU, the information about it can be passed to the payload. Provide an option rom that implements this legacy VGA BIOS compatibility requirement.

GRUB2_MASTER toplevel bool HEAD

Newest GRUB2 version

FILO_STABLE toplevel bool 0.6.0

Stable FILO version

FILO_MASTER toplevel bool HEAD

Newest FILO version

PAYLOAD_FILE toplevel string Payload path and filename

The path and filename of the ELF executable file to use as payload.

PAYLOAD_FILE toplevel string Linux path and filename

The path and filename of the bzImage kernel to use as payload.

PAYLOAD_FILE toplevel string Tianocore firmware volume

The result of a corebootPkg build

COMPRESSED_PAYLOAD_LZMA toplevel bool Use LZMA compression for payloads

In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.

LINUX_COMMAND_LINE toplevel string Linux command line

A command line to add to the Linux kernel.

LINUX_INITRD toplevel string Linux initrd

An initrd image to add to the Linux kernel.

Menu: Debugging
GDB_STUB toplevel bool GDB debugging support

If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details.

GDB_WAIT toplevel bool Wait for a GDB connection

If enabled, coreboot will wait for a GDB connection.

FATAL_ASSERTS toplevel bool Halt when hitting a BUG() or assertion error

If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().

DEBUG_CBFS toplevel bool Output verbose CBFS debug messages

This option enables additional CBFS related debug messages.

DEBUG_RAM_SETUP toplevel bool Output verbose RAM init debug messages

This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_CAR toplevel bool Output verbose Cache-as-RAM debug messages

This option enables additional CAR related debug messages.

DEBUG_PIRQ toplevel bool Check PIRQ table consistency

If unsure, say N.

DEBUG_SMBUS toplevel bool Output verbose SMBus debug messages

This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_SMI toplevel bool Output verbose SMI debug messages

This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_SMM_RELOCATION toplevel bool Debug SMM relocation code

This option enables additional SMM handler relocation related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_MALLOC toplevel bool Output verbose malloc debug messages

This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_ACPI toplevel bool Output verbose ACPI debug messages

This option enables additional ACPI related debug messages.

Note: This option will slightly increase the size of the coreboot image.

If unsure, say N.

REALMODE_DEBUG toplevel bool Enable debug messages for option ROM execution

This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.

X86EMU_DEBUG toplevel bool Output verbose x86emu debug messages

This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_JMP toplevel bool Trace JMP/RETF

Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_TRACE toplevel bool Trace all opcodes

Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_PNP toplevel bool Log Plug&Play accesses

Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_DISK toplevel bool Log Disk I/O

Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_PMM toplevel bool Log PMM

Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.


X86EMU_DEBUG_VBE toplevel bool Debug VESA BIOS Extensions

Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_INT10 toplevel bool Redirect INT10 output to console

Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_INTERRUPTS toplevel bool Log intXX calls

Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_CHECK_VMEM_ACCESS toplevel bool Log special memory accesses

Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_MEM toplevel bool Log all memory accesses

Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_IO toplevel bool Log IO accesses

Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_TIMINGS toplevel bool Output timing information

Print timing information needed by i915tool.

If unsure, say N.

DEBUG_TPM toplevel bool Output verbose TPM debug messages

This option enables additional TPM related debug messages.

DEBUG_SPI_FLASH toplevel bool Output verbose SPI flash debug messages

This option enables additional SPI flash related debug messages.

DEBUG_USBDEBUG toplevel bool Output verbose USB 2.0 EHCI debug dongle messages

This option enables additional USB 2.0 debug dongle related messages.

Select this to debug the connection of usbdebug dongle. Note that you need some other working console to receive the messages.

DEBUG_INTEL_ME toplevel bool Verbose logging for Intel Management Engine

Enable verbose logging for Intel Management Engine driver that is present on Intel 6-series chipsets.

TRACE toplevel bool Trace function calls

If enabled, every function will print information to console once the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) the 0xaaaabbbb is the actual function and 0xccccdddd is EIP of calling function. Please note some printk releated functions are omitted from trace to have good looking console dumps.

DEBUG_COVERAGE toplevel bool Debug code coverage

If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped.

POWER_BUTTON_DEFAULT_ENABLE toplevel bool

Select when the board has a power button which can optionally be disabled by the user.

POWER_BUTTON_DEFAULT_DISABLE toplevel bool

Select when the board has a power button which can optionally be enabled by the user, e.g. when the board ships with a jumper over the power switch contacts.

POWER_BUTTON_FORCE_ENABLE toplevel bool

Select when the board requires that the power button is always enabled.

POWER_BUTTON_FORCE_DISABLE toplevel bool

Select when the board requires that the power button is always disabled, e.g. when it has been hardwired to ground.

POWER_BUTTON_IS_OPTIONAL toplevel bool

Internal option that controls ENABLE_POWER_BUTTON visibility.

REG_SCRIPT toplevel bool

Internal option that controls whether we compile in register scripts.

MAX_REBOOT_CNT toplevel int

Internal option that sets the maximum number of bootblock executions allowed with the normal image enabled before assuming the normal image is defective and switching to the fallback image.