Coreboot Options

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This is an automatically generated list of coreboot v2 compile-time options.

Last update: 2009/07/01 00:10:41.

Option Comment Default Export Format
CONFIG_ARCH_X86 "X86 is the default" 1 always
CONFIG_ARCH "Default architecture is i386, options are alpha and ppc" "i386" always
CONFIG_HAVE_MOVNTI "This cpu supports the MOVNTI directive" 0 always
CONFIG_CROSS_COMPILE "Cross compiler prefix" "" always
CC "Target C Compiler" "$(CONFIG_CROSS_COMPILE)gcc" always
HOSTCC "Host C Compiler" "gcc" always
CONFIG_CPU_OPT "Additional per-cpu CFLAGS" none used
CONFIG_OBJCOPY "Objcopy command" "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff" always
COREBOOT_VERSION "coreboot version" grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)" always "\"%s\""
COREBOOT_EXTRA_VERSION "\"%s\""
COREBOOT_BUILD "Build date" "$(shell date)" always "\"%s\""
COREBOOT_COMPILE_TIME "Build time" "$(shell date +%T)" always "\"%s\""
COREBOOT_COMPILE_BY "Who build this image" "$(shell whoami)" always "\"%s\""
COREBOOT_COMPILE_HOST "Build host" "$(shell hostname)" always "\"%s\""
COREBOOT_COMPILE_DOMAIN "Build domain name" "$(shell dnsdomainname)" always "\"%s\""
COREBOOT_COMPILER "Build compiler" tail -1)" always "\"%s\""
COREBOOT_LINKER "Build linker" grep \" ld\")" always "\"%s\""
COREBOOT_ASSEMBLER "Build assembler" "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )" always "\"%s\""
CONFIG_CHIP_CONFIGURE "Use new chip_configure method for configuring (non-pci) devices" 0 used
CONFIG_USE_INIT "Use stage 1 initialization code" 0 always
COREBOOT_V2 "This is used by code to determine v2 vs v3" 1 always
CONFIG_HAVE_FALLBACK_BOOT "Set if fallback booting required" 0 always "%d"
CONFIG_HAVE_FAILOVER_BOOT "Set if failover booting required" 0 always "%d"
CONFIG_USE_FALLBACK_IMAGE "Set to build a fallback image" 0 used "%d"
CONFIG_USE_FAILOVER_IMAGE
CONFIG_FALLBACK_SIZE "Default fallback image size" 65536 used "0x%x"
CONFIG_FAILOVER_SIZE
CONFIG_ROM_SIZE "Size of your ROM" none used "0x%x"
CONFIG_ROM_IMAGE_SIZE "Default image size" 65535 always "0x%x"
CONFIG_ROM_SECTION_SIZE "Default rom section size" {CONFIG_FALLBACK_SIZE} used "0x%x"
CONFIG_ROM_SECTION_OFFSET "Default rom section offset" {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE} used "0x%x"
CONFIG_PAYLOAD_SIZE "Default payload size" {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE} always "0x%x"
CONFIG_ROMBASE "Base address of coreboot in ROM" {CONFIG_PAYLOAD_SIZE} always "0x%x"
CONFIG_ROMSTART "Start address of coreboot in ROM" none used "0x%x"
CONFIG_RESET "Hardware reset vector address" {CONFIG_ROMBASE} always "0x%x"
CONFIG_EXCEPTION_VECTORS "Address of exception vector table" {CONFIG_ROMBASE+0x100} always "0x%x"
CONFIG_STACK_SIZE "Default stack size" 0x2000 always "0x%x"
CONFIG_HEAP_SIZE "Default heap size" 0x2000 always "0x%x"
CONFIG_RAMBASE "Base address of coreboot in RAM" none always "0x%x"
CONFIG_RAMSTART "Start address of coreboot in RAM" none used "0x%x"
CONFIG_USE_DCACHE_RAM "Use data cache as temporary RAM if possible" 0 always
CONFIG_CAR_FAM10 "AMD family 10 CAR requires additional setup" 0 always
CONFIG_DCACHE_RAM_BASE "Base address of data cache when using it for temporary RAM" 0xc0000 always "0x%x"
CONFIG_DCACHE_RAM_SIZE "Size of data cache when using it for temporary RAM" 0x1000 always "0x%x"
CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE "Size of region that for global variable of cache as ram stage" 0 always "0x%x"
CONFIG_AP_CODE_IN_CAR
CONFIG_MEM_TRAIN_SEQ
CONFIG_WAIT_BEFORE_CPUS_INIT
CONFIG_XIP_ROM_BASE "Start address of area to cache during coreboot execution directly from ROM" 0 used "0x%x"
CONFIG_XIP_ROM_SIZE "Size of area to cache during coreboot execution directly from ROM" 0 used "0x%x"
CONFIG_COMPRESS "Set for compressed image" 1 always
CONFIG_UNCOMPRESSED "Set for uncompressed image" {!CONFIG_COMPRESS} always "%d"
CONFIG_LB_MEM_TOPK "Kilobytes of memory to initialized before executing code from RAM" 2048 always "%d"
CONFIG_HAVE_OPTION_TABLE "Export CMOS option table" 0 always
CONFIG_USE_OPTION_TABLE "Use option table" {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE} always "%d"
CONFIG_LB_CKS_RANGE_START "First CMOS byte to use for coreboot options" 49 always "%d"
CONFIG_LB_CKS_RANGE_END "Last CMOS byte to use for coreboot options" 125 always "%d"
CONFIG_LB_CKS_LOC "Pair of bytes to use for CMOS checksum" 126 always "%d"
CONFIG_CRT0 "Main initialization target" "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb" always
CONFIG_DEBUG "Enable x86emu debugging code" 0 always
CONFIG_CONSOLE_VGA "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)" 0 always
CONFIG_CONSOLE_VGA_MULTI
CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
CONFIG_CONSOLE_BTEXT
CONFIG_CONSOLE_LOGBUF "Log messages to buffer" 0 always
CONFIG_CONSOLE_SROM "Log messages to SROM console" 0 always
CONFIG_CONSOLE_SERIAL8250 "Log messages to 8250 uart based serial console" 0 always
CONFIG_USBDEBUG_DIRECT "Log messages to ehci debug port console" 0 always
CONFIG_DEFAULT_CONSOLE_LOGLEVEL "Console will log at this level unless changed" 7 always
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 8 always
CONFIG_SERIAL_POST "Enable SERIAL POST codes" 0 always
CONFIG_NO_POST "Disable POST codes" none used
CONFIG_TTYS0_BASE "Base address for 8250 uart for the serial console" 0x3f8 always "0x%x"
CONFIG_TTYS0_BAUD "Default baud rate for serial console" 115200 always
CONFIG_TTYS0_DIV "Allow UART divisor to be set explicitly" none used "%d"
CONFIG_TTYS0_LCS "Default flow control settings for the 8250 serial console uart" 0x3 always "0x%x"
CONFIG_USE_PRINTK_IN_CAR "use printk instead of print in CAR stage code" 0 always
CONFIG_ASSEMBLER_DEBUG "Create disassembly files for debugging" 0 always
CONFIG_MAINBOARD "Mainboard name" "Mainboard_not_set" always
CONFIG_MAINBOARD_PART_NUMBER "Part number of mainboard" "Part_number_not_set" always "\"%s\""
CONFIG_MAINBOARD_VENDOR "Vendor of mainboard" "Vendor_not_set" always "\"%s\""
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID "PCI Vendor ID of mainboard manufacturer" 0 always
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID "PCI susbsystem device id assigned my mainboard manufacturer" 0 always "0x%x"
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL "Default power on after power fail setting" none used
CONFIG_SYS_CLK_FREQ "System clock frequency in MHz" none used
CONFIG_MAX_PCI_BUSES "Maximum number of PCI buses to search for devices" 255 always
CONFIG_SMP "Define if we support SMP" 0 always
CONFIG_MAX_CPUS
CONFIG_MAX_PHYSICAL_CPUS
CONFIG_LOGICAL_CPUS "Should multiple cpus per die be enabled?" 0 always
CONFIG_AP_IN_SIPI_WAIT "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)" 0 always
CONFIG_HAVE_MP_TABLE "Define to build an MP table" none used
CONFIG_SERIAL_CPU_INIT
CONFIG_APIC_ID_OFFSET "We need to share this value between cache_as_ram_auto.c and northbridge.c" 0 always
CONFIG_ENABLE_APIC_EXT_ID "Enable APIC ext id mode 8 bit" 0 always
CONFIG_LIFT_BSP_APIC_ID "decide if we lift bsp apic id while ap apic id" 0 always
CONFIG_MULTIBOOT "Use Multiboot (rather than ELF boot notes) to boot the payload" 1 always
CONFIG_IDE_PAYLOAD "Boot from IDE device" 0 always
CONFIG_ROM_PAYLOAD "Boot image is located in ROM" 0 always
CONFIG_ROM_PAYLOAD_START "ROM stream start location" {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1} always "0x%x"
CONFIG_COMPRESSED_PAYLOAD_NRV2B "NRV2B compressed boot image is located in ROM" 0 always
CONFIG_COMPRESSED_PAYLOAD_LZMA "LZMA compressed boot image is located in ROM" 0 always
CONFIG_PRECOMPRESSED_PAYLOAD "boot image is already compressed" 0 always
CONFIG_SERIAL_PAYLOAD "Download boot image from serial port" 0 always
CONFIG_FS_PAYLOAD "Boot from a filesystem" 0 always
CONFIG_FS_EXT2 "Enable ext2 filesystem support" 0 always
CONFIG_FS_ISO9660 "Enable ISO9660 filesystem support" 0 always
CONFIG_FS_FAT "Enable FAT filesystem support" 0 always
CONFIG_CBFS "The new CBFS file system" 0 always
CONFIG_AUTOBOOT_DELAY "Delay (in seconds) before autobooting" 2 always
CONFIG_AUTOBOOT_CMDLINE "Default command line when autobooting" "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200" always "\"%s\""
CONFIG_USE_WATCHDOG_ON_BOOT "Use the watchdog on booting" 0 always
CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT "Enable support for plugin Hypertransport busses" 1 always
CONFIG_AGP_PLUGIN_SUPPORT "Enable support for plugin AGP busses" 1 always
CONFIG_CARDBUS_PLUGIN_SUPPORT "Enable support cardbus plugin cards" 1 always
CONFIG_PCIX_PLUGIN_SUPPORT "Enable support for plugin PCI-X busses" 1 always
CONFIG_PCIEXP_PLUGIN_SUPPORT "Enable support for plugin PCI-E busses" 1 always
CONFIG_HAVE_PIRQ_TABLE "Define if we have a PIRQ table" none used
CONFIG_PIRQ_ROUTE "Define if we have a PIRQ table and want routing IRQs" 0 always
CONFIG_IRQ_SLOT_COUNT "Number of IRQ slots" none used
CONFIG_PCIBIOS_IRQ "PCIBIOS IRQ support" none used
CONFIG_IOAPIC "IOAPIC support" none used
CONFIG_IDE "Define to include IDE support" 0 always
CONFIG_IDE_BOOT_DRIVE "Disk number of boot drive" 0 always
CONFIG_IDE_SWAB "Swap bytes when reading from IDE device" none used
CONFIG_IDE_OFFSET "Sector at which to start searching for boot image" 0 always
CONFIG_PCI_IO_CFG_EXT "allow 4K register space via io CFG port" 0 always
CONFIG_PCIC0_CFGADDR "Address of PCI Configuration Address Register" none used "0x%x"
CONFIG_PCIC0_CFGDATA "Address of PCI Configuration Data Register" none used "0x%x"
CONFIG_ISA_IO_BASE "Base address of PCI/ISA I/O address range" none used "0x%x"
CONFIG_ISA_MEM_BASE "Base address of PCI/ISA memory address range" none used "0x%x"
CONFIG_PNP_CFGADDR "PNP Configuration Address Register offset" none used "0x%x"
CONFIG_PNP_CFGDATA "PNP Configuration Data Register offset" none used "0x%x"
CONFIG_IO_BASE "Base address of memory mapped I/O operations" none used "0x%x"
CONFIG_EMBEDDED_RAM_SIZE "Embedded boards generally have fixed RAM size" none used
CONFIG_GDB_STUB "Compile in gdb stub support?" 0 used
CONFIG_HAVE_INIT_TIMER "Have a init_timer function" 0 always
CONFIG_HAVE_HARD_RESET "Have hard reset" none used
CONFIG_HAVE_SMI_HANDLER "Set, if the board needs an SMI handler" 0 always
CONFIG_MEMORY_HOLE "Set to deal with memory hole" none used
CONFIG_MAX_REBOOT_CNT "Set maximum reboots" 3 always
CONFIG_HAVE_FANCTL "Include board specific FAN control initialization" 0 used
CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 "Use timer2 to callibrate the x86 time stamp counter" 0 used
CONFIG_INTEL_PPRO_MTRR "" none used
CONFIG_UDELAY_TSC "Implement udelay with the x86 time stamp counter" 0 used
CONFIG_UDELAY_IO "Implement udelay with x86 io registers" 0 used
CONFIG_FAKE_SPDROM "Use this to fake spd rom values" 0 always
CONFIG_HAVE_ACPI_TABLES "Define to build ACPI tables" 0 always
CONFIG_HAVE_ACPI_RESUME "Define to build ACPI with resume support" 0 always
CONFIG_ACPI_SSDTX_NUM "extra ssdt num for PCI Device" 0 always
CONFIG_AGP_APERTURE_SIZE "AGP graphics virtual memory aperture size" none used "0x%x"
CONFIG_HT_CHAIN_UNITID_BASE "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0" 1 always
CONFIG_HT_CHAIN_END_UNITID_BASE
CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
CONFIG_SB_HT_CHAIN_ON_BUS0
CONFIG_PCI_BUS_SEGN_BITS
CONFIG_MMCONF_SUPPORT "enable mmconfig for pci conf" 0 always
CONFIG_MMCONF_SUPPORT_DEFAULT "enable mmconfig for pci conf" 0 always
CONFIG_MMCONF_BASE_ADDRESS "enable mmconfig base address" none used "0x%x"
CONFIG_HW_MEM_HOLE_SIZEK
CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
CONFIG_VAR_MTRR_HOLE "using hole in MTRR instead of increasing method" 1 always
CONFIG_K8_HT_FREQ_1G_SUPPORT "Optern E0 later could support 1G HT, but still depends MB design" 0 always
CONFIG_K8_REV_F_SUPPORT
CONFIG_CBB "Opteron cpu bus num base" 0 always
CONFIG_CDB "Opteron cpu device num base" 0x18 always
CONFIG_HT3_SUPPORT "Hypertransport 3 support, include ac HT and unganged sublink feature" 0 always
CONFIG_EXT_RT_TBL_SUPPORT "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8" 0 always
CONFIG_EXT_CONF_SUPPORT "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4" 0 always
CONFIG_DIMM_SUPPORT "0x%x"
CONFIG_CPU_SOCKET_TYPE "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3" 0x10 always
CONFIG_CPU_ADDR_BITS "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48" 36 always
CONFIG_VGA "Include VGA initialisation code" 0 always
CONFIG_VGA_ROM_RUN "Init x86 ROMs on VGA-class PCI devices" 0 always
CONFIG_PCI_ROM_RUN "Init x86 ROMs on all PCI devices" 0 always
CONFIG_PCI_OPTION_ROM_RUN_YABEL "Use Yabel instead of old bios emulator" 0 used
CONFIG_YABEL_DEBUG_FLAGS "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h" 0 used
CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs." 0 used
CONFIG_PCI_OPTION_ROM_RUN_REALMODE "Use Yabel instead of old bios emulator" 0 used
CONFIG_PCI_64BIT_PREF_MEM
CONFIG_AMDMCT "use AMD MCT to init RAM instead of native code" 0 always
CONFIG_AMD_UCODE_PATCH_FILE "name of the microcode patch file" none used "\"%s\""
CONFIG_K8_MEM_BANK_B_ONLY "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert." 0 always
CONFIG_VIDEO_MB
CONFIG_GFXUMA
CONFIG_HAVE_MAINBOARD_RESOURCES "Enable if the mainboard/chipset requires extra entries in the memory map" 0 always
CONFIG_HAVE_LOW_TABLES "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte" 1 always
CONFIG_HAVE_HIGH_TABLES "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory" 0 always
CONFIG_SPLASH_GRAPHIC "Paint a splash screen" 0 used
CONFIG_GX1_VIDEO "Build in GX1's graphic support" 0 used
CONFIG_GX1_VIDEOMODE "Define video mode after reset" none used
CONFIG_PCIE_CONFIGSPACE_HOLE "Leave a hole for PCIe config space in the device allocator" 0 always
CONFIG_SANDPOINT_ALTIMUS "Configure Sandpoint with Altimus PMC" 0 never
CONFIG_SANDPOINT_TALUS "Configure Sandpoint with Talus PMC" 0 never
CONFIG_SANDPOINT_UNITY "Configure Sandpoint with Unity PMC" 0 never
CONFIG_SANDPOINT_VALIS "Configure Sandpoint with Valis PMC" 0 never
CONFIG_SANDPOINT_GYRUS "Configure Sandpoint with Gyrus PMC" 0 never
CONFIG_BRIQ_750FX "Configure briQ with PowerPC 750FX" 0 never
CONFIG_BRIQ_7400 "Configure briQ with PowerPC G4" 0 never