Coreboot Options

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Until recently, coreboot was using a proprietary config system. For some time you can look at the old list of options.

This is an automatically generated list of coreboot compile-time options.

Last update: 2010/02/09 15:05:25. (r5100)

Option Source Format Short Description Description
Menu: General setup
EXPERT toplevel bool Expert mode

This allows you to select certain advanced configuration options.

Warning: Only enable this option if you really know what you are doing! You have been warned!

LOCALVERSION toplevel string Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.

Menu: Mainboard
BOARD_ROMSIZE_KB_4096 mainboard bool ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file of the matching size.

COREBOOT_ROMSIZE_KB_128 mainboard bool 128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256 mainboard bool 256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512 mainboard bool 512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024 mainboard bool 1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048 mainboard bool 2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096 mainboard bool 4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

Menu: Chipset
(comment) CPU
SMP cpu bool

This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.

VAR_MTRR_HOLE cpu bool

Unset this if you don't want the MTRR code to use subtractive MTRRs

(comment) Northbridge
(comment) Southbridge
Menu: AMD Geode GX1 video support
(comment) Super I/O
(comment) Devices
VGA_BRIDGE_SETUP devices bool Setup bridges on path to VGA adapter

Allow bridges to set up legacy decoding ranges for VGA. Don't disable this unless you're sure you don't want the briges setup for VGA.

VGA_ROM_RUN devices bool Run VGA option ROMs

Execute VGA option ROMs, if found. This is required to enable PCI/AGP/PCI-E video cards.

PCI_ROM_RUN devices bool Run non-VGA option ROMs

Execute non-VGA PCI option ROMs, if found.

Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs).

PCI_OPTION_ROM_RUN_REALMODE devices bool Real mode

If you select this option, PCI option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)

PCI_OPTION_ROM_RUN_X86EMU devices bool x86emu

If you select this option, the x86emu CPU emulator will be used to execute PCI option ROMs. When choosing this option, x86emu will pass through all hardware accesses to memory and IO devices to the underlying memory and IO addresses. While this option prevents option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Choosing x86emu, option ROM execution is slower than native execution in real mode, but faster than the full system emulation YABEL This is the default choice for non-x86 systems.

PCI_OPTION_ROM_RUN_YABEL devices bool YABEL

If you select this option, the YABEL system emulator will be used to execute PCI option ROMs. YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one). This option best prevents option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the other option ROM initialization methods.

YABEL_DEBUG_FLAGS devices hex Hex value for YABEL debug flags

See debug.h for values 0 is no debug output, 0x31ff is _verbose_.

Menu: Console options
CONSOLE_SERIAL8250 console bool Serial port console output

Send coreboot debug output to a serial port console.

CONSOLE_SERIAL_COM1 console bool COM1/ttyS0, I/O port 0x3f8

Serial console on COM1/ttyS0 at I/O port 0x3f8.

CONSOLE_SERIAL_COM2 console bool COM2/ttyS1, I/O port 0x2f8

Serial console on COM2/ttyS1 at I/O port 0x2f8.

CONSOLE_SERIAL_COM3 console bool COM3/ttyS2, I/O port 0x3e8

Serial console on COM3/ttyS2 at I/O port 0x3e8.

CONSOLE_SERIAL_COM4 console bool COM4/ttyS3, I/O port 0x2e8

Serial console on COM4/ttyS3 at I/O port 0x2e8.

TTYS0_BASE console hex

Map the COM port names to the respective I/O port.

CONSOLE_SERIAL_115200 console bool 115200

Set serial port Baud rate to 115200.

CONSOLE_SERIAL_57600 console bool 57600

Set serial port Baud rate to 57600.

CONSOLE_SERIAL_38400 console bool 38400

Set serial port Baud rate to 38400.

CONSOLE_SERIAL_19200 console bool 19200

Set serial port Baud rate to 19200.

CONSOLE_SERIAL_9600 console bool 9600

Set serial port Baud rate to 9600.

TTYS0_BAUD console int

Map the Baud rates to an integer.

SERIAL_POST console bool Show POST codes on the serial port console

If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the serial console.

USBDEBUG_DIRECT console bool USB 2.0 EHCI debug dongle support

This option allows you to use a so-called USB EHCI Debug device to retrieve the coreboot debug messages (instead, or in addition to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI Debug Port capability. Controllers which are known to work:

  • 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
  • 8086:24cd Intel ICH4/ICH4-M
  • 8086:24dd Intel ICH5
  • 8086:265c Intel ICH6
  • 8086:268c Intel 631xESB/632xESB/3100
  • 8086:27cc Intel ICH7
  • 8086:2836 Intel ICH8
  • 8086:283a Intel ICH8
  • 8086:293a Intel ICH9
  • 10de:0088 NVIDIA MCP2A
  • 10de:005b NVIDIA CK804
  • 10de:026e NVIDIA MCP51
  • 10de:036d NVIDIA MCP55
  • 10de:03f2 NVIDIA MCP61
  • 1002:4386 ATI/AMD SB600
  • 1106:3104 VIA VX800

See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.

CONSOLE_VGA_ONBOARD_AT_FIRST console bool Use onboard VGA as primary video device

If not selected, the last adapter found will be used.

MAXIMUM_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

MAXIMUM_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

MAXIMUM_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

MAXIMUM_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

MAXIMUM_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

MAXIMUM_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

MAXIMUM_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

MAXIMUM_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

MAXIMUM_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

MAXIMUM_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

DEFAULT_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

DEFAULT_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

DEFAULT_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

DEFAULT_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

DEFAULT_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

DEFAULT_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

DEFAULT_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

DEFAULT_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

DEFAULT_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

DEFAULT_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

HAVE_OPTION_TABLE toplevel bool

This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.

VGA toplevel bool

Build board-specific VGA code.

GFXUMA toplevel bool

Enable Unified Memory Architecture for graphics.

HAVE_LOW_TABLES toplevel bool

This Option is unused in the code. Since two boards try to set it to 'n', they may be broken. We either need to make the option useful or get rid of it. The broken boards are: asus/m2v-mx_se supermicro/h8dme

HAVE_HIGH_TABLES toplevel bool

This variable specifies whether a given northbridge has high table support. It is set in northbridge/*/Kconfig. Whether or not the high tables are actually written by coreboot is configurable by the user via WRITE_HIGH_TABLES.

HAVE_ACPI_TABLES toplevel bool

This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. Whether or not the ACPI tables are actually generated by coreboot is configurable by the user via GENERATE_ACPI_TABLES.

HAVE_MP_TABLE toplevel bool

This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.

HAVE_PIRQ_TABLE toplevel bool

This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.

Menu: System tables
GENERATE_ACPI_TABLES toplevel bool Generate ACPI tables

Generate ACPI tables for this board.

If unsure, say Y.

GENERATE_MP_TABLE toplevel bool Generate an MP table

Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board.

If unsure, say Y.

GENERATE_PIRQ_TABLE toplevel bool Generate a PIRQ table

Generate a PIRQ table for this board.

If unsure, say Y.

Menu: Payload
PAYLOAD_NONE toplevel bool None

Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.

PAYLOAD_ELF toplevel bool An ELF executable payload

Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

FALLBACK_PAYLOAD_FILE toplevel string Payload path and filename

The path and filename of the ELF executable file to use as payload.

COMPRESSED_PAYLOAD_LZMA toplevel bool Use LZMA compression for payloads

In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.

Menu: VGA BIOS
VGA_BIOS toplevel bool Add a VGA BIOS image

Select this option if you have a VGA BIOS image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

FALLBACK_VGA_BIOS_FILE toplevel string VGA BIOS path and filename

The path and filename of the file to use as VGA BIOS.

FALLBACK_VGA_BIOS_ID toplevel string VGA device PCI IDs

The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix).

Menu: Debugging
GDB_STUB toplevel bool GDB debugging support

If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/i386/lib/c_start.S for details.