Difference between revisions of "Developer Manual"

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(Some more info for the development manual.)
m (View From The CPU: Intel Architecture)
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<div style="color: red">'''This is work in progress!'''</div>
 
<div style="color: red">'''This is work in progress!'''</div>
  
== Introduction ==
+
This manual is intended for aspiring coreboot developers to help them get up to speed with the code base and the tasks required to add support for new chipsets, devices, and mainboards. It covers coreboot v4.
  
This manual is intended for aspiring LinuxBIOS developers to help them get up to speed with the code base and the tasks required to add support for new chipsets, devices, and mainboards. It currently covers LinuxBIOSv2, but will be extended to also cover the development version LinuxBIOSv3 later.
+
== How to support a new board ==
 +
 
 +
People often ask how to support a new board. If you are willing to put in the effort to write the port, then there is a good chance that you will succeed. Supporting a new board that uses a chipset that is already supported by coreboot is much less work for obvious reasons than supporting a new board with an unsupported chipset. Don't expect a new board to be supported by developers, especially an Intel board just because you would like it supported. Supporting a new board can take from an hour to over a year of time. If you would like a new board supported then you should expect to do the work on the port yourself.
 +
 
 +
====Supporting a new board with the same cpu family, chipset and superIO====
 +
 
 +
To support a new board with an already supported chipset look for the most similar board in the coreboot tree to the new board that you wish to support. After you find the most similar board, look for the differences between your new board and the most similar board.
 +
 
 +
If your new board has the same cpu family, cpu socket, chipset and superIO then you can try the coreboot build for the supported board on the new board with a backup flash device and debugging turned on. Look at the debug output to determine where the boot process stops or what errors are encountered on the way. Common differences between boards with exactly the same cpu, chipset and superIO are IRQ routing, ACPI and flash write enable routines or jumpers. Make changes to the board configuration, ACPI or IRQ routing etc etc until you find the proper settings. This can take from an hour of time to a few months based upon your coding skills and hardware issues.
 +
 
 +
====Supporting a new board with the same cpu family, chipset but different superIO====
 +
 
 +
If your new board has the same cpu family, cpu socket, chipset but the superIO is different but it is a supported superIO then you will have to change the board config to use the different superIO. More on this later....
 +
 
 +
Common differences between boards with exactly the same cpu, chipset but a different superIO are IRQ routing, ACPI and flash write enable routines or jumpers. Make changes to the board configuration, ACPI or IRQ routing etc etc until you find the proper settings. This can take from an hour of time to a few months based upon your coding skills and hardware issues.
 +
 
 +
====Supporting a new board with a unsupported cpu, chipset or superIO====
 +
 
 +
If your new board uses a cpu, chipset or superIO not supported by coreboot then you will have a lot of work in front of you. You will need developer data sheets for the cpu, chipset and superIO. AMD has been releasing data sheets to the public that includes most of the information required to support a new cpu and chipset. AMD has also been releasing complete coreboot patches to many of their recent cpu's and chipsets. Many of the superIO vendors have public documents available. Intel has been closed about releasing specifications at a low enough level to support a new cpu or chipset. Specifications are generally only provided to high volume OEM's. New developers requesting data sheets might have to wait for several months after signing NDA's until they receive the specifications.
 +
 
 +
== Recommended hardware and software tools ==
 +
 
 +
See [[Developer Manual/Tools]] for a list of recommended tools which are useful for coreboot users and developers.
  
 
== Hardware Overview ==
 
== Hardware Overview ==
  
== LinuxBIOS Overview ==
+
=== Intel Architecture ===
  
== Serial output and the Super I/O ==
+
==== Hardware Reset ====
  
The [[wikipedia:Super I/O|Super I/O]] is a chip found on most of today's mainboards which is &mdash; among other things &mdash; responsible for the serial ports of the mainboard (e.g. COM1, COM2). This chip is usually the first thing you'll want to support, as it's required to get serial debugging output from the mainboard (via a null-modem cable and the proper software, e.g. [[minicom]] or CuteCom).
+
From Intel's "64 and IA-32 Architectures Software Developer’s Manual" (doc 253668-021 October 2006), Volume 3A, Section 9.1.4:
  
[[Image:Winbond w83977ef.jpg|thumb|right|<small>Winbond W83977EF Super&nbsp;I/O</small>]]
+
<blockquote>
[[Image:Ite it8705f.jpg|thumb|right|<small>ITE IT8705F Super&nbsp;I/O</small>]]
+
The first instruction that is fetched and executed following a hardware reset is located at '''physical address 0xFFFFFFF0'''. This address is 16 bytes below the processor’s uppermost physical address.  The EPROM containing the software-initialization code must be located at this address.
 +
<br />
 +
The address 0xFFFFFFF0 is beyond the 1-MByte addressable range of the processor while in real-address mode. The processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In real-address mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with 0xF000 and the base address is loaded with 0xFFFF0000. The starting address is thus formed by adding the base address to the value in the EIP register (that is, 0xFFFF0000 + 0xFFF0 = 0xFFFFFFF0).
 +
<br />
 +
The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To insure that the base address in the CS register remains unchanged until the EPROM based software-initialization code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would cause the CS selector value to be changed).
 +
</blockquote>
  
The steps for adding support for a new Super I/O chip are:
+
==== FWH/LPC Flash Memory ====
* Add a directory src/superio/''vendor''/''device'' (e.g. src/superio/winbond/w83627ehg).
+
 
* In that directory, add a file ''device''_early_serial.c (e.g. w83627ehg_early_serial.c). This file will be responsible to setup a serial port on the mainboard so that you can get serial debugging output. This will work even ''before'' the RAM is initialized, thus is useful/required for debugging the RAM initialization process.
+
Modern mainboards are often equipped with Firmware Hub (FWH) or Low Pin Count (LPC) flash memory used to store the system bootloader ("BIOS"). Execution begins by fetching instructions 16 bytes below the flash memory's uppermost physical address.
* In this file you now declare a function ''device''_enable_serial() which enables the requested serial port. Example:
+
 
  static void w83627ehg_enable_serial(device_t dev, unsigned int iobase)
+
== coreboot Overview ==
  {
+
 
        pnp_enter_ext_func_mode(dev);
+
=== View From The CPU: Intel Architecture ===
        pnp_set_logical_device(dev);
+
 
        pnp_set_enable(dev, 0);
+
# At '''0xFFFFFFF0''', start execution at '''reset_vector''' from '''src/cpu/x86/16bit/reset16.inc''', which simply jumps to '''_start'''.
        pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+
# '''_start''' from '''src/cpu/x86/16bit/entry16.inc''', invalidates the TLBs, sets up a GDT for selector 0x08 (code) and 0x10 (data), switches to protected mode, and jumps to '''__protected_start''' (setting the CS to the new selector 0x08). The selectors provide full flat access to the entire physical memory map.
        pnp_set_enable(dev, 1);
+
# '''__protected_start''' from '''src/cpu/x86/32bit/entry32.inc''', sets all other segment registers to the 0x10 selector.
        pnp_exit_ext_func_mode(dev);
+
# Execution continues with various '''mainboardinit''' fragments:
  }
+
## '''__fpu_start''' from '''cpu/x86/fpu_enable.inc'''.
* Mainboards which have this Super I/O chip, will call this function in their ''auto.c'' or ''cache_as_ram_auto.c'' file. Example:
+
## '''(unlabeled)''' from '''cpu/x86/sse_enable.inc'''
  #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+
## Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. '''cpu/amd/model_lx/cache_as_ram.inc'''.
  [...]
+
# The final '''mainboardinit''' fragment is mainboard-specific, in C, called '''romstage.c'''. For non-cache-as-RAM targets, it is compiled with '''romcc'''. It includes and uses other C-code fragments for:
  #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+
## Initializing MSRs, MTRRs, APIC.
  [...]
+
## Setting up the southbridge minimally ("early setup").
  w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
+
## Setting up Super I/O serial.
  uart_init();
+
## Initializing the console.
  console_init();
+
## Initializing RAM controller and RAM itself.
:Whether the Super I/O is at config address ''0x2e'' (the usual case) or ''0x4e'' (or some other address) is mainboard-dependent. You can find out the address by running [[superiotool]].
+
# Execution continues at '''__main''' from '''src/arch/x86/init/crt0_romcc_epilogue.inc''', where the non-romcc C coreboot code is copied (possibly decompressed) to RAM, then the RAM entry point is jumped to.
 +
# The RAM entry point is '''_start''' in '''src/arch/x86/lib/c_start.S''', where new descriptor tables are set up, the stack and BSS are cleared, the IDT is initialized, and '''hardwaremain()''' is called (operation is now full 32-bit protected mode C program with stack).
 +
# '''hardwaremain()''' is from '''src/boot/hardwaremain.c''', the console is initialized, devices are enumerated and initialized, configured and enabled.
 +
# The payload is called, either via '''elfboot()''' from '''boot/elfboot.c''', or '''filo()''' from '''boot/filo.c'''.
 +
 
 +
== Failover/Fallback/Normal images overview ==
 +
 
 +
See [[Developer Manual/Bootblock]]
 +
 
 +
== Memory map ==
 +
 
 +
On x86 systems, many memory ranges are reserved for special purposes or have some other peculiar properties. The article [[Developer Manual/Memory map]] has details about this fact.
 +
 
 +
== Serial output and the Super I/O ==
 +
 
 +
See [[Developer Manual/Super IO]].
  
 
== Northbridge ==
 
== Northbridge ==
Line 43: Line 85:
 
== RAM init ==
 
== RAM init ==
  
Resources:
+
See [[Developer Manual/RAM init]].
* [http://www.simmtester.com/page/news/showpubnews.asp?num=101 Understanding DDR Serial Presence Detect (SPD) Table]
+
* [http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf Micron 512 MB SDRAM Datasheet] (PDF) -- contains some helpful explanations
+
  
 
== Southbridge ==
 
== Southbridge ==
Line 51: Line 91:
 
== Mainboard ==
 
== Mainboard ==
  
=== IRQ Table ===
+
=== devicetree.cb ===
 +
 
 +
The mainboard's '''devicetree.cb''' file contains many build and platform configuration settings. One of the most important items is the mainboard device list.
 +
 
 +
A device needs to be listed in the mainboard '''devicetree.cb''' if it requires more setup than standard PCI initialization (resource allocation). Typically, that includes the CPU, northbridge, southbridge, and Super I/O. These devices are usually required for system specific configuration as well as indicate the system bus structure ('''pci_domain''').
 +
 
 +
When a device in '''devicetree.cb''' is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the '''device_operations''' and the '''chip_operations''' structures. You will find these structures in the devices source files.
 +
 
 +
=== irq_table.c ===
 +
 
 +
See [[Creating Valid IRQ Tables]].
 +
 
 +
== Creating a new target ==
 +
 
 +
To create a new mainboard target you have to add several files.
 +
 
 +
* Multiple files in src/mainboard/''vendorname''/''mainboardname'' (replace ''vendorname'' and ''mainboardname'', of course).
 +
 
 +
== Documentation and datasheets ==
 +
 
 +
=== Useful hardware/concepts documentation for developers ===
 +
 
 +
These external documents and slides explain fundamental concepts of hardware that coreboot supports.
 +
 
 +
'''Interrupts'''
 +
 
 +
* [http://www.bsdcan.org/2007/schedule/attachments/13-PCI_Interrupts_for_x86_Machines_under_FreeBSD_John_Baldwin PCI Interrupts on x86 machines] from John Baldwin
 +
* [http://www.microsoft.com/taiwan/whdc/archive/ACPI-MP.mspx PCI IRQ Routing on a Multiprocessor ACPI System] at Microsoft's Windows Hardware Developer Central
  
== Creating a new Target ==
+
'''System Managment Mode'''
  
== Miscellaneous Tips ==
+
* [http://www.rcollins.org/ddj/Jan97/Jan97.html System Managment Mode Overview] by Robery R. Collins
  
=== minicom ===
+
=== Specific datasheets ===
Minicom is not just a serial terminal. It was written long before the internet existed and electronic communication was only possible with a modem to a mailbox-computer. Minicom is written with the ncurses library and provides its magic via a text interface. Other than logging, it provides z-modem up- and download-capability.
+
  
=== CuteCom ===
+
See [[Datasheets]].
This is an easy to use serial-terminal-program which is even able to write all communication into a log-file. It needs a computer with installed Qt-libs.[[Image:CuteCom.png|thumb|left]]
+
  
 
{{GPL}}
 
{{GPL}}

Revision as of 10:13, 26 December 2011

This is work in progress!

This manual is intended for aspiring coreboot developers to help them get up to speed with the code base and the tasks required to add support for new chipsets, devices, and mainboards. It covers coreboot v4.

How to support a new board

People often ask how to support a new board. If you are willing to put in the effort to write the port, then there is a good chance that you will succeed. Supporting a new board that uses a chipset that is already supported by coreboot is much less work for obvious reasons than supporting a new board with an unsupported chipset. Don't expect a new board to be supported by developers, especially an Intel board just because you would like it supported. Supporting a new board can take from an hour to over a year of time. If you would like a new board supported then you should expect to do the work on the port yourself.

Supporting a new board with the same cpu family, chipset and superIO

To support a new board with an already supported chipset look for the most similar board in the coreboot tree to the new board that you wish to support. After you find the most similar board, look for the differences between your new board and the most similar board.

If your new board has the same cpu family, cpu socket, chipset and superIO then you can try the coreboot build for the supported board on the new board with a backup flash device and debugging turned on. Look at the debug output to determine where the boot process stops or what errors are encountered on the way. Common differences between boards with exactly the same cpu, chipset and superIO are IRQ routing, ACPI and flash write enable routines or jumpers. Make changes to the board configuration, ACPI or IRQ routing etc etc until you find the proper settings. This can take from an hour of time to a few months based upon your coding skills and hardware issues.

Supporting a new board with the same cpu family, chipset but different superIO

If your new board has the same cpu family, cpu socket, chipset but the superIO is different but it is a supported superIO then you will have to change the board config to use the different superIO. More on this later....

Common differences between boards with exactly the same cpu, chipset but a different superIO are IRQ routing, ACPI and flash write enable routines or jumpers. Make changes to the board configuration, ACPI or IRQ routing etc etc until you find the proper settings. This can take from an hour of time to a few months based upon your coding skills and hardware issues.

Supporting a new board with a unsupported cpu, chipset or superIO

If your new board uses a cpu, chipset or superIO not supported by coreboot then you will have a lot of work in front of you. You will need developer data sheets for the cpu, chipset and superIO. AMD has been releasing data sheets to the public that includes most of the information required to support a new cpu and chipset. AMD has also been releasing complete coreboot patches to many of their recent cpu's and chipsets. Many of the superIO vendors have public documents available. Intel has been closed about releasing specifications at a low enough level to support a new cpu or chipset. Specifications are generally only provided to high volume OEM's. New developers requesting data sheets might have to wait for several months after signing NDA's until they receive the specifications.

Recommended hardware and software tools

See Developer Manual/Tools for a list of recommended tools which are useful for coreboot users and developers.

Hardware Overview

Intel Architecture

Hardware Reset

From Intel's "64 and IA-32 Architectures Software Developer’s Manual" (doc 253668-021 October 2006), Volume 3A, Section 9.1.4:

The first instruction that is fetched and executed following a hardware reset is located at physical address 0xFFFFFFF0. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the software-initialization code must be located at this address.
The address 0xFFFFFFF0 is beyond the 1-MByte addressable range of the processor while in real-address mode. The processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In real-address mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with 0xF000 and the base address is loaded with 0xFFFF0000. The starting address is thus formed by adding the base address to the value in the EIP register (that is, 0xFFFF0000 + 0xFFF0 = 0xFFFFFFF0).
The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To insure that the base address in the CS register remains unchanged until the EPROM based software-initialization code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would cause the CS selector value to be changed).

FWH/LPC Flash Memory

Modern mainboards are often equipped with Firmware Hub (FWH) or Low Pin Count (LPC) flash memory used to store the system bootloader ("BIOS"). Execution begins by fetching instructions 16 bytes below the flash memory's uppermost physical address.

coreboot Overview

View From The CPU: Intel Architecture

  1. At 0xFFFFFFF0, start execution at reset_vector from src/cpu/x86/16bit/reset16.inc, which simply jumps to _start.
  2. _start from src/cpu/x86/16bit/entry16.inc, invalidates the TLBs, sets up a GDT for selector 0x08 (code) and 0x10 (data), switches to protected mode, and jumps to __protected_start (setting the CS to the new selector 0x08). The selectors provide full flat access to the entire physical memory map.
  3. __protected_start from src/cpu/x86/32bit/entry32.inc, sets all other segment registers to the 0x10 selector.
  4. Execution continues with various mainboardinit fragments:
    1. __fpu_start from cpu/x86/fpu_enable.inc.
    2. (unlabeled) from cpu/x86/sse_enable.inc
    3. Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. cpu/amd/model_lx/cache_as_ram.inc.
  5. The final mainboardinit fragment is mainboard-specific, in C, called romstage.c. For non-cache-as-RAM targets, it is compiled with romcc. It includes and uses other C-code fragments for:
    1. Initializing MSRs, MTRRs, APIC.
    2. Setting up the southbridge minimally ("early setup").
    3. Setting up Super I/O serial.
    4. Initializing the console.
    5. Initializing RAM controller and RAM itself.
  6. Execution continues at __main from src/arch/x86/init/crt0_romcc_epilogue.inc, where the non-romcc C coreboot code is copied (possibly decompressed) to RAM, then the RAM entry point is jumped to.
  7. The RAM entry point is _start in src/arch/x86/lib/c_start.S, where new descriptor tables are set up, the stack and BSS are cleared, the IDT is initialized, and hardwaremain() is called (operation is now full 32-bit protected mode C program with stack).
  8. hardwaremain() is from src/boot/hardwaremain.c, the console is initialized, devices are enumerated and initialized, configured and enabled.
  9. The payload is called, either via elfboot() from boot/elfboot.c, or filo() from boot/filo.c.

Failover/Fallback/Normal images overview

See Developer Manual/Bootblock

Memory map

On x86 systems, many memory ranges are reserved for special purposes or have some other peculiar properties. The article Developer Manual/Memory map has details about this fact.

Serial output and the Super I/O

See Developer Manual/Super IO.

Northbridge

RAM init

See Developer Manual/RAM init.

Southbridge

Mainboard

devicetree.cb

The mainboard's devicetree.cb file contains many build and platform configuration settings. One of the most important items is the mainboard device list.

A device needs to be listed in the mainboard devicetree.cb if it requires more setup than standard PCI initialization (resource allocation). Typically, that includes the CPU, northbridge, southbridge, and Super I/O. These devices are usually required for system specific configuration as well as indicate the system bus structure (pci_domain).

When a device in devicetree.cb is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the device_operations and the chip_operations structures. You will find these structures in the devices source files.

irq_table.c

See Creating Valid IRQ Tables.

Creating a new target

To create a new mainboard target you have to add several files.

  • Multiple files in src/mainboard/vendorname/mainboardname (replace vendorname and mainboardname, of course).

Documentation and datasheets

Useful hardware/concepts documentation for developers

These external documents and slides explain fundamental concepts of hardware that coreboot supports.

Interrupts

System Managment Mode

Specific datasheets

See Datasheets.

GNU head This work is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This work is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.