Difference between revisions of "Developer Manual/Memory map"

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This page contains the description of various memory areas important for coreboot development.
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This page contains the description of various '''memory areas''' important for coreboot development.
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= Physical memory properties =
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== Below 1MB ==
  
=Physical memory properties=
 
==Below 1MB==
 
 
All memory below 1 MB has special rules attached to it. Due to legacy reasons, you can't allocate memory freely in that area without taking care.
 
All memory below 1 MB has special rules attached to it. Due to legacy reasons, you can't allocate memory freely in that area without taking care.
*0x00000 - 0x9FFFF: Low 640kB. Should not be clobbered on S3 suspend/resume (exceptions?)
 
*0xA0000 - 0xAFFFF: VGA graphics memory.
 
*0xB0000 - 0xB7FFF: Old monochrome graphics text mode memory. May not apply for recent cards.
 
*0xB8000 - 0xBFFFF: VGA text mode memory.
 
  
==Above 1MB==
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* '''0x00000 - 0x9FFFF''': Low 640kB. Should not be clobbered on S3 suspend/resume (exceptions?)
*0xFEC0_0000 may be fixed location IO APIC. Other possible locations are 0xFECX_YZ00 (not that 0xFEC cannot be changed)
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* '''0xA0000 - 0xAFFFF''': VGA graphics memory.
*0xFEEx_xxxx are internal APIC cycles for IRQ (MSI)
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* '''0xB0000 - 0xB7FFF''': Old monochrome graphics text mode memory. May not apply for recent cards.
*FEC0_0000 - FEC7_FFFF VIA APIC in SB (fixed)
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* '''0xB8000 - 0xBFFFF''': VGA text mode memory.
*FEC8_0000 - FECB_FFFF -VIA VPXII APIC
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*FED4_4000 - FED4_FFFF trusted platform module MEM decode (fixed)
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== Above 1MB ==
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* '''0xFEC0_0000''': May be fixed location IO APIC. Other possible locations are 0xFECX_YZ00 (note that 0xFEC cannot be changed)
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* '''0xFEC0_0000''': SB600 APIC BAR, can be changed
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* '''0xFEEx_xxxx''': These are internal APIC cycles for IRQ (MSI)
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* '''0xFEC0_0000 - 0xFEC7_FFFF''': VIA APIC in SB (fixed)
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* '''0xFEC8_0000 - 0xFECB_FFFF''': VIA VPXII APIC
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* '''0xFED4_4000 - 0xFED4_FFFF''': Trusted platform module (TPM) MEM decode (fixed)
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* '''0xFF00_0000 - 0xFFFF_FFFF''': 16 MByte ROM mapped into address space
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* '''0xFF80_0000 - 0xFFFF_FFFF''': 8 MByte ROM mapped into address space
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* '''0xFFC0_0000 - 0xFFFF_FFFF''': 4 MByte ROM mapped into address space
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* '''0xFFE0_0000 - 0xFFFF_FFFF''': 2 MByte ROM mapped into address space
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* '''0xFFF0_0000 - 0xFFFF_FFFF''': 1 MByte ROM mapped into address space
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* '''0xFFF8_0000 - 0xFFFF_FFFF''': 512 kByte ROM mapped into address space
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* '''0xFFFC_0000 - 0xFFFF_FFFF''': 256 kByte ROM mapped into address space
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* '''0xFFFE_0000 - 0xFFFF_FFFF''': 128 kByte ROM mapped into address space
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Some southbridges will restrict initial ROM mapping size to 1 MB or less. Some southbridges can't support more than 1MB or 4 MB. Some southbridges allow you to map the ROM anywhere.
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= coreboot related settings/usage =
  
=Coreboot related settings/usage=
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* '''0x00000200''': Location of stage2 in v3 (note: this may be obsolete in v4. TODO: Check)
*0x00000200: Location of stage2 in v3
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* '''0xFEC00000''': '''DEVICE_MEM_HIGH'''. The area between '''DEVICE_MEM_HIGH''' and 0xFFFFFFFF (4 GB) will be avoided by the resource allocator.
*0xFEC00000: DEVICE_MEM_HIGH. The area between DEVICE_MEM_HIGH and 0xFFFFFFFF (4 GB) will be avoided by the resource allocator.
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Latest revision as of 22:33, 18 September 2010

This page contains the description of various memory areas important for coreboot development.

Physical memory properties

Below 1MB

All memory below 1 MB has special rules attached to it. Due to legacy reasons, you can't allocate memory freely in that area without taking care.

  • 0x00000 - 0x9FFFF: Low 640kB. Should not be clobbered on S3 suspend/resume (exceptions?)
  • 0xA0000 - 0xAFFFF: VGA graphics memory.
  • 0xB0000 - 0xB7FFF: Old monochrome graphics text mode memory. May not apply for recent cards.
  • 0xB8000 - 0xBFFFF: VGA text mode memory.

Above 1MB

  • 0xFEC0_0000: May be fixed location IO APIC. Other possible locations are 0xFECX_YZ00 (note that 0xFEC cannot be changed)
  • 0xFEC0_0000: SB600 APIC BAR, can be changed
  • 0xFEEx_xxxx: These are internal APIC cycles for IRQ (MSI)
  • 0xFEC0_0000 - 0xFEC7_FFFF: VIA APIC in SB (fixed)
  • 0xFEC8_0000 - 0xFECB_FFFF: VIA VPXII APIC
  • 0xFED4_4000 - 0xFED4_FFFF: Trusted platform module (TPM) MEM decode (fixed)
  • 0xFF00_0000 - 0xFFFF_FFFF: 16 MByte ROM mapped into address space
  • 0xFF80_0000 - 0xFFFF_FFFF: 8 MByte ROM mapped into address space
  • 0xFFC0_0000 - 0xFFFF_FFFF: 4 MByte ROM mapped into address space
  • 0xFFE0_0000 - 0xFFFF_FFFF: 2 MByte ROM mapped into address space
  • 0xFFF0_0000 - 0xFFFF_FFFF: 1 MByte ROM mapped into address space
  • 0xFFF8_0000 - 0xFFFF_FFFF: 512 kByte ROM mapped into address space
  • 0xFFFC_0000 - 0xFFFF_FFFF: 256 kByte ROM mapped into address space
  • 0xFFFE_0000 - 0xFFFF_FFFF: 128 kByte ROM mapped into address space

Some southbridges will restrict initial ROM mapping size to 1 MB or less. Some southbridges can't support more than 1MB or 4 MB. Some southbridges allow you to map the ROM anywhere.

coreboot related settings/usage

  • 0x00000200: Location of stage2 in v3 (note: this may be obsolete in v4. TODO: Check)
  • 0xFEC00000: DEVICE_MEM_HIGH. The area between DEVICE_MEM_HIGH and 0xFFFFFFFF (4 GB) will be avoided by the resource allocator.