Developer Manual/Super IO - Revision history

Uwe at 01:07, 19 September 2010

2010-09-19T01:07:14Z

Stepan at 13:34, 25 February 2010

2010-02-25T13:34:14Z

Uwe: Created page with 'The Super I/O is a chip found on most of today's mainboards which is — among other things — responsible for the serial ports of the mainboard …'

2009-06-24T13:34:00Z

Created page with 'The Super I/O is a chip found on most of today's mainboards which is — among other things — responsible for the serial ports of the mainboard …'

New page

The [[wikipedia:Super I/O|Super I/O]] is a chip found on most of today's mainboards which is — among other things — responsible for the serial ports of the mainboard (e.g. COM1, COM2). This chip is usually the first thing you'll want to support, as it's required to get serial debugging output from the mainboard (via a null-modem cable and the proper software, e.g. [[minicom]] or CuteCom).

[[Image:Winbond w83977ef.jpg|thumb|right|<small>Winbond W83977EF Super I/O</small>]]
[[Image:Ite it8705f.jpg|thumb|right|<small>ITE IT8705F Super I/O</small>]]

The steps for adding support for a new Super I/O chip are:
* Add a directory src/superio/''vendor''/''device'' (e.g. src/superio/winbond/w83627ehg).
* In that directory, add a file ''device''_early_serial.c (e.g. w83627ehg_early_serial.c). This file will be responsible to setup a serial port on the mainboard so that you can get serial debugging output. This will work even ''before'' the RAM is initialized, thus is useful/required for debugging the RAM initialization process.
* In this file you now declare a function ''device''_enable_serial() which enables the requested serial port. Example:
static void w83627ehg_enable_serial(device_t dev, unsigned int iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
* Mainboards which have this Super I/O chip, will call this function in their ''auto.c'' or ''cache_as_ram_auto.c'' file. Example:
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
[...]
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
[...]
w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
:Whether the Super I/O is at config address ''0x2e'' (the usual case) or ''0x4e'' (or some other address) is mainboard-dependent. You can find out the address by running [[superiotool]].

=== Virtual logical devices ===

Some Super I/Os use register 0x30 of one logical device number (LDN) for more then one function enable. For example, it can be used to enable some GPIOs, GAME, MIDI etc. To overcome this issue a concept of virtual LDN has been introduced. Virtual LDNs can be used in coreboot to map the enable bit position in register 0x30 to virtual LDN, which will just enable the functionality map to that bit.

Original LDN always just switch on or off bit0 of register 0x30. Virtual LDN is created as follows.
Low [7:0] bits are used to describe the original LDN. High [10:8] bits select the position of the bit enable in the register 0x30.

If LDN is 0x7 it will handle bit0 of register 0x30. If the (virtual) LDN is 0x107 it will handle bit1 of same register etc.

@@ Line 1: / Line 1: @@
-The [[wikipedia:Super I/O|Super I/O]] is a chip found on most of today's mainboards which is &mdash; among other things &mdash; responsible for the serial ports of the mainboard (e.g. COM1, COM2). This chip is usually the first thing you'll want to support, as it's required to get serial debugging output from the mainboard (via a null-modem cable and the proper software, e.g. [[minicom]] or CuteCom).
+The [[wikipedia:Super I/O|Super I/O]] is a chip found on most of today's mainboards which is &mdash; among other things &mdash; responsible for the serial ports of the mainboard (e.g. COM1, COM2). This chip is usually the first thing you'll want to support, as it's required to get serial debugging output from the mainboard (via a null-modem cable and the proper software, e.g. minicom or CuteCom).
 [[Image:Winbond w83977ef.jpg|thumb|right|<small>Winbond W83977EF Super&nbsp;I/O</small>]]
@@ Line 5: / Line 5: @@
 The steps for adding support for a new Super I/O chip are:
-* Add a directory src/superio/''vendor''/''device'' (e.g. src/superio/winbond/w83627ehg).
+* Add a directory '''src/superio/''vendor''/''device''''' (e.g. '''src/superio/winbond/w83627ehg''').
-* In that directory, add a file ''device''_early_serial.c (e.g. w83627ehg_early_serial.c). This file will be responsible to setup a serial port on the mainboard so that you can get serial debugging output. This will work even ''before'' the RAM is initialized, thus is useful/required for debugging the RAM initialization process.
+* In that directory, add a file '''''device''_early_serial.c''' (e.g. '''w83627ehg_early_serial.c'''). This file will be responsible to setup a serial port on the mainboard so that you can get serial debugging output. This will work even ''before'' the RAM is initialized, thus is useful/required for debugging the RAM initialization process.
-* In this file you now declare a function ''device''_enable_serial() which enables the requested serial port. Example:
+* In this file you now declare a function '''''device''_enable_serial()''' which enables the requested serial port. Example:
    static void w83627ehg_enable_serial(device_t dev, unsigned int iobase)
+   {
@@ Line 17: / Line 17: @@
           pnp_exit_ext_func_mode(dev);
+   }
-* Mainboards which have this Super I/O chip, will call this function in their ''romstage.c'' file. Example:
+* Mainboards which have this Super I/O chip, will call this function in their '''romstage.c''' file. Example:
    #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
    [...]
@@ Line 25: / Line 25: @@
    uart_init();
    console_init();
-:Whether the Super I/O is at config address ''0x2e'' (the usual case) or ''0x4e'' (or some other address) is mainboard-dependent. You can find out the address by running [[superiotool]].
+:Whether the Super I/O is at config address '''0x2e''' (the usual case) or '''0x4e''' (or some other address) is mainboard-dependent. You can find out the address by running [[superiotool]].
 === Virtual logical devices ===
-Some Super I/Os use register 0x30 of one logical device number (LDN) for more then one function enable. For example, it can be used to enable some GPIOs, GAME, MIDI etc. To overcome this issue a concept of virtual LDN has been introduced. Virtual LDNs can be used in coreboot to map the enable bit position in register 0x30 to virtual LDN, which will just enable the functionality map to that bit.
+Some Super I/Os use register 0x30 of one logical device number (LDN) for more than one function enable. For example, it can be used to enable some GPIOs, GAME, MIDI etc. To overcome this issue a concept of virtual LDN has been introduced. Virtual LDNs can be used in coreboot to map the enable bit position in register 0x30 to virtual LDN, which will just enable the functionality map to that bit.
-Original LDN always just switch on or off bit0 of register 0x30. Virtual LDN is created as follows.
+Original LDN always just switch on or off bit0 of register 0x30. Virtual LDN is created as follows. Low [7:0] bits are used to describe the original LDN. High [10:8] bits select the position of the bit enable in the register 0x30.
 Low [7:0] bits are used to describe the original LDN. High [10:8] bits select the position of the bit enable in the register 0x30.
 If LDN is 0x7 it will handle bit0 of register 0x30. If the (virtual) LDN is 0x107 it will handle bit1 of same register etc.