Difference between revisions of "EHCI Debug Port"

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[[Image:PLX_NET20DC.jpg|thumb|right|PLX NET20DC USB Debug Device.]]
+
[[Image:PLX_NET20DC.jpg|thumb|right|Ajays NET20DC USB Debug Device.]]
 +
 
 
Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.
 
Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.
  
The '''EHCI Debug Port''' is an optional capability of EHCI controllers. All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.
+
The '''EHCI Debug Port''' is an optional capability of EHCI controllers which can be used for that purpose.
  
== Debug Class Device ==
+
All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.
  
While the Debug Class functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.
+
While the '''Debug Class''' functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.
  
== Considerations in coreboot ==
+
== Supported chipsets ==
  
We'll use Mode 1 since a full USB stack and EHCI driver isn't running when we're using the debug port. We get early two-way communication from PCI memory write accesses. printf() should transmit also to the debug port on any (all?) EHCI controllers sporting the capability. Linux already supports this and we could probably copy code or headers from the kernel.
+
The following southbridges have USB debug support in coreboot:
  
=== Supported chipsets ===
+
{| border="0" style="font-size: smaller" valign="top"
 +
|- bgcolor="#6699dd"
 +
! align="left" | Vendor
 +
! align="left" | Southbridge
 +
! align="left" | Status
 +
! align="left" | Comments
  
The following southbridges have USB debug support in coreboot:
+
|- bgcolor="#eeeeee" valign="top"
 +
| AMD
 +
| SB600
 +
| style="background:lime" | OK
 +
| Tested by [[User:Uwe|Uwe Hermann]].
 +
|- bgcolor="#eeeeee" valign="top"
 +
| AMD
 +
| SB700
 +
| style="background:orange" | WIP
 +
| Probably won't work, a patch is being prepared.
  
* NVIDIA MCP55
+
|- bgcolor="#dddddd" valign="top"
* SiS 966
+
| Intel
* AMD SB600
+
| 82801GX (ICH7)
* AMD SB700
+
| style="background:lime" | OK
* Intel 82801GX/ICH7 (untested)
+
| Tested by [[User:SvenS|Sven Schnelle]] on Lenovo Thinkpad X60/T60.
 +
|
  
=== Using EHCI Debug ===
+
|- bgcolor="#eeeeee" valign="top"
 +
| NVIDIA
 +
| MCP55
 +
| style="background:lime" | OK
 +
| Tested by [[User:Uwe|Uwe Hermann]]. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.
  
To get a USB debug console, enable '''CONFIG_USBDEBUG''' (menu option '''USB 2.0 EHCI debug dongle support''') in kconfig:
+
|- bgcolor="#dddddd" valign="top"
 +
| SiS
 +
| SiS966
 +
| style="background:yellow" | Untested
 +
| '''Note:''' It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).
 +
 
 +
|}
 +
 
 +
== Using the EHCI debug port ==
 +
 
 +
=== usb_debug kernel module and minicom ===
 +
 
 +
To get a USB debug console, enable '''CONFIG_USBDEBUG''' (menu option '''USB 2.0 EHCI debug dongle support''') in coreboot's kconfig.
 +
 
 +
On your "host PC" you need a Linux system which is recent enough to provide the '''usb_debug''' kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a '''/dev/ttyUSB0''' device to which you can connect as usual using any serial terminal program, e.g. '''minicom''' (115200, 8n1).
 +
 
 +
TODO: Is the Baud rate actually configurable somewhere?
 +
 
 +
You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.
 +
 
 +
Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.
 +
 
 +
=== usb_debug_io.c ===
 +
 
 +
As an alternative, you can also use [http://tracker.coreboot.org/trac/coreboot/ticket/57 this small libusb-based user-space program] on the host PC to retrieve the coreboot logs.
  
 
== Finding the USB debug port ==
 
== Finding the USB debug port ==
Line 30: Line 74:
 
Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port is rather difficult because you need to look at lots of information.
 
Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port is rather difficult because you need to look at lots of information.
  
Carl-Daniel Hailfinger has written [http://coreboot.org/pipermail/coreboot/2008-September/038635.html a script] which can help finding that port.
+
Carl-Daniel Hailfinger [http://www.coreboot.org/pipermail/coreboot/2008-September/038618.html has written] [http://www.coreboot.org/pipermail/coreboot/attachments/20080909/ae11c291/attachment.sh a script] which can help finding that port.
  
 
== Hardware capability ==
 
== Hardware capability ==
Line 36: Line 80:
 
The Debug Port is optional, please check if EHCI controllers near you support it:
 
The Debug Port is optional, please check if EHCI controllers near you support it:
  
  $ '''lspci -vs $(lspci|grep EHCI|cut -f1 -d' ')'''
+
  $ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do
 +
$ '''      lspci -vs $i'''
 +
$ '''done'''
 
  00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
 
  00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
 
  Subsystem: IBM Unknown device 0566
 
  Subsystem: IBM Unknown device 0566
Line 44: Line 90:
 
  Capabilities: [58] '''Debug port'''
 
  Capabilities: [58] '''Debug port'''
  
Look for a line like the last one above.
+
Look for a line like the last one above. Please include the PCI device ID too:
  
Please include the PCI device id too:
+
  $ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do
 
+
$ '''      lspci -ns $i'''
  $ '''lspci -ns $(lspci|grep EHCI|cut -f1 -d' ')'''
+
$ '''done'''
 
  00:1d.7 0c03: 8086:265c (rev 03)
 
  00:1d.7 0c03: 8086:265c (rev 03)
  
Line 75: Line 121:
 
* 1106:3104 VIA VX800 (rev 90)
 
* 1106:3104 VIA VX800 (rev 90)
  
=== Controllers verified to lack the Debug port capability ===
+
=== Controllers verified to lack the debug port capability ===
  
 
* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)
 
* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)
Line 84: Line 130:
 
* 1039:7002 SiS EHCI (rev 00)
 
* 1039:7002 SiS EHCI (rev 00)
  
== Where to buy ==
+
== Devices/Dongles ==
  
Currently there seems to be only two devices which can use the EHCI Debug Port, the '''NET20DC''' and the '''AMIDebug RX'''.
+
To be able to use the debug port it needs to be connected to a compatible device.
 +
Currently there seems to be only two commercial devices available which can use the EHCI Debug Port, the '''NET20DC''' and the '''AMIDebug RX'''.
 +
 
 +
=== DIY ===
 +
But you can also make your own usb debug dongle, see [[DIY_EHCI_debug_dongle]].
  
 
=== NET20DC ===
 
=== NET20DC ===
Line 99: Line 149:
  
 
* http://www.ami.com/amidebugrx/
 
* http://www.ami.com/amidebugrx/
 +
 +
== See also ==
 +
* [[EHCI Gadget Debug]]
  
 
== More information ==
 
== More information ==
Line 104: Line 157:
 
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) — The Debug Port is described in Appendix C.
 
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) — The Debug Port is described in Appendix C.
 
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) — This is what has to be connected to the EHCI controller.
 
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) — This is what has to be connected to the EHCI controller.
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) &mdash ''dead URL''
+
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) — ''dead URL''
 
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]
 
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]
 
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]
 
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]

Revision as of 11:30, 7 June 2013

Ajays NET20DC USB Debug Device.

Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.

The EHCI Debug Port is an optional capability of EHCI controllers which can be used for that purpose.

All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.

While the Debug Class functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.

Supported chipsets

The following southbridges have USB debug support in coreboot:

Vendor Southbridge Status Comments
AMD SB600 OK Tested by Uwe Hermann.
AMD SB700 WIP Probably won't work, a patch is being prepared.
Intel 82801GX (ICH7) OK Tested by Sven Schnelle on Lenovo Thinkpad X60/T60.
NVIDIA MCP55 OK Tested by Uwe Hermann. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.
SiS SiS966 Untested Note: It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).

Using the EHCI debug port

usb_debug kernel module and minicom

To get a USB debug console, enable CONFIG_USBDEBUG (menu option USB 2.0 EHCI debug dongle support) in coreboot's kconfig.

On your "host PC" you need a Linux system which is recent enough to provide the usb_debug kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a /dev/ttyUSB0 device to which you can connect as usual using any serial terminal program, e.g. minicom (115200, 8n1).

TODO: Is the Baud rate actually configurable somewhere?

You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.

Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.

usb_debug_io.c

As an alternative, you can also use this small libusb-based user-space program on the host PC to retrieve the coreboot logs.

Finding the USB debug port

Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port is rather difficult because you need to look at lots of information.

Carl-Daniel Hailfinger has written a script which can help finding that port.

Hardware capability

The Debug Port is optional, please check if EHCI controllers near you support it:

$ for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do
$       lspci -vs $i
$ done
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
Subsystem: IBM Unknown device 0566
Flags: bus master, medium devsel, latency 0, IRQ 5
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [50] Power Management version 2
Capabilities: [58] Debug port

Look for a line like the last one above. Please include the PCI device ID too:

$ for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do
$       lspci -ns $i
$ done
00:1d.7 0c03: 8086:265c (rev 03)

If your controller isn't already listed below then please add it or send an email to the mailing list if you don't have a wiki account yet and want one, or want us to add your controller to the page.

Controllers verified to have the debug port capability

  • 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
  • 8086:24cd Intel ICH4/ICH4-M
  • 8086:24dd Intel ICH5
  • 8086:265c Intel ICH6
  • 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)
  • 8086:27cc Intel ICH7
  • 8086:2836 Intel ICH8
  • 8086:283a Intel ICH8
  • 8086:293a Intel ICH9 (rev 2)
  • 8086:3a3a Intel ICH10
  • 8086:3a3c Intel ICH10
  • 10de:0088 NVIDIA MCP2A (rev a2)
  • 10de:005b NVIDIA CK804 (rev a3)
  • 10de:026e NVIDIA MCP51 (rev a3)
  • 10de:036d NVIDIA MCP55 (rev a2)
  • 10de:03f2 NVIDIA MCP61 (rev a3)
  • 1002:4386 ATI/AMD SB600
  • 1002:4396 ATI/AMD SB700
  • 1106:3104 VIA VX800 (rev 90)

Controllers verified to lack the debug port capability

  • 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)
  • 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)
  • 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)
  • 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
  • 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)
  • 1039:7002 SiS EHCI (rev 00)

Devices/Dongles

To be able to use the debug port it needs to be connected to a compatible device. Currently there seems to be only two commercial devices available which can use the EHCI Debug Port, the NET20DC and the AMIDebug RX.

DIY

But you can also make your own usb debug dongle, see DIY_EHCI_debug_dongle.

NET20DC

AMIDebug RX

See also

More information