Difference between revisions of "Easy projects"

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m (AMD 740G information gathering: We also want -V for superiotool in case an unknown chip is used.)
(flashrom)
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If you're a coreboot or flashrom newbie, this page is for you.
 
If you're a coreboot or flashrom newbie, this page is for you.
  
= flashrom =
+
== coreboot ==
  
The [[flashrom]] tool can read/write coreboot/BIOS images from/to flash chips.
 
  
== Add timing info to flash chip definitions ==
+
=== AMD 740G information gathering ===
  
Go through the list of flash chips in flashchips.c inside the flashrom source. For each chip (except SPI chips), read through the data sheets and add a comment to the flash chip definition which contains the timing information in microseconds(!) for the probe sequence.
+
(This project description is not finished yet)
  
This will make probing a lot more reliable.
+
If you have a board with AMD 740G chipset, please run (as root)
  
Every annotated chip helps.
+
$ '''flashrom -V'''
 +
$ '''lspci -nnvvvxxxx'''
 +
$ '''superiotool -deV'''
 +
$ '''dmidecode'''
  
== Add the bus type to flash chip definitions ==
+
and mail the output to the [[Mailinglist|coreboot mailing list]] together with the exact model number/name of your board.
  
Go through the list of flash chips in flashchips.c inside the flashrom source. Look for chip definitions which have .bustype = CHIP_BUSTYPE_NONSPI and look at their data sheets. Read the data sheets and try to figure out the flash bus they use (Parallel/LPC/FWH/SPI). Change the bustype field to CHIP_BUSTYPE_PARALLEL etc. and post a patch to the list.
+
This helps us evaluate which boards are good targets for coreboot.
  
This will make probing faster and more reliable.
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Here are some boards:
  
Even a single updated chip helps.
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* http://www.czechcomputer.cz/cat_tree.jsp?bpath=Z%C3%A1kladn%C3%AD+desky\Socket+AM2%2B\AMD+740G
  
[[Flashrom#Communication_bus_protocol]] has a writeup on how to figure out the bus type.
+
=== Use CBFS wherever possible ===
  
== Add new flash chip definitions ==
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* <code>src/cpu/amd/model_lx/vsmsetup.c</code> is a very good candidate. The VSM blobs should be loaded from [[CBFS]]. See [http://review.coreboot.org/gitweb?p=coreboot.git;a=commitdiff;h=9839cbd53fdcfcee52c406d9f52af924192e618d commit 9839cbd53fdcfcee52c406d9f52af924192e618d] for the new location of the code.
  
We have a few dozen chip IDs listed in flash.h, but not in flashchips.c. Find them, dig up the data sheets and add chip definitions for them to flashchips.c. You can use similar flash chips as a guideline.
+
=== Formatting and whitespace cleanup ===
  
This will reduce the number of undetected chips.
+
We try to maintain the code in the [[Development_Guidelines#Coding_Style Linux style]], but occasionally white-space and other formatting issues find their way into the project. Formatting and white-space changes should be done in small groups as a separate patch from code changes. Be careful running indent/lindent. The results are not always the right thing to do and require review.
  
Every added chip broadens flashrom support.
+
Ideally a check/test should be integrated into the build system pointing out these issues already when committing or testing the commit. Such tests probably already exist in other projects and just need to be copied.
  
== Test flashrom ==
+
== Payloads ==
  
If you have a desktop (no laptops/notebooks/netbooks), please run
+
coreboot can use a number of different [[Payloads|payloads]].
flashrom
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and check if it finds your flash chip. If it does and any of the operations are listed as unsupported, we'd like to hear about it. If your flash chip is not found, we'd like to hear about it as well.
+
  
In both cases, please send the output of
+
=== Add/test new supported payloads ===
flashrom -V
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to the coreboot [[Mailinglist|mailing list]] (preferred) or to [mailto:flashrom@coreboot.org flashrom@coreboot.org]
+
  
= coreboot =
+
* Test syslinux (probably requires [[SeaBIOS]] in addition, needs to be checked).
 +
* Port [[GPXE]] to "native" coreboot (it works fine together with [[SeaBIOS]] though).
  
I'll skip explaining what coreboot is. The whole wiki is about this topic and I can't summarize it in one sentence.
+
== flashrom ==
  
== coreboot v2 ==
+
The [http://www.flashrom.org flashrom] tool can read/write coreboot/BIOS images from/to flash chips.
  
The workhorse version of coreboot. Lots of supported boards, but difficult to work with.
+
* See [http://flashrom.org/Easy_projects flashrom's Easy Projects] list for details.
 
+
===AMD 740G information gathering===
+
(This project description is not finished yet)
+
 
+
If you have a board with AMD 740G chipset, please run (as root)
+
flashrom -V
+
lspci -nnvvvxxxx
+
superiotool -edV
+
dmidecode
+
and mail the output to FIXME together with the exact model number/name of your board.
+
 
+
This helps us evaluate which boards are good targets for coreboot.
+
 
+
== coreboot v3 ==
+
 
+
The next generation version of coreboot. Few supported boards, still in the design testing phase, easy to work with.
+
 
+
TODO: Add easy tasks here.
+
 
+
= Payloads =
+
 
+
coreboot can use a number of different [[Payloads|payloads]].
+
 
+
== Add/test new supported payloads ==
+
 
+
* Test syslinux (probably requires [[SeaBIOS]] in addition, needs to be checked).
+
* Port [[GPXE]] to "native" coreboot (it works fine together with [[SeaBIOS]] though).
+
  
= Other =
+
== Other ==
  
* Add support for using coreboot in VirtualBox.
+
* Add [http://tracker.coreboot.org/trac/coreboot/ticket/95 support for using coreboot in VirtualBox].

Revision as of 13:34, 2 April 2013

You probably came here trying to find a small (minutes to hours) and easy task where you can get your hands dirty and get results immediately.

If you're a coreboot or flashrom newbie, this page is for you.

coreboot

AMD 740G information gathering

(This project description is not finished yet)

If you have a board with AMD 740G chipset, please run (as root)

$ flashrom -V
$ lspci -nnvvvxxxx
$ superiotool -deV
$ dmidecode

and mail the output to the coreboot mailing list together with the exact model number/name of your board.

This helps us evaluate which boards are good targets for coreboot.

Here are some boards:

Use CBFS wherever possible

Formatting and whitespace cleanup

We try to maintain the code in the Development_Guidelines#Coding_Style Linux style, but occasionally white-space and other formatting issues find their way into the project. Formatting and white-space changes should be done in small groups as a separate patch from code changes. Be careful running indent/lindent. The results are not always the right thing to do and require review.

Ideally a check/test should be integrated into the build system pointing out these issues already when committing or testing the commit. Such tests probably already exist in other projects and just need to be copied.

Payloads

coreboot can use a number of different payloads.

Add/test new supported payloads

  • Test syslinux (probably requires SeaBIOS in addition, needs to be checked).
  • Port GPXE to "native" coreboot (it works fine together with SeaBIOS though).

flashrom

The flashrom tool can read/write coreboot/BIOS images from/to flash chips.

Other