Difference between revisions of "Glossary"

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=== ACPI ===
 
=== ACPI ===
 
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
 
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
 +
* [[ACPI|ACPI and coreboot]]
 
* http://www.acpi.info/
 
* http://www.acpi.info/
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
+
* http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface
 +
* http://kernelslacker.livejournal.com/88243.html (acpitool to generate a C source (see mailing list also))
  
 
=== AGP ===
 
=== AGP ===
'''Advanced Graphics Port'''
+
'''Advanced Graphics Port''', a point-to-point channel for attaching a video card to a mainboard with AGP slot.
* http://en.wikipedia.org/wiki/AGP
+
* http://en.wikipedia.org/wiki/Accelerated_Graphics_Port
  
 
=== AGP Aperture ===
 
=== AGP Aperture ===
 
The memory range that is set aside for AGP access.
 
The memory range that is set aside for AGP access.
* http://en.wikipedia.org/wiki/AGP
+
* http://en.wikipedia.org/wiki/Accelerated_Graphics_Port
  
 
=== AHCI ===
 
=== AHCI ===
 
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
 
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
* http://en.wikipedia.org/wiki/AHCI
+
* http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface
 
* http://www.intel.com/technology/serialata/ahci.htm
 
* http://www.intel.com/technology/serialata/ahci.htm
 +
* http://download.intel.com/technology/serialata/pdf/rev1_3.pdf (AHCI spec 1.3)
  
 
=== APIC ===
 
=== APIC ===
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.
+
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: '''Local APICs''' (LAPIC) are CPU-bound, '''IO-APICs''' are bridge-bound.
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
+
* http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller
 
* http://osdev.berlios.de/pic.html
 
* http://osdev.berlios.de/pic.html
  
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=== BAR ===
 
=== BAR ===
Base Address Register.
+
'''Base Address Register''' (on PCI device).
 +
* http://en.wikipedia.org/wiki/Base_Address_Register#Bus_enumeration
 +
* http://wiki.osdev.org/PCI#Base_Address_Registers
  
 
=== BIOS ===
 
=== BIOS ===
Basic Input/Output System.
+
'''Basic Input/Output System'''.
 +
* http://en.wikipedia.org/wiki/BIOS
  
 +
=== BIST ===
 +
The '''Built-In Self Test''', a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.
  
 
== C ==
 
== C ==
  
 
=== CAR ===  
 
=== CAR ===  
Cache as RAM.
+
'''Cache as RAM'''.
  
 
=== CMOS ===  
 
=== CMOS ===  
complementary metal oxyde semiconductor
+
'''Complementary metal oxyde semiconductor''', a [http://en.wikipedia.org/wiki/CMOS class of semiconductors]. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.
 +
* http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory
  
=== cpu  ===
+
=== CPU ===
central processing unit ( e.g. an Athlon64 )
+
'''Central processing unit''' (e.g. an Athlon64).
 +
* http://en.wikipedia.org/wiki/Central_processing_unit
 +
 
 +
=== crt0 ===
 +
'''C Run Time 0''' - This is now called the romstage in coreboot.
 +
* http://en.wikipedia.org/wiki/Crt0
 +
 
 +
=== crt0s ===
 +
Sources that make up the romstage in coreboot, see [[#crt0|crt0]].
  
 
== D ==
 
== D ==
  
 
=== DCR ===
 
=== DCR ===
Decode Control Register.
+
'''Decode Control Register'''.
  
 
=== DID ===
 
=== DID ===
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.
+
'''Device ID''', a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.
  
 
=== DMA ===
 
=== DMA ===
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
+
'''Direct Memory Access'''. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
 
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
 
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
 
* http://en.wikipedia.org/wiki/Direct_memory_access
 
* http://en.wikipedia.org/wiki/Direct_memory_access
 +
 +
=== DSDT ===
 +
'''Differentiated System Descriptor Table''', generated by BIOS and necessary for [[#ACPI|ACPI]]. Implementation of [[ACPI|ACPI in coreboot]] needs to be done in a "cleanroom" development process to avoid legal issues.
 +
* http://acpi.sourceforge.net/dsdt/index.php
  
 
== E ==
 
== E ==
EEPROM electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM)
 
  
ehci Enhanced Host Controller Interface (USB host controller)
+
=== EEPROM ===
 +
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).
 +
 
 +
=== EHCI ===
 +
Enhanced Host Controller Interface (USB host controller).
  
 
== F ==
 
== F ==
Line 91: Line 115:
 
* http://en.wikipedia.org/wiki/GPIO
 
* http://en.wikipedia.org/wiki/GPIO
  
=== gsoc ===
+
=== GSoC ===
Google Summer of Code
+
[[GSoC|Google Summer of Code]].
  
 
== H ==
 
== H ==
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* http://en.wikipedia.org/wiki/Hypertransport
 
* http://en.wikipedia.org/wiki/Hypertransport
 
* http://www.hypertransport.org
 
* http://www.hypertransport.org
 
+
* http://www.hotchips.org/archives/hc14/3_Tue/28_AMD_Hammer_MP_HC_v8.pdf
  
 
== I ==
 
== I ==
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=== JTAG ===
 
=== JTAG ===
debugging and test 4-wire interface named after an organization which defined it
+
Debugging and test 4-wire interface named after an organization which defined it.
  
 
== L ==
 
== L ==
 +
 +
=== LAR ===
 +
is the Linuxbios ARchiver, now called Lightweight [[LAR_Design|ARchiver]]. It is a small utility that we use to create and change coreboot images and their modules.
  
 
=== LPC ===
 
=== LPC ===
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'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
 
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
 
* http://computer.laborlawtalk.com/Least%20Recently%20Used
 
* http://computer.laborlawtalk.com/Least%20Recently%20Used
 
  
 
== M ==
 
== M ==
 +
 +
=== Memory Training ===
 +
 +
'''Memory training''' is a very complex technlogical area. We are accumulating references to it as we find them.
 +
 +
* A [http://www.freshpatents.com/Training-of-signal-transfer-channels-between-memory-controller-and-memory-device-dt20080515ptan20080112255.php patent for GDDR4]
 +
* Key to understanding training is the concept of an [http://en.wikipedia.org/wiki/Eye_diagram eye diagram]
 +
 +
It is amazing, but there is very little out there.
  
 
=== MII ===
 
=== MII ===
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=== MPTable ===
 
=== MPTable ===
 
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
 
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
* http://www.uruk.org/~erich/mps.html
+
* http://www.uruk.org/mps/
 
* http://www.intel.com/design/pentium/datashts/242016.htm
 
* http://www.intel.com/design/pentium/datashts/242016.htm
  
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'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
 
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
 
* http://en.wikipedia.org/wiki/MTRR
 
* http://en.wikipedia.org/wiki/MTRR
 
  
 
== O ==
 
== O ==
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PCI IRQ routing table,
 
PCI IRQ routing table,
 
* http://www.microsoft.com/whdc/archive/pciirq.mspx
 
* http://www.microsoft.com/whdc/archive/pciirq.mspx
* http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148
 
 
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
 
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
 
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
 
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
Line 212: Line 245:
 
=== PLCC ===
 
=== PLCC ===
 
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
 
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
 +
* http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier
 
* http://www.webopedia.com/TERM/P/PLCC.html
 
* http://www.webopedia.com/TERM/P/PLCC.html
  
Line 228: Line 262:
 
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access
 
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access
  
=== rvs ===
+
=== RCS ===
revision control system
+
Revision control systems.
  
 
== S ==
 
== S ==
Line 241: Line 275:
  
 
=== Shadow RAM ===
 
=== Shadow RAM ===
 
+
RAM which content is copied from ROM residing at the same address for speedup purposes.
RAM which content is copied from ROM residing at the same address for speedup purposes
+
  
 
=== SIO ===
 
=== SIO ===
Line 258: Line 291:
 
=== SMRAM ===
 
=== SMRAM ===
 
System Management Random Access Memory.
 
System Management Random Access Memory.
 +
 +
=== SOIC ===
 +
'''Small-Outline Integrated Circuit'''.
 +
* http://en.wikipedia.org/wiki/Small-outline_integrated_circuit
  
 
=== SPD ===
 
=== SPD ===
Line 270: Line 307:
 
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.
 
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.
 
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
 
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
 
  
 
== T ==
 
== T ==

Revision as of 14:11, 26 September 2010

A

ACPI

The Advanced Configuration & Power Interface is an industry standard for letting the OS control power management.

AGP

Advanced Graphics Port, a point-to-point channel for attaching a video card to a mainboard with AGP slot.

AGP Aperture

The memory range that is set aside for AGP access.

AHCI

The Advanced Host Controller Interface. Describes the register-level interface for a SATA host controller.

APIC

Advanced Programmable Interrupt Controller. An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.


B

BAR

Base Address Register (on PCI device).

BIOS

Basic Input/Output System.

BIST

The Built-In Self Test, a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.

C

CAR

Cache as RAM.

CMOS

Complementary metal oxyde semiconductor, a class of semiconductors. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.

CPU

Central processing unit (e.g. an Athlon64).

crt0

C Run Time 0 - This is now called the romstage in coreboot.

crt0s

Sources that make up the romstage in coreboot, see crt0.

D

DCR

Decode Control Register.

DID

Device ID, a way of identifying the hardware in question. See VID for more info.

DMA

Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

DSDT

Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI. Implementation of ACPI in coreboot needs to be done in a "cleanroom" development process to avoid legal issues.

E

EEPROM

Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).

EHCI

Enhanced Host Controller Interface (USB host controller).

F

Flashing

Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.

Framebuffer

The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:

  • Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
  • On-screen, meaning that the framebuffer is directly coupled to the visible display


G

GART

Graphics Address Relocation Table.

GATT

Graphics Aperture Translation Table.

GPIO

General Purpose Input/Output.

GSoC

Google Summer of Code.

H

Hypertransport

A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.

I

I2C

Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control.

IDSEL/AD

Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?

IRQ

Interrupt ReQuest (Handler).


J

JTAG

Debugging and test 4-wire interface named after an organization which defined it.

L

LAR

is the Linuxbios ARchiver, now called Lightweight ARchiver. It is a small utility that we use to create and change coreboot images and their modules.

LPC

Low Pin Count, an interface aimed at replacing the ISA bus.

LRU

Least Recently Used, a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.

M

Memory Training

Memory training is a very complex technlogical area. We are accumulating references to it as we find them.

It is amazing, but there is very little out there.

MII

Media Independent Interface. This is a chip commonly found on ethernet devices, together with a PHY.

MMIO

Memory-mapped I/O and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.

MPTable

Multi Processor Table. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.

MTRR

Memory Type Range Register. This can be used to control the way a processor accesses memory ranges.

O

OHCI

Open Host Controller Interface. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).


P

PAM

Programmable Attribute Map. Hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers, accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.

PAT

Page Attribute Table. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.

PAT

Performance Acceleration Technology.

PCI

Peripheral Component Interconnect.

PCI Configuration Space

PCI Express / PCIe

PHY

PHY layer device. A device that provides low level access to the physical layer.

PIC

A Programmable Interrupt Controller is a device to control peripheral devices, offloading the main CPU.

PIO

Programmed Input/Output interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.

PIR

Programmable Interrupt Routing?

PIRQ

PCI IRQ routing table,

PLCC

Plastic Leaded Chip Carrier, a square surface-mount chip package.

PLL

Phase Locked Loop is a device to keep (electrical) signals synchronised throughout the system.

POST

The Power On Self Test is a test to check that devices the computer will rely on are functioning, and initializes devices.

R

RDMA

Remote Direct Memory Access is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.

RCS

Revision control systems.

S

SB

Southbridge. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...

SBA

SideBand Addressing.

Shadow RAM

RAM which content is copied from ROM residing at the same address for speedup purposes.

SIO

Serial Input/Output.

SMBus

The System Management Bus is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.

SMM

System Management Mode. Processor mode that is mainly used for power management purposes.

SMRAM

System Management Random Access Memory.

SOIC

Small-Outline Integrated Circuit.

SPD

Serial Presence Detect. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.

SPI

The Serial Peripheral Interface Bus is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.

SuperIO

The SuperIO is the chip that provides floppy, serial and parallel functionality/ports.

T

TLB

Translation Lookaside Buffer. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.


U

UC

Strong UnCacheable. Memory type setting in MTRR/PAT.

UC

UnCacheable. Memory type setting in MTRR/PAT.

  • For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

UHCI

Universal Host Controller Interface. USB standard.


V

VGAcon

The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).

VID

Vendor ID, a way of identifying the hardware manufacturer.

A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.

VMEBus

VERSAmodule Eurocard Bus or Versa Module Europa Bus. A computer bus originally developed for the Motorola 68000.

W

WB

Write-Back. Memory type setting in MTRR/PAT.

WC

Write-Combining. Memory type setting in MTRR/PAT.

WP

Write Protected. Memory type setting in MTRR/PAT.

WT

Write-Through. Memory type setting in MTRR/PAT.

  • For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3