Difference between revisions of "Glossary"

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m ('''Glossary''': Some small additions in existing entries)
m (some highlights)
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== '''Glossary''' ==  
 
== '''Glossary''' ==  
  
'''This page is a work in progress'''
+
'''This page is a work in progress. Entries are not in alphabetical order.'''
  
 
'''MMIO''' (Memory-mapped I/O) and port I/O (also called port-mapped I/O or
 
'''MMIO''' (Memory-mapped I/O) and port I/O (also called port-mapped I/O or
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http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
 
http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
 
----------------------------------------------------
 
----------------------------------------------------
The purpose of the VGAcon (VGA controller) is to isolate the details of VGA
+
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA
 
signal generation from all the other modules in a (hardware) design. It
 
signal generation from all the other modules in a (hardware) design. It
 
allows the pixel information to be written into its video memory using a
 
allows the pixel information to be written into its video memory using a
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----------------------------------------------------
 
----------------------------------------------------
 
'''APIC''' (Advanced Programmable Interrupt Controller). An advanced version of
 
'''APIC''' (Advanced Programmable Interrupt Controller). An advanced version of
a PIC that can handle interrupts from and for multiple CPUs.
+
a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.
  
 
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
 
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
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----------------------------------------------------
 
----------------------------------------------------
SMRAM (System Management Random Access Memory).
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'''SMRAM''' (System Management Random Access Memory).
  
  
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----------------------------------------------------
 
----------------------------------------------------
PIR (Programmable Interrupt Routing?)
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'''PIR''' (Programmable Interrupt Routing?)
  
  
 
----------------------------------------------------
 
----------------------------------------------------
DCR (Decode Control Register)
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'''DCR''' (Decode Control Register)
  
  
 
----------------------------------------------------
 
----------------------------------------------------
LPC (Low Pin Count). An interface aimed at replacing he ISA bus.
+
'''LPC''' (Low Pin Count). An interface aimed at replacing he ISA bus.
  
 
http://www.intel.com/design/chipsets/industry/lpc.htm
 
http://www.intel.com/design/chipsets/industry/lpc.htm
 
----------------------------------------------------
 
----------------------------------------------------
IDSEL/AD (Initialization Device SELect/Address and Data).
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'''IDSEL/AD''' (Initialization Device SELect/Address and Data).
  
 
Each PCI slot has a signal called IDSEL. It is used to differentiate
 
Each PCI slot has a signal called IDSEL. It is used to differentiate
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http://www.fpga4fun.com/PCI4.html
 
http://www.fpga4fun.com/PCI4.html
 
----------------------------------------------------
 
----------------------------------------------------
PHY (PHY layer device). A device that provides low level access
+
'''PHY''' (PHY layer device). A device that provides low level access
 
to the physical layer.
 
to the physical layer.
  
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http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
 
http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
 
----------------------------------------------------
 
----------------------------------------------------
MII (Media Independent Interface). This is a chip commonly found
+
'''MII''' (Media Independent Interface). This is a chip commonly found
 
on ethernet devices, together with a PHY.
 
on ethernet devices, together with a PHY.
  
 
http://en.wikipedia.org/wiki/MII
 
http://en.wikipedia.org/wiki/MII
 
----------------------------------------------------
 
----------------------------------------------------
MTRR (Memory Type Range Register). This can be used to control the way a
+
'''MTRR''' (Memory Type Range Register). This can be used to control the way a
 
processor accesses memory ranges.
 
processor accesses memory ranges.
  
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----------------------------------------------------
 
----------------------------------------------------
PAT (Page Attribute Table). Can be used independently or in combination
+
'''PAT''' (Page Attribute Table). Can be used independently or in combination
 
with MTRR to setup memory type access ranges. Allows more finely-grained control
 
with MTRR to setup memory type access ranges. Allows more finely-grained control
 
than MTRR.
 
than MTRR.
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http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
 
http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
 
----------------------------------------------------
 
----------------------------------------------------
TLB (Translation Lookaside Buffer). The TLB stores the most recently used
+
'''TLB''' (Translation Lookaside Buffer). The TLB stores the most recently used
 
page-directory and page-table entries, which translates into speedier
 
page-directory and page-table entries, which translates into speedier
 
access to said memory.
 
access to said memory.
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For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
 
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
 
----------------------------------------------------
 
----------------------------------------------------
UC (strong UnCacheable). Memory type setting in MTRR/PAT.
+
'''UC''' (strong UnCacheable). Memory type setting in MTRR/PAT.
  
UC- (UnCacheable). Memory type setting in MTRR/PAT.
+
'''UC-''' (UnCacheable). Memory type setting in MTRR/PAT.
  
WC (Write-Combining). Memory type setting in MTRR/PAT.
+
'''WC''' (Write-Combining). Memory type setting in MTRR/PAT.
  
WT (Write-Through). Memory type setting in MTRR/PAT.
+
'''WT''' (Write-Through). Memory type setting in MTRR/PAT.
  
WB (Write-Back). Memory type setting in MTRR/PAT.
+
'''WB''' (Write-Back). Memory type setting in MTRR/PAT.
  
WP (Write Protected). Memory type setting in MTRR/PAT.
+
'''WP''' (Write Protected). Memory type setting in MTRR/PAT.
  
 
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
 
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
 
----------------------------------------------------
 
----------------------------------------------------
PAT (Performance Acceleration Technology).
+
'''PAT''' (Performance Acceleration Technology).
  
 
http://www.intel.com/design/chipsets/pat.htm
 
http://www.intel.com/design/chipsets/pat.htm
 
----------------------------------------------------
 
----------------------------------------------------
AGP (Advanced Graphics Port).
+
'''AGP''' (Advanced Graphics Port).
  
 
http://en.wikipedia.org/wiki/AGP
 
http://en.wikipedia.org/wiki/AGP
 
----------------------------------------------------
 
----------------------------------------------------
AGP Aperture. The memory range that is set aside for AGP access.
+
'''AGP Aperture'''. The memory range that is set aside for AGP access.
  
 
http://en.wikipedia.org/wiki/AGP
 
http://en.wikipedia.org/wiki/AGP
  
 
----------------------------------------------------
 
----------------------------------------------------
GART (Graphics Address Relocation Table)
+
'''GART''' (Graphics Address Relocation Table)
  
 
http://www.linuxelectrons.com/article.php/20031021142247752
 
http://www.linuxelectrons.com/article.php/20031021142247752

Revision as of 11:16, 3 April 2006

Glossary

This page is a work in progress. Entries are not in alphabetical order.

MMIO (Memory-mapped I/O) and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.

http://encyclopedia.thefreedictionary.com/mmio


PIO (Programmed Input/Output) interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.

http://encyclopedia.thefreedictionary.com/pio


The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:

  • Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
  • On-screen, meaning that the framebuffer is directly coupled to the visible display

http://encyclopedia.thefreedictionary.com/framebuffer


POST (Power On Self Test) is a test to check that devices the computer will rely on are functioning, and initializes devices.

http://encyclopedia.thefreedictionary.com/booting


I2C - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for more info.

Code examples(?): ...


VID - Vendor ID, a way of identifying the hardware manufacturer. See 'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and 'http://pciids.sourceforge.net/' for more info.

A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.


DID - Device ID, a way of identifying the hardware in question. See VID (above) for more info.


DMA (Direct Memory Access) allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

http://encyclopedia.thefreedictionary.com/direct%20memory%20access


RDMA (Remote Direct Memory Access) is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.

http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access


The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students fpga project)

http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm


AHCI (Advanced Host Controller Interface). Describes the register-level interface for a SATA host controller.

http://encyclopedia.thefreedictionary.com/ahci http://www.intel.com/technology/serialata/ahci.htm


OHCI (Open Host Controller Interface). IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel)

http://encyclopedia.thefreedictionary.com/ohci http://developer.intel.com/technology/1394/download/ohci_11.htm


UHCI (Universal Host Controller Interface). USB standard.

http://encyclopedia.thefreedictionary.com/dict.asp?Word=uhci http://developer.intel.com/technology/usb/uhci11d.htm


SPI (Serial Peripheral Interface Bus) is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.

http://encyclopedia.thefreedictionary.com/Serial%20Peripheral%20Interface http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus


SIO (Serial Input/Output)

http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search


PIC (Programmable Interrupt Controller) is a device to control peripheral devices, offloading the main CPU.

http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller http://www.interq.or.jp/japan/se-inoue/e_pic1.htm


PLL (Phase Locked Loop) is a device to keep (electrical) signals synchronised throughout the system.

http://en.wikipedia.org/wiki/PLL


SuperIO is the chip that provides floppy, serial and parallel functionality/ports.

http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html


SPD (Serial Presence Detect). On every (?) memory module there's an eprom that provides BIOS with information on how to properly configure the memory module.

http://www.simmtester.com/page/news/showpubnews.asp?num=101


SMBus (System Management Bus) is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.

http://www.smbus.org/ http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus See I2C for more info.


ACPI (Advanced Configuration & Power Interface) is an industry standard for letting the OS control power management.

http://www.acpi.info/ http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface


APIC (Advanced Programmable Interrupt Controller). An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.

http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller http://osdev.berlios.de/pic.html


VMEBus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus originally developed for the Motorola 68000.

http://encyclopedia.thefreedictionary.com/VMEbus


PCI (Peripheral Component Interconnect).

http://encyclopedia.thefreedictionary.com/PCI


PCI Configuration Space.

http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space http://www.techfest.com/hardware/bus/pci.htm


PIRQ (Pci IRQ routing table).

http://www.microsoft.com/whdc/archive/pciirq.mspx http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148 http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view


PAM (Programmable Attribute Map).

hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.


SMM (System Management Mode)

Processor mode that is mainly used for power management purposes.


SMRAM (System Management Random Access Memory).



MPTable (Multi Processor Table). Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.

http://www.uruk.org/~erich/mps.html http://www.intel.com/design/pentium/datashts/242016.htm



PIR (Programmable Interrupt Routing?)



DCR (Decode Control Register)



LPC (Low Pin Count). An interface aimed at replacing he ISA bus.

http://www.intel.com/design/chipsets/industry/lpc.htm


IDSEL/AD (Initialization Device SELect/Address and Data).

Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?

http://www.techfest.com/hardware/bus/pci.htm http://www.fpga4fun.com/PCI4.html


PHY (PHY layer device). A device that provides low level access to the physical layer.

http://en.wikipedia.org/wiki/PHY http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer


MII (Media Independent Interface). This is a chip commonly found on ethernet devices, together with a PHY.

http://en.wikipedia.org/wiki/MII


MTRR (Memory Type Range Register). This can be used to control the way a processor accesses memory ranges.

http://en.wikipedia.org/wiki/MTRR


PAT (Page Attribute Table). Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.

http://www.intel.com/design/pentium4/manuals/index_new.htm http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10


TLB (Translation Lookaside Buffer). The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.

http://www.linuxelectrons.com/article.php/20031021142247752 For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1


UC (strong UnCacheable). Memory type setting in MTRR/PAT.

UC- (UnCacheable). Memory type setting in MTRR/PAT.

WC (Write-Combining). Memory type setting in MTRR/PAT.

WT (Write-Through). Memory type setting in MTRR/PAT.

WB (Write-Back). Memory type setting in MTRR/PAT.

WP (Write Protected). Memory type setting in MTRR/PAT.

For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3


PAT (Performance Acceleration Technology).

http://www.intel.com/design/chipsets/pat.htm


AGP (Advanced Graphics Port).

http://en.wikipedia.org/wiki/AGP


AGP Aperture. The memory range that is set aside for AGP access.

http://en.wikipedia.org/wiki/AGP


GART (Graphics Address Relocation Table)

http://www.linuxelectrons.com/article.php/20031021142247752


SBA (SideBand Addressing)

http://www.linuxelectrons.com/article.php/20031021142247752


GATT (Graphics Aperture Translation Table)

http://www.linuxelectrons.com/article.php/20031021142247752


PLCC (Plastic Leaded Chip Carrier). A square Surface-mount chip package.

http://www.webopedia.com/TERM/P/PLCC.html


LRU (Least Recently Used). A rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.

http://computer.laborlawtalk.com/Least%20Recently%20Used


GPIO (General Purpose Input/Output).

http://en.wikipedia.org/wiki/GPIO


SB (Southbridge)

Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...