Difference between revisions of "Glossary"

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(add BAR, thanks to Philipp Degler for submitting this.)
(Alphabetized List)
Line 1: Line 1:
 
== '''Glossary''' ==  
 
== '''Glossary''' ==  
  
'''This page is a work in progress. Entries are not in alphabetical order.'''
+
'''This page is a work in progress.'''
  
'''MMIO''' (Memory-mapped I/O) and port I/O (also called port-mapped I/O or
+
'''ACPI''' (Advanced Configuration & Power Interface) is an industry standard
PMIO) are two complementary methods of performing input/output
+
for letting the OS control power management.
between the CPU and I/O devices in a computer.
+
  
http://encyclopedia.thefreedictionary.com/mmio
+
http://www.acpi.info/
 +
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
 
----------------------------------------------------
 
----------------------------------------------------
'''PIO''' (Programmed Input/Output) interface is the original method used to
+
'''AGP''' (Advanced Graphics Port).
transfer data between the CPU (through the IDE controller) and an IDE/ATA
+
device.
+
  
http://encyclopedia.thefreedictionary.com/pio
+
http://en.wikipedia.org/wiki/AGP
 
----------------------------------------------------
 
----------------------------------------------------
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the
+
'''AGP Aperture'''. The memory range that is set aside for AGP access.
graphics information for one frame or picture. This information typically
+
consists of color values for every pixel on the screen.
+
A framebuffer is either:
+
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
+
* On-screen, meaning that the framebuffer is directly coupled to the visible display
+
  
http://encyclopedia.thefreedictionary.com/framebuffer
+
http://en.wikipedia.org/wiki/AGP
 
----------------------------------------------------
 
----------------------------------------------------
'''POST''' (Power On Self Test) is a test to check that devices the computer
+
'''AHCI''' (Advanced Host Controller Interface). Describes the register-level
will rely on are functioning, and initializes devices.
+
interface for a SATA host controller.
  
http://encyclopedia.thefreedictionary.com/booting
+
http://encyclopedia.thefreedictionary.com/ahci
------------------------------------------
+
http://www.intel.com/technology/serialata/ahci.htm
'''I2C''' - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient
+
----------------------------------------------------
inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for
+
'''APIC''' (Advanced Programmable Interrupt Controller). An advanced version of
more info.
+
a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.
  
Code examples(?): ...
+
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
------------------------------------------
+
http://osdev.berlios.de/pic.html
'''VID''' - Vendor ID, a way of identifying the hardware manufacturer. See
+
----------------------------------------------------
'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and
+
'''BAR''' (Base Address Register)
'http://pciids.sourceforge.net/'
+
for more info.
+
  
A way of obtaining info for your hardware is through the 'lspci' command.
+
----------------------------------------------------
Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for
+
'''DCR''' (Decode Control Register)
more verbose output.
+
 
------------------------------------------
+
----------------------------------------------------
 
'''DID''' - Device ID, a way of identifying the hardware in question. See VID
 
'''DID''' - Device ID, a way of identifying the hardware in question. See VID
 
(above) for more info.
 
(above) for more info.
Line 57: Line 48:
 
http://encyclopedia.thefreedictionary.com/direct%20memory%20access
 
http://encyclopedia.thefreedictionary.com/direct%20memory%20access
 
----------------------------------------------------
 
----------------------------------------------------
'''RDMA''' (Remote Direct Memory Access) is a concept whereby two or more
+
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the
computers communicate via DMA directly from main memory of one system to
+
graphics information for one frame or picture. This information typically
the main memory of another.
+
consists of color values for every pixel on the screen.
 +
A framebuffer is either:
 +
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
 +
* On-screen, meaning that the framebuffer is directly coupled to the visible display
  
http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
+
http://encyclopedia.thefreedictionary.com/framebuffer
 
----------------------------------------------------
 
----------------------------------------------------
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA
+
'''GART''' (Graphics Address Relocation Table)
signal generation from all the other modules in a (hardware) design. It
+
allows the pixel information to be written into its video memory using a
+
very simple interface, while it is alone responsible for generating the
+
required signals for displaying the pixel information on a VGA monitor.
+
(Note: This is mostly relevant to a hardware design - the text is
+
copied from a students fpga project)
+
  
http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm
+
http://www.linuxelectrons.com/article.php/20031021142247752
 
----------------------------------------------------
 
----------------------------------------------------
'''AHCI''' (Advanced Host Controller Interface). Describes the register-level
+
'''GATT''' (Graphics Aperture Translation Table)
interface for a SATA host controller.
+
  
http://encyclopedia.thefreedictionary.com/ahci
+
http://www.linuxelectrons.com/article.php/20031021142247752
http://www.intel.com/technology/serialata/ahci.htm
+
 
----------------------------------------------------
 
----------------------------------------------------
'''OHCI''' (Open Host Controller Interface). IEEE1394 (Firewire) and
+
'''GPIO''' (General Purpose Input/Output).
USB standard (mostly used by other companies than Intel)
+
  
http://encyclopedia.thefreedictionary.com/ohci
+
http://en.wikipedia.org/wiki/GPIO
http://developer.intel.com/technology/1394/download/ohci_11.htm
+
 
----------------------------------------------------
 
----------------------------------------------------
'''UHCI''' (Universal Host Controller Interface). USB standard.
+
'''I2C''' - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient
 +
inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for
 +
more info.
  
http://encyclopedia.thefreedictionary.com/dict.asp?Word=uhci
+
Code examples(?): ...
http://developer.intel.com/technology/usb/uhci11d.htm
+
------------------------------------------
 +
'''IDSEL/AD''' (Initialization Device SELect/Address and Data).
 +
 
 +
Each PCI slot has a signal called IDSEL. It is used to differentiate
 +
between the different cards?
 +
 
 +
http://www.techfest.com/hardware/bus/pci.htm
 +
http://www.fpga4fun.com/PCI4.html
 
----------------------------------------------------
 
----------------------------------------------------
'''SPI''' (Serial Peripheral Interface Bus) is a very loose standard for
+
'''LPC''' (Low Pin Count). An interface aimed at replacing he ISA bus.
controlling almost any digital electronics that accepts a clocked serial
+
stream of bits.
+
  
http://encyclopedia.thefreedictionary.com/Serial%20Peripheral%20Interface
+
http://www.intel.com/design/chipsets/industry/lpc.htm
http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
+
 
----------------------------------------------------
 
----------------------------------------------------
'''SIO''' (Serial Input/Output)
+
'''LRU''' (Least Recently Used). A rule used in operating systems that utilises
 
+
a paging system. LRU selects a page to be paged out if it has been
http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search
+
used less recently than any other page. This may be applied to a cache
 +
system as well.
  
 +
http://computer.laborlawtalk.com/Least%20Recently%20Used
 
----------------------------------------------------
 
----------------------------------------------------
'''PIC''' (Programmable Interrupt Controller) is a device to control peripheral devices,
+
'''MII''' (Media Independent Interface). This is a chip commonly found
offloading the main CPU.
+
on ethernet devices, together with a PHY.
 
+
http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
+
http://www.interq.or.jp/japan/se-inoue/e_pic1.htm
+
  
 +
http://en.wikipedia.org/wiki/MII
 
----------------------------------------------------
 
----------------------------------------------------
'''PLL''' (Phase Locked Loop) is a device to keep (electrical) signals synchronised
+
'''MMIO''' (Memory-mapped I/O) and port I/O (also called port-mapped I/O or
throughout the system.
+
PMIO) are two complementary methods of performing input/output
 +
between the CPU and I/O devices in a computer.
  
http://en.wikipedia.org/wiki/PLL
+
http://encyclopedia.thefreedictionary.com/mmio
 
----------------------------------------------------
 
----------------------------------------------------
'''SuperIO''' is the chip that provides floppy, serial and parallel
+
'''MPTable''' (Multi Processor Table). Intel MP specification is a hardware
functionality/ports.
+
compatibility guide for machine hardware designers and OS software
 +
writers to produce SMP-capable machines and OSes in a vendor-independent manner.
 +
v1.1 and v1.4 versions exist.
  
http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
+
http://www.uruk.org/~erich/mps.html
 +
http://www.intel.com/design/pentium/datashts/242016.htm
 
----------------------------------------------------
 
----------------------------------------------------
'''SPD''' (Serial Presence Detect). On every (?) memory module there's
+
'''MTRR''' (Memory Type Range Register). This can be used to control the way a
an eprom that provides BIOS with information on how to properly
+
processor accesses memory ranges.
configure the memory module.
+
  
http://www.simmtester.com/page/news/showpubnews.asp?num=101
+
http://en.wikipedia.org/wiki/MTRR
 
----------------------------------------------------
 
----------------------------------------------------
'''SMB'''us (System Management Bus) is a simple two-wire bus used for
+
'''OHCI''' (Open Host Controller Interface). IEEE1394 (Firewire) and
communication with low-bandwidth devices on a motherboard. It is
+
USB standard (mostly used by other companies than Intel)
based on (actually a subset of) I2C.
+
  
http://www.smbus.org/
+
http://encyclopedia.thefreedictionary.com/ohci
http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus
+
http://developer.intel.com/technology/1394/download/ohci_11.htm
See I2C for more info.
+
 
----------------------------------------------------
 
----------------------------------------------------
'''ACPI''' (Advanced Configuration & Power Interface) is an industry standard
+
'''PAM''' (Programmable Attribute Map).
for letting the OS control power management.
+
  
http://www.acpi.info/
+
hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
+
 
----------------------------------------------------
 
----------------------------------------------------
'''APIC''' (Advanced Programmable Interrupt Controller). An advanced version of
+
'''PAT''' (Page Attribute Table). Can be used independently or in combination
a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.
+
with MTRR to setup memory type access ranges. Allows more finely-grained control
 +
than MTRR.
  
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
+
http://www.intel.com/design/pentium4/manuals/index_new.htm
http://osdev.berlios.de/pic.html
+
http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
 
----------------------------------------------------
 
----------------------------------------------------
'''VME'''Bus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus
+
'''PAT''' (Performance Acceleration Technology).
originally developed for the Motorola 68000.
+
  
http://encyclopedia.thefreedictionary.com/VMEbus
+
http://www.intel.com/design/chipsets/pat.htm
 
----------------------------------------------------
 
----------------------------------------------------
 
'''PCI''' (Peripheral Component Interconnect).
 
'''PCI''' (Peripheral Component Interconnect).
Line 158: Line 147:
 
http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space
 
http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space
 
http://www.techfest.com/hardware/bus/pci.htm
 
http://www.techfest.com/hardware/bus/pci.htm
 +
----------------------------------------------------
 +
'''PHY''' (PHY layer device). A device that provides low level access
 +
to the physical layer.
 +
 +
http://en.wikipedia.org/wiki/PHY
 +
http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
 +
----------------------------------------------------
 +
'''PIC''' (Programmable Interrupt Controller) is a device to control peripheral devices,
 +
offloading the main CPU.
 +
 +
http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
 +
http://www.interq.or.jp/japan/se-inoue/e_pic1.htm
 +
----------------------------------------------------
 +
'''PIO''' (Programmed Input/Output) interface is the original method used to
 +
transfer data between the CPU (through the IDE controller) and an IDE/ATA
 +
device.
 +
 +
http://encyclopedia.thefreedictionary.com/pio
 +
----------------------------------------------------
 +
'''PIR''' (Programmable Interrupt Routing?)
 
----------------------------------------------------
 
----------------------------------------------------
 
'''PIRQ''' (Pci IRQ routing table).
 
'''PIRQ''' (Pci IRQ routing table).
Line 167: Line 176:
 
https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
 
https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
 
----------------------------------------------------
 
----------------------------------------------------
'''PAM''' (Programmable Attribute Map).
+
'''PLCC''' (Plastic Leaded Chip Carrier). A square Surface-mount chip package.
 
+
hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.
+
  
 +
http://www.webopedia.com/TERM/P/PLCC.html
 
----------------------------------------------------
 
----------------------------------------------------
'''SMM''' (System Management Mode)
+
'''PLL''' (Phase Locked Loop) is a device to keep (electrical) signals synchronised
 
+
throughout the system.
Processor mode that is mainly used for power management purposes.
+
  
 +
http://en.wikipedia.org/wiki/PLL
 
----------------------------------------------------
 
----------------------------------------------------
'''SMRAM''' (System Management Random Access Memory).
+
'''POST''' (Power On Self Test) is a test to check that devices the computer
 +
will rely on are functioning, and initializes devices.
  
 +
http://encyclopedia.thefreedictionary.com/booting
 +
------------------------------------------
 +
'''RDMA''' (Remote Direct Memory Access) is a concept whereby two or more
 +
computers communicate via DMA directly from main memory of one system to
 +
the main memory of another.
  
 +
http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
 
----------------------------------------------------
 
----------------------------------------------------
'''MPTable''' (Multi Processor Table). Intel MP specification is a hardware
+
'''SB''' (Southbridge)
compatibility guide for machine hardware designers and OS software
+
writers to produce SMP-capable machines and OSes in a vendor-independent manner.
+
v1.1 and v1.4 versions exist.
+
 
+
http://www.uruk.org/~erich/mps.html
+
http://www.intel.com/design/pentium/datashts/242016.htm
+
 
+
  
 +
Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...
 
----------------------------------------------------
 
----------------------------------------------------
'''PIR''' (Programmable Interrupt Routing?)
+
'''SBA''' (SideBand Addressing)
 
+
  
 +
http://www.linuxelectrons.com/article.php/20031021142247752
 
----------------------------------------------------
 
----------------------------------------------------
'''DCR''' (Decode Control Register)
+
'''SIO''' (Serial Input/Output)
 
+
  
 +
http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search
 
----------------------------------------------------
 
----------------------------------------------------
'''LPC''' (Low Pin Count). An interface aimed at replacing he ISA bus.
+
'''SMB'''us (System Management Bus) is a simple two-wire bus used for
 +
communication with low-bandwidth devices on a motherboard. It is
 +
based on (actually a subset of) I2C.
  
http://www.intel.com/design/chipsets/industry/lpc.htm
+
http://www.smbus.org/
 +
http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus
 +
See I2C for more info.
 
----------------------------------------------------
 
----------------------------------------------------
'''IDSEL/AD''' (Initialization Device SELect/Address and Data).
+
'''SMM''' (System Management Mode)
  
Each PCI slot has a signal called IDSEL. It is used to differentiate
+
Processor mode that is mainly used for power management purposes.
between the different cards?
+
 
+
http://www.techfest.com/hardware/bus/pci.htm
+
http://www.fpga4fun.com/PCI4.html
+
 
----------------------------------------------------
 
----------------------------------------------------
'''PHY''' (PHY layer device). A device that provides low level access
+
'''SMRAM''' (System Management Random Access Memory).
to the physical layer.
+
  
http://en.wikipedia.org/wiki/PHY
 
http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
 
 
----------------------------------------------------
 
----------------------------------------------------
'''MII''' (Media Independent Interface). This is a chip commonly found
+
'''SPD''' (Serial Presence Detect). On every (?) memory module there's
on ethernet devices, together with a PHY.
+
an eprom that provides BIOS with information on how to properly
 +
configure the memory module.
  
http://en.wikipedia.org/wiki/MII
+
http://www.simmtester.com/page/news/showpubnews.asp?num=101
 
----------------------------------------------------
 
----------------------------------------------------
'''BAR''' (Base Address Register)
+
'''SPI''' (Serial Peripheral Interface Bus) is a very loose standard for
 +
controlling almost any digital electronics that accepts a clocked serial
 +
stream of bits.
  
 +
http://encyclopedia.thefreedictionary.com/Serial%20Peripheral%20Interface
 +
http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
 
----------------------------------------------------
 
----------------------------------------------------
'''MTRR''' (Memory Type Range Register). This can be used to control the way a
+
'''SuperIO''' is the chip that provides floppy, serial and parallel
processor accesses memory ranges.
+
functionality/ports.
  
http://en.wikipedia.org/wiki/MTRR
+
http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
 
+
----------------------------------------------------
+
'''PAT''' (Page Attribute Table). Can be used independently or in combination
+
with MTRR to setup memory type access ranges. Allows more finely-grained control
+
than MTRR.
+
 
+
http://www.intel.com/design/pentium4/manuals/index_new.htm
+
http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
+
 
----------------------------------------------------
 
----------------------------------------------------
 
'''TLB''' (Translation Lookaside Buffer). The TLB stores the most recently used
 
'''TLB''' (Translation Lookaside Buffer). The TLB stores the most recently used
Line 248: Line 251:
  
 
'''UC-''' (UnCacheable). Memory type setting in MTRR/PAT.
 
'''UC-''' (UnCacheable). Memory type setting in MTRR/PAT.
 
'''WC''' (Write-Combining). Memory type setting in MTRR/PAT.
 
 
'''WT''' (Write-Through). Memory type setting in MTRR/PAT.
 
 
'''WB''' (Write-Back). Memory type setting in MTRR/PAT.
 
 
'''WP''' (Write Protected). Memory type setting in MTRR/PAT.
 
  
 
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
 
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
 
----------------------------------------------------
 
----------------------------------------------------
'''PAT''' (Performance Acceleration Technology).
 
  
http://www.intel.com/design/chipsets/pat.htm
+
'''UHCI''' (Universal Host Controller Interface). USB standard.
----------------------------------------------------
+
'''AGP''' (Advanced Graphics Port).
+
  
http://en.wikipedia.org/wiki/AGP
+
http://encyclopedia.thefreedictionary.com/dict.asp?Word=uhci
 +
http://developer.intel.com/technology/usb/uhci11d.htm
 
----------------------------------------------------
 
----------------------------------------------------
'''AGP Aperture'''. The memory range that is set aside for AGP access.
+
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA
 
+
signal generation from all the other modules in a (hardware) design. It
http://en.wikipedia.org/wiki/AGP
+
allows the pixel information to be written into its video memory using a
 +
very simple interface, while it is alone responsible for generating the
 +
required signals for displaying the pixel information on a VGA monitor.
 +
(Note: This is mostly relevant to a hardware design - the text is
 +
copied from a students fpga project)
  
 +
http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm
 
----------------------------------------------------
 
----------------------------------------------------
'''GART''' (Graphics Address Relocation Table)
+
'''VID''' - Vendor ID, a way of identifying the hardware manufacturer. See
 +
'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and
 +
'http://pciids.sourceforge.net/'
 +
for more info.
  
http://www.linuxelectrons.com/article.php/20031021142247752
+
A way of obtaining info for your hardware is through the 'lspci' command.
----------------------------------------------------
+
Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for
'''SBA''' (SideBand Addressing)
+
more verbose output.
 +
--------------------------------------------------
 +
'''VME'''Bus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus
 +
originally developed for the Motorola 68000.
  
http://www.linuxelectrons.com/article.php/20031021142247752
+
http://encyclopedia.thefreedictionary.com/VMEbus
 
----------------------------------------------------
 
----------------------------------------------------
'''GATT''' (Graphics Aperture Translation Table)
+
'''WB''' (Write-Back). Memory type setting in MTRR/PAT.
  
http://www.linuxelectrons.com/article.php/20031021142247752
+
'''WC''' (Write-Combining). Memory type setting in MTRR/PAT.
----------------------------------------------------
+
'''PLCC''' (Plastic Leaded Chip Carrier). A square Surface-mount chip package.
+
  
http://www.webopedia.com/TERM/P/PLCC.html
+
'''WP''' (Write Protected). Memory type setting in MTRR/PAT.
----------------------------------------------------
+
'''LRU''' (Least Recently Used). A rule used in operating systems that utilises
+
a paging system. LRU selects a page to be paged out if it has been
+
used less recently than any other page. This may be applied to a cache
+
system as well.
+
  
http://computer.laborlawtalk.com/Least%20Recently%20Used
+
'''WT''' (Write-Through). Memory type setting in MTRR/PAT.
----------------------------------------------------
+
'''GPIO''' (General Purpose Input/Output).
+
  
http://en.wikipedia.org/wiki/GPIO
 
----------------------------------------------------
 
'''SB''' (Southbridge)
 
 
Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...
 
  
 +
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
 
----------------------------------------------------
 
----------------------------------------------------

Revision as of 13:46, 11 May 2006

Glossary

This page is a work in progress.

ACPI (Advanced Configuration & Power Interface) is an industry standard for letting the OS control power management.

http://www.acpi.info/ http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface


AGP (Advanced Graphics Port).

http://en.wikipedia.org/wiki/AGP


AGP Aperture. The memory range that is set aside for AGP access.

http://en.wikipedia.org/wiki/AGP


AHCI (Advanced Host Controller Interface). Describes the register-level interface for a SATA host controller.

http://encyclopedia.thefreedictionary.com/ahci http://www.intel.com/technology/serialata/ahci.htm


APIC (Advanced Programmable Interrupt Controller). An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.

http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller http://osdev.berlios.de/pic.html


BAR (Base Address Register)


DCR (Decode Control Register)


DID - Device ID, a way of identifying the hardware in question. See VID (above) for more info.


DMA (Direct Memory Access) allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

http://encyclopedia.thefreedictionary.com/direct%20memory%20access


The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:

  • Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
  • On-screen, meaning that the framebuffer is directly coupled to the visible display

http://encyclopedia.thefreedictionary.com/framebuffer


GART (Graphics Address Relocation Table)

http://www.linuxelectrons.com/article.php/20031021142247752


GATT (Graphics Aperture Translation Table)

http://www.linuxelectrons.com/article.php/20031021142247752


GPIO (General Purpose Input/Output).

http://en.wikipedia.org/wiki/GPIO


I2C - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for more info.

Code examples(?): ...


IDSEL/AD (Initialization Device SELect/Address and Data).

Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?

http://www.techfest.com/hardware/bus/pci.htm http://www.fpga4fun.com/PCI4.html


LPC (Low Pin Count). An interface aimed at replacing he ISA bus.

http://www.intel.com/design/chipsets/industry/lpc.htm


LRU (Least Recently Used). A rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.

http://computer.laborlawtalk.com/Least%20Recently%20Used


MII (Media Independent Interface). This is a chip commonly found on ethernet devices, together with a PHY.

http://en.wikipedia.org/wiki/MII


MMIO (Memory-mapped I/O) and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.

http://encyclopedia.thefreedictionary.com/mmio


MPTable (Multi Processor Table). Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.

http://www.uruk.org/~erich/mps.html http://www.intel.com/design/pentium/datashts/242016.htm


MTRR (Memory Type Range Register). This can be used to control the way a processor accesses memory ranges.

http://en.wikipedia.org/wiki/MTRR


OHCI (Open Host Controller Interface). IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel)

http://encyclopedia.thefreedictionary.com/ohci http://developer.intel.com/technology/1394/download/ohci_11.htm


PAM (Programmable Attribute Map).

hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.


PAT (Page Attribute Table). Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.

http://www.intel.com/design/pentium4/manuals/index_new.htm http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10


PAT (Performance Acceleration Technology).

http://www.intel.com/design/chipsets/pat.htm


PCI (Peripheral Component Interconnect).

http://encyclopedia.thefreedictionary.com/PCI


PCI Configuration Space.

http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space http://www.techfest.com/hardware/bus/pci.htm


PHY (PHY layer device). A device that provides low level access to the physical layer.

http://en.wikipedia.org/wiki/PHY http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer


PIC (Programmable Interrupt Controller) is a device to control peripheral devices, offloading the main CPU.

http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller http://www.interq.or.jp/japan/se-inoue/e_pic1.htm


PIO (Programmed Input/Output) interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.

http://encyclopedia.thefreedictionary.com/pio


PIR (Programmable Interrupt Routing?)


PIRQ (Pci IRQ routing table).

http://www.microsoft.com/whdc/archive/pciirq.mspx http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148 http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view


PLCC (Plastic Leaded Chip Carrier). A square Surface-mount chip package.

http://www.webopedia.com/TERM/P/PLCC.html


PLL (Phase Locked Loop) is a device to keep (electrical) signals synchronised throughout the system.

http://en.wikipedia.org/wiki/PLL


POST (Power On Self Test) is a test to check that devices the computer will rely on are functioning, and initializes devices.

http://encyclopedia.thefreedictionary.com/booting


RDMA (Remote Direct Memory Access) is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.

http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access


SB (Southbridge)

Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...


SBA (SideBand Addressing)

http://www.linuxelectrons.com/article.php/20031021142247752


SIO (Serial Input/Output)

http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search


SMBus (System Management Bus) is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.

http://www.smbus.org/ http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus See I2C for more info.


SMM (System Management Mode)

Processor mode that is mainly used for power management purposes.


SMRAM (System Management Random Access Memory).


SPD (Serial Presence Detect). On every (?) memory module there's an eprom that provides BIOS with information on how to properly configure the memory module.

http://www.simmtester.com/page/news/showpubnews.asp?num=101


SPI (Serial Peripheral Interface Bus) is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.

http://encyclopedia.thefreedictionary.com/Serial%20Peripheral%20Interface http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus


SuperIO is the chip that provides floppy, serial and parallel functionality/ports.

http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html


TLB (Translation Lookaside Buffer). The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.

http://www.linuxelectrons.com/article.php/20031021142247752 For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1


UC (strong UnCacheable). Memory type setting in MTRR/PAT.

UC- (UnCacheable). Memory type setting in MTRR/PAT.

For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3


UHCI (Universal Host Controller Interface). USB standard.

http://encyclopedia.thefreedictionary.com/dict.asp?Word=uhci http://developer.intel.com/technology/usb/uhci11d.htm


The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students fpga project)

http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm


VID - Vendor ID, a way of identifying the hardware manufacturer. See 'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and 'http://pciids.sourceforge.net/' for more info.

A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.


VMEBus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus originally developed for the Motorola 68000.

http://encyclopedia.thefreedictionary.com/VMEbus


WB (Write-Back). Memory type setting in MTRR/PAT.

WC (Write-Combining). Memory type setting in MTRR/PAT.

WP (Write Protected). Memory type setting in MTRR/PAT.

WT (Write-Through). Memory type setting in MTRR/PAT.


For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3