Difference between revisions of "Glossary"

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== '''Glossary''' ==  
+
== A ==
  
'''ACPI''' (Advanced Configuration & Power Interface) is an industry standard
+
=== ACPI ===
for letting the OS control power management.
+
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
 +
* [[ACPI|ACPI and coreboot]]
 +
* http://www.acpi.info/
 +
* http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface
 +
* http://kernelslacker.livejournal.com/88243.html (acpitool to generate a C source (see mailing list also))
  
http://www.acpi.info/
+
=== AGP ===
 +
'''Advanced Graphics Port''', a point-to-point channel for attaching a video card to a mainboard with AGP slot.
 +
* http://en.wikipedia.org/wiki/Accelerated_Graphics_Port
  
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
+
=== AGP Aperture ===
----------------------------------------------------
+
The memory range that is set aside for AGP access.
'''AGP''' (Advanced Graphics Port).
+
* http://en.wikipedia.org/wiki/Accelerated_Graphics_Port
  
http://en.wikipedia.org/wiki/AGP
+
=== AHCI ===
----------------------------------------------------
+
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
'''AGP Aperture'''. The memory range that is set aside for AGP access.
+
* http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface
 +
* http://www.intel.com/technology/serialata/ahci.htm
 +
* http://download.intel.com/technology/serialata/pdf/rev1_3.pdf (AHCI spec 1.3)
  
http://en.wikipedia.org/wiki/AGP
+
=== APIC ===
----------------------------------------------------
+
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: '''Local APICs''' (LAPIC) are CPU-bound, '''IO-APICs''' are bridge-bound.
'''AHCI''' (Advanced Host Controller Interface). Describes the register-level
+
* http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller
interface for a SATA host controller.
+
* http://osdev.berlios.de/pic.html
  
http://encyclopedia.thefreedictionary.com/ahci
 
  
http://www.intel.com/technology/serialata/ahci.htm
+
== B ==
----------------------------------------------------
+
'''APIC''' (Advanced Programmable Interrupt Controller). An advanced version of
+
a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.
+
  
http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
+
=== BAR ===
 +
'''Base Address Register''' (on PCI device).
 +
* http://en.wikipedia.org/wiki/Base_Address_Register#Bus_enumeration
 +
* http://wiki.osdev.org/PCI#Base_Address_Registers
  
http://osdev.berlios.de/pic.html
+
=== BIOS ===
----------------------------------------------------
+
'''Basic Input/Output System'''.
'''BAR''' (Base Address Register)
+
* http://en.wikipedia.org/wiki/BIOS
----------------------------------------------------
+
'''CAR''' (Cache as RAM)
+
----------------------------------------------------
+
'''DCR''' (Decode Control Register)
+
----------------------------------------------------
+
'''DID''' - Device ID, a way of identifying the hardware in question. See VID for more info.
+
----------------------------------------------------
+
'''DMA''' (Direct Memory Access) allows certain hardware subsystems within a
+
computer to access system memory for reading and/or writing independently
+
of the main CPU. Examples of systems that use DMA: Hard Disk Controller,
+
Disk Drive Controller, Graphics Card, Sound Card.
+
  
DMA is an essential feature of all modern computers, as it allows devices
+
=== BIST ===
of different speeds to communicate without subjecting the CPU to a massive
+
The '''Built-In Self Test''', a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.
interrupt load.
+
  
http://encyclopedia.thefreedictionary.com/direct%20memory%20access
+
== C ==
----------------------------------------------------
+
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the
+
graphics information for one frame or picture. This information typically
+
consists of color values for every pixel on the screen.
+
  
A framebuffer is either:
+
=== CAR ===
 +
'''Cache as RAM'''.
  
 +
=== CMOS ===
 +
'''Complementary metal oxyde semiconductor''', a [http://en.wikipedia.org/wiki/CMOS class of semiconductors]. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.
 +
* http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory
 +
 +
=== CPU ===
 +
'''Central processing unit''' (e.g. an Athlon64).
 +
* http://en.wikipedia.org/wiki/Central_processing_unit
 +
 +
=== crt0 ===
 +
'''C Run Time 0''' - This is now called the romstage in coreboot.
 +
* http://en.wikipedia.org/wiki/Crt0
 +
 +
=== crt0s ===
 +
Sources that make up the romstage in coreboot, see [[#crt0|crt0]].
 +
 +
== D ==
 +
 +
=== DCR ===
 +
'''Decode Control Register'''.
 +
 +
=== DID ===
 +
'''Device ID''', a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.
 +
 +
=== DMA ===
 +
'''Direct Memory Access'''. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
 +
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
 +
* http://en.wikipedia.org/wiki/Direct_memory_access
 +
 +
=== DSDT ===
 +
'''Differentiated System Descriptor Table''', generated by BIOS and necessary for [[#ACPI|ACPI]]. Implementation of [[ACPI|ACPI in coreboot]] needs to be done in a "cleanroom" development process to avoid legal issues.
 +
* http://acpi.sourceforge.net/dsdt/index.php
 +
 +
== E ==
 +
 +
=== EEPROM ===
 +
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).
 +
 +
=== EHCI ===
 +
Enhanced Host Controller Interface (USB host controller).
 +
 +
== F ==
 +
 +
=== Flashing ===
 +
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.
 +
 +
=== Framebuffer ===
 +
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.
 +
A framebuffer is either:
 
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
 
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
 
* On-screen, meaning that the framebuffer is directly coupled to the visible display
 
* On-screen, meaning that the framebuffer is directly coupled to the visible display
  
http://encyclopedia.thefreedictionary.com/framebuffer
+
* http://en.wikipedia.org/wiki/Framebuffer
----------------------------------------------------
+
'''GART''' (Graphics Address Relocation Table)
+
  
http://www.linuxelectrons.com/article.php/20031021142247752
 
----------------------------------------------------
 
'''GATT''' (Graphics Aperture Translation Table)
 
  
http://www.linuxelectrons.com/article.php/20031021142247752
+
== G ==
----------------------------------------------------
+
'''GPIO''' (General Purpose Input/Output).
+
  
http://en.wikipedia.org/wiki/GPIO
+
=== GART ===
----------------------------------------------------
+
Graphics Address Relocation Table.
'''Hypertransport'''
+
* http://www.linuxelectrons.com/article.php/20031021142247752
  
 +
=== GATT ===
 +
Graphics Aperture Translation Table.
 +
* http://www.linuxelectrons.com/article.php/20031021142247752
 +
 +
=== GNB ===
 +
Graphic NorthBridge.
 +
 +
Part of the newer AMD Fusion chips.
 +
 +
=== GPP ===
 +
General Purpose Ports.
 +
 +
Part of the newer AMD Fusion chips.
 +
 +
=== GPIO ===
 +
General Purpose Input/Output.
 +
* http://en.wikipedia.org/wiki/GPIO
 +
 +
=== GSoC ===
 +
[[GSoC|Google Summer of Code]].
 +
 +
== H ==
 +
 +
=== Hypertransport ===
 
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
 
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
 +
* http://en.wikipedia.org/wiki/Hypertransport
 +
* http://www.hypertransport.org
 +
* http://www.hotchips.org/archives/hc14/3_Tue/28_AMD_Hammer_MP_HC_v8.pdf
 +
 +
== I ==
 +
 +
=== I2C ===
 +
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.
 +
* http://www.esacademy.com/faq/i2c/index.htm
 +
 +
=== IDSEL/AD ===
 +
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
 +
* http://www.techfest.com/hardware/bus/pci.htm
 +
* http://www.fpga4fun.com/PCI4.html
 +
 +
=== IRQ ===
 +
Interrupt ReQuest (Handler).
 +
 +
 +
== J ==
 +
 +
=== JTAG ===
 +
Debugging and test 4-wire interface named after an organization which defined it.
 +
 +
== L ==
 +
 +
=== LAR ===
 +
is the Linuxbios ARchiver, now called Lightweight [[LAR_Design|ARchiver]]. It is a small utility that we use to create and change coreboot images and their modules.
 +
 +
=== LPC ===
 +
'''Low Pin Count''', an interface aimed at replacing the ISA bus.
 +
* http://www.intel.com/design/chipsets/industry/lpc.htm
  
http://computing-dictionary.thefreedictionary.com/hypertransport
+
=== LRU ===
 +
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
 +
* http://computer.laborlawtalk.com/Least%20Recently%20Used
  
http://www.hypertransport.org
+
== M ==
----------------------------------------------------
+
'''I2C''' - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient
+
inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for
+
more info.
+
  
Code examples(?): ...
+
=== Memory Training ===
------------------------------------------
+
'''IDSEL/AD''' (Initialization Device SELect/Address and Data).
+
  
Each PCI slot has a signal called IDSEL. It is used to differentiate
+
'''Memory training''' is a very complex technlogical area. We are accumulating references to it as we find them.
between the different cards?
+
  
http://www.techfest.com/hardware/bus/pci.htm
+
* A [http://www.freshpatents.com/Training-of-signal-transfer-channels-between-memory-controller-and-memory-device-dt20080515ptan20080112255.php patent for GDDR4]
 +
* Key to understanding training is the concept of an [http://en.wikipedia.org/wiki/Eye_diagram eye diagram]
  
http://www.fpga4fun.com/PCI4.html
+
It is amazing, but there is very little out there.
----------------------------------------------------
+
'''LPC''' (Low Pin Count). An interface aimed at replacing he ISA bus.
+
  
http://www.intel.com/design/chipsets/industry/lpc.htm
+
=== MII ===
----------------------------------------------------
+
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.
'''LRU''' (Least Recently Used). A rule used in operating systems that utilises
+
* http://en.wikipedia.org/wiki/MII
a paging system. LRU selects a page to be paged out if it has been
+
used less recently than any other page. This may be applied to a cache
+
system as well.
+
  
http://computer.laborlawtalk.com/Least%20Recently%20Used
+
=== MMIO ===
----------------------------------------------------
+
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
'''MII''' (Media Independent Interface). This is a chip commonly found
+
* http://en.wikipedia.org/wiki/MMIO
on ethernet devices, together with a PHY.
+
  
http://en.wikipedia.org/wiki/MII
+
=== MPTable ===
----------------------------------------------------
+
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
'''MMIO''' (Memory-mapped I/O) and port I/O (also called port-mapped I/O or
+
* http://www.uruk.org/mps/
PMIO) are two complementary methods of performing input/output
+
* http://www.intel.com/design/pentium/datashts/242016.htm
between the CPU and I/O devices in a computer.
+
  
http://encyclopedia.thefreedictionary.com/mmio
+
=== MTRR ===
----------------------------------------------------
+
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
'''MPTable''' (Multi Processor Table). Intel MP specification is a hardware
+
* http://en.wikipedia.org/wiki/MTRR
compatibility guide for machine hardware designers and OS software
+
writers to produce SMP-capable machines and OSes in a vendor-independent manner.
+
v1.1 and v1.4 versions exist.
+
  
http://www.uruk.org/~erich/mps.html
+
== O ==
  
http://www.intel.com/design/pentium/datashts/242016.htm
+
=== OHCI ===
----------------------------------------------------
+
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).
'''MTRR''' (Memory Type Range Register). This can be used to control the way a
+
* http://en.wikipedia.org/wiki/Ohci
processor accesses memory ranges.
+
* http://developer.intel.com/technology/1394/download/ohci_11.htm
  
http://en.wikipedia.org/wiki/MTRR
 
----------------------------------------------------
 
'''OHCI''' (Open Host Controller Interface). IEEE1394 (Firewire) and
 
USB standard (mostly used by other companies than Intel)
 
  
http://encyclopedia.thefreedictionary.com/ohci
+
== P ==
  
http://developer.intel.com/technology/1394/download/ohci_11.htm
+
=== PAM ===
----------------------------------------------------
+
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.
'''PAM''' (Programmable Attribute Map).
+
  
hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.
+
=== PAT ===
----------------------------------------------------
+
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
'''PAT''' (Page Attribute Table). Can be used independently or in combination
+
* http://www.intel.com/design/pentium4/manuals/index_new.htm
with MTRR to setup memory type access ranges. Allows more finely-grained control
+
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
than MTRR.
+
  
http://www.intel.com/design/pentium4/manuals/index_new.htm
+
=== PAT ===
 +
Performance Acceleration Technology.
 +
* http://www.intel.com/design/chipsets/pat.htm
  
http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
+
=== PCI ===
----------------------------------------------------
+
Peripheral Component Interconnect.
'''PAT''' (Performance Acceleration Technology).
+
* http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect
  
http://www.intel.com/design/chipsets/pat.htm
+
=== PCI Configuration Space ===
----------------------------------------------------
+
* http://en.wikipedia.org/wiki/PCI_Configuration_Space
'''PCI''' (Peripheral Component Interconnect).
+
* http://www.techfest.com/hardware/bus/pci.htm
  
http://encyclopedia.thefreedictionary.com/PCI
+
=== PCI Express / PCIe ===
----------------------------------------------------
+
* http://en.wikipedia.org/wiki/Pci_express
'''PCI Configuration Space'''.
+
  
http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space
+
=== PHY ===
 +
'''PHY layer device'''. A device that provides low level access to the physical layer.
 +
* http://en.wikipedia.org/wiki/PHY
 +
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
  
http://www.techfest.com/hardware/bus/pci.htm
+
=== PIC ===
----------------------------------------------------
+
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.
'''PCI Express''' or '''PCIe'''
+
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
 +
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm
  
http://computing-dictionary.thefreedictionary.com/PCI+Express
+
=== PIO ===
----------------------------------------------------
+
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
'''PHY''' (PHY layer device). A device that provides low level access
+
* http://en.wikipedia.org/wiki/Programmed_input/output
to the physical layer.
+
  
http://en.wikipedia.org/wiki/PHY
+
=== PIR ===
 +
Programmable Interrupt Routing?
  
http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
+
=== PIRQ ===
----------------------------------------------------
+
PCI IRQ routing table,
'''PIC''' (Programmable Interrupt Controller) is a device to control peripheral devices,
+
* http://www.microsoft.com/whdc/archive/pciirq.mspx
offloading the main CPU.
+
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
 +
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
  
http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
+
=== PLCC ===
 +
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
 +
* http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier
 +
* http://www.webopedia.com/TERM/P/PLCC.html
  
http://www.interq.or.jp/japan/se-inoue/e_pic1.htm
+
=== PLL ===
----------------------------------------------------
+
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.
'''PIO''' (Programmed Input/Output) interface is the original method used to
+
* http://en.wikipedia.org/wiki/PLL
transfer data between the CPU (through the IDE controller) and an IDE/ATA
+
device.
+
  
http://encyclopedia.thefreedictionary.com/pio
+
=== POST ===
----------------------------------------------------
+
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.
'''PIR''' (Programmable Interrupt Routing?)
+
* http://en.wikipedia.org/wiki/Power-on_self_test
----------------------------------------------------
+
'''PIRQ''' (Pci IRQ routing table).
+
  
http://www.microsoft.com/whdc/archive/pciirq.mspx
+
== R ==
  
http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148
+
=== RDMA ===
 +
'''Remote Direct Memory Access''' is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
 +
* http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access
  
http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
+
=== RCS ===
 +
Revision control systems.
  
Interesting tool?:
+
== S ==
https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
+
----------------------------------------------------
+
'''PLCC''' (Plastic Leaded Chip Carrier). A square Surface-mount chip package.
+
  
http://www.webopedia.com/TERM/P/PLCC.html
+
=== SB ===
----------------------------------------------------
+
'''Southbridge'''. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...
'''PLL''' (Phase Locked Loop) is a device to keep (electrical) signals synchronised
+
throughout the system.
+
  
http://en.wikipedia.org/wiki/PLL
+
=== SBA ===
----------------------------------------------------
+
SideBand Addressing.
'''POST''' (Power On Self Test) is a test to check that devices the computer
+
* http://www.linuxelectrons.com/article.php/20031021142247752
will rely on are functioning, and initializes devices.
+
  
http://encyclopedia.thefreedictionary.com/booting
+
=== Shadow RAM ===
------------------------------------------
+
RAM which content is copied from ROM residing at the same address for speedup purposes.
'''RDMA''' (Remote Direct Memory Access) is a concept whereby two or more
+
computers communicate via DMA directly from main memory of one system to
+
the main memory of another.
+
  
http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
+
=== SIO ===
----------------------------------------------------
+
Serial Input/Output.
'''SB''' (Southbridge)
+
* http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search
  
Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...
+
=== SMBus ===
----------------------------------------------------
+
The '''System Management Bus''' is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.
'''SBA''' (SideBand Addressing)
+
* http://www.smbus.org/
 +
* http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus
  
http://www.linuxelectrons.com/article.php/20031021142247752
+
=== SMM ===
----------------------------------------------------
+
'''System Management Mode'''. Processor mode that is mainly used for power management purposes.
'''SIO''' (Serial Input/Output)
+
  
http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search
+
=== SMRAM ===
----------------------------------------------------
+
System Management Random Access Memory.
'''SMB'''us (System Management Bus) is a simple two-wire bus used for
+
communication with low-bandwidth devices on a motherboard. It is
+
based on (actually a subset of) I2C.
+
  
http://www.smbus.org/
+
=== SOIC ===
 +
'''Small-Outline Integrated Circuit'''.
 +
* http://en.wikipedia.org/wiki/Small-outline_integrated_circuit
  
http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus
+
=== SPD ===
See I2C for more info.
+
'''Serial Presence Detect'''. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.
----------------------------------------------------
+
* http://www.simmtester.com/page/news/showpubnews.asp?num=101
'''SMM''' (System Management Mode)
+
  
Processor mode that is mainly used for power management purposes.
+
=== SPI ===
----------------------------------------------------
+
The '''Serial Peripheral Interface Bus''' is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.
'''SMRAM''' (System Management Random Access Memory).
+
* http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
----------------------------------------------------
+
'''SPD''' (Serial Presence Detect). On every (?) memory module there's
+
an eprom that provides BIOS with information on how to properly
+
configure the memory module.
+
  
http://www.simmtester.com/page/news/showpubnews.asp?num=101
+
=== SuperIO ===
----------------------------------------------------
+
The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.
'''SPI''' (Serial Peripheral Interface Bus) is a very loose standard for
+
* http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
controlling almost any digital electronics that accepts a clocked serial
+
stream of bits.
+
  
http://encyclopedia.thefreedictionary.com/Serial%20Peripheral%20Interface
+
== T ==
  
http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
+
=== TLB ===
----------------------------------------------------
+
'''Translation Lookaside Buffer'''. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.
'''SuperIO''' is the chip that provides floppy, serial and parallel
+
* http://www.linuxelectrons.com/article.php/20031021142247752
functionality/ports.
+
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
  
http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
 
----------------------------------------------------
 
'''TLB''' (Translation Lookaside Buffer). The TLB stores the most recently used
 
page-directory and page-table entries, which translates into speedier
 
access to said memory.
 
  
http://www.linuxelectrons.com/article.php/20031021142247752
+
== U ==
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
+
----------------------------------------------------
+
'''UC''' (strong UnCacheable). Memory type setting in MTRR/PAT.
+
  
'''UC-''' (UnCacheable). Memory type setting in MTRR/PAT.
+
=== UC ===
 +
Strong '''UnCacheable'''. Memory type setting in MTRR/PAT.
  
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
+
=== UC ===
----------------------------------------------------
+
'''UnCacheable'''. Memory type setting in MTRR/PAT.
 +
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
  
'''UHCI''' (Universal Host Controller Interface). USB standard.
+
=== UHCI ===
 +
'''Universal Host Controller Interface'''. USB standard.
 +
* http://en.wikipedia.org/wiki/UHCI
 +
* http://developer.intel.com/technology/usb/uhci11d.htm
  
http://encyclopedia.thefreedictionary.com/dict.asp?Word=uhci
+
=== UMI ===
 +
Unified Media Interface
  
http://developer.intel.com/technology/usb/uhci11d.htm
+
== V ==
----------------------------------------------------
+
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA
+
signal generation from all the other modules in a (hardware) design. It
+
allows the pixel information to be written into its video memory using a
+
very simple interface, while it is alone responsible for generating the
+
required signals for displaying the pixel information on a VGA monitor.
+
(Note: This is mostly relevant to a hardware design - the text is
+
copied from a students fpga project)
+
  
http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm
+
=== VGAcon ===
----------------------------------------------------
+
The purpose of the '''VGAcon''' (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).
'''VID''' - Vendor ID, a way of identifying the hardware manufacturer. See
+
* http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm
'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and
+
'http://pciids.sourceforge.net/'
+
for more info.
+
  
A way of obtaining info for your hardware is through the 'lspci' command.
+
=== VID ===
Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for
+
'''Vendor ID''', a way of identifying the hardware manufacturer.
more verbose output.
+
* http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx
--------------------------------------------------
+
* http://pciids.sourceforge.net/
'''VME'''Bus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus
+
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.
originally developed for the Motorola 68000.
+
  
http://encyclopedia.thefreedictionary.com/VMEbus
+
=== VMEBus ===
----------------------------------------------------
+
'''VERSAmodule Eurocard Bus''' or '''Versa Module Europa Bus'''. A computer bus originally developed for the Motorola 68000.
'''WB''' (Write-Back). Memory type setting in MTRR/PAT.
+
* http://en.wikipedia.org/wiki/VMEbus
  
'''WC''' (Write-Combining). Memory type setting in MTRR/PAT.
+
== W ==
  
'''WP''' (Write Protected). Memory type setting in MTRR/PAT.
+
=== WB ===
 +
Write-Back. Memory type setting in MTRR/PAT.
  
'''WT''' (Write-Through). Memory type setting in MTRR/PAT.
+
=== WC ===
 +
Write-Combining. Memory type setting in MTRR/PAT.
  
 +
=== WP ===
 +
Write Protected. Memory type setting in MTRR/PAT.
  
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
+
=== WT ===
----------------------------------------------------
+
Write-Through. Memory type setting in MTRR/PAT.
 +
* For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

Latest revision as of 07:08, 9 March 2014

A

ACPI

The Advanced Configuration & Power Interface is an industry standard for letting the OS control power management.

AGP

Advanced Graphics Port, a point-to-point channel for attaching a video card to a mainboard with AGP slot.

AGP Aperture

The memory range that is set aside for AGP access.

AHCI

The Advanced Host Controller Interface. Describes the register-level interface for a SATA host controller.

APIC

Advanced Programmable Interrupt Controller. An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.


B

BAR

Base Address Register (on PCI device).

BIOS

Basic Input/Output System.

BIST

The Built-In Self Test, a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.

C

CAR

Cache as RAM.

CMOS

Complementary metal oxyde semiconductor, a class of semiconductors. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.

CPU

Central processing unit (e.g. an Athlon64).

crt0

C Run Time 0 - This is now called the romstage in coreboot.

crt0s

Sources that make up the romstage in coreboot, see crt0.

D

DCR

Decode Control Register.

DID

Device ID, a way of identifying the hardware in question. See VID for more info.

DMA

Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

DSDT

Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI. Implementation of ACPI in coreboot needs to be done in a "cleanroom" development process to avoid legal issues.

E

EEPROM

Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).

EHCI

Enhanced Host Controller Interface (USB host controller).

F

Flashing

Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.

Framebuffer

The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:

  • Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
  • On-screen, meaning that the framebuffer is directly coupled to the visible display


G

GART

Graphics Address Relocation Table.

GATT

Graphics Aperture Translation Table.

GNB

Graphic NorthBridge.

Part of the newer AMD Fusion chips.

GPP

General Purpose Ports.

Part of the newer AMD Fusion chips.

GPIO

General Purpose Input/Output.

GSoC

Google Summer of Code.

H

Hypertransport

A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.

I

I2C

Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control.

IDSEL/AD

Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?

IRQ

Interrupt ReQuest (Handler).


J

JTAG

Debugging and test 4-wire interface named after an organization which defined it.

L

LAR

is the Linuxbios ARchiver, now called Lightweight ARchiver. It is a small utility that we use to create and change coreboot images and their modules.

LPC

Low Pin Count, an interface aimed at replacing the ISA bus.

LRU

Least Recently Used, a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.

M

Memory Training

Memory training is a very complex technlogical area. We are accumulating references to it as we find them.

It is amazing, but there is very little out there.

MII

Media Independent Interface. This is a chip commonly found on ethernet devices, together with a PHY.

MMIO

Memory-mapped I/O and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.

MPTable

Multi Processor Table. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.

MTRR

Memory Type Range Register. This can be used to control the way a processor accesses memory ranges.

O

OHCI

Open Host Controller Interface. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).


P

PAM

Programmable Attribute Map. Hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers, accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.

PAT

Page Attribute Table. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.

PAT

Performance Acceleration Technology.

PCI

Peripheral Component Interconnect.

PCI Configuration Space

PCI Express / PCIe

PHY

PHY layer device. A device that provides low level access to the physical layer.

PIC

A Programmable Interrupt Controller is a device to control peripheral devices, offloading the main CPU.

PIO

Programmed Input/Output interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.

PIR

Programmable Interrupt Routing?

PIRQ

PCI IRQ routing table,

PLCC

Plastic Leaded Chip Carrier, a square surface-mount chip package.

PLL

Phase Locked Loop is a device to keep (electrical) signals synchronised throughout the system.

POST

The Power On Self Test is a test to check that devices the computer will rely on are functioning, and initializes devices.

R

RDMA

Remote Direct Memory Access is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.

RCS

Revision control systems.

S

SB

Southbridge. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...

SBA

SideBand Addressing.

Shadow RAM

RAM which content is copied from ROM residing at the same address for speedup purposes.

SIO

Serial Input/Output.

SMBus

The System Management Bus is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.

SMM

System Management Mode. Processor mode that is mainly used for power management purposes.

SMRAM

System Management Random Access Memory.

SOIC

Small-Outline Integrated Circuit.

SPD

Serial Presence Detect. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.

SPI

The Serial Peripheral Interface Bus is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.

SuperIO

The SuperIO is the chip that provides floppy, serial and parallel functionality/ports.

T

TLB

Translation Lookaside Buffer. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.


U

UC

Strong UnCacheable. Memory type setting in MTRR/PAT.

UC

UnCacheable. Memory type setting in MTRR/PAT.

  • For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

UHCI

Universal Host Controller Interface. USB standard.

UMI

Unified Media Interface

V

VGAcon

The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).

VID

Vendor ID, a way of identifying the hardware manufacturer.

A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.

VMEBus

VERSAmodule Eurocard Bus or Versa Module Europa Bus. A computer bus originally developed for the Motorola 68000.

W

WB

Write-Back. Memory type setting in MTRR/PAT.

WC

Write-Combining. Memory type setting in MTRR/PAT.

WP

Write Protected. Memory type setting in MTRR/PAT.

WT

Write-Through. Memory type setting in MTRR/PAT.

  • For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3