Glossary - Revision history

Uwe: /* B */ Add BIST.

2010-09-26T14:11:38Z

‎B: Add BIST.

Uwe at 17:33, 22 September 2010

2010-09-22T17:33:06Z

Uwe: Updates, fixes for A-C.

2010-09-22T17:02:13Z

Updates, fixes for A-C.

Wt at 17:48, 13 September 2010

2010-09-13T17:48:18Z

Ward: /* PLCC */

2009-02-04T21:11:19Z

‎PLCC

Ward: /* S */ add entry for SOIC

2009-02-04T21:08:01Z

‎S: add entry for SOIC

Hailfinger: /* Hypertransport */

2008-09-09T22:18:14Z

‎Hypertransport

Uwe: /* M */ Move memory training here.

2008-08-20T10:40:00Z

‎M: Move memory training here.

Stepan: its not the corebootArchiver

2008-02-10T16:16:23Z

its not the corebootArchiver

Stepan at 13:04, 15 January 2008

2008-01-15T13:04:16Z

← Older revision		Revision as of 14:11, 26 September 2010
Line 39:		Line 39:
	* http://en.wikipedia.org/wiki/BIOS		* http://en.wikipedia.org/wiki/BIOS

		+	=== BIST ===
		+	The '''Built-In Self Test''', a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.

	== C ==		== C ==

@@ Line 63: / Line 63: @@
 === DCR ===
-Decode Control Register.
+'''Decode Control Register'''.
 === DID ===
-Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.
+'''Device ID''', a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.
 === DMA ===
-Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
+'''Direct Memory Access'''. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
 DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
 * http://en.wikipedia.org/wiki/Direct_memory_access
 === DSDT ===
-Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also. Implementation of ACPI needs to be done in a "cleanroom" development process to avoid legal issues.
+'''Differentiated System Descriptor Table''', generated by BIOS and necessary for [[#ACPI|ACPI]]. Implementation of [[ACPI|ACPI in coreboot]] needs to be done in a "cleanroom" development process to avoid legal issues.
 * http://acpi.sourceforge.net/dsdt/index.php

@@ Line 3: / Line 3: @@
 === ACPI ===
 The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
 * http://www.acpi.info/
-* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
+* http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface
-* http://kernelslacker.livejournal.com/88243.html     acpitool to generate a C source (see mailing list also)
+* http://kernelslacker.livejournal.com/88243.html (acpitool to generate a C source (see mailing list also))
 === AGP ===
-'''Advanced Graphics Port'''
+'''Advanced Graphics Port''', a point-to-point channel for attaching a video card to a mainboard with AGP slot.
-* http://en.wikipedia.org/wiki/AGP
+* http://en.wikipedia.org/wiki/Accelerated_Graphics_Port
 === AGP Aperture ===
 The memory range that is set aside for AGP access.
-* http://en.wikipedia.org/wiki/AGP
+* http://en.wikipedia.org/wiki/Accelerated_Graphics_Port
 === AHCI ===
 The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
-* http://en.wikipedia.org/wiki/AHCI
+* http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface
 * http://www.intel.com/technology/serialata/ahci.htm
 === APIC ===
-'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.
+'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: '''Local APICs''' (LAPIC) are CPU-bound, '''IO-APICs''' are bridge-bound.
-* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
+* http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller
 * http://osdev.berlios.de/pic.html
@@ Line 29: / Line 31: @@
 === BAR ===
-Base Address Register (on PCI device).
+'''Base Address Register''' (on PCI device).
 === BIOS ===
-Basic Input/Output System.
+'''Basic Input/Output System'''.
@@ Line 38: / Line 43: @@
 === CAR ===
-Cache as RAM.
+'''Cache as RAM'''.
 === CMOS ===
-Complementary metal oxyde semiconductor.
+'''Complementary metal oxyde semiconductor''', a [http://en.wikipedia.org/wiki/CMOS class of semiconductors]. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.
 === CPU ===
-Central processing unit (e.g. an Athlon64)
+'''Central processing unit''' (e.g. an Athlon64).
 === crt0 ===
-C Run Time 0 - This is now called the romstage.
+'''C Run Time 0''' - This is now called the romstage in coreboot.
 === crt0s ===
-Sources that make up the romstage.
+Sources that make up the romstage in coreboot, see [[#crt0|crt0]].
 == D ==

@@ Line 45: / Line 45: @@
 === CPU ===
 Central processing unit (e.g. an Athlon64)
 == D ==

@@ Line 229: / Line 229: @@
 === PLCC ===
 '''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
 * http://www.webopedia.com/TERM/P/PLCC.html

@@ Line 274: / Line 274: @@
 === SMRAM ===
 System Management Random Access Memory.
 === SPD ===
@@ Line 286: / Line 290: @@
 The '''SuperIO''' is the chip that provides floppy, serial and parallel functionality/ports.
 * http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
 == T ==

@@ Line 108: / Line 108: @@
 * http://en.wikipedia.org/wiki/Hypertransport
 * http://www.hypertransport.org
+* http://www.hotchips.org/archives/hc14/3_Tue/28_AMD_Hammer_MP_HC_v8.pdf
 == I ==

@@ Line 144: / Line 144: @@
 == M ==
 === MII ===
@@ Line 161: / Line 170: @@
 '''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
 * http://en.wikipedia.org/wiki/MTRR
 == O ==

@@ Line 133: / Line 133: @@
 === LAR ===
-is the coreboot[[LAR_Design|Archiver]]. It is a small utility that we use to create and change coreboot images and their modules.
+is the Linuxbios ARchiver, now called Lightweight [[LAR_Design|ARchiver]]. It is a small utility that we use to create and change coreboot images and their modules.
 === LPC ===