Difference between revisions of "HP COMPAQ NC6320"

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Line 7: Line 7:
 
* Southbridge: ICH7-M
 
* Southbridge: ICH7-M
 
* superio: SMSC LPC47N217
 
* superio: SMSC LPC47N217
* ec: SMSC LPC47N217
+
* ec: SMSC KBC1021-MT
* flash chip: M25PE80,1024 kB, soldered,SOIC-8  
+
* flash chip: M25PE80,1024 kB, soldered,SOIC-8
  
 
== How to flash ==
 
== How to flash ==
Line 229: Line 229:
 
== grub in BIOS ==
 
== grub in BIOS ==
 
lspci is incomplete:
 
lspci is incomplete:
grub> lspci -i
+
grub> lspci -i
 
  00:00.0 8086:27a0 [0600] Host Bridge
 
  00:00.0 8086:27a0 [0600] Host Bridge
 
  00:02.0 8086:27a2 [0300] VGA Controller
 
  00:02.0 8086:27a2 [0300] VGA Controller
Line 305: Line 305:
 
  grub> setpci -s 00:1f.0 0.W
 
  grub> setpci -s 00:1f.0 0.W
 
  Register 0 of 0:31.0 is 8086
 
  Register 0 of 0:31.0 is 8086
 +
 +
== small python helper ==
 +
This small python helper will help me with the superio init(trough southbridge).
 +
 +
It's derived from coreboot code(and so under the same license).
 +
 +
It's specific to my configuration options tough...
 +
 +
$ cat coreboothelper.py
 +
#! /usr/bin/env python
 +
def PCI_DEV(SEGBUS, DEV, FN):
 +
    return ((((SEGBUS) & 0xFFF) << 20) | (((DEV) & 0x1F) << 15) | (((FN)  & 0x07) << 12))
 +
 +
def pci_write_config8(dev,where,value):
 +
    addr = (dev>>4) | where
 +
    print "outl({0:#x},{1:#x});".format(0x80000000 | (addr & ~3), 0xCF8)
 +
    print "outb({0:#x},{1:#x});".format(value, 0xCFC + (addr & 3))
 +
 +
def pci_write_config16(dev,where,value):
 +
    addr = (dev>>4) | where
 +
    print "outl({0:#x},{1:#x});".format(0x80000000 | (addr & ~3), 0xCF8)
 +
    print "outw({0:#x},{1:#x});".format(value, 0xCFC + (addr & 2))
 +
 +
def pci_read_config16(dev,where):
 +
    addr = (dev>>4) | where
 +
    print "outl({0:#x},{1:#x});".format((0x80000000 | (addr & ~3)), 0xCF8)
 +
    print "inw({0:#x});".format(0xCFC + (addr & 2))
 +
 +
 +
$ python
 +
Python 2.7.3 (default, Dec 22 2012, 21:27:36)
 +
[GCC 4.7.2] on linux2
 +
Type "help", "copyright", "credits" or "license" for more information.
 +
>>> from coreboothelper import *
 +
>>> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x92)
 +
outl(0x8000f864,0xcf8);
 +
outb(0x92,0xcfc);

Latest revision as of 11:03, 18 January 2013

Status

Nothing work yet, no output on serial.

Hardware

  • CPU: T7200
  • Northbridge: 945GM
  • Southbridge: ICH7-M
  • superio: SMSC LPC47N217
  • ec: SMSC KBC1021-MT
  • flash chip: M25PE80,1024 kB, soldered,SOIC-8

How to flash

  • disassemble the laptop
  • Put the power adapter in the laptop's power plug
  • power off the laptop
  • attach the pomona clip and flash(backup the BIOS before.)

how to unpack the BIOS

See http://paste.flashrom.org/view.php?id=1523

Ec Issue

The ec firmware(4000_KBC.bin) probably has to be in the image at the same fixed position than the BIOS.

LPC

# lspci -nnvvvxxx -s 00:1f.0
00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 01)
	Subsystem: Hewlett-Packard Company Device [103c:30aa]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-INTx-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information: Len=0c <?>
	Kernel modules: leds-ss4200, iTCO_wdt, intel-rng
00: 86 80 b9 27 07 00 10 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 aa 30
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 10 00 00 80 00 00 00 01 11 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 80 80 80 80 92 00 00 00 80 80 80 80 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 05 3c 01 05 7c 00 00 00 00 00 00 00 00 00
90: 39 02 04 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 24 06 00 00 e1 00 00 00 13 1c 0a 00 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 08 60 60 91 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 00 c0 00 00 00 00 00 00
e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00
f0: 01 00 d9 fe 00 00 00 00 86 0f 02 00 00 00 00 00

Patch (not working)

The nc6320 is very similar to the Roda rk886ex, with only the superio that is different.

From c9e8a0dbc5519024be2acc5877c4f2b62a0461d6 Mon Sep 17 00:00:00 2001
From: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date: Mon, 14 Jan 2013 00:28:07 +0100
Subject: [PATCH] Changes for nc6320

Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
---
 src/mainboard/roda/rk886ex/Kconfig       |  2 +-
 src/mainboard/roda/rk886ex/devicetree.cb |  2 +-
 src/mainboard/roda/rk886ex/romstage.c    | 92 +++++++-------------------------
 3 files changed, 20 insertions(+), 76 deletions(-)

diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 84a8543..0095f4d 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCI7420
-	select SUPERIO_SMSC_LPC47N227
+	select SUPERIO_SMSC_LPC47N217
 	select SUPERIO_RENESAS_M3885X
 	select EC_ACPI
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index aadba9d..955561a 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/intel/i945
 			#device pci 1e.2 off end # AC'97 Audio
 			#device pci 1e.3 off end # AC'97 Modem
                         device pci 1f.0 on # LPC bridge
-                                chip superio/smsc/lpc47n227
+                                chip superio/smsc/lpc47n217
 					device pnp 2e.1 on # Parallel port
 						 io 0x60 = 0x378
 						irq 0x70 = 5
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index d75d33f..8be7b4e 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -35,6 +35,7 @@
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
+#include "superio/smsc/lpc47n217/early_serial.c"
 #include "option_table.h"
 
 void setup_ich7_gpios(void)
@@ -68,82 +69,35 @@ void setup_ich7_gpios(void)
 
 static void ich7_enable_lpc(void)
 {
-	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
-	       lpt_en = 1<<2; // enable LPT
-	}
 	// Enable Serial IRQ
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x8);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
-	// Enable 0x02e0
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2001); //CNF2_LPC_EN| lpt_en);
+	// Enable 0x04e0
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x34e1);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
 	// COM3 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+	//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
 	// COM4 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
-}
-
-/* This box has two superios, so enabling serial becomes slightly excessive.
- * We disable a lot of stuff to make sure that there are no conflicts between
- * the two. Also set up the GPIOs from the beginning. This is the "no schematic
- * but safe anyways" method.
- */
-static inline void pnp_enter_ext_func_mode(device_t dev)
-{
-	unsigned int port = dev >> 8;
-	outb(0x55, port);
+	//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
 }
 
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	unsigned int port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void pnp_write_register(device_t dev, int reg, int val)
-{
-	unsigned int port = dev >> 8;
-	outb(reg, port);
-	outb(val, port+1);
-}
 
 static void early_superio_config(void)
 {
-	device_t dev;
-
-	dev=PNP_DEV(0x2e, 0x00);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
-	pnp_write_register(dev, 0x02, 0x88); // UART power on
-	pnp_write_register(dev, 0x03, 0x72); // Floppy
-	pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
-	pnp_write_register(dev, 0x14, 0x03); // Floppy
-	pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
-	pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
-	pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
-	pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
-	pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
-	pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
-	pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
-	/* These are the SMI status registers in the SIO: */
-	pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
-
-	pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
-	pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
-	pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
-	pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
-	pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
-	pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
-	pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
-	pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
-	pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
-
-	pnp_exit_ext_func_mode(dev);
+	/* Found SMSC LPC47N217 (id=0x7a, rev=0x01) at 0x4e */
+	device_t dev = PNP_DEV(0x4e, LPC47N217_SP1);
+	lpc47n217_enable_serial(dev, CONFIG_TTYS0_BASE);
+//	uart_init();
+#if 0
+	outb(0x24, 0xcd6);
+	outb(0x1, 0xcd7);
+	outb(0xea, 0xcd6);
+	outb(0x1, 0xcd7);
+	*(u8 *)0xfed80101 = 0x98;
+#endif
 }
 
 static void rcba_config(void)
@@ -243,13 +197,6 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-static void init_artec_dongle(void)
-{
-	// Enable 4MB decoding
-	outb(0xf1, 0x88);
-	outb(0xf4, 0x88);
-}
-
 #include <cbmem.h>
 
 void main(unsigned long bist)
@@ -285,9 +232,6 @@ void main(unsigned long bist)
 	 */
 	i945_early_initialization();
 
-	/* This has to happen after i945_early_initialization() */
-	init_artec_dongle();
-
 	/* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
-- 
1.8.1

grub in BIOS

lspci is incomplete:

grub> lspci -i
00:00.0 8086:27a0 [0600] Host Bridge
00:02.0 8086:27a2 [0300] VGA Controller
        32-bit memory space 0 at 0x00000000e8400000 [non-prefetchable]
        IO space 1 at 0x6000
        32-bit memory space 2 at 0x00000000d0000000 [prefetchable]
        32-bit memory space 3 at 0x00000000e8480000 [non-prefetchable]
00:02.1 8086:27a6 [0380] Display Controller
        32-bit memory space 0 at 0x00000000e8500000 [non-prefetchable]
00:1b.0 8086:27d8 [0403] Multimedia device
        64-bit memory space 0 at 0x00000000e8580000 [non-prefetchable]
00:1c.0 8086:27d0 [0604] PCI-PCI Bridge
        32-bit memory space 2 at 0x0000000000080800 [non-prefetchable]
        32-bit memory space 3 at 0x00000000000000f0 [non-prefetchable]
        32-bit memory space 4 at 0x00000000e800e800 [non-prefetchable]
        IO space 5 at 0x1fff0
00:1c.2 8086:27d4 [0604] PCI-PCI Bridge
        32-bit memory space 2 at 0x0000000000181800 [non-prefetchable]
        32-bit memory space 3 at 0x0000000020005040 [non-prefetchable]
        32-bit memory space 4 at 0x00000000e7f0e400 [non-prefetchable]
        IO space 5 at 0x1fff0
00:1c.3 8086:27d6 [0604] PCI-PCI Bridge
        32-bit memory space 2 at 0x0000000000202000 [non-prefetchable]
        32-bit memory space 3 at 0x0000000020003020 [non-prefetchable]
        32-bit memory space 4 at 0x00000000e3f0e000 [non-prefetchable]
        IO space 5 at 0x1fff0
00:1d.0 8086:27c8 [0c03] USB Controller
        IO space 4 at 0x6020
00:1d.1 8086:27c9 [0c03] USB Controller
        IO space 4 at 0x6040
00:1d.2 8086:27ca [0c03] USB Controller
        IO space 4 at 0x6060
00:1d.3 8086:27cb [0c03] USB Controller
        IO space 4 at 0x6080
00:1d.7 8086:27cc [0c03] USB Controller [PI 20]
        32-bit memory space 0 at 0x00000000e8584000 [non-prefetchable]
00:1e.0 8086:2448 [0604] PCI-PCI Bridge [PI 01]
        32-bit memory space 2 at 0x0000000020030200 [non-prefetchable]
        32-bit memory space 3 at 0x00000000228000f0 [non-prefetchable]
        32-bit memory space 4 at 0x00000000e830e810 [non-prefetchable]
        IO space 5 at 0x1fff0
00:1f.0 8086:27b9 [0601] ISA Bridge
00:1f.1 8086:27df [0101] IDE Controller [PI 8a]
        IO space 0 at 0x0
        IO space 1 at 0x0
        IO space 2 at 0x0
        IO space 3 at 0x0
        IO space 4 at 0x60a0
00:1f.2 8086:27c5 [0106] SATA Controller [PI 01]
        IO space 0 at 0x13f0
        IO space 1 at 0x15f4
        IO space 2 at 0x1370
        IO space 3 at 0x1574
        IO space 4 at 0x60d0
        32-bit memory space 5 at 0x00000000e8585000 [non-prefetchable]
02:06.0 104c:8039 [0607] CardBus Bridge
        32-bit memory space 0 at 0x00000000e8100000 [non-prefetchable]
        32-bit memory space 1 at 0x00000000020000a0 [non-prefetchable]
        32-bit memory space 2 at 0x0000000000030300 [non-prefetchable]
02:06.1 104c:803a [0c00] Serial Bus Controller [PI 10]
        32-bit memory space 0 at 0x00000000e8101000 [non-prefetchable]
        32-bit memory space 1 at 0x00000000e8104000 [non-prefetchable]
02:06.2 104c:803b [0180] Mass storage Controller
        32-bit memory space 0 at 0x00000000e8108000 [non-prefetchable]
02:06.3 104c:803c [0805] System hardware
        32-bit memory space 0 at 0x00000000e8109000 [non-prefetchable]
02:06.4 104c:803d [0780] Communication controller
        32-bit memory space 0 at 0x00000000e810a000 [non-prefetchable]
        32-bit memory space 1 at 0x00000000e810b000 [non-prefetchable]
02:0e.0 14e4:169c [0200] Ethernet Controller
        32-bit memory space 0 at 0x00000000e8110000 [non-prefetchable]
08:00.0 8086:4222 [0280] Network controller
        32-bit memory space 0 at 0x00000000e8000000 [non-prefetchable]

but:

grub> setpci -s 00:1f.0 0.W
Register 0 of 0:31.0 is 8086

small python helper

This small python helper will help me with the superio init(trough southbridge).

It's derived from coreboot code(and so under the same license).

It's specific to my configuration options tough...

$ cat coreboothelper.py 
#! /usr/bin/env python
def PCI_DEV(SEGBUS, DEV, FN):
    return ((((SEGBUS) & 0xFFF) << 20) | (((DEV) & 0x1F) << 15) | (((FN)  & 0x07) << 12))

def pci_write_config8(dev,where,value):
    addr = (dev>>4) | where
    print "outl({0:#x},{1:#x});".format(0x80000000 | (addr & ~3), 0xCF8)
    print "outb({0:#x},{1:#x});".format(value, 0xCFC + (addr & 3))

def pci_write_config16(dev,where,value):
    addr = (dev>>4) | where
    print "outl({0:#x},{1:#x});".format(0x80000000 | (addr & ~3), 0xCF8)
    print "outw({0:#x},{1:#x});".format(value, 0xCFC + (addr & 2))

def pci_read_config16(dev,where):
    addr = (dev>>4) | where
    print "outl({0:#x},{1:#x});".format((0x80000000 | (addr & ~3)), 0xCF8)
    print "inw({0:#x});".format(0xCFC + (addr & 2))


$ python
Python 2.7.3 (default, Dec 22 2012, 21:27:36) 
[GCC 4.7.2] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> from coreboothelper import *
>>> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x92)
outl(0x8000f864,0xcf8);
outb(0x92,0xcfc);