Difference between revisions of "Board:lenovo/x60/Installation"

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#* Change the .probe field to probe_spi_res1
 
#* Change the .probe field to probe_spi_res1
 
#* Change the .model_id field to the RES1 ID given in the datasheet of the flash chip
 
#* Change the .model_id field to the RES1 ID given in the datasheet of the flash chip
#* Change the .write field to spi_chip_write1
+
#* Change the .write field to spi_chip_write_1
 
# Run <code>flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin</code>
 
# Run <code>flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin</code>
 
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.
 
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.
Line 28: Line 28:
 
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009121.html Peter's mail] before you panic.
 
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009121.html Peter's mail] before you panic.
 
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot
 
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot
# Undo the flashrom patch, so that you have a stock flashrom
 
# Run <code>bucts 0</code> (do '''NOT''' power off before running flashrom in the next step, or you '''will''' brick the machine!)
 
 
# Run <code>flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom</code>.
 
# Run <code>flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom</code>.
 
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.
 
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.
 +
# Run <code>bucts 0</code>
  
  
Line 39: Line 38:
 
== Recovery ==
 
== Recovery ==
 
If you had a bad flash you will need a recovery method.
 
If you had a bad flash you will need a recovery method.
you will need:
+
=== Required/advised hardware and informations ===
 
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] (for disassembling the laptop)
 
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] (for disassembling the laptop)
 
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.
 
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.
 
* An external flashrom programmer
 
* An external flashrom programmer
<to be continued>
+
 
 +
=== Howto ===
 +
0.  wire the pomona clip to a programmer that way:
 +
 
 +
From the #coreboot IRC Channel on FreeNode servers:
 +
Oct 01 15:35:48 <CareBear\>    one important thing is that when you connect the clip to the X60 you should not connect all pins
 +
[...]
 +
Oct 01 15:36:22 <CareBear\>    only connect these pins: 1, 2, 4, 5, 6
 +
[...]
 +
Oct 01 15:37:21 <CareBear\>    also important: first connect charger to laptop, then connect the clip
 +
[...]
 +
Oct 01 17:49:41 <CareBear\>    GNUtoo-desktop : the mainboard must be powered off, but with the charger connected
 +
[...]
 +
Oct 01 17:50:39 <CareBear\>    um, that way there is no way anything will break
 +
[...]
 +
Oct 01 17:51:00 <CareBear\>    it is important not to connect 3v3 from the outside
 +
Oct 01 17:51:39 <CareBear\>    because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside
 +
[...]
 +
Oct 01 17:52:48 <CareBear\>    it may also be fine - but it is unknown what happens
 +
[...]
 +
Oct 01 17:53:47 <CareBear\>    not supplying 3v3 from the outside is safer
 +
Oct 01 17:54:25 <CareBear\>    and because the machine is powered off, there is no risk of the chipset accessing the flash chip
 +
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...
 +
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...
 +
# connect the pomona clip to the BIOS chip
 +
# flash coreboot or the BIOS
 +
# remount the laptop
 +
 
 +
== Coreboot configuration ==
 +
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:
 +
[ ] Run VGA Option ROMs
 +
in make menuconfig.
 +
Note that you still need to include the option rom in coreboot:
 +
[*] Add a VGA BIOS image
 +
See [[VGA_support]] for details on how to include the VGA BIOS image.
 +
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).
 +
 
 +
From the #coreboot IRC Channel on FreeNode servers:
 +
Oct 04 13:47:09 <patrickg>      that's about running vga init on s3 wakeup - required for some older linux kernels
 +
[...]
 +
Oct 04 13:47:25 <patrickg>      BIOSes call it "POST on wakeup" or sth like that
 +
Oct 04 13:47:30 <patrickg>     older ~ 2.4 class ;)
  
 
== Status ==
 
== Status ==
<insert the status here>
+
* [[Thinkpad_X60s|Thinkpad X60s Status]]

Revision as of 22:23, 10 October 2012

Flashing on the laptop instructions.

Lenovo X60, X60s, T60 and T60p flashing instructions.

These Lenovo laptops have a register that must be flipped before coreboot can be flashed.

For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection).

You will need: the flashrom source, a small patch for it, and the bucts utility.

  1. Patch flashrom to use RES1 SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES1 command.
    Alternatively, you can copy the existing definition first as it is done in this patch. Choose either method: apply the patch in the link, or do the patch yourself, as per instruction below.
    • Find the definition of your flash chip in flashrom's flashchips.c
    • Change the .probe field to probe_spi_res1
    • Change the .model_id field to the RES1 ID given in the datasheet of the flash chip
    • Change the .write field to spi_chip_write_1
  2. Run flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin
    This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.
  3. Run dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k
  4. Run dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump
    Verify that the complete range is filled with ff bytes before proceeding! The above command must output:
    0000000 ffff ffff ffff ffff ffff ffff ffff ffff
    *
    0010000
    If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.
  5. Run dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc
  6. Run bucts 1
  7. Run flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom
    This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see Peter's mail before you panic.
  8. Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot
  9. Run flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom.
    This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.
  10. Run bucts 0


See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575

Recovery

If you had a bad flash you will need a recovery method.

Required/advised hardware and informations

Howto

0. wire the pomona clip to a programmer that way:

From the #coreboot IRC Channel on FreeNode servers:

Oct 01 15:35:48 <CareBear\>     one important thing is that when you connect the clip to the X60 you should not connect all pins
[...]
Oct 01 15:36:22 <CareBear\>     only connect these pins: 1, 2, 4, 5, 6
[...]
Oct 01 15:37:21 <CareBear\>     also important: first connect charger to laptop, then connect the clip
[...]
Oct 01 17:49:41 <CareBear\>     GNUtoo-desktop : the mainboard must be powered off, but with the charger connected
[...]
Oct 01 17:50:39 <CareBear\>     um, that way there is no way anything will break
[...]
Oct 01 17:51:00 <CareBear\>     it is important not to connect 3v3 from the outside
Oct 01 17:51:39 <CareBear\>     because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside
[...]
Oct 01 17:52:48 <CareBear\>     it may also be fine - but it is unknown what happens
[...]
Oct 01 17:53:47 <CareBear\>     not supplying 3v3 from the outside is safer
Oct 01 17:54:25 <CareBear\>     and because the machine is powered off, there is no risk of the chipset accessing the flash chip

In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...

  1. Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...
  2. connect the pomona clip to the BIOS chip
  3. flash coreboot or the BIOS
  4. remount the laptop

Coreboot configuration

  • It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:
[ ] Run VGA Option ROMs

in make menuconfig. Note that you still need to include the option rom in coreboot:

[*] Add a VGA BIOS image

See VGA_support for details on how to include the VGA BIOS image.

  • Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).

From the #coreboot IRC Channel on FreeNode servers:

Oct 04 13:47:09 <patrickg>      that's about running vga init on s3 wakeup - required for some older linux kernels
[...]
Oct 04 13:47:25 <patrickg>      BIOSes call it "POST on wakeup" or sth like that
Oct 04 13:47:30 <patrickg>      older ~ 2.4 class ;)

Status