Difference between revisions of "MSI JSPI1"

From coreboot
Jump to: navigation, search
(description of JSPI1 on MSI mainboards)
 
(correct expansion of MOSI)
 
Line 24: Line 24:
 
|MISO||SPI Master In/Slave Out
 
|MISO||SPI Master In/Slave Out
 
|-
 
|-
|MOSI||SPI Slave Out/Master In
+
|MOSI||SPI Master Out/Slave In
 
|-
 
|-
 
|#SS||SPI Slave (Chip) Select (active low)
 
|#SS||SPI Slave (Chip) Select (active low)

Latest revision as of 16:20, 6 November 2011

JSPI1 is a 5×2 2.0mm pitch pin header on many MSI motherboards. It is used to recover from bad boot ROM images. Specifically, it appears to be used to connect an alternate ROM with a working image. Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another SPI ROM to take its place on the bus.

JSPI1
name pin pin name
3VSB 1 2 3VSB
MISO 3 4 MOSI
#SS 5 6 SCLK
GND 7 8 GND
#HOLD 9 10 NC
name function
3VSB standby 3.3V
MISO SPI Master In/Slave Out
MOSI SPI Master Out/Slave In
#SS SPI Slave (Chip) Select (active low)
SCLK SPI Clock
GND ground/common
#HOLD SPI hold (active low)
NC Not Connected (no pin)

Template:Cc-by-3.0