Difference between revisions of "Nokia IP330"

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m (EEPROM behide the SuperIO)
 
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On board of the IP530 can be found the following:
 
On board of the IP530 can be found the following:
* Pentium III.
+
* CPU: Socket 7, AMD K6 II at 266 MHz normally,
* I440BX northbridge.
+
** Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those.  
 +
* I430TX northbridge.
 
* 82371 southbridge.
 
* 82371 southbridge.
 
* intel 21150 PCI to PCI bridge.
 
* intel 21150 PCI to PCI bridge.
* 28F400, 512 Kbyte flashrom.
+
* 28F200, 256 Kbyte flashrom.
* SMSC FDC37B787 superio with 1024 bits SPI eeprom attached.
+
* SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.
* LM78 power controller.
+
* LM72 temp controller.
* 4 intel 21143PD ethernet controllers with KS8716 PHY interface, with each a 1024 bits SPI eeprom attached.
+
* 3 intel 82558B ethernet controllers.
* Texas instruments PCI1225 PCMCIA/Cardbus controller with TPS22061 slot controller.
+
* 2 SD-RAM sockets.
* 4 SD-RAM sockets.
+
** 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM.
 +
** On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.
  
 
Below the description is given for the following;
 
Below the description is given for the following;
* For the connectors on the mainboard of the Nokia IP530, due missing documentation of the manufacturer.  
+
* For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer.  
 
* To create a flash option board on the J-DEBUG connector.  
 
* To create a flash option board on the J-DEBUG connector.  
* To create a USB port.
 
* HOWTO read the status of the jumpers.
 
* HOWTO enable/disable the LEDs.
 
 
* The layout of the SPI eeprom behind the SuperIO.
 
* The layout of the SPI eeprom behind the SuperIO.
  
----
 
==== J10 ====
 
 
The J10 connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.
 
 
{|border="1"
 
|+ JDEBUG connector
 
! Pin# !! Name !! Description || Pin# || Name || Description
 
|------------------------------
 
| 1|| unknown||?||2||VCC +5 Volt||n/a
 
|------------------------------
 
| 3|| A16 ||Address line A16 || 4||A18||Address line A18
 
|------------------------------
 
| 5|| A15 ||Address line A15 || 6||A17||Address line A17
 
|------------------------------
 
| 7|| A12 ||Address line A12 || 8||A14||Address line A14
 
|------------------------------
 
| 9||  A7 ||Address line A7  || 10||A13||Address line A13
 
|------------------------------
 
|11||  A6 ||Address line A6  || 12|| A8||Address line A8
 
|------------------------------
 
|13||  A5 ||Address line A5  || 14|| A9||Address line A9
 
|------------------------------
 
|15||  A4 ||Address line A4  || 16|| A11 ||Address line A11
 
|------------------------------
 
|17||  A3 ||Address line A3  || 18|| OE# ||Chip Enable Line OE#
 
|------------------------------
 
|19||  A2 ||Address line A2  || 20|| A10 ||Address line A10
 
|------------------------------
 
|21||  A1 ||Address line A1  || 22|| JP800.1 || BIOSCS#
 
|------------------------------
 
|23||  A0 ||Address line A0  || 24|| D7  ||Data line D7
 
|------------------------------
 
|25||  D0 ||Data line A0    || 26|| D6  ||Data line D6
 
|------------------------------
 
|27||  D1 ||Data line D1    || 28|| D5  ||Data line D5
 
|------------------------------
 
|29||  D2 ||Data line D2    || 30|| D4  ||Data line D4
 
|------------------------------
 
|31|| IOW#||Control line IOW#|| 32|| D3  ||Data line D3
 
|------------------------------
 
|33|| GND ||Ground          || 34|| IOR#||Control line IOR#
 
|}
 
 
For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used. 
 
 
[[media:Rom-option-board-schema.pdf|Schematic ROM option board]]
 
 
As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.
 
 
[[media:Rom-option-board.pdf|Printed Circuit Board (PCB) layout]]
 
 
The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time.
 
 
The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in.
 
 
[[media:Rom-option-board-overview.pdf|Components overview PCB]]
 
 
When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up. 
 
  
 
----
 
----
 +
=== Device connectors ===
  
==== Jumper JP800 - BIOSCS select ====
+
* '''J1'''  Backplane CPU fan
 +
* '''J2'''  Backplane system fan
 +
* '''J3'''  Backplane system fan
 +
* '''J4'''  Backplane system fan
 +
* '''J5'''  CPU fan (not used)
 +
* '''J9'''  IDE connector
 +
* '''J10''' The Floppy connector
 +
* '''J15''' Serial port connector (ML10), COM2
 +
* '''J16''' Phone connector (behind front)
 +
* '''J17''' Ethernet RJ45 connector eth s3
 +
* '''J18''' Ethernet RJ45 connector eth s4
 +
* '''J19''' Ethernet RJ45 connector eth s5
  
This jumper selected the on-board flash or the J-DEBUG connector where the BIOSCS# line is routed.
 
  
{|border="1"
+
-----
|+ J800 Jumper
+
! Pin# !! Name !! Description
+
|-
+
|1||JDEBUG.P22||This is connected to PIN 22 of the JDEBUG connection on the board
+
|-
+
|2||BIOSCS#||Connected to the ROMCS# line of the Northbridge
+
|-
+
|3||CS#||This is connected to CS# of the on-board flash chip.
+
|}
+
  
The WP# line of the on-board flashchip is controlled by Pin39 of the SMSC FDC37B787 Super I/O chip.
+
=== jumpers ===
 +
* JP1
 +
** 1-2 = short reset CMOS ?
  
On the production boards the J800 is not present and the R814 (0 Ohm) is placed, remove this resistor and solder in the 3 pin-jumper for JP800. And place the jumper on position 2-3 to select the on-board flash chip.
+
* JP2 (besides CPU, not soldered in)
 +
** 1-2  
 +
** 3-4
 +
** 5-6
  
----
+
* JP3
 +
** 1-2 = P or E mode
 +
** 2-3 = All BLK locked (default)
  
==== Jumper JP900 ====
+
* JP4
 +
** 1-2 = B.B. Unlocked
 +
** 2-3 = B.B locked (default)
  
This is a input signal on the Super I/O chip.
+
* JP5
 +
**
 +
**
 +
 +
* JP6
 +
** 1-6 B.B. Locked (default)
 +
** 2-5 B.B. Unlocked
 +
** 3-4 B.B. DPD Locked
  
{|border="1"
+
* JP11-JP13 Serial port COM2
|+ J900 Jumper
+
* JP12-JP14 Internal modem
! Pin# !! Name !! Description
+
|-
+
|1||GND||Ground of the system
+
|-
+
|2||GPIO16||Pin 4 of the SMSC FDC37B787 Super I/O chip.
+
|}
+
 
+
Pin 2 is pulled-up by resistor up VCC.
+
 
+
  #define REG_GP1x 0xF6
+
  #define JP900         0x20
+
 
+
  sio_enter_config( 0x3F0 );
+
  val = (sio_read( 0x3F0, REG_GP6x ) & JP901); 
+
  sio_leave_config( 0x3F0 );
+
  
  
 
----
 
----
  
==== Jumper JP901 ====
+
=== Power connectors ===
  
This is a input signal on the Super I/O chip.
+
* P1 option power connector
 +
* P2 IDE power connector
 +
* P3 Serial port connector (DB9), COM1
  
{|border="1"
+
* P6 Power connector
|+ J901 Jumper
+
! Pin# !! Name !! Description
+
|-
+
|1||GND||Ground of the system
+
|-
+
|2||GPIO67||Pin 90 of the SMSC FDC37B787 Super I/O chip.
+
|}
+
  
Pin 2 is pulled-up by resistor up VCC.
 
 
  #define REG_GP6x 0xYY
 
  #define JP901         0x80
 
 
 
  sio_enter_config( 0x3F0 );
 
  val = (sio_read( 0x3F0, REG_GP6x ) & JP901); 
 
  sio_leave_config( 0x3F0 );
 
 
 
----
 
 
==== Front LED ====
 
{|border="1"
 
|+ LEDs in front
 
! LED !! Control line !! Description
 
|-
 
|Fault||FDC37B787-GP13||active low
 
|}
 
 
  #define REG_GP1x 0xF6
 
  #define LED_FAULT 0x08
 
 
 
  sio_enter_config( 0x3F0 );
 
  val = sio_read( 0x3F0, REG_GP1x );
 
 
 
  // To enable the ALERT led
 
  val &= ~LED_ALERT;
 
 
 
  // To disable the ALERT led
 
  val |= LED_ALERT;
 
 
 
  // To enable the FAULT led
 
  val &= ~LED_FAULT;
 
 
 
  // To disable the FAULT led
 
  val |= LED_FAULT;
 
 
 
  sio_write( 0x3F0, REG_GP1x, val );
 
  sio_leave_config( 0x3F0 );
 
 
By using the sio_xxx() functions from flashrom, makes easy work dis-/en-abling the LEDs in the front.
 
 
----
 
 
==== EEPROM behide the SuperIO ====
 
==== EEPROM behide the SuperIO ====
 
{|border="1"
 
{|border="1"
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! address range !! length !! Content !! Description
 
! address range !! length !! Content !! Description
 
|-
 
|-
|0x00-0x05||6 bytes||IP530\x00||Product name
+
|0x00-0x05||6 bytes||IP330\x00||Product name
 
|-
 
|-
 
|0x06-0x13||14 bytes||0x55||Filler
 
|0x06-0x13||14 bytes||0x55||Filler
Line 325: Line 219:
 
|0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown
 
|0x20-0x23||4 bytes||0x10,0x00,0x00,0x00||Unknown
 
|-
 
|-
|0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu
+
|0x24-0x29||6 bytes||-||Board number, sticker between NB and SB
 
|-
 
|-
 
|0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces
 
|0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces
Line 342: Line 236:
 
|}
 
|}
  
On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.
+
On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision,  
  
 
<font color="red"><br>
 
<font color="red"><br>
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<br></font>
 
<br></font>
  
 +
The eeprom can be read through the LDN RTC of the superio.
 
----
 
----

Latest revision as of 07:46, 29 January 2011

This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by Marc Bertens.


The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.

The System has no VGA, all console activity must be done through a serial console. At the front the following can be found;

  • Power LED
  • Fault LED
  • 2 Serial interfaces COM1 and COM2
  • 3 Ethernet RJ45 sockets
  • Reset button
  • 1 Compact PCI slot

At the back the following can be found;

  • EURO Power connector
  • Power switch
  • Three FANs for system unit cooling
  • One FAN for CPU cooling


Development status

The current development status is; No coreboot running yet


Hardware status

Device/functionality Status Comments
CPU
CPU works WIP K6
L1 cache enabled WIP
L2 cache enabled WIP
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support N/A
Hardware virtualization N/A
RAM
EDO N/A
SDRAM WIP
SO-DIMM N/A
DDR N/A
DDR2 N/A
DDR3 N/A
Dual channel support N/A
ECC support WIP
On-board Hardware
On-board IDE 3.5" OK One IDE connector on-board
On-board IDE 2.5" N/A
On-board SATA N/A
On-board SCSI N/A
On-board USB N/A
On-board VGA N/A
On-board ethernet WIP Three intel SB82558B controllers.
On-board audio N/A
On-board modem N/A
On-board FireWire N/A
On-board smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards WIP
Mini-PCI add-on cards N/A
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards N/A
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards N/A
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A
Serial port 1 (COM1) OK
Serial port 2 (COM2) OK
Parallel port N/A
PS/2 keyboard N/A
PS/2 mouse N/A
Game port N/A
Infrared N/A
PC speaker N/A
DiskOnChip N/A
Miscellaneous
Sensors / fan control WIP
Hardware watchdog N/A
SMBus WIP
CAN bus N/A
CPU frequency scaling N/A
Other powersaving features N/A
ACPI No There's no ACPI implementation for this board, but it's on our TODO list.
Reboot N/A
Poweroff N/A
Suspend Unknown
Nonstandard LEDs WIP Special-purpose LED available on the board, Fault is controlled by the superio?
High precision event timers (HPET) N/A
Random number generator (RNG) N/A
Wake on modem ring N/A
Wake on LAN N/A
Wake on keyboard N/A
Wake on mouse N/A
Flashrom WIP Supported flashrom revision will be higher than 1257.


System Setup

On board of the IP530 can be found the following:

  • CPU: Socket 7, AMD K6 II at 266 MHz normally,
    • Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those.
  • I430TX northbridge.
  • 82371 southbridge.
  • intel 21150 PCI to PCI bridge.
  • 28F200, 256 Kbyte flashrom.
  • SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.
  • LM72 temp controller.
  • 3 intel 82558B ethernet controllers.
  • 2 SD-RAM sockets.
    • 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM.
    • On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.

Below the description is given for the following;

  • For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer.
  • To create a flash option board on the J-DEBUG connector.
  • The layout of the SPI eeprom behind the SuperIO.



Device connectors

  • J1 Backplane CPU fan
  • J2 Backplane system fan
  • J3 Backplane system fan
  • J4 Backplane system fan
  • J5 CPU fan (not used)
  • J9 IDE connector
  • J10 The Floppy connector
  • J15 Serial port connector (ML10), COM2
  • J16 Phone connector (behind front)
  • J17 Ethernet RJ45 connector eth s3
  • J18 Ethernet RJ45 connector eth s4
  • J19 Ethernet RJ45 connector eth s5



jumpers

  • JP1
    • 1-2 = short reset CMOS ?
  • JP2 (besides CPU, not soldered in)
    • 1-2
    • 3-4
    • 5-6
  • JP3
    • 1-2 = P or E mode
    • 2-3 = All BLK locked (default)
  • JP4
    • 1-2 = B.B. Unlocked
    • 2-3 = B.B locked (default)
  • JP5
  • JP6
    • 1-6 B.B. Locked (default)
    • 2-5 B.B. Unlocked
    • 3-4 B.B. DPD Locked
  • JP11-JP13 Serial port COM2
  • JP12-JP14 Internal modem



Power connectors

  • P1 option power connector
  • P2 IDE power connector
  • P3 Serial port connector (DB9), COM1
  • P6 Power connector

EEPROM behide the SuperIO

EEPROM information
address range length Content Description
0x00-0x05 6 bytes IP330\x00 Product name
0x06-0x13 14 bytes 0x55 Filler
0x14-0x17 4 bytes 0x05,0x00,0x00,0x00 Unknown
0x18-0x1B 4 bytes 0x04,0x00,0x00,0x00 Unknown
0x1C-0x1F 4 bytes 0x03,0x00,0x00,0x00 Unknown
0x20-0x23 4 bytes 0x10,0x00,0x00,0x00 Unknown
0x24-0x29 6 bytes - Board number, sticker between NB and SB
0x2A-0x37 14 bytes - Mfg. P/n (on the bottom side of the unit), filled out with spaces
0x38-0x3D 6 bytes 0x55 Filler
0x3E-0x3F 2 bytes 0xYY,0x00 Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42
0x40-0x51 18 bytes 0x55 Filler
0x52-0x5D 12 bytes - Serial number (on the bottom side of the unit)
0x5E-0x7D 32 bytes 0x55 Filler
0x7E-0x7F 2 bytes 0xFF,0xFF Unknown, probably the checksum value, but not used therefore filled 0xFFFF

On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision,


Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.

The eeprom can be read through the LDN RTC of the superio.