Nokia IP530 - Revision history

MBertens: /* TODO */

2011-01-23T16:01:48Z

‎TODO

2011-01-23T11:31:58Z

‎Flashing

2011-01-23T11:30:32Z

‎TODO

2011-01-23T11:28:30Z

‎Flashing

2011-01-23T11:25:04Z

‎Flashing

2011-01-23T11:23:04Z

‎System Setup

2011-01-23T11:16:06Z

‎Jumper JP900

2011-01-23T11:15:52Z

‎Jumper JP901

2011-01-23T11:15:01Z

‎Jumper JP900

2011-01-23T11:10:25Z

‎EEPROM behide the SuperIO

@@ Line 462: / Line 462: @@
 * Correctly setup the LM87 power management controller.
 * Support for board revisions other than A and B .
 ----

@@ Line 469: / Line 469: @@
 == Flashing ==
-Depending on the board revision, the board revision can be found on the inside of the machine, its on little stickers on the right-side of the board.
+Depending on the board revision, the board revision can be found on the bottom side of the IP530 or the inside of the machine, its on little stickers on the right-side of the board.
 There are currently to revisions (A/B) available doe the IP530.

@@ Line 462: / Line 462: @@
 * Correctly setup the LM87 power management controller.
+* Support for board revisions other than A and B .
 == Flashing ==

← Older revision		Revision as of 11:28, 23 January 2011
Line 458:		Line 458:

	----		----
		+
		+	== TODO ==
		+
		+	* Correctly setup the LM87 power management controller.
		+	*

	== Flashing ==		== Flashing ==

@@ Line 470: / Line 470: @@
 Both rom images are on the [[media:Linux-nokia-ip530-coreboot.tar.gz|Download 32Mb CF card image (7.9Mb)]]
-For flashing the images read the documentation of flashrom.
+For flashing the images read the documentation of flashrom. You need atleast Revision 1010 of flashrom.
 ----

@@ Line 150: / Line 150: @@
 * 4 SD-RAM sockets.
-Below the description is given for the connectors on the mainboard of the Nokia IP530, due missing documentation of the manufacturer.
+Below the description is given for the following;
 ----

@@ Line 251: / Line 251: @@
    #define REG_GP1x		0xF6
    #define JP900		        0x20
    sio_enter_config( 0x3F0 );
    val = (sio_read( 0x3F0, REG_GP6x ) & JP901);
    sio_leave_config( 0x3F0 );

← Older revision		Revision as of 11:15, 23 January 2011
Line 277:		Line 277:

	Pin 2 is pulled-up by resistor up VCC.		Pin 2 is pulled-up by resistor up VCC.
		+
		+	#define REG_GP6x 0xYY
		+	#define JP901 0x80
		+
		+	sio_enter_config( 0x3F0 );
		+	val = (sio_read( 0x3F0, REG_GP6x ) & JP901);
		+	sio_leave_config( 0x3F0 );
		+

	----		----

← Older revision		Revision as of 11:15, 23 January 2011
Line 249:		Line 249:

	Pin 2 is pulled-up by resistor up VCC.		Pin 2 is pulled-up by resistor up VCC.
		+
		+	#define REG_GP1x 0xF6
		+	#define REG_GP6x 0xYY
		+	#define JP900 0x20
		+	#define JP901 0x08
		+
		+	sio_enter_config( 0x3F0 );
		+	val = (sio_read( 0x3F0, REG_GP1x ) & JP900);
		+	val = (sio_read( 0x3F0, REG_GP6x ) & JP901);
		+	sio_leave_config( 0x3F0 );
		+

	----		----

@@ Line 355: / Line 355: @@
 |}
-On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware.
+On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.
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