Difference between revisions of "Nvidia CK804 Porting Notes"

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Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
 
Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
  
This table maps nibble values of these registers to APIC pin numbers.
+
These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).
 
+
These registers are in the LPC bridge configuration space.
+
  
 
'''Nibble values for routing registers:'''
 
'''Nibble values for routing registers:'''
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|- bgcolor="#6699ff"
 
|- bgcolor="#6699ff"
 
! align="left" | Nibble
 
! align="left" | Nibble
! align="left" | Pin
+
! align="left" | APIC Pin
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| 1h || 23
 
| 1h || 23
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| 3:0 || OHCI (device 2, function 0)
 
| 3:0 || OHCI (device 2, function 0)
 
|}
 
|}
 +
 +
One thing to note is that interrupts on both ports of the SATA controllers
 +
should be routed to the same pin so that the device behaves the way the
 +
driver expects them to.
 +
 +
{{Cc-by-2.5}}

Revision as of 18:28, 26 February 2008

This document does not (at present) attempt to be as complete as the AMD Geode Porting Guide, which has more general information.

Documentation

There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.

Audio and Network

If your CK804 has an AC97 codec, or ethernet PHY connected to it, you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.

Without CK804_USE_ACI = 1, the audio driver will time out when attempting to communicate with the codec.

Interrupt Routing Registers

Obtained via playing with these registers with setpci(8). Some information is still missing.

These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).

Nibble values for routing registers:

Nibble APIC Pin
1h 23
2h 22?
8h 20
Ch 12
Dh 21
Eh 14
Fh 15

7c.l:

Bits Description
27:24 SATA at device 7, second port
23:20 SATA at device 8, second port
15:0 PCI IRQ mappings?

80.l:

Bits Description
31:28 SATA at device 7, first port
27:24 SATA at device 8, first port
15:12 EHCI (device 2, function 1)

84.l:

Bits Description
11:8 NIC (device 10, function 0)
3:0 OHCI (device 2, function 0)

One thing to note is that interrupts on both ports of the SATA controllers should be routed to the same pin so that the device behaves the way the driver expects them to.

Creative Commons License
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This file is licensed under Creative Commons Attribution 2.5 License.
In short: you are free to distribute and modify the file as long as you attribute its author(s) or licensor(s).