Nvidia CK804 Porting Notes - Revision history

Uwe: /* Interrupt Routing Registers */

2010-02-03T14:11:58Z

‎Interrupt Routing Registers

Uwe: /* Interrupt Routing Registers */ Bugfix

2010-02-03T14:11:20Z

‎Interrupt Routing Registers: Bugfix

Uwe: /* Interrupt Routing Registers */ AC'97 info from edgecase on IRC

2010-02-02T17:45:01Z

‎Interrupt Routing Registers: AC'97 info from edgecase on IRC

Uwe at 16:51, 11 June 2009

2009-06-11T16:51:00Z

Hg87: /* Interrupt Routing Registers */

2009-06-11T09:28:08Z

‎Interrupt Routing Registers

Ruik: /* Interrupt Routing Registers */

2009-04-12T20:49:59Z

‎Interrupt Routing Registers

Jakllsch: add licencse tag, add a bit more flesh

2008-02-26T18:28:45Z

add licencse tag, add a bit more flesh

Uwe: Small cosmetic fixes.

2008-02-26T17:01:15Z

Small cosmetic fixes.

Jakllsch: some information collected about the CK804

2008-02-26T00:10:47Z

some information collected about the CK804

New page

This document does not (at present) attempt to be as complete as the [[AMD_Geode_Porting_Guide]], which has more general information.

== Documentation ==
There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.

== Audio and Network ==

If your CK804 has an AC97 codec, or ethernet PHY connected to it,
you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.

Without CK804_USE_ACI=1, the audio driver
will time out when attempting to communicate with the codec.

== Interrupt Routing Registers ==
Obtained via playing with these registers with setpci(8).
Some information is still missing.

This table maps nibble values of these registers to APIC pin numbers.

These registers are in the LPC bridge configuration space.

{| border="1" class="wikitable"
|+ nibble values for routing registers
! nibble !! pin
|-
| 1h || 23
|-
| 2h || 22?
|-
| 8h || 20
|-
| Ch || 12
|-
| Dh || 21
|-
| Eh || 14
|-
| Fh || 15
|}

{| border="1" class="wikitable"
|+ 7c.l
! bits !! description
|-
| 27:24 || SATA at device 7, second port
|-
| 23:20 || SATA at device 8, second port
|-
| 15:0 || PCI IRQ mappings?
|}

{| border="1" class="wikitable"
|+ 80.l
! bits !! description
|-
| 31:28 || SATA at device 7, first port
|-
| 27:24 || SATA at device 8, first port
|-
| 15:12 || EHCI (device 2, function 1)
|}

{| border="1" class="wikitable"
|+ 84.l
! bits !! description
|-
| 11:8 || NIC (device 10, function 0)
|-
| 3:0 || OHCI (device 2, function 0)
|}

← Older revision		Revision as of 14:11, 3 February 2010
Line 97:		Line 97:
	driver expects them to.		driver expects them to.

−	\|}

	{{Cc-by-2.5}}		{{Cc-by-2.5}}

@@ Line 86: / Line 86: @@
 ! align="left" | Description
 |- bgcolor="#eeeeee"
-| 29:16 || AC'97 audio (device 4, function 0)
+| 19:16 || AC'97 audio (device 4, function 0)
 |- bgcolor="#eeeeee"
 | 11:8 || NIC (device 10, function 0)

@@ Line 85: / Line 85: @@
 ! align="left" | Bits
 ! align="left" | Description
 |- bgcolor="#eeeeee"
 | 11:8 || NIC (device 10, function 0)
@@ Line 94: / Line 96: @@
 should be routed to the same pin so that the device behaves the way the
 driver expects them to.
 {{Cc-by-2.5}}

@@ Line 13: / Line 13: @@
 == Interrupt Routing Registers ==
-Please note that this is valid for [http://www.coreboot.org/Nvidia_MCP55_Porting_Notes MCP55] too.
+Please note that this is valid for [[Nvidia MCP55 Porting Notes|MCP55]] too.
 Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
@@ Line 96: / Line 96: @@
 {{Cc-by-2.5}}

@@ Line 13: / Line 13: @@
 == Interrupt Routing Registers ==
-Please note that this is valid for MPC55 too.
+Please note that this is valid for [http://www.coreboot.org/Nvidia_MCP55_Porting_Notes MCP55] too.
 Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
@@ Line 96: / Line 96: @@
 {{Cc-by-2.5}}

@@ Line 12: / Line 12: @@
 == Interrupt Routing Registers ==
 Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
@@ Line 26: / Line 28: @@
 | 1h || 23
 |- bgcolor="#dddddd"
-| 2h || 22?
+| 2h || 22
 |- bgcolor="#eeeeee"
 | 8h || 20
 |- bgcolor="#dddddd"

@@ Line 15: / Line 15: @@
 Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
-This table maps nibble values of these registers to APIC pin numbers.
+These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).
-−
 These registers are in the LPC bridge configuration space.
 '''Nibble values for routing registers:'''
@@ Line 24: / Line 22: @@
 |- bgcolor="#6699ff"
 ! align="left" | Nibble
-! align="left" | Pin
+! align="left" | APIC Pin
 |- bgcolor="#eeeeee"
 | 1h || 23
@@ Line 80: / Line 78: @@
 | 3:0 || OHCI (device 2, function 0)
 |}

@@ Line 1: / Line 1: @@
-This document does not (at present) attempt to be as complete as the [[AMD_Geode_Porting_Guide]], which has more general information.
+This document does not (at present) attempt to be as complete as the [[AMD Geode Porting Guide]], which has more general information.
 == Documentation ==
 There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.
 == Audio and Network ==
-If your CK804 has an AC97 codec, or ethernet PHY connected to it,
+If your CK804 has an AC97 codec, or ethernet PHY connected to it, you'll probably want to define '''CK804_USE_ACI''' and '''CK804_USE_NIC''' respectively.
 you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.
-Without CK804_USE_ACI=1, the audio driver
+Without '''CK804_USE_ACI = 1''', the audio driver will time out when attempting to communicate with the codec.
 will time out when attempting to communicate with the codec.
 == Interrupt Routing Registers ==
 Obtained via playing with these registers with setpci(8).
-Some information is still missing.
+Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.
 This table maps nibble values of these registers to APIC pin numbers.
@@ Line 20: / Line 19: @@
 These registers are in the LPC bridge configuration space.
-{| border="1" class="wikitable"
+'''Nibble values for routing registers:'''
-|+ nibble values for routing registers
-! nibble !! pin
+{| border="0" style="font-size: smaller"
-|-
+|- bgcolor="#6699ff"
 | 1h || 23
-|-
+|- bgcolor="#dddddd"
 | 2h || 22?
-|-
+|- bgcolor="#eeeeee"
 | 8h || 20
-|-
+|- bgcolor="#dddddd"
 | Ch || 12
-|-
+|- bgcolor="#eeeeee"
 | Dh || 21
-|-
+|- bgcolor="#dddddd"
 | Eh || 14
-|-
+|- bgcolor="#eeeeee"
 | Fh || 15
 |}
-{| border="1" class="wikitable"
+'''7c.l:'''
-|+ 7c.l
-! bits !! description
+{| border="0" style="font-size: smaller"
-|-
+|- bgcolor="#6699ff"
 | 27:24 || SATA at device 7, second port
-|-
+|- bgcolor="#dddddd"
 | 23:20 || SATA at device 8, second port
-|-
+|- bgcolor="#eeeeee"
 | 15:0 || PCI IRQ mappings?
 |}
-{| border="1" class="wikitable"
+'''80.l:'''
-|+ 80.l
-! bits !! description
+{| border="0" style="font-size: smaller"
-|-
+|- bgcolor="#6699ff"
 | 31:28 || SATA at device 7, first port
-|-
+|- bgcolor="#dddddd"
 | 27:24 || SATA at device 8, first port
-|-
+|- bgcolor="#eeeeee"
 | 15:12 || EHCI (device 2, function 1)
 |}
-{| border="1" class="wikitable"
+'''84.l:'''
-|+ 84.l
-! bits !! description
+{| border="0" style="font-size: smaller"
-|-
+|- bgcolor="#6699ff"
 | 11:8 || NIC (device 10, function 0)
-|-
+|- bgcolor="#dddddd"
 | 3:0 || OHCI (device 2, function 0)
 |}