Nvidia MCP55 Porting Notes - Revision history

Hg87: /* Example ACPI static IRQ routing */

2009-06-11T09:34:43Z

‎Example ACPI static IRQ routing

Hg87: /* Register */

2009-06-11T09:29:30Z

‎Register

Hg87: /* Interrupt Routing Registers */

2009-06-11T09:29:15Z

‎Interrupt Routing Registers

Hg87: /* Example Code for MPtable */

2009-06-11T09:26:11Z

‎Example Code for MPtable

Hg87 at 09:21, 11 June 2009

2009-06-11T09:21:04Z

Hg87: /* Interrupt Routing Registers */

2009-06-10T22:52:07Z

‎Interrupt Routing Registers

Hg87: Created page with '== Interrupt Routing Registers == '''Values for routing IRQ's:''' {| border="0" style="font-size: smaller" |- bgcolor="#6699ff" ! align="left" | Value ! align="left" | APIC Pin...'

2009-06-10T22:16:39Z

Created page with '== Interrupt Routing Registers == '''Values for routing IRQ's:''' {| border="0" style="font-size: smaller" |- bgcolor="#6699ff" ! align="left" | Value ! align="left" | APIC Pin...'

New page

== Interrupt Routing Registers ==

'''Values for routing IRQ's:'''

{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Value
! align="left" | APIC Pin (hex.)
! align="left" | APIC Pin (dec.)
|- bgcolor="#eeeeee"
|0x01 || 0x17 || 23
|- bgcolor="#dddddd"
|0x02 || 0x16 || 22
|- bgcolor="#eeeeee"
|0x03 || 0x10 || 16
|- bgcolor="#dddddd"
|0x04 || 0x11 || 17
|- bgcolor="#eeeeee"
|0x05 || 0x05 || 5
|- bgcolor="#dddddd"
|0x06 || 0x12 || 18
|- bgcolor="#eeeeee"
|0x07 || 0x7 || 7
|- bgcolor="#dddddd"
|0x08 || 0x14 || 20
|- bgcolor="#eeeeee"
|0x09 || 0x09 || 9
|- bgcolor="#dddddd"
|0x0A || 0x0a || 10
|- bgcolor="#eeeeee"
|0x0B || 0x0b || 11
|- bgcolor="#dddddd"
|0x0C || 0x13 || 19
|- bgcolor="#eeeeee"
|0x0D || 0x15 || 21
|- bgcolor="#dddddd"
|0x0E || 0x0E || 14
|- bgcolor="#eeeeee"
|0x0F || 0x0F || 15
|}

← Older revision		Revision as of 09:34, 11 June 2009
Line 315:		Line 315:
	})		})
	}		}
		+	== Thanks ... ==
		+	... go to Rudolf Marek who figured the informations out from the M57SLI's vendor dsdt.asl, and while he was doing this on a train his wallet was stolen.
		+	So please keep that informations careful, it's valuable. :)

@@ Line 41: / Line 41: @@
 |}
-== Register ==
+== Registers on M57SLI ==
 Each line is 4 bits.
 {| border="0" style="font-size: smaller"

← Older revision		Revision as of 09:29, 11 June 2009
Line 1:		Line 1:
	== Interrupt Routing Registers ==		== Interrupt Routing Registers ==
		+	Please note that this is valid for [http://www.coreboot.org/Nvidia_CK804_Porting_Notes CK804] too.

	'''Values for routing IRQ's:'''		'''Values for routing IRQ's:'''

← Older revision		Revision as of 09:26, 11 June 2009
Line 256:		Line 256:
	}		}
	}		}
		+
		+	== Example ACPI static IRQ routing ==
		+	For this the registers 0x7c-0x84 need to be set so that this static routing will work.
		+	/* PCI Routing Table */
		+	Name (_PRT, Package () {
		+	Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
		+	Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
		+	Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
		+	Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
		+	Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
		+	Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
		+	Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
		+	Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
		+	Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
		+	})
		+
		+	Device (PEBA) /* PCI-E Bridge A */
		+	{
		+	Name (_ADR, 0x000A0000)
		+	Name (_UID, 0x00)
		+	Name (_BBN, 0x02)
		+	Name (_Prt, Package () {
		+	Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
		+	Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
		+	Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
		+	Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
		+	})
		+	}
		+
		+	Bridge B-F needs also to get a routing setting, but not listed here.
		+	Device (PCID) /* PCI Device */
		+	{
		+	Name (_ADR, 0x00060000)
		+	Name (_UID, 0x00)
		+	Name (_BBN, 0x01)
		+	Name (_PRT, Package () {
		+	Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
		+	Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
		+	Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
		+	Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
		+	Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 },
		+	Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
		+	Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
		+	Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
		+	Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 },
		+	Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
		+	Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
		+	Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
		+	Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
		+	Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
		+	Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
		+	Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
		+	Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
		+	Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
		+	Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
		+	Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
		+	})
		+	}

← Older revision		Revision as of 09:21, 11 June 2009
Line 196:		Line 196:
	\|- bgcolor="#eeeeee"		\|- bgcolor="#eeeeee"
	\| A/INTD \|\| INTB \|\|		\| A/INTD \|\| INTB \|\|
		+	\|}
		+	== Example Code for MPtable ==
		+	This source is to do a propper mptable setup on M57SLI.
		+
		+	'''Setup the registers 0x7c-0x84 with the IRQ Values you want to have:'''
		+	/I/O APICs: APIC ID Version State Address/
		+	{
		+	device_t dev;
		+	struct resource *res;
		+	uint32_t dword;
		+	dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
		+	if (dev) {
		+	res = find_resource(dev, PCI_BASE_ADDRESS_1);
		+	if (res) {
		+	smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
		+	}
		+	dword = 0xc643c643;
		+	pci_write_config32(dev, 0x7c, dword);
		+	dword = 0x8da01009;
		+	pci_write_config32(dev, 0x80, dword);
		+	dword = 0x200018d2;
		+	pci_write_config32(dev, 0x84, dword);
		+	}
		+	}
		+	'''According to the Registers 0x7c-0x84 do the IRQ setup:'''
		+	#define PCI_INT(bus, dev, fn, pin) \
		+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL\|MP_IRQ_POLARITY_LOW,\
		+	bus_mcp55[bus], (((dev)<<2)\|(fn)), apicid_mcp55, (pin))
		+
		+	PCI_INT(0,sbdn+1,1, 10); /* SMBus */
		+	PCI_INT(0,sbdn+2,0, 22); /* USB */
		+	PCI_INT(0,sbdn+2,1, 23); /* USB */
		+	PCI_INT(0,sbdn+4,0, 21); /* IDE */
		+	PCI_INT(0,sbdn+5,0, 20); /* SATA */
		+	PCI_INT(0,sbdn+5,1, 21); /* SATA */
		+	PCI_INT(0,sbdn+5,2, 22); /* SATA */
		+	PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
		+	PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
		+	PCI_INT(1,0x0a,0, 18); /* Firewire */
		+
		+	/* The PCIe slots, each on its own bus */
		+	k = 1;
		+	for(i=0; i<=3; i++){
		+	for(j=7; j>=2; j--){
		+	if(k>3) k=0;
		+	PCI_INT(j,0,i, 16+k);
		+	k++;
		+	}
		+	k--;
		+	}
		+
		+	/* On bus 1: the PCI bus slots... */
		+	k=2;
		+	for(i=0; i<=3; i++){
		+	for(j=6; j<=10; j++){
		+	if(k>3) k=0;
		+	PCI_INT(1,j,i, 16+k);
		+	k++;
		+	}
		+	}

← Older revision		Revision as of 22:52, 10 June 2009
Line 39:		Line 39:
	\|0x0F \|\| 0x0F \|\| 15		\|0x0F \|\| 0x0F \|\| 15
	\|}		\|}
		+
		+	== Register ==
		+	Each line is 4 bits.
		+	{\| border="0" style="font-size: smaller"
		+	\|- bgcolor="#6699ff"
		+	! align="left" \| 0x7c
		+	! align="left" \| 0x80
		+	! align="left" \| 0x84
		+	\|- bgcolor="#eeeeee"
		+	\|INTA \|\| SCII \|\| INTG
		+	\|- bgcolor="#dddddd"
		+	\|INTB \|\| TCOI \|\| INTH
		+	\|- bgcolor="#eeeeee"
		+	\|INTC \|\| INTF \|\| INTJ
		+	\|- bgcolor="#dddddd"
		+	\|INTD \|\| INTQ \|\| INTK
		+	\|- bgcolor="#eeeeee"
		+	\|PCEA \|\| INTU \|\| INTL
		+	\|- bgcolor="#dddddd"
		+	\|PCEB \|\| INTS \|\| INTM
		+	\|- bgcolor="#eeeeee"
		+	\|PCEC \|\| IS0P \|\| INTN
		+	\|- bgcolor="#dddddd"
		+	\|PCED \|\| ITID \|\| ISA2
		+	\|}
		+
		+	== Wiring on M57SLI-S4 ==
		+	{\| border="0" style="font-size: smaller"
		+	\|- bgcolor="#6699ff"
		+	! align="left" \| Device/Pin
		+	! align="left" \| Routed to Pin
		+	! align="left" \| Description
		+	\|- bgcolor="#eeeeee"
		+	\| 1/INTA \|\| INTF \|\| ISALPC
		+	\|- bgcolor="#eeeeee"
		+	\| 1/INTB \|\| INTS \|\| SMBus
		+	\|- bgcolor="#dddddd"
		+	\| 2/INTA \|\| INTG \|\| Usb0
		+	\|- bgcolor="#dddddd"
		+	\| 2/INTB \|\| INTQ \|\| Usb1
		+	\|- bgcolor="#eeeeee"
		+	\| 4/INTA \|\| INTN \|\| IDE
		+	\|- bgcolor="#dddddd"
		+	\| 5/INTA \|\| ITID \|\| Sata1
		+	\|- bgcolor="#dddddd"
		+	\| 5/INTB \|\| IS0P \|\| Sata2
		+	\|- bgcolor="#dddddd"
		+	\| 5/INTC \|\| ISA2 \|\| Sata3
		+	\|- bgcolor="#eeeeee"
		+	\| 6/INTA \|\| INTU \|\| Bridge to Bus 1
		+	\|- bgcolor="#eeeeee"
		+	\| 6/INTB \|\| INTK \|\| Audio
		+	\|- bgcolor="#dddddd"
		+	\| 8/INTA \|\| INTJ \|\| Ethernet
		+	\|}
		+	Bridges to the PCI-E Slots & Devices
		+	{\| border="0" style="font-size: smaller"
		+	\|- bgcolor="#6699ff"
		+	! align="left" \| Device/Pin
		+	! align="left" \| Routed to Pin
		+	! align="left" \| Description
		+	\|- bgcolor="#eeeeee"
		+	\| F/INTA \|\| PCEB \|\| Bridge to Bus 7 - PCIE 16x (black)
		+	\|- bgcolor="#eeeeee"
		+	\| F/INTB \|\| PCEC \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| F/INTC \|\| PCED \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| F/INTD \|\| PCEA \|\|
		+	\|- bgcolor="#dddddd"
		+	\| E/INTA \|\| PCEC \|\| Bridge to Bus 6
		+	\|- bgcolor="#dddddd"
		+	\| E/INTB \|\| PCED \|\|
		+	\|- bgcolor="#dddddd"
		+	\| E/INTC \|\| PCEA \|\|
		+	\|- bgcolor="#dddddd"
		+	\| E/INTD \|\| PCEB \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| D/INTA \|\| PCED \|\| Bridge to Bus 5
		+	\|- bgcolor="#eeeeee"
		+	\| D/INTB \|\| PCEA \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| D/INTC \|\| PCEB \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| D/INTD \|\| PCEC \|\|
		+	\|- bgcolor="#dddddd"
		+	\| C/INTA \|\| PCEA \|\| Bridge to Bus 4
		+	\|- bgcolor="#dddddd"
		+	\| C/INTB \|\| PCEB \|\|
		+	\|- bgcolor="#dddddd"
		+	\| C/INTC \|\| PCEC \|\|
		+	\|- bgcolor="#dddddd"
		+	\| C/INTD \|\| PCED \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| B/INTA \|\| PCEB \|\| Bridge to Bus 3
		+	\|- bgcolor="#eeeeee"
		+	\| B/INTB \|\| PCEC \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| B/INTC \|\| PCED \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| B/INTD \|\| PCEA \|\|
		+	\|- bgcolor="#dddddd"
		+	\| A/INTA \|\| PCEC \|\| Bridge to Bus 2 - PCIE 16x (blue)
		+	\|- bgcolor="#dddddd"
		+	\| A/INTB \|\| PCED \|\|
		+	\|- bgcolor="#dddddd"
		+	\| A/INTC \|\| PCEA \|\|
		+	\|- bgcolor="#dddddd"
		+	\| A/INTD \|\| PCEB \|\|
		+	\|}
		+
		+	Bus 1 behind bridge from device 6
		+	{\| border="0" style="font-size: smaller"
		+	\|- bgcolor="#6699ff"
		+	! align="left" \| Device/Pin
		+	! align="left" \| Routed to Pin
		+	! align="left" \| Description
		+	\|- bgcolor="#eeeeee"
		+	\| 6/INTA \|\| INTC \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| 6/INTB \|\| INTD \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| 6/INTC \|\| INTA \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| 6/INTD \|\| INTB \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 7/INTA \|\| INTD \|\| PCI Slot 1
		+	\|- bgcolor="#dddddd"
		+	\| 7/INTB \|\| INTA \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 7/INTC \|\| INTB \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 7/INTD \|\| INTC \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| 8/INTA \|\| INTA \|\| PCI Slot 2
		+	\|- bgcolor="#eeeeee"
		+	\| 8/INTB \|\| INTB \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| 8/INTC \|\| INTC \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| 8/INTD \|\| INTD \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 9/INTA \|\| INTB \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 9/INTB \|\| INTC \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 9/INTC \|\| INTD \|\|
		+	\|- bgcolor="#dddddd"
		+	\| 9/INTD \|\| INTA \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| A/INTA \|\| INTC \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| A/INTB \|\| INTD \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| A/INTC \|\| INTA \|\|
		+	\|- bgcolor="#eeeeee"
		+	\| A/INTD \|\| INTB \|\|