Difference between revisions of "Project Ideas"

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The following are some ideas that have come up in the community. Some are more or less suitable for GSoC and prospective students' application should expand on some ideas and pair back others.
+
The following are ideas that have been proposed in the community. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases. But of course these are not the only things that could be done. Maybe you have a great idea that we just didn't think of yet. Please let us know!
  
== Linux Firmware Kit, BITS ==
 
  
There are various test suites for firmware aspects, esp. those that interacts with the operating systems. Unfortunately, some of these projects are dead, some seem to be forked and developed semi-publically, and having all that stuff in lots of different places is a big hassle.
+
Prospective  [[GSoC]] students' application should expand on the ideas and provide specific information in the application. If you have questions or comments, please please contact the coreboot [[Mailinglist|mailing list]] or visit our [[IRC]] channel <code>#coreboot</code> on [https://webchat.freenode.net irc.freenode.net]. Our [[GSoC#Mentors]] are here to help.
  
The goal of this project is to pick up the pieces, and create a single tool (most likely a bootable CD/USB drive image) that can be booted on vendor BIOS (for the Red Hat and Canonical developers that work on these) as well as coreboot (preferably seabios and FILO to improve testability - is an issue created/fixed by coreboot or seabios?). This can then be improved in various ways.
 
  
There's also intel-gpu-tools that might have some useful tests (at least for intel-boards): http://article.gmane.org/gmane.comp.video.dri.devel/63948
+
= coreboot Projects =
  
When applying for this task, please state in your proposal what you think might be worthy extensions to the existing tests.
+
== Infrastructure for accessing block devices  ==
  
Required knowledge for this task: Not so much coreboot/firmware level, but you should have some idea of the boot process of a Linux system (as these test suites are mostly Linux based). GSoC probably won't provide enough time to learn all that (Linux boot process, firmware interfaces such as ACPI) and still develop the tools in some useful way.
+
Create a simple interface to access block devices, such as NAND, SD cards, MMC, etc. This is needed on some lower-end ARM SoCs in order to load successive coreboot stages.
  
Further reading: https://wiki.ubuntu.com/Kernel/Reference/fwts http://biosbits.org/ http://linuxfirmwarekit.org/
+
'''Example:''' On Allwinner A10 SoCs, the hardware bootloader will load up to a 24KiB bootblock. That's barely sufficient to initialize DRAM and load the next stage from MMC, and is nowhere near enough to run all stages of coreboot. Coreboot will need to know how to read MMC.
  
== Infrastructure for automatic code checking ==
+
'''Links'''
We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:
+
* [[User_talk:MrNuke/Block_Device_API | Initial proposal]]
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
+
* [[Board:cubietech/cubieboard | Cubieboard page]]
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
+
* Use LLVM's static code checking facilities, report regressions.
+
* Work on code coverage support for coreboot code (dump data into ram, or via serial. Provide tools to fetch it). Analyse that data.
+
  
'''Links'''
+
'''Skill Level'''
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker]
+
* coreboot and ARM firmware: competent
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]
+
 
* Coverage: [http://ltp.sourceforge.net/test/coverage/lcov.php LCOV], [http://ggcov.sourceforge.net GGCOV]
+
'''Requirements'''
 +
* An ARM board with low-end SoC (for example, Cubieboard, with Allwinner A10)
  
 
'''Mentors'''
 
'''Mentors'''
* [[User:Stepan|Stefan Reinauer]]
+
<br/><br/>
  
 +
== coreboot mainboard test suite  ==
  
== coreboot test suite ==
+
Create a single tool (most likely a bootable CD/USB drive image) to be booted by coreboot (preferably seabios and FILO) that runs a suite of tests and gathers the results. The tool may also be run on vendor BIOS (for the Red Hat and Canonical developers that work on these) to verify is an issue created/fixed by coreboot or seabios?).  
Create a test suite to gather and report coreboot mainboard and payload settings. This project may leverage libpayload, coreinfo, memtest86, BITS, and other tools. The suite should gather result and report them at summary and detailed levels.  The goal is to help coreboot developers identify problems and to test coreboot features. This project should work closely with the testing rig and test reporting projects. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.
+
 
 +
When applying for this task, please state in your proposal what you think the base image/kernel would be used, the method of generating the image, what test you are targeting, and how results are gathered.  
  
 
'''Links'''
 
'''Links'''
* [http://biosbits.org/ BITS]
+
* https://wiki.ubuntu.com/Kernel/Reference/fwts
http://www.coreboot.org/Supported_Motherboards
+
* http://biosbits.org/  
 +
* https://help.ubuntu.com/community/LiveCDCustomization
 +
* https://os-autoinst.github.io/openQA/
 +
* [[Supported Motherboards]]
 +
 
 +
'''Skill Level'''
 +
* coreboot and firmware: novice
 +
* Linux scripting and application development: competent
 +
 
 +
'''Requirements'''
 +
* A coreboot mainboard 
  
 
'''Mentors'''
 
'''Mentors'''
* [[User:MJones|Marc Jones]]
+
<br/><br/>
  
== coreboot cheap testing rig ==
+
== coreboot mainboard test suite reporting  ==
The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:
+
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/Slides-LinuxBIOS-QA.pdf Quality Assurance Talk (Slides)]
+
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestIntegrationManual.pdf Test Integration Manual]
+
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/DevelopersManual.pdf Test Developers Manual]
+
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestSpecification.pdf Test Specification]
+
  
The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as X10, it's possible to drop the testing costs per board significantly.
+
We have an increasing interest in automated tests on real hardware, with reporting. Build something more scalable than the current system of git repository + [[Supported Motherboards]] (see the timeline below the table to see the problem unfold).
 +
There should be an authenticated reporting endpoint and some web frontend, that can run on a typical linux system (ultimately hosted on coreboot.org). It should be possible to filter for various criteria. Feature extraction from log files would be a good idea, too. It should also be possible to import the existing data set.
 +
Language/framework/library is pretty much your choice, but shouldn't be too exotic unless you can convince us that you intend to maintain it for the long term.
  
 
'''Links'''
 
'''Links'''
* http://qa.coresystems.de
+
* [[Supported Motherboards]]
* [[InSystemFlasher]] is a cheap DIY hardware prototype for building an automated testing rig for modern SPI-based boards. This could be used as a starting point.
+
 
 +
'''Skill Level'''
 +
* coreboot and firmware: novice
 +
* web development: competent
 +
* machine learning: certainly helps building a good project
 +
 
 +
'''Requirements'''
 +
* web development environment
  
 
'''Mentors'''
 
'''Mentors'''
* [[User:Stepan|Stefan Reinauer]]
+
<br/><br/>
  
 +
== coreboot on the open source Berkeley RISC V processor ==
 +
 +
We've got a preliminary port of coreboot to the Berkeley RISC V. Much work remains. There are three chips coming out end of 2015 and it would be great to be ready for them.
 +
 +
This work would be to make the build process bullet proof and then show that we can boot linux on RISCV under coreboot. If the student gets far enough we'll supply them with either an FGPA board or real hardware to take it even further. I've talked to the RISCV folks about this and we'll have really good support. They've been very helpful already.
 +
 +
'''Links'''
 +
* http://http://riscv.org/
 +
 +
'''Skill Level'''
 +
* coreboot and firmware: competent
 +
* linux: competent
 +
 +
'''Requirements'''
 +
* Need a system on which to build and run the RISCV toolchain, coreboot, and run simulators.
 +
 +
'''Mentors'''
 +
<br/>Ron Minnich<br/>
  
 
== coreboot mainboard test result reporting ==
 
== coreboot mainboard test result reporting ==
One of the biggest challenges in coreboot is support many systems in the same codebase. As systems age and coreboot continues to develop, the condition of mainboards becomes unknown. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot.  It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.
+
 
 +
One of the biggest challenges in coreboot is that it supports many systems in the same codebase. As coreboot develop and systems age, the condition of mainboards becomes unknown. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot.  It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.
 +
 
  
 
'''Links'''
 
'''Links'''
 
* http://openbenchmarking.org/
 
* http://openbenchmarking.org/
 
* http://www.coreboot.org/Supported_Motherboards
 
* http://www.coreboot.org/Supported_Motherboards
 +
* http://www.flashrom.org/Supported_hardware
 +
 +
'''Skill Level'''
 +
* coreboot and firmware: novice
 +
* wiki and web application development: competent
 +
 +
'''Requirements'''
 +
* LAMP setup
  
 
'''Mentors'''
 
'''Mentors'''
* [[User:Stepan|Stefan Reinauer]]
+
<br/><br/>
* [[User:MJones|Marc Jones]]
+
  
 +
== Infrastructure for automatic code checking ==
  
== coreboot ports for Family14 mainboards ==
+
coreboot has a build bot that builds various configurations of coreboot on every gerrit commit. We would like to extend the current build infrastructure with various code validation routines, for example:
Identify potential mainboards to port based on the recently released AMD Family 14 support. The goal would be to support publicly available plaftorms with a number of payloads and operating systems.
+
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
 +
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
 +
* Use LLVM's static code checking facilities, report regressions.
  
'''Mentors'''
+
'''Links'''
*[[User:Jason Wang|QingPei Wang]]
+
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker], http://klee.llvm.org/, http://oclint.org/
 +
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]
 +
* Semantic Tester: https://code.google.com/p/c-semantics/
 +
* [http://frama-c.com/ Frama-C]
 +
 
 +
'''Skill Level'''
 +
* coreboot and firmware: novice
 +
* compiler build and makefile knowledge: competent
 +
* Jenkins and test automation: novice
  
 +
'''Requirements'''
 +
* coreboot build environment 
  
== coreboot ACPI/S3/power managment ==
 
coreboot has support for ACPI tables and S3 support for some platforms, but it is very mainboard specific. Create a generic solution for ACPI table generation and S3 support.
 
  
 
'''Mentors'''
 
'''Mentors'''
*
+
<br/><br/>
  
 +
== coreboot ports for mainboards ==
  
==coreboot port to ARM SOC's with PCIe==
+
Identify potential mainboards to port based on the recently release cpu and chipset support. The goal would be to support publicly available platforms with a number of payloads and operating systems.
  
[http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm Xilinx Zynq-7030]
+
'''Skill Level'''
 +
* coreboot and firmware: novice to competent
  
[http://www.altera.com/devices/fpga/cyclone-v-fpgas/hard-processor-system/cyv-soc-hps.html  Altera Cyclone V ]
 
  
[http://www.st.com/internet/mcu/product/251211.jsp  ST spear1340]
+
'''Requirements'''
 +
* mainboard to port
 +
* flash recovery mechanism
  
 +
'''Mentors'''
 +
<br/><br/>
 +
 +
== coreboot ARM SoC's mainboard port==
  
[[ARM]] SOC's with PCIe are available. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.
+
While the links below are still relevant, there's now a coreboot port for ARM Exynos5. It was contributed by Google and the chip is used in a Chromebook. The port isn't quite done, but some of the heavy lifting is done, so ports to other SoCs should be easier.
 +
* [http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm Xilinx Zynq-7030]
 +
* [http://www.altera.com/devices/fpga/cyclone-v-fpgas/hard-processor-system/cyv-soc-hps.html  Altera Cyclone V ]
 +
* [http://www.st.com/internet/mcu/product/251211.jsp  ST spear1340]
  
Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family.
+
[[ARM]] SoC's with PCIe are available. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.
We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed.  
+
  
There was an ARM project started in 2011.  
+
Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family. We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed.  
  
 +
There was an ARM project started in 2011:
 
http://blogs.coreboot.org/blog/2011/05/11/gsoc2011-project-porting-coreboot-to-arm-architecture/
 
http://blogs.coreboot.org/blog/2011/05/11/gsoc2011-project-porting-coreboot-to-arm-architecture/
 +
 +
 +
'''Skill Level'''
 +
* coreboot and firmware: competent to expert
 +
* ARM architecture: novice to competent
 +
 +
'''Requirements'''
 +
* ARM mainboard
 +
* flash recovery mechanism
 +
 +
'''Mentors'''
 +
<br/><br/>
 +
 +
== Implement advanced coreboot features on existing mainboards ==
 +
 +
A lot of cool new coreboot features are only available on a small subset of the supported mainboards. Those features include:
 +
* global variables in romstage
 +
* relocatable ramstage
 +
* cbmem console
 +
* timestamps/performance data
 +
 +
This project would identify how to bring those features forward to more boards and complete porting of said mainboards.
 +
 +
'''Skill Level'''
 +
* coreboot and firmware: competent
 +
 +
'''Requirements'''
 +
* coreboot mainboard(s)
 +
 +
 +
'''Mentors'''
 +
<br/><br/>
 +
 +
== coreboot ACPI 4.0 and S3 power management  ==
 +
 +
coreboot has support for ACPI tables and S3 support for some platforms, but the implementations are mainboard specific and mostly based on ACPI 2.0. Create a generic solution for ACPI 4.0 table generation and S3 support across all mainboards.
 +
 +
'''Skill Level'''
 +
* coreboot and firmware: competent to expert
 +
* ACPI and power managment: novice to competent
 +
 +
'''Requirements'''
 +
* coreboot mainboard
 +
* flash recovery mechanism 
 +
 +
'''Mentors'''
 +
<br/><br/>
 +
 +
== Tianocore as payload ==
 +
 +
What SeaBIOS is for PC-BIOS interfaces, Tianocore is for UEFI. Tianocore is the reference implementation that most commercial UEFIs are built on. While coreboot favors other design goals than UEFI, it is really useful to support this standard that's being pushed on the market, just like SeaBIOS really helped coreboot by providing a BIOS "frontend".
 +
 +
There's already some code, but there's still much room for improvement. See the trello board linked below for the current status.
 +
 +
Possible tasks depend a lot on existing knowledge of the candidate. Few of the tasks are large enough to fill the entire GSoC time frame with one of them. Feel free to discuss with us on IRC what a suitable target could be for you.
 +
 +
'''Links'''
 +
* http://www.tianocore.org/
 +
* https://github.com/pgeorgi/edk2/tree/coreboot-pkg
 +
* https://trello.com/b/pEdlwYTb/tiano-payload (possible TODOs for the project)
 +
 +
 +
'''Skill Level'''
 +
* coreboot: competent to expert
 +
* UEFI/BIOS firmare: novice to competent
 +
 +
'''Requirements'''
 +
* coreboot mainboard
 +
  
 
'''Mentors'''
 
'''Mentors'''
* Bari Ari
+
* [[User:PatrickGeorgi]]
* [[User:Rminnich|Ron Minnich]]
+
<br/><br/>
* [[User:Jason Wang|QingPei Wang]]
+
  
 
== coreboot panic room ==
 
== coreboot panic room ==
  
Create a safe boot solution for coreboot to easily and cheaply recover the system in case of a panic().  
+
Create a safe boot solution for coreboot to easily and cheaply recover the system.  
  
Ron would like to base this solution around SerialICE. The basic idea is that the system always boots to SerialICE. There is a test in CMOS for 'last boot worked' and, if this is set, SerialICE finds a coreboot in cbfs and runs it. If 'last boot worked' is not set, or the user hits some magic keyboard sequence, SerialICE takes control.  
+
The basic idea is that the system flash image always contains executable for SerialICE. Instead of loading a coreboot romstage, firmware can boot to SerialICE based on some GPIO state, a keypress sequence or a logged failure on earlier boots. It is possible to integrate this into the coreboot build tree as a bootblock option, in the same spot as the fallback/normal switch and the simple loader.
  
SerialICE needs to be extended (not much) to make this work. Having this capability would make it possible for Ron to get some very hard ports working that are just not possible today. At the same time, there are lots of hardware boards to test this idea on, so it should be easy to get it working.
+
Having this capability opens up new possibilities:
  
It might be possible to integrate this into the coreboot build as a bootblock option (in the same spot as the fallback/normal switch and the simple loader).
+
During the lifetime of a mainboard, new requirements for ACPI hacks and CPU microcodes introduce the need to update boot firmware at customer site. The firmware shall have recovery path against any failures during the firmware update process. The most straight-forward solution is to do intelligent allocation of files in the CBFS such that files critical to the recovery are located on write-protected pages. The recovery path shall require only an USB mass-storage with compatible filesystem (ext2, fat32).
  
 +
The ability to dual-boot reduces the amount of tools required to reverse-engineer proprietary BIOS on ports for new mainboards. It is increasingly common that the flash chips are a) not socketed or b) physically hard to access (laptops). Even if chipset support existed already for a board, there are a lot of configuration registers for PCI-e links and GPIO signals that are difficult to get right by code disassembly only. With panic room implementation there would be no need to use external programmers or flashchip hot-swap method to alternate between SerialICE (for proprietary BIOS) and coreboot romstage boots.
 +
 +
SerialICE requires minimal hardware resources and does not require installed RAM or display hardware. It could be used as the first power-on environment after mainboard PCB verification and assembly to verify integrated components enumerate correctly. At the end of this first power-on, actual board firmware can be programmed without the need for external programmers and SOIC-8 clips, as the SPI controller embedded in the chipset can be used instead. As setting up EHCI debug port console is fairly simple across different chipsets, it can be used to print detailed diagnostics instead of POST codes on LPC bus.
 +
 +
 +
GSoC 2011 project [http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/] was able to:
 +
* Link flashrom with libpayload and flash from USB drive in a pre-OS environment.
 +
* Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.
 +
* Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.
 +
* Demonstrate booting alternative payload on keypress.
 +
 +
 +
There are remaining open tasks to:
 +
* Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.
 +
* Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.
 +
* Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.
 +
* After panic(), dump RAM contents before they are overwritten.
 +
 +
'''Skill Level'''
 +
* coreboot: competent to expert
 +
 +
'''Requirements'''
 +
* coreboot mainboard
 +
* flash recovery mechanism
  
There was a panic room project started in 2011
 
http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/
 
  
 
'''Mentors'''
 
'''Mentors'''
* [[User:Rminnich|Ron Minnich]]
+
<br/><br/>
  
 
== Board config infrastructure ==
 
== Board config infrastructure ==
  
 
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.
 
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.
 +
 +
We had some data structure work being done in coreboot v3 (based on DTS device tree source), but the approach back then didn't have the desired results. Still, if you want to tackle this task you can get some valuable information in past coreboot v3 discussions about what's feasible and what's infeasible.
  
 
'''Links'''
 
'''Links'''
* ?
+
* Check out the various devicetree.cb files in the src/ directory of the coreboot repository.
  
 
'''Mentors'''
 
'''Mentors'''
* ?
+
<br/><br/>
 
+
  
 
== Refactor AMD code ==
 
== Refactor AMD code ==
  
 
AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.
 
AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.
 +
 +
Alternatively, figure out a way how to build them in parallel and have coreboot select the right one on runtime.
  
 
'''Links'''
 
'''Links'''
* ?
+
* src/cpu/amd/ inside the coreboot source tree
 +
 
 +
'''Skill Level'''
 +
* coreboot: competent
 +
 
 +
'''Requirements'''
 +
* AMD coreboot mainboard and required silicon
 +
* flash recovery mechanism
  
 
'''Mentors'''
 
'''Mentors'''
* [[User:Stepan|Stefan Reinauer]]
+
<br/><br/>
 +
 
 +
== AMD VSA ==
 +
 
 +
Get the existing source code of AMD's VSA compiled and working with an open source toolchain. Integrate it into the current build system.
 +
 
 +
'''Links'''
 +
* [[OpenVSA]], [[AMD Geode Porting Guide]]
 +
 
 +
'''Skill Level'''
 +
* coreboot: competent
 +
 
 +
'''Requirements'''
 +
* coreboot mainboard that uses VSA
 +
* flash recovery mechanism
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== Native graphics init ==
 +
 
 +
Implement native initialization of the graphics hardware (probably AMD or Intel) so no Video BIOS is needed.
 +
 
 +
This should be added in a maintainable way, that means that updates in the Linux code, if that is used to build upon, can be easily integrated. The code needs to be structured in such a way, that – at least for a certain generation – other boards can use native graphics initialization.
 +
 
 +
A test and performance possibility, like a payload testing the correct initialization, needs to be added too.
 +
 
 +
This could be done in combination with making a board port.
 +
 
 +
'''Links'''
 +
* [https://docs.google.com/document/d/1g8FMob25VZYxbWri2iFB8YiSL8gwF9vKJH3HGxr0xQU/edit?pli=1# Fast User Interface – Death to Video BIOS]
 +
* [http://www.coreboot.org/pipermail/coreboot/2013-March/075512.html Small discussion about initialization of AMD graphics hardware]
 +
* [http://www.coreboot.org/pipermail/coreboot/2013-April/075655.html “Recruitment” message to mailing lists]
 +
 
 +
'''Skill Level'''
 +
* coreboot: competent
 +
* Linux graphics stack: competent
 +
 
 +
'''Requirements'''
 +
* coreboot mainboard
 +
* flash recovery mechanism
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== End user flash tool ==
 +
 
 +
A tool that takes a coreboot image without payload, and payload binaries (so the user can select which payload to use), combines them according to user wishes.
 +
It copies other required components (EC/ME firmware, VGABIOS) from the running system (ie. dump flash, extract data) and compares their hash against a white list (so we can vouch for their compatibility), then writes the result to flash, unlocking flash if necessary.
 +
 
 +
Ideally it's a portable graphical tool (assuming that flashrom is available for the target OS). It could use libflashrom, the bios_extract tools, and cbfstool in the background and provide the glue to make things work.
 +
 
 +
Additional info about the purpose of this tool:
 +
The challenge is to give users a simple way to create a '''working''' coreboot image with all the necessary components, including the components we can't provide as coreboot.org downloads for technical or legal reasons. This tool is intended as one-stop shop (one-click tool by default) to create working images without the user having to worry about which options are correct for his/her system. If any options are not applicable for a given system or if those options might result in a system not booting as expected, they should not be shown at all. It is explicitly not desired to just get a GUI exposing the complexity of the underlying tools (we have that, and it's called the command line).
 +
 
 +
Technical challenges for the design and implementation:
 +
To provide a working image for a given board, hardware peculiarities have to be handled automatically as much as possible. The tool has to
 +
* extract/dump some data/contents from the running system while coreboot is not yet installed, zero or more of the following
 +
** EDID data
 +
** PCI configuration (lspci -nn)
 +
** old flash chip contents
 +
** VGA BIOS in its mangled form dumped from memory (C segment)
 +
** VGA BIOS in its original form extracted from the flash chip contents
 +
** onboard network firmware/configuration/MACaddr, possibly extracted from the flash chip contents or other in-system data sources
 +
* possibly download and mangle BIOS update files from a vendor site
 +
** mostly in case the data mentioned above can't be extracted from the running system or in case newer data is available as download from the vendor
 +
* detect the exact variant of the hardware including any special handling needed (e.g. there are dozens of different Thinkpad T60/T60p variants all using the exact same coreboot code, but some need a VGA option ROM and some don't, the TFT panel definitions differ, etc.)
 +
* check whether the extracted data (mostly VGA BIOS etc.) matches the data that's known to work, e.g. by comparing hashes
 +
* check whether the extracted data has correct internal checksums and if not, check whether fixups are needed or wanted for this particular hardware (e.g. some C segment dumps from VGA option ROMs have broken checksums and their checksums should be fixed automatically by the tool, other VGA option ROMs should yield an error instead)
 +
* present the end user only with the choices that make sense for this specific piece of hardware
 +
* warn the user if hardware with this exact hardware has no complete (or none at all) rule set for working images
 +
* provide a way to import or store rules for doing all the stuff above for multiple boards or board variants
 +
 
 +
The complexity of that logic is very hard to handle if you're open-coding everything, and it might make sense to either invent a language for the rules and actions mentioned above or use JSON or XML wisely. Please note that the tool itself is not supposed to be written in JSON or XML, but rather a cross-platform capable language, preferably with a graphical (i.e. not text mode) user interface.
 +
 
 +
Providing example logic for one supported coreboot mainboard (not qemu!) based on wiki contents (e.g. for Thinkpad T60) would be a goal as well.
 +
 
 +
'''Skill Level'''
 +
* coreboot: novice
 +
* Systems programming, GUI programming: competent
 +
 
 +
'''Requirements'''
 +
* coreboot mainboard
 +
* flash recovery mechanism
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== proper fmap support in upstream ==
 +
 
 +
fmap, short for flash map is a partitioning format used on Chromebooks and other devices. Standardizing on it could simplify our CBFS handling a lot.
 +
 
 +
'''Skill Level'''
 +
* coreboot: novice
 +
* Systems programming
 +
 
 +
'''Requirements'''
 +
* coreboot mainboard
 +
* flash recovery mechanism
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== proper configuration support in upstream (devtree -> kconfig -> runtime values) ==
 +
'''Skill Level'''
 +
* coreboot: medium
 +
* C, build system.
 +
 
 +
'''Requirements'''
 +
* knowledge of what types of configuration exist in coreboot
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== provide subsystem level logging in printk, not just ‘SPEW’ ==
 +
'''Skill Level'''
 +
* coreboot: novice
 +
* Systems programming
 +
 
 +
'''Requirements'''
 +
* none
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== console via SMBus ==
 +
 
 +
Not all boards have an accessible serial port, but all boards with socketed RAM have a somehow accessible SMBus (used for reading the SPD-EEPROMs), which can be used very early in the boot process. As a device to receive the logs for example a beaglebone black or a cheap stm32 board with the i2c-star firmware can be used. The console via SMBus isn't that much slower than a serial console and ways faster than the speakermodem output.
 +
 
 +
'''Skill Level'''
 +
* coreboot: medium
 +
* soldering: medium
 +
 
 +
'''Requirements'''
 +
* none
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
== ARM64 qemu port ==
 +
 
 +
Develop mainboard/chipset support for a ARM64 qemu target. In order to work on ARM64 code one usually needs a ARM64 board. To reduce that barrier, work on a ARM64 qemu port.
 +
 
 +
'''Skill Level'''
 +
* coreboot: medium
 +
 
 +
'''Requirements'''
 +
* none
 +
 
 +
'''Mentors'''
 +
<br/>adurbin<br/>
 +
= flashrom Projects =
 +
 
 +
Flashrom is a project that is closely associated with coreboot and we work together where possible. They maintain a list of project ideas on their own website:
 +
 
 +
[http://www.flashrom.org/GSoC flashrom project ideas]
 +
 
 +
 
 +
'''Mentors'''
 +
<br/><br/>
 +
 
 +
= SerialICE Projects =
 +
 
 +
SerialICE is a project that started out as tool for coreboot development. They maintain a list of project ideas on their own website:
 +
 
 +
 
 +
* [http://serialice.com/GSoC SerialICE project ideas]

Latest revision as of 01:14, 20 April 2015

The following are ideas that have been proposed in the community. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases. But of course these are not the only things that could be done. Maybe you have a great idea that we just didn't think of yet. Please let us know!


Prospective GSoC students' application should expand on the ideas and provide specific information in the application. If you have questions or comments, please please contact the coreboot mailing list or visit our IRC channel #coreboot on irc.freenode.net. Our GSoC#Mentors are here to help.


coreboot Projects

Infrastructure for accessing block devices

Create a simple interface to access block devices, such as NAND, SD cards, MMC, etc. This is needed on some lower-end ARM SoCs in order to load successive coreboot stages.

Example: On Allwinner A10 SoCs, the hardware bootloader will load up to a 24KiB bootblock. That's barely sufficient to initialize DRAM and load the next stage from MMC, and is nowhere near enough to run all stages of coreboot. Coreboot will need to know how to read MMC.

Links

Skill Level

  • coreboot and ARM firmware: competent

Requirements

  • An ARM board with low-end SoC (for example, Cubieboard, with Allwinner A10)

Mentors

coreboot mainboard test suite

Create a single tool (most likely a bootable CD/USB drive image) to be booted by coreboot (preferably seabios and FILO) that runs a suite of tests and gathers the results. The tool may also be run on vendor BIOS (for the Red Hat and Canonical developers that work on these) to verify is an issue created/fixed by coreboot or seabios?).

When applying for this task, please state in your proposal what you think the base image/kernel would be used, the method of generating the image, what test you are targeting, and how results are gathered.

Links

Skill Level

  • coreboot and firmware: novice
  • Linux scripting and application development: competent

Requirements

  • A coreboot mainboard

Mentors

coreboot mainboard test suite reporting

We have an increasing interest in automated tests on real hardware, with reporting. Build something more scalable than the current system of git repository + Supported Motherboards (see the timeline below the table to see the problem unfold). There should be an authenticated reporting endpoint and some web frontend, that can run on a typical linux system (ultimately hosted on coreboot.org). It should be possible to filter for various criteria. Feature extraction from log files would be a good idea, too. It should also be possible to import the existing data set. Language/framework/library is pretty much your choice, but shouldn't be too exotic unless you can convince us that you intend to maintain it for the long term.

Links

Skill Level

  • coreboot and firmware: novice
  • web development: competent
  • machine learning: certainly helps building a good project

Requirements

  • web development environment

Mentors

coreboot on the open source Berkeley RISC V processor

We've got a preliminary port of coreboot to the Berkeley RISC V. Much work remains. There are three chips coming out end of 2015 and it would be great to be ready for them.

This work would be to make the build process bullet proof and then show that we can boot linux on RISCV under coreboot. If the student gets far enough we'll supply them with either an FGPA board or real hardware to take it even further. I've talked to the RISCV folks about this and we'll have really good support. They've been very helpful already.

Links

Skill Level

  • coreboot and firmware: competent
  • linux: competent

Requirements

  • Need a system on which to build and run the RISCV toolchain, coreboot, and run simulators.

Mentors
Ron Minnich

coreboot mainboard test result reporting

One of the biggest challenges in coreboot is that it supports many systems in the same codebase. As coreboot develop and systems age, the condition of mainboards becomes unknown. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.


Links

Skill Level

  • coreboot and firmware: novice
  • wiki and web application development: competent

Requirements

  • LAMP setup

Mentors

Infrastructure for automatic code checking

coreboot has a build bot that builds various configurations of coreboot on every gerrit commit. We would like to extend the current build infrastructure with various code validation routines, for example:

  • Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
  • Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
  • Use LLVM's static code checking facilities, report regressions.

Links

Skill Level

  • coreboot and firmware: novice
  • compiler build and makefile knowledge: competent
  • Jenkins and test automation: novice

Requirements

  • coreboot build environment


Mentors

coreboot ports for mainboards

Identify potential mainboards to port based on the recently release cpu and chipset support. The goal would be to support publicly available platforms with a number of payloads and operating systems.

Skill Level

  • coreboot and firmware: novice to competent


Requirements

  • mainboard to port
  • flash recovery mechanism

Mentors

coreboot ARM SoC's mainboard port

While the links below are still relevant, there's now a coreboot port for ARM Exynos5. It was contributed by Google and the chip is used in a Chromebook. The port isn't quite done, but some of the heavy lifting is done, so ports to other SoCs should be easier.

ARM SoC's with PCIe are available. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.

Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family. We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed.

There was an ARM project started in 2011: http://blogs.coreboot.org/blog/2011/05/11/gsoc2011-project-porting-coreboot-to-arm-architecture/


Skill Level

  • coreboot and firmware: competent to expert
  • ARM architecture: novice to competent

Requirements

  • ARM mainboard
  • flash recovery mechanism

Mentors

Implement advanced coreboot features on existing mainboards

A lot of cool new coreboot features are only available on a small subset of the supported mainboards. Those features include:

  • global variables in romstage
  • relocatable ramstage
  • cbmem console
  • timestamps/performance data

This project would identify how to bring those features forward to more boards and complete porting of said mainboards.

Skill Level

  • coreboot and firmware: competent

Requirements

  • coreboot mainboard(s)


Mentors

coreboot ACPI 4.0 and S3 power management

coreboot has support for ACPI tables and S3 support for some platforms, but the implementations are mainboard specific and mostly based on ACPI 2.0. Create a generic solution for ACPI 4.0 table generation and S3 support across all mainboards.

Skill Level

  • coreboot and firmware: competent to expert
  • ACPI and power managment: novice to competent

Requirements

  • coreboot mainboard
  • flash recovery mechanism

Mentors

Tianocore as payload

What SeaBIOS is for PC-BIOS interfaces, Tianocore is for UEFI. Tianocore is the reference implementation that most commercial UEFIs are built on. While coreboot favors other design goals than UEFI, it is really useful to support this standard that's being pushed on the market, just like SeaBIOS really helped coreboot by providing a BIOS "frontend".

There's already some code, but there's still much room for improvement. See the trello board linked below for the current status.

Possible tasks depend a lot on existing knowledge of the candidate. Few of the tasks are large enough to fill the entire GSoC time frame with one of them. Feel free to discuss with us on IRC what a suitable target could be for you.

Links


Skill Level

  • coreboot: competent to expert
  • UEFI/BIOS firmare: novice to competent

Requirements

  • coreboot mainboard


Mentors



coreboot panic room

Create a safe boot solution for coreboot to easily and cheaply recover the system.

The basic idea is that the system flash image always contains executable for SerialICE. Instead of loading a coreboot romstage, firmware can boot to SerialICE based on some GPIO state, a keypress sequence or a logged failure on earlier boots. It is possible to integrate this into the coreboot build tree as a bootblock option, in the same spot as the fallback/normal switch and the simple loader.

Having this capability opens up new possibilities:

During the lifetime of a mainboard, new requirements for ACPI hacks and CPU microcodes introduce the need to update boot firmware at customer site. The firmware shall have recovery path against any failures during the firmware update process. The most straight-forward solution is to do intelligent allocation of files in the CBFS such that files critical to the recovery are located on write-protected pages. The recovery path shall require only an USB mass-storage with compatible filesystem (ext2, fat32).

The ability to dual-boot reduces the amount of tools required to reverse-engineer proprietary BIOS on ports for new mainboards. It is increasingly common that the flash chips are a) not socketed or b) physically hard to access (laptops). Even if chipset support existed already for a board, there are a lot of configuration registers for PCI-e links and GPIO signals that are difficult to get right by code disassembly only. With panic room implementation there would be no need to use external programmers or flashchip hot-swap method to alternate between SerialICE (for proprietary BIOS) and coreboot romstage boots.

SerialICE requires minimal hardware resources and does not require installed RAM or display hardware. It could be used as the first power-on environment after mainboard PCB verification and assembly to verify integrated components enumerate correctly. At the end of this first power-on, actual board firmware can be programmed without the need for external programmers and SOIC-8 clips, as the SPI controller embedded in the chipset can be used instead. As setting up EHCI debug port console is fairly simple across different chipsets, it can be used to print detailed diagnostics instead of POST codes on LPC bus.


GSoC 2011 project [1] was able to:

  • Link flashrom with libpayload and flash from USB drive in a pre-OS environment.
  • Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.
  • Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.
  • Demonstrate booting alternative payload on keypress.


There are remaining open tasks to:

  • Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.
  • Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.
  • Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.
  • After panic(), dump RAM contents before they are overwritten.

Skill Level

  • coreboot: competent to expert

Requirements

  • coreboot mainboard
  • flash recovery mechanism


Mentors

Board config infrastructure

Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.

We had some data structure work being done in coreboot v3 (based on DTS device tree source), but the approach back then didn't have the desired results. Still, if you want to tackle this task you can get some valuable information in past coreboot v3 discussions about what's feasible and what's infeasible.

Links

  • Check out the various devicetree.cb files in the src/ directory of the coreboot repository.

Mentors

Refactor AMD code

AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.

Alternatively, figure out a way how to build them in parallel and have coreboot select the right one on runtime.

Links

  • src/cpu/amd/ inside the coreboot source tree

Skill Level

  • coreboot: competent

Requirements

  • AMD coreboot mainboard and required silicon
  • flash recovery mechanism

Mentors

AMD VSA

Get the existing source code of AMD's VSA compiled and working with an open source toolchain. Integrate it into the current build system.

Links

Skill Level

  • coreboot: competent

Requirements

  • coreboot mainboard that uses VSA
  • flash recovery mechanism

Mentors

Native graphics init

Implement native initialization of the graphics hardware (probably AMD or Intel) so no Video BIOS is needed.

This should be added in a maintainable way, that means that updates in the Linux code, if that is used to build upon, can be easily integrated. The code needs to be structured in such a way, that – at least for a certain generation – other boards can use native graphics initialization.

A test and performance possibility, like a payload testing the correct initialization, needs to be added too.

This could be done in combination with making a board port.

Links

Skill Level

  • coreboot: competent
  • Linux graphics stack: competent

Requirements

  • coreboot mainboard
  • flash recovery mechanism

Mentors

End user flash tool

A tool that takes a coreboot image without payload, and payload binaries (so the user can select which payload to use), combines them according to user wishes. It copies other required components (EC/ME firmware, VGABIOS) from the running system (ie. dump flash, extract data) and compares their hash against a white list (so we can vouch for their compatibility), then writes the result to flash, unlocking flash if necessary.

Ideally it's a portable graphical tool (assuming that flashrom is available for the target OS). It could use libflashrom, the bios_extract tools, and cbfstool in the background and provide the glue to make things work.

Additional info about the purpose of this tool: The challenge is to give users a simple way to create a working coreboot image with all the necessary components, including the components we can't provide as coreboot.org downloads for technical or legal reasons. This tool is intended as one-stop shop (one-click tool by default) to create working images without the user having to worry about which options are correct for his/her system. If any options are not applicable for a given system or if those options might result in a system not booting as expected, they should not be shown at all. It is explicitly not desired to just get a GUI exposing the complexity of the underlying tools (we have that, and it's called the command line).

Technical challenges for the design and implementation: To provide a working image for a given board, hardware peculiarities have to be handled automatically as much as possible. The tool has to

  • extract/dump some data/contents from the running system while coreboot is not yet installed, zero or more of the following
    • EDID data
    • PCI configuration (lspci -nn)
    • old flash chip contents
    • VGA BIOS in its mangled form dumped from memory (C segment)
    • VGA BIOS in its original form extracted from the flash chip contents
    • onboard network firmware/configuration/MACaddr, possibly extracted from the flash chip contents or other in-system data sources
  • possibly download and mangle BIOS update files from a vendor site
    • mostly in case the data mentioned above can't be extracted from the running system or in case newer data is available as download from the vendor
  • detect the exact variant of the hardware including any special handling needed (e.g. there are dozens of different Thinkpad T60/T60p variants all using the exact same coreboot code, but some need a VGA option ROM and some don't, the TFT panel definitions differ, etc.)
  • check whether the extracted data (mostly VGA BIOS etc.) matches the data that's known to work, e.g. by comparing hashes
  • check whether the extracted data has correct internal checksums and if not, check whether fixups are needed or wanted for this particular hardware (e.g. some C segment dumps from VGA option ROMs have broken checksums and their checksums should be fixed automatically by the tool, other VGA option ROMs should yield an error instead)
  • present the end user only with the choices that make sense for this specific piece of hardware
  • warn the user if hardware with this exact hardware has no complete (or none at all) rule set for working images
  • provide a way to import or store rules for doing all the stuff above for multiple boards or board variants

The complexity of that logic is very hard to handle if you're open-coding everything, and it might make sense to either invent a language for the rules and actions mentioned above or use JSON or XML wisely. Please note that the tool itself is not supposed to be written in JSON or XML, but rather a cross-platform capable language, preferably with a graphical (i.e. not text mode) user interface.

Providing example logic for one supported coreboot mainboard (not qemu!) based on wiki contents (e.g. for Thinkpad T60) would be a goal as well.

Skill Level

  • coreboot: novice
  • Systems programming, GUI programming: competent

Requirements

  • coreboot mainboard
  • flash recovery mechanism

Mentors

proper fmap support in upstream

fmap, short for flash map is a partitioning format used on Chromebooks and other devices. Standardizing on it could simplify our CBFS handling a lot.

Skill Level

  • coreboot: novice
  • Systems programming

Requirements

  • coreboot mainboard
  • flash recovery mechanism

Mentors

proper configuration support in upstream (devtree -> kconfig -> runtime values)

Skill Level

  • coreboot: medium
  • C, build system.

Requirements

  • knowledge of what types of configuration exist in coreboot

Mentors

provide subsystem level logging in printk, not just ‘SPEW’

Skill Level

  • coreboot: novice
  • Systems programming

Requirements

  • none

Mentors

console via SMBus

Not all boards have an accessible serial port, but all boards with socketed RAM have a somehow accessible SMBus (used for reading the SPD-EEPROMs), which can be used very early in the boot process. As a device to receive the logs for example a beaglebone black or a cheap stm32 board with the i2c-star firmware can be used. The console via SMBus isn't that much slower than a serial console and ways faster than the speakermodem output.

Skill Level

  • coreboot: medium
  • soldering: medium

Requirements

  • none

Mentors

ARM64 qemu port

Develop mainboard/chipset support for a ARM64 qemu target. In order to work on ARM64 code one usually needs a ARM64 board. To reduce that barrier, work on a ARM64 qemu port.

Skill Level

  • coreboot: medium

Requirements

  • none

Mentors
adurbin

flashrom Projects

Flashrom is a project that is closely associated with coreboot and we work together where possible. They maintain a list of project ideas on their own website:

flashrom project ideas


Mentors

SerialICE Projects

SerialICE is a project that started out as tool for coreboot development. They maintain a list of project ideas on their own website: