coreboot - Recent changes [en]

User:GNUtoo

2013-05-23T14:10:26Z

‎How to get rid of the vbios of the x60 [New Version]:

File:I915 reg.h.gz

2013-05-23T13:40:56Z

GNUtoo uploaded "File:I915 reg.h.gz"

User:GNUtoo

2013-05-23T13:38:46Z

‎How to get rid of the vbios of the x60 [New Version]:

File:Dennis.tar.gz

2013-05-23T13:37:00Z

GNUtoo uploaded "File:Dennis.tar.gz" Ron Minnich's final/ directory in i915tool

User:GNUtoo

2013-05-23T13:09:43Z

‎How to get rid of the vbios of the x60 [New Version]:

Git

2013-05-23T12:19:59Z

‎Pushing to Topics:

Binary situation

2013-05-22T16:06:34Z

Binary situation

2013-05-22T16:04:18Z

Created page with "While we aim for a 100% free boot process, recent developments (and general unwillingness by some hardware companies to provide specifications) make it hard to achieve. = Int..."

New page

While we aim for a 100% free boot process, recent developments (and general unwillingness by some hardware companies to provide specifications) make it hard to achieve.

= Intel =
On Intel based chipsets (since Intel 5 Series) the following binary components persist:
* Management Engine firmware: The management engine is a separate CPU that does various management tasks and needs its own firmware. This firmware exists in a 1.5MB and a 5MB version, where the latter provides the "Intel AMT" functions (ie. remote access, "anti-theft", ...). Probably signed with an Intel key. It's unlikely that this is ever replaced by something open source.
* VGABIOS: Runs on the CPU. Unless you can live with staying in the dark until Linux takes over, you'll need this. Luckily there's work in progress to replace it with open source code. Until then you can at least contain it by emulation (see YABEL).
* CPU microcode: Intel provides this as redistributable binary, the format is partially reverse engineered, it's covered by a 2048b RSA signature. Unlikely that it can be replaced. Depending on the CPU (incl. its stepping) it might be possible to get by without it.
* Gigabit Ethernet Firmware: If your board uses the on-chipset GbE, it requires a small binary (8KB) with unknown content.
* Memory Reference Code: (Sandybridge and newer). This is code that runs on the CPU and initializes RAM. Can be reverse engineered with enough persistence, but not done so far.

= recent AMD =
* IMC: An embedded controller of sorts in the southbridge. 8051-based, can probably be reimplemented (partially done, but unpublished)
* XHCI: Some binary with unknown content (maybe just a dataset of trace lengths, maybe firmware). If not present, USB3 (and related USB ports) won't work.
* NIC Firmware: If your board uses the on-chip broadcom NIC, you need this firmware. Few boards do (thanks to Broadcom seemingly having some "interesting" terms and conditions on its use)
* CPU microcode: AMD provides this as redistributable binary, the format is partially reverse engineered, it's covered by a 2048b RSA signature. Unlikely that it can be replaced. Depending on the CPU (incl. its stepping) it might be possible to get by without it.
* SMU: Another embedded controller, this time in the northbridge.

In theory it might be possible to successfully boot an AMD board without all these binaries, with potentially reduced capabilities (no NIC, USB3, fan control)

ASUS F2A85-M

2013-05-22T13:19:52Z

File:IMG 20130522 084444.jpg

2013-05-22T13:10:35Z

Ward uploaded "File:IMG 20130522 084444.jpg" Asus F2A85-M rom chip

User:GNUtoo

2013-05-21T15:32:07Z

‎How to get rid of the vbios of the x60 [New Version]:

Supported Motherboards

2013-05-20T22:03:48Z

Supported Chipsets and Devices

2013-05-18T18:02:57Z

@@ Line 60: / Line 60: @@
 == How to get rid of the vbios of the x60 [New Version] ==
 Apply the [http://review.coreboot.org/#/c/3277/ coreboot patches], and adapt them for your mainboard
@@ Line 77: / Line 79: @@
 Build and flash coreboot.
-git clone [https://code.google.com/p/i915tool/ i915tool].
+git clone [https://code.google.com/r/gnutoo-i915tool-x60/source/list my fork of the i915tool] until the code is merged in the [https://code.google.com/p/i915tool/ official i915tool].
 Get the [http://www.coreboot.org/images/4/42/Dennis.tar.gz tarball] that contains the generated code, extract it.
-Also get the i915_regs.h header and put it in final/
+Also get the [http://www.coreboot.org/images/3/39/I915_reg.h.gz i915_regs.h.gz] file, decompress it and put it in final/
 Then go into i915tool and apply some patches for the x60 or redo them for your mainboard.
@@ Line 116: / Line 118: @@
   io_i915_write32(0xcffbe001,i);
+  }

@@ Line 79: / Line 79: @@
 git clone [https://code.google.com/p/i915tool/ i915tool].
-Get the tarball that contains the generated code, extract it.
+Get the [http://www.coreboot.org/images/4/42/Dennis.tar.gz tarball] that contains the generated code, extract it.
 Also get the i915_regs.h header and put it in final/

@@ Line 60: / Line 60: @@
 == How to get rid of the vbios of the x60 [New Version] ==
-Apply the coreboot patches, or re-do them for your mainboard
+Apply the [http://review.coreboot.org/#/c/3277/ coreboot patches], and adapt them for your mainboard
 Then configure coreboot with:

@@ Line 117: / Line 117: @@
 == Pushing Drafts ==
   git push origin HEAD:refs/drafts/master
 == Evolving patches ==

← Older revision		Revision as of 13:19, 22 May 2013
Line 134:		Line 134:

	}}		}}
		+
		+	== Hardware info ==
		+
		+	This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package:
		+
		+	{\|
		+	\|\| [[Image:IMG_20130522_084444.jpg\|thumb\|Winbond 25Q64F]]
		+	\|}
		+
		+	The chip manual is available [http://www.nexflash.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64FV.htm here]

@@ Line 3: / Line 3: @@
 = Intel =
 On Intel based chipsets (since Intel 5 Series) the following binary components persist:
- * Management Engine firmware: The management engine is a separate CPU that does various management tasks and needs its own firmware. This firmware exists in a 1.5MB and a 5MB version, where the latter provides the "Intel AMT" functions (ie. remote access, "anti-theft", ...). Probably signed with an Intel key. It's unlikely that this is ever replaced by something open source.
+* Management Engine firmware: The management engine is a separate CPU that does various management tasks and needs its own firmware. This firmware exists in a 1.5MB and a 5MB version, where the latter provides the "Intel AMT" functions (ie. remote access, "anti-theft", ...). Probably signed with an Intel key. It's unlikely that this is ever replaced by something open source.
- * VGABIOS: Runs on the CPU. Unless you can live with staying in the dark until Linux takes over, you'll need this. Luckily there's work in progress to replace it with open source code. Until then you can at least contain it by emulation (see YABEL).
+* VGABIOS: Runs on the CPU. Unless you can live with staying in the dark until Linux takes over, you'll need this. Luckily there's work in progress to replace it with open source code. Until then you can at least contain it by emulation (see YABEL).
- * CPU microcode: Intel provides this as redistributable binary, the format is partially reverse engineered, it's covered by a 2048b RSA signature. Unlikely that it can be replaced. Depending on the CPU (incl. its stepping) it might be possible to get by without it.
+* CPU microcode: Intel provides this as redistributable binary, the format is partially reverse engineered, it's covered by a 2048b RSA signature. Unlikely that it can be replaced. Depending on the CPU (incl. its stepping) it might be possible to get by without it.
- * Gigabit Ethernet Firmware: If your board uses the on-chipset GbE, it requires a small binary (8KB) with unknown content.
+* Gigabit Ethernet Firmware: If your board uses the on-chipset GbE, it requires a small binary (8KB) with unknown content.
- * Memory Reference Code: (Sandybridge and newer). This is code that runs on the CPU and initializes RAM. Can be reverse engineered with enough persistence, but not done so far.
+* Memory Reference Code: (Sandybridge and newer). This is code that runs on the CPU and initializes RAM. Can be reverse engineered with enough persistence, but not done so far.
 = recent AMD =
- * IMC: An embedded controller of sorts in the southbridge. 8051-based, can probably be reimplemented (partially done, but unpublished)
+* IMC: An embedded controller of sorts in the southbridge. 8051-based, can probably be reimplemented (partially done, but unpublished)
- * XHCI: Some binary with unknown content (maybe just a dataset of trace lengths, maybe firmware). If not present, USB3 (and related USB ports) won't work.
+* XHCI: Some binary with unknown content (maybe just a dataset of trace lengths, maybe firmware). If not present, USB3 (and related USB ports) won't work.
- * NIC Firmware: If your board uses the on-chip broadcom NIC, you need this firmware. Few boards do (thanks to Broadcom seemingly having some "interesting" terms and conditions on its use)
+* NIC Firmware: If your board uses the on-chip broadcom NIC, you need this firmware. Luckily few boards do (thanks to Broadcom seemingly having some "interesting" terms and conditions on its use)
- * CPU microcode: AMD provides this as redistributable binary, the format is partially reverse engineered, it's covered by a 2048b RSA signature. Unlikely that it can be replaced. Depending on the CPU (incl. its stepping) it might be possible to get by without it.
+* CPU microcode: AMD provides this as redistributable binary, the format is partially reverse engineered, it's covered by a 2048b RSA signature. Unlikely that it can be replaced. Depending on the CPU (incl. its stepping) it might be possible to get by without it.
- * SMU: Another embedded controller, this time in the northbridge.
+* SMU: Another embedded controller, this time in the northbridge.
 In theory it might be possible to successfully boot an AMD board without all these binaries, with potentially reduced capabilities (no NIC, USB3, fan control)

← Older revision		Revision as of 15:32, 21 May 2013
(13 intermediate revisions by one user not shown)
Line 58:		Line 58:
	* compile prettyregs.c		* compile prettyregs.c
	* run prettyregs		* run prettyregs
		+
		+	== How to get rid of the vbios of the x60 [New Version] ==
		+	Apply the coreboot patches, or re-do them for your mainboard
		+
		+	Then configure coreboot with:
		+	[*] Output verbose x86emu debug messages
		+	[ ] Trace JMP/RETF
		+	[ ] Trace all opcodes
		+	[ ] Log Plug&Play accesses
		+	[ ] Log Disk I/O
		+	[ ] Log PMM
		+	[ ] Debug VESA BIOS Extensions
		+	[ ] Redirect INT10 output to console
		+	[ ] Log intXX calls
		+	[ ] Log special memory accesses
		+	[ ] Log all memory accesses
		+	[*] Log IO accesses
		+	Build and flash coreboot.
		+
		+	git clone [https://code.google.com/p/i915tool/ i915tool].
		+
		+	Get the tarball that contains the generated code, extract it.
		+
		+	Also get the i915_regs.h header and put it in final/
		+
		+	Then go into i915tool and apply some patches for the x60 or redo them for your mainboard.
		+
		+	Run make:
		+	$ cd i915tool
		+	$ make
		+	Then go into the x60 directory(or the directory of your device):
		+	$ cd x60
		+	use picocom -b 115200 /dev/ttyUSB0 or stty to set the bauds of the Serial port.
		+	Then get logs:
		+	$ cat /dev/ttyUSB0 \| tee coreboot.log
		+	Then remove the binary symbols, dos2unix will help identifying where they are:
		+	$ dos2unix coreboot.log
		+	dos2unix: Binary symbol found at line 136332
		+	dos2unix: Skipping binary file coreboot.log
		+	Then do:
		+	$ dos2unix coreboot.log
		+	Then remove the lines before and after the log, the log looks like that:
		+	[0047229e]c000:51cb outl(0x80001014, 0x0cf8)
		+	[0047325f]c000:51d4 inw(0x0cfc) = 0x50a1
		+	Then run make and fix the errors:
		+	$ make
		+	Then copy to coreboot as it says.
		+	Then if necessary try to compact the source code a bit, here for me I have a really long list of:
		+	io_i915_write32(0xcffbe001,0x8001);
		+	io_i915_write32(0xcffbe001,0x8005);
		+	io_i915_write32(0xcffbe001,0x8009);
		+	io_i915_write32(0xcffbe001,0x800d);
		+	io_i915_write32(0xcffbe001,0x8011);
		+	That can be replaced with:
		+	int i = 0;
		+	for (i=0x8001;i<0x3fffa;i+=4){
		+	io_i915_write32(0xcffbe001,i);
		+	}

@@ Line 1,667: / Line 1,667: @@
 | X201
 | style="background:yellow" | [[Lenovo x201|Under review...]]
-| Intel&reg;&nbsp;Sandybridge
+| Intel&reg;&nbsp;mobile 5
 | Intel&reg;&nbsp;BD82X6X and Ricoh&reg;&nbsp; RL5C476
 | NSC&reg;PC87382 and NSC&reg;&nbsp; PC87392

@@ Line 21: / Line 21: @@
 |- bgcolor="#eeeeee" valign="top"
 | AMD
-| Fam14h - G-Series
+| Fam15h (Trinity) - R-Series
 | style="background:lime" | OK
 |- bgcolor="#eeeeee" valign="top"
 | AMD
-| Fam12h - Llano
+| Fam12h (Llano)
 | style="background:lime" | OK
 |- bgcolor="#eeeeee" valign="top"
@@ Line 205: / Line 215: @@
 |- bgcolor="#eeeeee" valign="top"
 | AMD
-| SB800
+| SB800 / Hudson 1
 | style="background: lime " | OK
-|- bgcolor="#dddddd" valign="top"
+|- bgcolor="#eeeeee" valign="top"
 | Broadcom
 | BCM21000
@@ Line 620: / Line 634: @@
 <sup>19</sup> Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet.<br />
 <sup>20</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br />
 </small>
 __FORCETOC__