coreboot - Changes related to "Supported Motherboards" [en]

Samsung XE550C22-H02US

2013-06-19T14:43:35Z

‎Status

Mailinglist

2013-06-15T18:59:01Z

Added coreboot-gerrit mailing list

Supported Motherboards

2013-06-14T12:53:33Z

‎Motherboards supported in coreboot v4: CFR-AF's URL changed for some reason

Lenovo x60x

2013-06-13T01:10:35Z

‎Flashing on the laptop instructions.

Samsung XE550C22-H02US

2013-06-13T00:32:22Z

Google Chromebook Pixel

2013-06-12T23:23:40Z

VIA EPIA-M850

2013-06-12T17:07:28Z

@@ Line 94: / Line 94: @@
 |WakeOnMouse_status = Untested
-|Flashrom_status = WIP
+|Flashrom_status = OK
-|Flashrom_comments = External programmer required.
+|Flashrom_comments = needs assembly of a jumper to the mainboard
 }}

@@ Line 8: / Line 8: @@
 If you want to get brief news about coreboot's progress, please subscribe to the [http://www.coreboot.org/mailman/listinfo/coreboot-announce coreboot-announce mailing list]. This list is moderated and will only get very few posts per month.
 '''flashrom'''
@@ Line 25: / Line 29: @@
 * http://www.coreboot.org/pipermail/coreboot-announce/
 '''flashrom'''

@@ Line 1,735: / Line 1,735: @@
 |- bgcolor="#eeeeee"
 | ADLINK
-| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131 CoreModule2-GF]
+| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1283 CoreModule2-GF]
 | style="background:lime" | OK
 | colspan="9" | see LiPPERT FrontRunner-AF below
@@ Line 1,981: / Line 1,981: @@
 |- bgcolor="#eeeeee"
 | LiPPERT
-| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131 FrontRunner-AF]
+| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1283 FrontRunner-AF]
 | style="background:lime" | OK
 | AMD&nbsp;Fam14h

@@ Line 4: / Line 4: @@
 These Lenovo laptops have a register that must be flipped before coreboot can be flashed.
-For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream.  Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection).
+For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream.  Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.
 You will need: the flashrom source, a small patch for it, and [http://git.stuge.se/?p=bucts.git the bucts utility].

← Older revision		Revision as of 00:32, 13 June 2013
Line 1:		Line 1:
		+	see [[Chromebooks\|Chromebooks]]
	= aka Samsung Lumpy aka chromebook =		= aka Samsung Lumpy aka chromebook =

← Older revision		Revision as of 23:23, 12 June 2013
(2 intermediate revisions by one user not shown)
Line 1:		Line 1:
		+	see [[Chromebooks\|Chromebooks]] in the wiki
	== Proprietary parts ==		== Proprietary parts ==
	* MRC.bin: memory initialization, mandatory for now (although the code for the Lenovo X201 has replaced it for the X201)		* MRC.bin: memory initialization, mandatory for now (although the code for the Lenovo X201 has replaced it for the X201)

@@ Line 1: / Line 1: @@
 Placeholder for EPIA-M850 board. Content coming soon. Please yell at mrnuke on #coreboot if nothing changes soon. He's from Texas, he won't mind.
@@ Line 135: / Line 137: @@
   $ make xconfig
-Mainboard -> Select VIA->EPIA-M850
+* Mainboard -> Select VIA->EPIA-M850
-VGA BIOS -> Select "Add a VGA BIOS image" + "VGA BIOS path and filename:" path/to/vgabios.bin
+* VGA BIOS -> Select "Add a VGA BIOS image" + "VGA BIOS path and filename:" path/to/vgabios.bin
-Console -> Make sure serial console is on and turned all the way up to SPEW (in case things go south)
+* Console -> Make sure serial console is on and turned all the way up to SPEW (in case things go south)
-System tables -> Make sure at least a PIRQ table is generated. Generating other tables does not hurt us, so they can remain enabled.
+* System tables -> Make sure at least a PIRQ table is generated. Generating other tables does not hurt us, so they can remain enabled.
-Debugging -> Output verbose RAM init debug messages.
+* Debugging -> Output verbose RAM init debug messages.
-For the first try, it is higly recommended to use SeaBIOS as a payload.
+* For the first try, it is higly recommended to use SeaBIOS as a payload.
-Save and exit
+* Save and exit
 ===== Configure linux =====
@@ Line 157: / Line 159: @@
 If you encounter any errors, or even if you succeed and are happy, let us know.