Talk:GIGABYTE GA-M57SLI-S4 - Revision history

Quux: legacy BIOS

2010-12-02T07:03:19Z

legacy BIOS

2010-12-02T06:26:16Z

BIOS reengineer

2008-11-16T14:59:49Z

2007-05-26T20:30:44Z

thf does not work with m57sli lpc

2007-05-09T23:38:25Z

2007-05-09T23:33:59Z

2 Mbit ? successreport thf

2007-05-07T17:32:26Z

thf

2007-04-28T12:24:52Z

swap ce and wp poss. ?

New page

swap #CE and #WP and thus route #CE through the #WP jumper with 8 pin SPI possible ?
--[[User:Quux|da Great QUUX]] 14:24, 28 April 2007 (CEST)

← Older revision		Revision as of 07:03, 2 December 2010
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−	[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun] on '''AWARD''' BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI.	+	[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun] on '''AWARD''' ('legacy') BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI.

← Older revision		Revision as of 06:26, 2 December 2010
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	''2 MByte:'' the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check.		''2 MByte:'' the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check.
	----		----
		+
		+	[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun] on '''AWARD''' BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI.

@@ Line 11: / Line 11: @@
 '''badly in need:'''
-* report on usability of top hat flash on M57SLI
 * is it practical to upgrade the secondary pad with an 2 MBit flash part ?
 ''2 MByte:'' the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check.
 ----

@@ Line 9: / Line 9: @@
 ----
-'''
+'''badly in need:'''
 badly in need:'''
 * report on usability of top hat flash on M57SLI
 * is it practical to upgrade the secondary pad with an 2 MBit flash part ?
 ----

← Older revision		Revision as of 23:33, 9 May 2007
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	on GA M57SLI, is FWH mode used ? is it necessary to use different ID on ID-pins ?		on GA M57SLI, is FWH mode used ? is it necessary to use different ID on ID-pins ?
		+
		+	----
		+	'''
		+	badly in need:'''
		+
		+	* report on usability of top hat flash on M57SLI
		+	* is it practical to upgrade the secondary pad with an 2 MBit flash part ?

	----		----

← Older revision		Revision as of 17:32, 7 May 2007
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	swap #CE and #WP and thus route #CE through the #WP jumper with 8 pin SPI possible ?		swap #CE and #WP and thus route #CE through the #WP jumper with 8 pin SPI possible ?
	--[[User:Quux\|da Great QUUX]] 14:24, 28 April 2007 (CEST)		--[[User:Quux\|da Great QUUX]] 14:24, 28 April 2007 (CEST)
		+
		+
		+	----
		+	Alternatively, you might flip a standard plcc-32 socket over the mainboard-chip. then wire a secondary plcc-32 socket to it wired 1:1 - except you connect /reset and /oe on the replacment chip, while you route the /oe from the mainboard to an NC pin on the secondary chip. Take off (hot unplug) the socket after successful boot-up to reflash the original chip. (so called "top hat flash" method, use at own risk, no successful report on GA M57 yet)
		+
		+	on GA M57SLI, is FWH mode used ? is it necessary to use different ID on ID-pins ?
		+
		+	----