[coreboot-gerrit] Patch merged into coreboot/master: d6d6db3 lynxpoint: fix enable_pm1() function

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d6d6db3717d09f2b6a4590eec6016ca7d417c2f9
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Mar 27 21:13:02 2013 -0500

    lynxpoint: fix enable_pm1() function
    
    The new enable_pm1() function was doing 2 things wrong:
    
    1. It was doing a RMW of the pm1 register. This means we were
       keeping around the enables from the OS during S3 resume. This
       is bad in the face of the RTC alarm waking us up because it would
       cause an infinite stream of SMIs.
    2. The register size of PM1_EN is 16-bits. However, the previous
       implementation was accessing it as a 32-bit register.
    
    The PM1 enables should only be set to what we expect to handle in the
    firmware before the OS changes to ACPI mode.
    
    Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2978
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Sat Mar 30 02:02:43 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Mon Apr  1 23:25:20 2013, giving +2
See http://review.coreboot.org/2978 for details.

-gerrit