[coreboot-gerrit] Patch merged into coreboot/master: ebf142a boot: add disable_cache_rom() function

gerrit at coreboot.org gerrit at coreboot.org
Mon Apr 1 23:29:13 CEST 2013

the following patch was just integrated into master:
commit ebf142a12ce4911b766bd618483434519efba0d5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 29 16:23:23 2013 -0500

    boot: add disable_cache_rom() function
    On certain architectures such as x86 the bootstrap processor
    does most of the work. When CACHE_ROM is employed it's appropriate
    to ensure that the caching enablement of the ROM is disabled so that
    the caching settings are symmetric before booting the payload or OS.
    Tested this on an x86 machine that turned on ROM caching. Linux did not
    complain about asymmetric MTRR settings nor did the ROM show up as
    cached in the MTRR settings.
    Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2980
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Sat Mar 30 02:18:43 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Mon Apr  1 23:29:11 2013, giving +2
See http://review.coreboot.org/2980 for details.


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