[coreboot-gerrit] Patch set updated for coreboot: a85f3b1 haswell: use new interface to disable rom caching

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3007

-gerrit

commit a85f3b132c3142e6052b7262e03063559352519c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Apr 1 15:40:45 2013 -0500

    haswell: use new interface to disable rom caching
    
    The haswell code was using the old assumption of which MTRR
    was used for the ROM cache. Now that there is an API for doing
    this use it as the old assumption is no longer valid.
    
    Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/intel/haswell/mp_init.c | 23 +----------------------
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c
index c8bd5c2..cc13892 100644
--- a/src/cpu/intel/haswell/mp_init.c
+++ b/src/cpu/intel/haswell/mp_init.c
@@ -145,28 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel)
  * ensure the caching is disabled for tha APs before going to sleep. */
 static void cleanup_rom_caching(void)
 {
-#if CONFIG_CACHE_ROM
-	msr_t msr;
-	unsigned int last_var_mtrr;
-
-	msr = rdmsr(MTRRcap_MSR);
-	last_var_mtrr = (msr.lo & 0xff) - 1;
-
-	/* Check if the MTRR is valid. */
-	msr = rdmsr(MTRRphysMask_MSR(last_var_mtrr));
-	if ((msr.lo & MTRRphysMaskValid) == 0)
-		return;
-	msr = rdmsr(MTRRphysBase_MSR(last_var_mtrr));
-	/* Assum that if the MTRR is of write protected type, the MTRR is used
-	 * to cache the ROM. */
-	if ((msr.lo & MTRR_NUM_TYPES) == MTRR_TYPE_WRPROT) {
-		msr.lo = msr.hi = 0;
-		disable_cache();
-		wrmsr(MTRRphysMask_MSR(last_var_mtrr), msr);
-		wrmsr(MTRRphysBase_MSR(last_var_mtrr), msr);
-		enable_cache();
-	}
-#endif
+	x86_mtrr_disable_rom_caching();
 }
 
 /* By the time APs call ap_init() caching has been setup, and microcode has