[coreboot-gerrit] Patch merged into coreboot/master: 6d0fe9c armv7: specify condition code for msr instruction

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 6d0fe9cad003d752af3214ae9a91d7411d582950
Author: David Hendricks <dhendrix at chromium.org>
Date:   Sun Apr 7 17:26:34 2013 -0700

    armv7: specify condition code for msr instruction
    
    This adds condition codes when using the msr instruction. Although
    described as "optional" in the Cortex-A series programmer's guide,
    our experience with using the msr instruction in the payload suggests
    that the condition code is not optional and that this only worked
    in coreboot (and u-boot) because the processor comes up in SVC32 mode.
    
    (credit to Gabe Black for finding this, I'm only uploading the patch)
    
    Signed-off-by: Gabe Black <gabeblack at chromium.org>
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b
    Reviewed-on: http://review.coreboot.org/3037
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Mon Apr  8 04:53:13 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Mon Apr  8 18:31:08 2013, giving +2
See http://review.coreboot.org/3037 for details.

-gerrit