[coreboot-gerrit] Patch set updated for coreboot: 852344a exynos5250/snow: debugging display bring-up
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Fri Apr 12 22:02:22 CEST 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3076
-gerrit
commit 852344a67335a3fa65b1332500b0956285bc9465
Author: David Hendricks <dhendrix at chromium.org>
Date: Fri Apr 12 12:53:15 2013 -0700
exynos5250/snow: debugging display bring-up
** do not submit **
This is just a WIP patch with loads of extra debug prints. Any
functional changes will be split out into other patches.
Change-Id: I275e646d30d291323f3ace602cac8d3ea76af2f0
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/cpu/samsung/exynos5-common/exynos-fb.c | 28 +++++++++++++++--------
src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 +-
src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 11 +++++++--
src/mainboard/google/snow/ramstage.c | 34 ++++++++++++++--------------
4 files changed, 45 insertions(+), 30 deletions(-)
diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c
index b57e276..0cce458 100644
--- a/src/cpu/samsung/exynos5-common/exynos-fb.c
+++ b/src/cpu/samsung/exynos5-common/exynos-fb.c
@@ -27,6 +27,7 @@
#include <arch/io.h>
#include <stdlib.h>
#include <string.h>
+#include <time.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/power.h>
@@ -207,6 +208,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
return -ERR_PLL_NOT_UNLOCKED;
}
+#if 0
start = get_timer(0);
do {
if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) {
@@ -219,6 +221,21 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
printk(BIOS_DEBUG, "Video Clock Not ok\n");
return -ERR_VIDEO_CLOCK_BAD;
}
+#endif
+ int not_fucked = 0;
+ start = timer_us();
+ while (timer_us() < start + (STREAM_ON_TIMEOUT * 1000)) {
+ if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) {
+ not_fucked = 1;
+ break;
+ }
+ }
+
+ if (!not_fucked) {
+ printk(BIOS_DEBUG, "Video Clock Not ok, we are still fucked.\n");
+ return -ERR_VIDEO_CLOCK_BAD;
+ }
+
/* Set to use the register calculated M/N video */
s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
@@ -505,7 +522,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
/*
* Initialize DP display
*/
-int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
+int dp_controller_init(struct s5p_dp_device *dp_device)
{
int ret;
struct s5p_dp_device *dp = dp_device;
@@ -561,15 +578,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
return ret;
}
- /*
- * This delay is T3 in the LCD timing spec (defined as >200ms). We set
- * this down to 60ms since that's the approximate maximum amount of time
- * it'll take a bridge to start outputting LVDS data. The delay of
- * >200ms is just a conservative value to avoid turning on the backlight
- * when there's random LCD data on the screen. Shaving 140ms off the
- * boot is an acceptable trade-off.
- */
- *wait_ms = 60;
return 0;
}
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
index 2988d5d..4df848d 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h
+++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
@@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
struct exynos5_fimd_panel;
void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
-int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
+int dp_controller_init(struct s5p_dp_device *dp_device);
int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
#endif /* _S5P_DP_CORE_H */
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
index 60e1398..0c6b214 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
+++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
@@ -184,12 +184,13 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
while (!(reg & RPLY_RECEIV))
reg = readl(&base->dp_int_sta);
+ printk(BIOS_DEBUG, "%s: checkpoint 1, dp_int_sta: 0x%08x\n", __func__, reg);
/* Clear interrupt source for AUX CH command reply */
writel(RPLY_RECEIV, &base->dp_int_sta);
/* Clear interrupt source for AUX CH access error */
reg = readl(&base->dp_int_sta);
- printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg);
+ printk(BIOS_DEBUG, "%s: checkpoint 2, dp_int_sta: 0x%08x\n", __func__, reg);
if (reg & AUX_ERR) {
writel(AUX_ERR, &base->dp_int_sta);
return -1;
@@ -203,6 +204,8 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
return -1;
}
+ printk(BIOS_DEBUG, "%s: done, dp_int_sta: 0x%08x, aux_ch_sta: 0x%08x\n",
+ __func__, reg, readl(&base->aux_ch_sta));
return 0;
}
@@ -356,8 +359,10 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
reg = readl(&base->sys_ctl_1);
- if (!(reg & DET_STA))
+ if (!(reg & DET_STA)) {
+ printk(BIOS_DEBUG, "%s: sys_ctl_1: 0x%08x\n", __func__, reg);
return -1;
+ }
reg = readl(&base->sys_ctl_2);
writel(reg, &base->sys_ctl_2);
@@ -365,10 +370,12 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
reg = readl(&base->sys_ctl_2);
if (reg & CHA_STA) {
+ printk(BIOS_DEBUG, "%s: sys_ctl_2: 0x%08x\n", __func__, reg);
printk(BIOS_DEBUG, "Input stream clk is changing\n");
return -1;
}
+ printk(BIOS_DEBUG, "%s: done\n", __func__);
return 0;
}
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index ad0266b..0bb264a 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -98,8 +98,6 @@ static void exynos_dp_bridge_setup(void)
gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE);
udelay(10);
gpio_set_value(dp_rst_l, 1);
-
- udelay(90000); /* FIXME: this might be unnecessary */
}
static void exynos_dp_bridge_init(void)
@@ -116,19 +114,13 @@ static void exynos_dp_bridge_init(void)
* roughly 50ms after PD is de-asserted. The phantom high
* makes it hard for us to know when the NXP chip is up.
*/
- udelay(90000); /* FIXME: this might be unnecessary */
+ udelay(90000);
}
static int exynos_dp_hotplug(void)
{
- int x = gpio_get_value(dp_hpd);
/* Check HPD. If it's high, we're all good. */
-// if (gpio_get_value(dp_hpd))
-// return 0;
- printk(BIOS_DEBUG, "%s: dp_hpd: 0x%02x\n", __func__, x);
- if (x)
- return 0;
- return -1;
+ return gpio_get_value(dp_hpd) ? 0 : 1;
}
static void exynos_dp_reset(void)
@@ -139,6 +131,7 @@ static void exynos_dp_reset(void)
udelay(300 * 1000);
}
+#define LCD_T3_DELAY_MS 60
#define LCD_T5_DELAY_MS 10
#define LCD_T6_DELAY_MS 10
@@ -199,7 +192,6 @@ static struct video_info snow_dp_video_info = {
static void mainboard_init(device_t dev)
{
int dp_tries;
- unsigned int wait_ms;
struct s5p_dp_device dp_device = {
.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
.video_info = &snow_dp_video_info,
@@ -215,20 +207,28 @@ static void mainboard_init(device_t dev)
exynos_dp_bridge_setup();
for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
- if (wait_ms) {
- udelay(wait_ms);
- wait_ms = 0;
- }
-
exynos_dp_bridge_init();
if (exynos_dp_hotplug()) {
exynos_dp_reset();
continue;
}
- if (dp_controller_init(&dp_device, &wait_ms))
+ if (dp_controller_init(&dp_device))
continue;
+ printk(BIOS_INFO, "%s: DP controller init done, powering on "
+ "backlight\n", __func__);
+
+ /*
+ * This delay is T3 in the LCD timing spec (defined as >200ms). We set
+ * this down to 60ms since that's the approximate maximum amount of time
+ * it'll take a bridge to start outputting LVDS data. The delay of
+ * >200ms is just a conservative value to avoid turning on the backlight
+ * when there's random LCD data on the screen. Shaving 140ms off the
+ * boot is an acceptable trade-off.
+ */
+ udelay(LCD_T3_DELAY_MS * 1000);
+
snow_backlight_vdd();
snow_backlight_pwm();
snow_backlight_en();
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