[coreboot-gerrit] New patch to review for coreboot: 7327d66 snow: Add support for EC based recovery.

[Gabe Black (gabeblack@chromium.org)]

Gabe Black (gabeblack at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3092

-gerrit

commit 7327d665a7b2c9b4d43155f3985c7f16a2b7f0b0
Author: Gabe Black <gabeblack at chromium.org>
Date:   Mon Apr 15 18:09:15 2013 -0700

    snow: Add support for EC based recovery.
    
    Implement the get_recovery_mode_switch function using the newly added I2C
    based Chrome EC support.
    
    Change-Id: I9d0200629887f202edf017cba3222a7d7f5b053e
    Signed-off-by: Gabe Black <gabeblack at chromium.org>
---
 src/mainboard/google/snow/chromeos.c | 33 +++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c
index e74df6d..f33f103 100644
--- a/src/mainboard/google/snow/chromeos.c
+++ b/src/mainboard/google/snow/chromeos.c
@@ -18,20 +18,20 @@
  */
 
 #include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <arch/io.h>
 
 #include <cpu/samsung/exynos5250/cpu.h>
 #include <cpu/samsung/exynos5250/gpio.h>
 #include <cpu/samsung/exynos5-common/gpio.h>
 
-#include <device/device.h>
-
 #define ACTIVE_LOW	0
 #define ACTIVE_HIGH	1
 #define WP_GPIO		6
 #define DEVMODE_GPIO	54
+#define RECMODE_GPIO	0
 #define FORCE_RECOVERY_MODE	0
 #define FORCE_DEVELOPER_MODE	0
 #define LID_OPEN	5
@@ -41,17 +41,16 @@
 
 #define GPIO_COUNT	6
 
+static struct exynos5_gpio_part1 *gpio_pt1 =
+	(struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE;
+static struct exynos5_gpio_part2 *gpio_pt2 =
+	(struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE;
+
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
-	struct exynos5_gpio_part1 *gpio_pt1;
-	struct exynos5_gpio_part2 *gpio_pt2;
-
 	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
 	gpios->count = GPIO_COUNT;
 
-	gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE;
-	gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE;
-
 	/* Write Protect: active low */
 	gpios->gpios[0].port = EXYNOS5_GPD1;
 	gpios->gpios[0].polarity = ACTIVE_LOW;
@@ -60,9 +59,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 							GPIO_MAX_NAME_LENGTH);
 
 	/* Recovery: active low */
-	gpios->gpios[1].port = EXYNOS5_GPY1;
-	gpios->gpios[1].polarity = ACTIVE_LOW;
-	gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE);
+	gpios->gpios[1].port = -1;
+	gpios->gpios[1].polarity = ACTIVE_HIGH;
+	gpios->gpios[1].value = get_recovery_mode_switch();
 	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
 
 	/* Lid: active high */
@@ -109,9 +108,15 @@ int get_developer_mode_switch(void)
 
 int get_recovery_mode_switch(void)
 {
-	int ec_rec_mode = 0;
+	uint32_t ec_events;
+
+	/* The GPIO is active low. */
+	if (!s5p_gpio_get_value(&gpio_pt1->y1, RECMODE_GPIO))
+		return 1;
 
-	return ec_rec_mode;
+	ec_events = google_chromeec_get_events_b();
+	return !!(ec_events &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
 }
 
 int get_recovery_mode_from_vbnv(void)