[coreboot-gerrit] New patch to review for coreboot: 36ae8c6 AMD Parmer: remov unused macros and turn off unused pcie port
Siyuan Wang (wangsiyuanbuaa@gmail.com)
gerrit at coreboot.org
Tue Apr 16 07:51:58 CEST 2013
Siyuan Wang (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3099
-gerrit
commit 36ae8c6d00410f61eeb3d7c964dff843634f52a4
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date: Tue Apr 16 13:59:37 2013 +0800
AMD Parmer: remov unused macros and turn off unused pcie port
1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE,
GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used.
This is based on >>AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h<< [1].
2) Disable unused PCIE port in devicetree.cb.
PCIE port 3 is not used in Parmer.
This is based on item 3 of >>AMD Thatcher: Fix PCIE link issues<< [2].
[1] http://review.coreboot.org/#/c/3087/
[2] http://review.coreboot.org/#/c/3011/
Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a
Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
---
src/mainboard/amd/parmer/PlatformGnbPcie.c | 8 ++---
src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 40 -----------------------
src/mainboard/amd/parmer/devicetree.cb | 2 +-
3 files changed, 5 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c
index 51dd9fd..f38ad13 100644
--- a/src/mainboard/amd/parmer/PlatformGnbPcie.c
+++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c
@@ -27,13 +27,13 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
PCIe_PORT_DESCRIPTOR PortList [] = {
- /* PCIe port, Lanes 8:23, PCI Device Number 2 */
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
{
0, /* Descriptor flags */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
- /* PCIe port, Lanes 16:23, PCI Device Number 3 */
+ /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
0, /* Descriptor flags */
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
@@ -54,7 +54,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
- /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 */
+ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{
0, /* Descriptor flags */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
@@ -68,7 +68,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
- /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */
+ /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h
index 3f14805..b3c69cf 100644
--- a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h
@@ -24,46 +24,6 @@
#include "AGESA.h"
#include "amdlib.h"
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb
index 9bbbcf7..62b37e1 100644
--- a/src/mainboard/amd/parmer/devicetree.cb
+++ b/src/mainboard/amd/parmer/devicetree.cb
@@ -33,7 +33,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIE SLOT0 x16
- device pci 3.0 on end # PCIE SLOT0 x16
+ device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
device pci 6.0 on end # PCIE Slot1 x1
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