[coreboot-gerrit] Patch set updated for coreboot: 24b6aba haswell: 24MHz monotonic time implementation

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3153

-gerrit

commit 24b6abaff5d42024a563a3c238525370c64a3083
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Apr 29 16:57:10 2013 -0500

    haswell: 24MHz monotonic time implementation
    
    Haswell ULT devices have a 24MHz package-level counter. Use
    this counter to provide a timer_monotonic_get() implementation.
    
    Change-Id: Ic79843fcbfbbb6462ee5ebd12b39502307750dbb
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/intel/haswell/Kconfig           |  7 ++++
 src/cpu/intel/haswell/Makefile.inc      |  1 +
 src/cpu/intel/haswell/monotonic_timer.c | 62 +++++++++++++++++++++++++++++++++
 3 files changed, 70 insertions(+)

diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 5f27d4c..13861f9 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -54,4 +54,11 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
 	  the system will reset otherwise the ramstage will be reloaded from
 	  cbfs.
 
+config MONOTONIC_TIMER_MSR
+	def_bool n
+	depends on INTEL_LYNXPOINT_LP
+	select HAVE_MONOTONIC_TIMER
+	help
+	 Provide a monotonic timer using the 24MHz MSR counter.
+
 endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a19a8c5..90ffd66 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -5,6 +5,7 @@ romstage-y += romstage.c
 
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
+ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
 
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 
diff --git a/src/cpu/intel/haswell/monotonic_timer.c b/src/cpu/intel/haswell/monotonic_timer.c
new file mode 100644
index 0000000..c51bcbd
--- /dev/null
+++ b/src/cpu/intel/haswell/monotonic_timer.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <timer.h>
+
+#define MSR_COUNTER_24_MHz 0x637
+static struct monotonic_counter {
+	int initialized;
+	struct mono_time time;
+	uint32_t last_value;
+} mono_counter;
+
+static inline uint32_t read_counter_msr(void)
+{
+	/* Even though the MSR is 64-bit it is assumed that the hardware
+	 * is polled frequently enough to only use the lower 32-bits. */
+	msr_t counter_msr;
+
+	counter_msr = rdmsr(MSR_COUNTER_24_MHz);
+
+	return counter_msr.lo;
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	uint32_t current_tick;
+	uint32_t usecs_elapsed;
+
+	if (!mono_counter.initialized) {
+		mono_counter.last_value = read_counter_msr();
+		mono_counter.initialized = 1;
+	}
+
+	current_tick = read_counter_msr();
+	usecs_elapsed = (current_tick - mono_counter.last_value) / 24;
+
+	/* Update current time and tick values only if a full tick occurred. */
+	if (usecs_elapsed) {
+		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
+		mono_counter.last_value = current_tick;
+	}
+
+	/* Save result. */
+	*mt = mono_counter.time;
+}