[coreboot-gerrit] Patch set updated for coreboot: 0578a98 AMD Fam16: Add OSC method to PCI0

Bruce Griffith (Bruce.Griffith@se-eng.com) gerrit at coreboot.org
Thu Aug 1 14:56:18 CEST 2013

Bruce Griffith (Bruce.Griffith at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3823


commit 0578a9845dee4cd707efbf659ec0588f0060cd3f
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Thu Jul 18 10:30:47 2013 -0600

    AMD Fam16: Add OSC method to PCI0
    The _OSC method is used to tell the OS what capabilities
    it can take control over from the firmware.  This method
    is described in chapter 6.2.9 of the ACPI spec v3.0.
    The method takes 4 inputs (UUID, Rev ID, Input Count,
    and Capabilities Buffer) and returns a Capabilites
    Buffer the same size as the input Buffer.  This Buffer
    is generally 3 Dwords long consisting of an Errors
    Dword, a Supported Capabilities Dword, and a Control
    Dword.  The OS will request control of certain
    capabilities and the firmware must grant or deny control
    of those features.  We do not want to have control over
    anything so let the OS control as much as it can.
    The _OSC method is required for PCIe devices and dmesg
    checks for its existence and issues an error if it is
    not found.
    This is the same change as was made to Family14 here:
    	00a0e76: AMD Fam14 DSDT: Add OSC method
    Along with its subsequent warnings fix here:
    	8764b0e: Fam14 DSDT: Also return for unrecognized UUID in _OSC
    Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>
 src/southbridge/amd/agesa/hudson/acpi/fch.asl | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
index 5d3a29c..06b4fe7 100755
--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
@@ -21,6 +21,25 @@
 /* South Bridge */
 /*  _SB.PCI0 */
+/* Operating System Capabilities Method */
+	// Create DWord-addressable fields from the Capabilities Buffer
+	CreateDWordField(Arg3,0,CDW1)
+	CreateDWordField(Arg3,4,CDW2)
+	CreateDWordField(Arg3,8,CDW3)
+	/* Check for proper PCI/PCIe UUID */
+	If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+	{
+		/* Let OS control everything */
+		Return (Arg3)
+	} Else {
+		Or(CDW1,4,CDW1)	// Unrecognized UUID
+		Return(Arg3)
+	}
 /* Describe the Southbridge devices */
 /* 0:11.0 - SATA */

More information about the coreboot-gerrit mailing list