[coreboot-gerrit] New patch to review for coreboot: 24f441d AMD Kabini: Add AGESA/PI code for new processor family

Bruce Griffith (Bruce.Griffith@se-eng.com) gerrit at coreboot.org
Thu Aug 1 14:56:22 CEST 2013


Bruce Griffith (Bruce.Griffith at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3836

-gerrit

commit 24f441d29916ebdc04e5e6abbe77dabf94eca805
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Thu Jul 25 15:14:15 2013 +0800

    AMD Kabini: Add AGESA/PI code for new processor family
    
    Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
    Reviewed-by: Nick Dill <nick.dill at se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith at se-eng.com>
---
 src/vendorcode/amd/agesa/Makefile.inc              |     1 +
 src/vendorcode/amd/agesa/f16kb/AGESA.h             |  3912 +++
 src/vendorcode/amd/agesa/f16kb/AMD.h               |   476 +
 src/vendorcode/amd/agesa/f16kb/Dispatcher.h        |    51 +
 .../amd/agesa/f16kb/Include/AdvancedApi.h          |   166 +
 .../amd/agesa/f16kb/Include/CommonReturns.h        |   159 +
 src/vendorcode/amd/agesa/f16kb/Include/Filecode.h  |   581 +
 .../amd/agesa/f16kb/Include/GeneralServices.h      |   201 +
 .../amd/agesa/f16kb/Include/GnbInterface.h         |   123 +
 src/vendorcode/amd/agesa/f16kb/Include/Ids.h       |  1426 +
 src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h     |   123 +
 src/vendorcode/amd/agesa/f16kb/Include/IdsPerf.h   |   139 +
 .../amd/agesa/f16kb/Include/KeralaInstall.h        |   143 +
 .../amd/agesa/f16kb/Include/OptionApmInstall.h     |    84 +
 .../amd/agesa/f16kb/Include/OptionC6Install.h      |   101 +
 .../amd/agesa/f16kb/Include/OptionCdit.h           |    89 +
 .../amd/agesa/f16kb/Include/OptionCditInstall.h    |    74 +
 .../amd/agesa/f16kb/Include/OptionCpbInstall.h     |   105 +
 .../Include/OptionCpuCacheFlushOnHaltInstall.h     |   102 +
 .../f16kb/Include/OptionCpuCoreLevelingInstall.h   |   100 +
 .../agesa/f16kb/Include/OptionCpuFamiliesInstall.h |   228 +
 .../agesa/f16kb/Include/OptionCpuFeaturesInstall.h |    83 +
 .../Include/OptionCpuSpecificServicesInstall.h     |  1297 +
 .../OptionCpuSpecificServicesInstallReset.h        |   545 +
 .../amd/agesa/f16kb/Include/OptionCrat.h           |   193 +
 .../amd/agesa/f16kb/Include/OptionCratInstall.h    |   127 +
 src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h |    89 +
 .../amd/agesa/f16kb/Include/OptionDmiInstall.h     |   125 +
 .../f16kb/Include/OptionFamily16hEarlySample.h     |    75 +
 .../agesa/f16kb/Include/OptionFamily16hInstall.h   |   332 +
 .../amd/agesa/f16kb/Include/OptionFchInstall.h     |  1026 +
 .../amd/agesa/f16kb/Include/OptionGfxRecovery.h    |    81 +
 .../agesa/f16kb/Include/OptionGfxRecoveryInstall.h |    53 +
 src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h |   134 +
 .../amd/agesa/f16kb/Include/OptionGnbInstall.h     |   932 +
 .../amd/agesa/f16kb/Include/OptionHtInstall.h      |   244 +
 .../amd/agesa/f16kb/Include/OptionHtcInstall.h     |   102 +
 .../amd/agesa/f16kb/Include/OptionIdsInstall.h     |   506 +
 .../agesa/f16kb/Include/OptionIoCstateInstall.h    |   103 +
 .../agesa/f16kb/Include/OptionL3FeaturesInstall.h  |    79 +
 .../f16kb/Include/OptionLowPwrPstateInstall.h      |    55 +
 .../amd/agesa/f16kb/Include/OptionMemory.h         |   365 +
 .../amd/agesa/f16kb/Include/OptionMemoryInstall.h  |  1629 +
 .../amd/agesa/f16kb/Include/OptionMemoryRecovery.h |    62 +
 .../f16kb/Include/OptionMemoryRecoveryInstall.h    |   231 +
 .../amd/agesa/f16kb/Include/OptionMmioMapInstall.h |    93 +
 .../agesa/f16kb/Include/OptionMsgBasedC1eInstall.h |    70 +
 .../amd/agesa/f16kb/Include/OptionMultiSocket.h    |   215 +
 .../agesa/f16kb/Include/OptionMultiSocketInstall.h |   104 +
 .../f16kb/Include/OptionPrefetchModeInstall.h      |   107 +
 .../f16kb/Include/OptionPreserveMailboxInstall.h   |    57 +
 .../amd/agesa/f16kb/Include/OptionPsiInstall.h     |   103 +
 .../amd/agesa/f16kb/Include/OptionPstate.h         |   117 +
 .../f16kb/Include/OptionPstateHpcModeInstall.h     |    57 +
 .../amd/agesa/f16kb/Include/OptionPstateInstall.h  |   230 +
 .../agesa/f16kb/Include/OptionS3ScriptInstall.h    |    91 +
 .../amd/agesa/f16kb/Include/OptionSlit.h           |    98 +
 .../amd/agesa/f16kb/Include/OptionSlitInstall.h    |    81 +
 .../amd/agesa/f16kb/Include/OptionSrat.h           |    84 +
 .../amd/agesa/f16kb/Include/OptionSratInstall.h    |    75 +
 .../agesa/f16kb/Include/OptionTdpLimitingInstall.h |    84 +
 .../amd/agesa/f16kb/Include/OptionWhea.h           |    83 +
 .../amd/agesa/f16kb/Include/OptionWheaInstall.h    |    74 +
 src/vendorcode/amd/agesa/f16kb/Include/Options.h   |    68 +
 src/vendorcode/amd/agesa/f16kb/Include/OptionsHt.h |   109 +
 .../amd/agesa/f16kb/Include/PlatformInstall.h      |  2361 ++
 .../f16kb/Include/PlatformMemoryConfiguration.h    |   516 +
 src/vendorcode/amd/agesa/f16kb/Include/Topology.h  |   164 +
 .../amd/agesa/f16kb/Include/gcc-intrin.h           |   624 +
 .../f16kb/Legacy/PlatformMemoryConfiguration.inc   |   701 +
 .../amd/agesa/f16kb/Legacy/Proc/Dispatcher.c       |   158 +
 .../amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c    |   486 +
 .../amd/agesa/f16kb/Legacy/Proc/arch2008.asm       |  2676 ++
 .../amd/agesa/f16kb/Legacy/Proc/hobTransfer.c      |   421 +
 src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc    |  3299 ++
 src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc      |   462 +
 src/vendorcode/amd/agesa/f16kb/Legacy/bridge32.inc |   576 +
 src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c        |  1360 +
 src/vendorcode/amd/agesa/f16kb/Lib/amdlib.h        |   384 +
 src/vendorcode/amd/agesa/f16kb/Lib/helper.c        |    68 +
 src/vendorcode/amd/agesa/f16kb/Makefile.inc        |   102 +
 src/vendorcode/amd/agesa/f16kb/Porting.h           |   282 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c   |   198 +
 .../CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c     |   150 +
 .../Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c  |   250 +
 .../Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h  |    78 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c |   195 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c |   369 +
 .../CPU/Family/0x16/KB/F16KbEquivalenceTable.c     |   120 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c |   178 +
 .../Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c  |   143 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c  |   371 +
 .../Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c |   107 +
 .../0x16/KB/F16KbMicrocodePatch0700002A_Enc.c      |  3539 ++
 .../0x16/KB/F16KbMicrocodePatch07000106_Enc.c      |  3539 ++
 .../CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c |   111 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c |   264 +
 .../Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c    |   365 +
 .../Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h    |    78 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c |  1147 +
 .../Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c      |   500 +
 .../Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h      |    84 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h |   535 +
 .../Family/0x16/KB/F16KbPowerMgmtSystemTables.c    |   153 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c |   278 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c    |   613 +
 .../Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c  |   112 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c |  1015 +
 .../f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h |   152 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c   |   124 +
 .../f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c     |   166 +
 .../Proc/CPU/Family/0x16/cpuF16CacheDefaults.c     |   129 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c   |   123 +
 .../agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.h   |    76 +
 .../f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c     |   473 +
 .../f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.h     |    90 +
 .../Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c  |   104 +
 .../Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c  |   250 +
 .../f16kb/Proc/CPU/Family/0x16/cpuF16PowerMgmt.h   |   294 +
 .../f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c   |   417 +
 .../f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h   |   144 +
 .../CPU/Family/0x16/cpuF16WheaInitDataTables.c     |   127 +
 .../agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h  |   125 +
 .../agesa/f16kb/Proc/CPU/Feature/PreserveMailbox.h |    97 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c      |   194 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h      |   127 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c  |   260 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h  |   156 +
 .../f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c   |   199 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c    |   751 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h    |   138 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c     |   347 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c |   374 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c      |   175 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h      |   133 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c     |   513 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.h     |    85 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c      |   872 +
 .../f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c    |   265 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.c |   283 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h |   281 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c      |   201 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h      |   130 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c |   207 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h |   283 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h   |   399 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h  |   127 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h |   110 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c      |   213 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h      |   130 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuPstateGather.c |   410 +
 .../f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h      |    98 +
 .../f16kb/Proc/CPU/Feature/cpuPstateLeveling.c     |  1100 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.c |   940 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h |   314 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c     |   398 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c     |   618 +
 .../agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h  |   129 +
 .../amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c     |   288 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c       |  1274 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.h       |   399 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c    |   927 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h    |  1314 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm |   367 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.c   |   160 +
 .../amd/agesa/f16kb/Proc/CPU/cahalt64.asm          |   173 +
 .../amd/agesa/f16kb/Proc/CPU/cahaltasm.S           |   201 +
 .../amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c    |  1453 +
 .../amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h    |   303 +
 src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c  |   171 +
 .../amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c        |   469 +
 .../amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h        |   290 +
 .../amd/agesa/f16kb/Proc/CPU/cpuEnvInit.h          |    73 +
 .../amd/agesa/f16kb/Proc/CPU/cpuEventLog.c         |   396 +
 .../agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c    |   485 +
 .../agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h    |  1052 +
 .../amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c  |  1286 +
 .../amd/agesa/f16kb/Proc/CPU/cpuLateInit.c         |   289 +
 .../amd/agesa/f16kb/Proc/CPU/cpuLateInit.h         |  1137 +
 .../amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c   |   431 +
 .../amd/agesa/f16kb/Proc/CPU/cpuPostInit.c         |   416 +
 .../amd/agesa/f16kb/Proc/CPU/cpuPostInit.h         |   233 +
 .../amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c        |   275 +
 .../f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c      |   332 +
 .../f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.h      |   127 +
 .../f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h      |    93 +
 .../amd/agesa/f16kb/Proc/CPU/cpuRegisters.h        |   498 +
 .../amd/agesa/f16kb/Proc/CPU/cpuServices.h         |   342 +
 .../amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c        |   234 +
 .../amd/agesa/f16kb/Proc/CPU/heapManager.c         |   889 +
 .../amd/agesa/f16kb/Proc/CPU/heapManager.h         |   258 +
 .../amd/agesa/f16kb/Proc/CPU/mmioMapManager.h      |   143 +
 .../amd/agesa/f16kb/Proc/Common/AmdFch.h           |    65 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitEarly.c     |   323 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitEnv.c       |   188 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitLate.c      |   323 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitMid.c       |   178 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitPost.c      |   349 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitReset.c     |   257 +
 .../amd/agesa/f16kb/Proc/Common/AmdInitResume.c    |   245 +
 .../amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c |   159 +
 .../amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c |   217 +
 .../amd/agesa/f16kb/Proc/Common/AmdS3Save.c        |   424 +
 .../amd/agesa/f16kb/Proc/Common/CommonInits.c      |   143 +
 .../amd/agesa/f16kb/Proc/Common/CommonInits.h      |    65 +
 .../amd/agesa/f16kb/Proc/Common/CommonReturns.c    |   262 +
 .../amd/agesa/f16kb/Proc/Common/CreateStruct.c     |   313 +
 .../amd/agesa/f16kb/Proc/Common/CreateStruct.h     |   195 +
 .../amd/agesa/f16kb/Proc/Common/S3RestoreState.c   |   441 +
 .../amd/agesa/f16kb/Proc/Common/S3SaveState.c      |   651 +
 .../amd/agesa/f16kb/Proc/Common/S3SaveState.h      |   365 +
 .../amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaEnv.c    |    80 +
 .../amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c   |    59 +
 .../amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaMid.c    |   509 +
 .../amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c  |    61 +
 .../amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c      |   242 +
 .../amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.h      |    91 +
 .../agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h  |    67 +
 .../amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c    |    47 +
 .../amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h |  1219 +
 .../amd/agesa/f16kb/Proc/Fch/Common/FchDef.h       |   438 +
 .../amd/agesa/f16kb/Proc/Fch/Common/FchLib.c       |   598 +
 .../amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c     |   260 +
 .../amd/agesa/f16kb/Proc/Fch/Common/MemLib.c       |   145 +
 .../amd/agesa/f16kb/Proc/Fch/Common/PciLib.c       |    94 +
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h      |  1624 +
 .../amd/agesa/f16kb/Proc/Fch/FchPlatform.h         |   117 +
 .../Family/Yangtze/YangtzeHwAcpiEnvService.c       |   485 +
 .../Family/Yangtze/YangtzeHwAcpiLateService.c      |   152 +
 .../Family/Yangtze/YangtzeHwAcpiMidService.c       |    48 +
 .../Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c   |   124 +
 .../amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c    |   102 +
 .../amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c   |   167 +
 .../amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiMid.c    |    64 +
 .../amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c  |   213 +
 .../Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c  |    87 +
 .../Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c |   189 +
 .../amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c         |    74 +
 .../amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c          |    63 +
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 .../Fch/Imc/Family/Yangtze/YangtzeImcService.c     |    97 +
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 .../amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c          |   140 +
 .../amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c         |    81 +
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 .../Fch/Interface/Family/Yangtze/EnvDefYangtze.c   |   359 +
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 .../agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c    |   114 +
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 .../agesa/f16kb/Proc/Fch/Interface/FchInitMid.c    |   100 +
 .../agesa/f16kb/Proc/Fch/Interface/FchInitReset.c  |   115 +
 .../amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c |   102 +
 .../f16kb/Proc/Fch/Interface/FchTaskLauncher.c     |    69 +
 .../f16kb/Proc/Fch/Interface/FchTaskLauncher.h     |    62 +
 .../agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c    |   196 +
 .../agesa/f16kb/Proc/Fch/Interface/InitResetDef.c  |    90 +
 .../amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c          |    79 +
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 .../Fch/Pcie/Family/Yangtze/YangtzeAbEnvService.c  |   253 +
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 .../amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c        |    67 +
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 .../Sata/Family/Yangtze/YangtzeSataEnvService.c    |   224 +
 .../Sata/Family/Yangtze/YangtzeSataResetService.c  |   125 +
 .../Fch/Sata/Family/Yangtze/YangtzeSataService.c   |   699 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciEnv.c    |    82 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciLate.c   |    89 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciLib.c    |    67 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciMid.c    |    76 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c        |    74 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c       |    65 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c        |    69 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c        |    74 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c        |   104 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c     |    88 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataIdeEnv.c     |   100 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c    |    71 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLib.c     |    46 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataIdeMid.c     |    75 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c       |   116 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c        |   258 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataMid.c        |   196 +
 .../amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c      |    63 +
 .../Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c    |   129 +
 .../Fch/Sd/Family/Yangtze/YangtzeSdResetService.c  |    47 +
 .../Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c  |    47 +
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c |    65 +
 .../amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c           |    60 +
 src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c |    61 +
 .../Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c  |    89 +
 .../Spi/Family/Yangtze/YangtzeLpcResetService.c    |   790 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c          |    94 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/LpcLate.c         |    58 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/LpcMid.c          |    60 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c        |    70 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/SpiEnv.c          |    61 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/SpiLate.c         |   113 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/SpiMid.c          |    61 +
 .../amd/agesa/f16kb/Proc/Fch/Spi/SpiReset.c        |    45 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/EhciEnv.c         |    60 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/EhciLate.c        |    60 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c         |   158 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c       |    62 +
 .../Fch/Usb/Family/Yangtze/YangtzeEhciEnvService.c |    44 +
 .../Usb/Family/Yangtze/YangtzeEhciLateService.c    |    47 +
 .../Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c |   188 +
 .../Fch/Usb/Family/Yangtze/YangtzeOhciEnvService.c |    96 +
 .../Usb/Family/Yangtze/YangtzeOhciLateService.c    |    48 +
 .../Fch/Usb/Family/Yangtze/YangtzeOhciMidService.c |   107 +
 .../Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c |   482 +
 .../Usb/Family/Yangtze/YangtzeXhciLateService.c    |   130 +
 .../Fch/Usb/Family/Yangtze/YangtzeXhciMidService.c |    48 +
 .../Usb/Family/Yangtze/YangtzeXhciResetService.c   |   118 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/OhciEnv.c         |    60 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/OhciLate.c        |    60 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/OhciMid.c         |   213 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c       |    62 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c          |    69 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c         |    67 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c          |    68 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c        |    62 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/XhciEnv.c         |   115 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c        |    62 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/XhciMid.c         |    77 +
 .../amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c       |    83 +
 .../amd/agesa/f16kb/Proc/GNB/Common/Gnb.h          |   171 +
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h   |    99 +
 .../agesa/f16kb/Proc/GNB/Common/GnbFamServices.h   |   141 +
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h       |   348 +
 .../f16kb/Proc/GNB/Common/GnbGfxFamServices.h      |   102 +
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h     |   195 +
 .../agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c   |   111 +
 .../agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h   |    55 +
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h      |   398 +
 .../f16kb/Proc/GNB/Common/GnbPcieFamServices.h     |   242 +
 .../f16kb/Proc/GNB/Common/GnbRegistersCommon.h     |  1557 +
 .../f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h   |  1445 +
 .../agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h   |  3954 +++
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h       |   204 +
 .../agesa/f16kb/Proc/GNB/Common/GnbUraServices.h   |    87 +
 .../amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h  |   103 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c      |   128 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c        |   138 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c       |   136 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c        |   118 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c       |   150 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c      |    93 +
 .../amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c     |    94 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h   |    57 +
 .../f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c   |   530 +
 .../f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h   |   156 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c   |   143 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h   |    65 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c     |   176 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h     |    69 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c    |   122 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h    |    66 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c   |   125 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h   |    73 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c      |   403 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h      |   166 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c   |   156 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h   |    73 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c    |   157 +
 .../Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.h    |    73 +
 .../Modules/GnbFamTranslation/GnbPcieTranslation.c |   515 +
 .../GNB/Modules/GnbFamTranslation/GnbTranslation.c |   245 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c   |   135 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c   |   264 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h   |    71 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c   |   113 +
 .../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c  |   135 +
 .../Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h   |    51 +
 .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c |   184 +
 .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h |    56 +
 .../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c    |   609 +
 .../Modules/GnbGfxInitLibV1/GfxEnumConnectors.h    |    64 +
 .../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c  |   217 +
 .../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h  |    79 +
 .../GnbGfxIntTableV3/GfxIntegratedInfoTable.c      |   504 +
 .../GnbGfxIntTableV3/GfxIntegratedInfoTable.h      |    73 +
 .../Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c   |   257 +
 .../Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.h   |    70 +
 .../GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c |  1233 +
 .../GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.h |   321 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c      |    92 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h  |  3230 ++
 .../Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c      |   229 +
 .../Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c      |   375 +
 .../Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h      |    55 +
 .../Modules/GnbInitKB/GfxIntegratedInfoTableKB.c   |   526 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c    |   192 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h    |    53 +
 .../Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c      |   161 +
 .../Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c     |   153 +
 .../Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c     |   253 +
 .../Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h     |    53 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c |   479 +
 .../Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c    |   459 +
 .../Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c      |   302 +
 .../Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c      |  1022 +
 .../Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h      |    78 +
 .../Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h  |   234 +
 .../Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c  |   165 +
 .../Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c      |   429 +
 .../Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c     |   120 +
 .../Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c  |   585 +
 .../Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h  |    68 +
 .../Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h    |  2103 ++
 .../Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h  | 32414 +++++++++++++++++++
 .../f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c |   499 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c    |   260 +
 .../Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c  |   122 +
 .../Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c |   447 +
 .../Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h |   157 +
 .../Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c      |   626 +
 .../Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c   |   938 +
 .../Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c     |    94 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c   |   463 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h   |    80 +
 .../Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c     |   392 +
 .../Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c    |   470 +
 .../Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c      |   225 +
 .../f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h    |   113 +
 .../f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c   |   224 +
 .../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h    |    99 +
 .../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c    |   386 +
 .../GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h    |   122 +
 .../GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c    |   348 +
 .../GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.h    |    80 +
 .../Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c    |   463 +
 .../Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.h    |   107 +
 .../f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c  |   374 +
 .../f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h  |    63 +
 .../Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c      |   326 +
 .../Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h      |    54 +
 .../Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c  |   135 +
 .../Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h  |    74 +
 .../Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h |    54 +
 .../GNB/Modules/GnbPcieConfig/PcieConfigData.c     |   533 +
 .../GNB/Modules/GnbPcieConfig/PcieConfigData.h     |    57 +
 .../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c |   799 +
 .../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h |   221 +
 .../GNB/Modules/GnbPcieConfig/PcieInputParser.c    |   277 +
 .../GNB/Modules/GnbPcieConfig/PcieInputParser.h    |    83 +
 .../GNB/Modules/GnbPcieConfig/PcieMapTopology.c    |   645 +
 .../GNB/Modules/GnbPcieConfig/PcieMapTopology.h    |    57 +
 .../Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h    |    60 +
 .../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c   |   173 +
 .../Modules/GnbPcieInitLibV1/PcieAspmBlackList.h   |    55 +
 .../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h |    55 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h |    73 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c |   622 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePifServices.h |   120 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c  |   273 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h  |    94 +
 .../Modules/GnbPcieInitLibV1/PciePortServices.c    |   396 +
 .../Modules/GnbPcieInitLibV1/PciePortServices.h    |   118 +
 .../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h   |    74 +
 .../Modules/GnbPcieInitLibV1/PcieSiliconServices.h |    72 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c  |    95 +
 .../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h  |    55 +
 .../GnbPcieInitLibV1/PcieTopologyServices.c        |   722 +
 .../GnbPcieInitLibV1/PcieTopologyServices.h        |   135 +
 .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c  |   661 +
 .../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h  |   131 +
 .../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c   |   300 +
 .../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h   |   127 +
 .../Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h    |    52 +
 .../Modules/GnbPcieInitLibV4/PciePortServicesV4.c  |   202 +
 .../Modules/GnbPcieInitLibV4/PciePortServicesV4.h  |    64 +
 .../GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h |    71 +
 .../GnbPcieInitLibV4/PcieWrapperServicesV4.c       |   204 +
 .../GnbPcieInitLibV4/PcieWrapperServicesV4.h       |    77 +
 .../Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h    |   141 +
 .../Modules/GnbPcieInitLibV5/PciePhyServicesV5.c   |   111 +
 .../Modules/GnbPcieInitLibV5/PciePifServicesV5.c   |   269 +
 .../Modules/GnbPcieInitLibV5/PciePortServicesV5.c  |   147 +
 .../GnbPcieInitLibV5/PcieSiliconServicesV5.c       |   198 +
 .../GnbPcieInitLibV5/PcieTopologyServicesV5.c      |   152 +
 .../GnbPcieInitLibV5/PcieWrapperServicesV5.c       |   184 +
 .../GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c |   376 +
 .../GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h |    55 +
 .../Modules/GnbPcieTrainingV2/GnbPcieTrainingV2.h  |    51 +
 .../GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c |   801 +
 .../GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h |    63 +
 .../Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c  |   375 +
 .../Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.h  |    55 +
 .../Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c |   169 +
 .../f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c     |   143 +
 .../f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h     |    78 +
 .../f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c    |   142 +
 .../Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c     |   198 +
 .../Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c |   330 +
 .../Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h |   123 +
 .../f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c     |   128 +
 .../f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c     |   357 +
 .../f16kb/Proc/GNB/Modules/GnbTable/GnbTable.h     |   238 +
 .../Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c     |   388 +
 .../amd/agesa/f16kb/Proc/HT/Fam16/htNbFam16.c      |   150 +
 .../agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c |   300 +
 .../agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.h |   110 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c    |   112 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.h    |   579 +
 .../amd/agesa/f16kb/Proc/HT/htInterface.c          |   262 +
 .../amd/agesa/f16kb/Proc/HT/htInterface.h          |   489 +
 .../amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c  |   263 +
 .../amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.h  |   114 +
 .../amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c   |   538 +
 .../amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.h   |   161 +
 .../agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c   |   393 +
 .../agesa/f16kb/Proc/HT/htInterfaceNonCoherent.h   |   137 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c    |   589 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c      |   251 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.h      |  1200 +
 .../amd/agesa/f16kb/Proc/HT/htNbCommonHardware.h   |   122 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c  |   669 +
 src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h  |   297 +
 .../amd/agesa/f16kb/Proc/HT/htTopologies.h         |    71 +
 .../amd/agesa/f16kb/Proc/IDS/Control/IdsLib32.asm  |   335 +
 .../amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm  |   342 +
 .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c      |   211 +
 .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c |   654 +
 .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h |    80 +
 .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c   |   755 +
 .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h   |   119 +
 .../amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c   |   185 +
 .../Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c   |   308 +
 .../Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h   |    49 +
 .../f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h  |   287 +
 src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h   |   433 +
 .../amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c      |  1015 +
 .../amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h   |   169 +
 .../amd/agesa/f16kb/Proc/IDS/OptionsIds.h          |    92 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c  |   145 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/CRAT/mfCrat.h    |    95 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c  |   357 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h  |    80 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c      |   721 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c      |   290 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h      |    80 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c      |   177 +
 .../f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c   |   206 +
 .../f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c      |   548 +
 .../f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.h      |    72 +
 .../agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c    |   172 +
 .../agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.h    |    78 +
 .../agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c    |   153 +
 .../f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c    |   179 +
 .../f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h    |    77 +
 .../Proc/Mem/Feat/PARTRN/mfParallelTraining.c      |   288 +
 .../Proc/Mem/Feat/PARTRN/mfStandardTraining.c      |    85 +
 .../Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c   |   348 +
 .../Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c    |   115 +
 .../Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c |  1112 +
 .../RDWR2DTRAINING/mfRdWr2DPatternGeneration.c     |   424 +
 .../Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c     |  1368 +
 .../Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.h     |   266 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c        |   718 +
 .../amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c    |   401 +
 .../amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c    |   388 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mdef.c           |   155 +
 .../amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c        |   187 +
 .../amd/agesa/f16kb/Proc/Mem/Main/minit.c          |   149 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c  |   253 +
 .../agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c   |   695 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c          |   186 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c  |   244 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c       |   300 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c       |   126 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c   |   750 +
 .../agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c   |   146 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c  |   165 +
 .../agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c |   288 +
 .../agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c |   344 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c     |   262 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmflow.c         |   406 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mmlvddr3.h       |    80 +
 .../amd/agesa/f16kb/Proc/Mem/Main/mu.asm           |   496 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.c  |   250 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c |   760 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnS3kb.h        |    84 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c       |  1217 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c      |   129 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c  |   147 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c          |   628 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.h          |   410 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c       |   551 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c        |   268 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c       |  1078 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c       |   847 +
 .../amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c        |  1258 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c    |   608 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c  |   949 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c |  1648 +
 .../amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c           |  1241 +
 .../amd/agesa/f16kb/Proc/Mem/NB/mnflow.c           |   317 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c |   871 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c |  1345 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c |   601 +
 .../amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c         |   243 +
 .../amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c  |   130 +
 .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c        |   345 +
 .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c        |   180 +
 .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c         |   172 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c    |  1336 +
 .../amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c        |   325 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c |   195 +
 .../amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c         |   216 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c |   281 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c |   233 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c |   239 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c       |   235 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h       |   134 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtlrdimm3.h |   132 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c     |   167 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h     |    90 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c    |   318 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h    |    87 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c    |   503 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h    |    96 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c    |  1202 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h    |   180 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c   |   163 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c    |   718 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c  |   262 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c          |   124 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c  |   906 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h  |   117 +
 .../f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c   |   996 +
 .../agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c |  1185 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c       |  1478 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c         |   225 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c         |   312 +
 .../agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c    |   623 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttml.c          |   263 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c      |   425 +
 .../amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c         |   345 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/ma.h       |   162 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/merrhdl.h  |   103 +
 .../amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h  |   113 +
 .../amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h  |    81 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h |    83 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h     |   335 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h    |    80 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h       |  1500 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h       |  1579 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h    |   242 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h    |   533 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mp.h       |   523 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mport.h    |    70 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mt.h       |   634 +
 src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h       |   272 +
 src/vendorcode/amd/agesa/f16kb/cpcarmac.inc        |   476 +
 src/vendorcode/amd/agesa/f16kb/gcccar.inc          |  1301 +
 669 files changed, 249353 insertions(+)

diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
index 824595d..99356a6 100644
--- a/src/vendorcode/amd/agesa/Makefile.inc
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -3,3 +3,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb
diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h
new file mode 100644
index 0000000..5c40110
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h
@@ -0,0 +1,3912 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 85818 $   @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include  "Porting.h"
+#include  "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE              0x00028000ul
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA                0x00028100ul
+#define AGESA_DO_RESET                 0x00028101ul
+#define AGESA_ALLOCATE_BUFFER          0x00028102ul
+#define AGESA_DEALLOCATE_BUFFER        0x00028103ul
+#define AGESA_LOCATE_BUFFER            0x00028104ul
+#define AGESA_RUNFUNC_ONAP             0x00028105ul
+
+// AGESA ADVANCED CALLOUTS, HyperTransport
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD                 0x00028140ul
+#define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141ul
+#define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142ul
+#define AGESA_READ_SPD_RECOVERY        0x00028143ul
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145ul
+#define AGESA_EXTERNAL_VOLTAGE_ADJUST  0x00028147ul
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA       0x00028200ul
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET      0x00028301ul
+#define AGESA_GNB_GFX_GET_VBIOS_IMAGE  0x00028302ul
+
+// AGESA FCH CALLOUTS
+#define AGESA_FCH_OEM_CALLOUT          0x00028401ul
+
+//------------------------------------------------------------------------
+//
+// HyperTransport Interface
+
+
+
+//-----------------------------------------------------------------------------
+//                         HT DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+
+// Width equates for call backs
+#define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
+#define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
+#define HT_WIDTH_4_BITS              4
+#define HT_WIDTH_2_BITS              2
+#define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
+
+// Frequency Limit equates for call backs which take a frequency supported mask.
+#define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2800M     0x27FFFul                   ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M     0x67FFFul                   ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M     0xE7FFFul                   ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M     0x1E7FFFul
+#define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
+#define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFFul                ///< Specifies a no limit of HT frequency.
+
+// Unit ID Clumping special values
+#define HT_CLUMPING_DISABLE          0x00000000ul
+#define HT_CLUMPING_NO_LIMIT         0xFFFFFFFFul
+
+#define HT_LIST_TERMINAL             0xFF             ///< End of list.
+#define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
+#define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
+
+// Event Notify definitions
+
+// Event definitions.
+
+// Coherent subfunction events
+#define HT_EVENT_COH_EVENTS             0x10001000ul
+#define HT_EVENT_COH_NO_TOPOLOGY        0x10011000ul    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000        0x10021000ul    //   No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000ul    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED    0x10041000ul    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000ul    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+
+// Non-coherent subfunction events
+#define HT_EVENT_NCOH_EVENTS         0x10002000ul
+#define HT_EVENT_NCOH_BUID_EXCEED    0x10012000ul       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000    0x10022000ul       //   No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000ul       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000ul       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000ul       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000ul       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+
+// Optimization subfunction events
+#define HT_EVENT_OPT_EVENTS               0x10003000ul
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000ul  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000ul  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS         0x10033000ul  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000ul  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+
+// HW Fault events
+#define HT_EVENT_HW_EVENTS           0x10004000ul
+#define HT_EVENT_HW_SYNCFLOOD        0x10014000ul       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC            0x10024000ul       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+
+// The Recovery HT component uses 0x10005000 for events.
+// For consistency, we avoid that range here.
+
+#define HT_MAX_NC_BUIDS 32
+//----------------------------------------------------------------------------
+//                         HT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// Specify the state redundant links are to be left in after match.
+///
+/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
+/// or powered off.
+
+typedef enum {
+  MATCHED,                               ///< The link matches the requested customization.
+                                         ///< When used with IGNORE_LINK,
+                                         ///< this will generally require other software to initialize the link.
+                                         ///< When used with SKIP_REGANG,
+                                         ///< the two unganged links will be available for distribution.
+
+  POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
+                                         ///< Power Off is only supported for coherent links.
+                                         ///< Link power off may occur at a warm reset rather than immediately.
+                                         ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
+
+  UNMATCHED,                             ///< The link should be processed according to normal defaults.
+                                         ///< Effectively, the link does not match the requested customization.
+                                         ///< This can be used to exclude links from a following match any.
+
+  MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
+} FINAL_LINK_STATE;
+
+/// Swap a device from its current id to a new one.
+
+typedef struct {
+  IN       UINT8 FromId;                 ///< The device responding to FromId,
+  IN       UINT8 ToId;                   ///< will be moved to ToId.
+} BUID_SWAP_ITEM;
+
+
+/// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+/// the final in order list of device ids is provided. (There can be more swaps than devices.)
+/// The unused entries in both are filled with 0xFF.
+
+typedef struct {
+  IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
+  IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
+} BUID_SWAP_LIST;
+
+
+/// Control Manual Initialization of Non-Coherent Chains
+///
+/// This interface is checked every time a non-coherent chain is
+/// processed.  BUID assignment may be controlled explicitly on a
+/// non-coherent chain. Provide a swap list.  Swaps controls the
+/// BUID assignment and FinalIds provides the device to device
+/// Linking.  Device orientation can be detected automatically, or
+/// explicitly.  See interface documentation for more details.
+///
+/// If a manual swap list is not supplied,
+/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+/// based on each device's unit count.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                       ///< The Socket on which this chain is located
+  IN       UINT8 Link;                         ///< The Link on the host for this chain
+  // Override fields
+  IN       BUID_SWAP_LIST SwapList;            ///< The swap list
+} MANUAL_BUID_SWAP_LIST;
+
+
+/// Override options for DEVICE_CAP_OVERRIDE.
+///
+/// Specify which override actions should be performed.  For Checks, 1 means to check the item
+/// and 0 means to skip the check.  For the override options, 1 means to apply the override and
+/// 0 means to ignore the override.
+
+typedef struct {
+  IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
+  IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
+  IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
+  IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
+  IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
+  IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
+  IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
+} DEVICE_CAP_OVERRIDE_OPTIONS;
+
+/// Override capabilities of a device.
+///
+/// This interface is checked once for every Link on every IO device.
+/// Provide the width and frequency capability if needed for this device.
+/// This is used along with device capabilities, the limit interfaces, and northbridge
+/// limits to compute the default settings.  The components of the device's PCI config
+/// address are provided, so its settings can be consulted if need be.
+/// The optional callout is a catch all.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
+  // Override fields
+  IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
+  IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
+  IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
+  IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
+  IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
+} DEVICE_CAP_OVERRIDE;
+
+/// Callout param struct for override capabilities of a device.
+///
+/// If the optional callout is implemented this param struct is passed to it.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
+  // Override fields
+     OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
+     OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
+     OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
+     OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
+} DEVICE_CAP_CALLOUT_PARAMS;
+
+///  Limits for CPU to CPU Links.
+///
+///  For each coherent connection this interface is checked once.
+///  Provide the frequency and width if needed for this Link (usually based on board
+///  restriction).  This is used with CPU device capabilities and northbridge limits
+///  to compute the default settings.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Limit fields
+  IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
+  IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
+  IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
+} CPU_TO_CPU_PCB_LIMITS;
+
+///  Get limits for non-coherent Links.
+///
+/// For each non-coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction).  This is used with device capabilities, device overrides, and northbridge limits
+/// to compute the default settings.
+///
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
+  IN       UINT8 HostLink;                 ///< The Link about to be initialized
+  IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
+  // Limit fields
+  IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
+  IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
+  IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
+} IO_PCB_LIMITS;
+
+///  Manually control bus number assignment.
+///
+/// This interface is checked every time a non-coherent chain is processed.
+/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
+/// assignments, this interface can provide explicit control.  For each chain, provide
+/// the bus number range to use.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this chain is located
+  IN       UINT8 Link;                   ///< The Link on the host for this chain
+  // Override fields
+  IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
+  IN       UINT8 SubBus;                 ///< Subordinate Bus number
+} OVERRIDE_BUS_NUMBERS;
+
+
+///  Ignore a Link.
+///
+///  This interface is checked every time a coherent Link is found and then every
+///  time a non-coherent Link from a CPU is found.
+///  Any coherent or non-coherent Link from a CPU can be ignored and not used
+///  for discovery or initialization.  Useful for connection based systems.
+///  (Note: not checked for IO device to IO Device Links.)
+///  (Note: not usable for internal links (MCM processors).)
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this Link is located
+  IN       UINT8 Link;                   ///< The Link about to be initialized
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
+} IGNORE_LINK;
+
+
+///  Skip reganging of subLinks.
+///
+///  This interface is checked whenever two subLinks are both connected to the same CPUs.
+///  Normally, unganged sublinks between the same two CPUs are reganged.
+///  Provide a matching structure to leave the Links unganged.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
+} SKIP_REGANG;
+
+///  The System Socket layout, which sockets are physically connected.
+///
+///  The hardware method for Socket naming is preferred.  Use this software method only
+///  if required.
+
+typedef struct {
+  IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
+  IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
+  IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
+} SYSTEM_PHYSICAL_SOCKET_MAP;
+
+//----------------------------------------------------------------------------
+///
+/// This is the input structure for AmdHtInitialize.
+///
+typedef struct {
+  // Basic level customization
+  IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
+                                         ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
+  IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
+                                         ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
+  IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
+                                         ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUM}
+
+  // Advanced Level Customization
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
+                                                          ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+  IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
+  IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
+                                                          ///< Use either auto bus numbering or override bus
+                                                          ///< numbers, not both.
+                                                          ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
+
+  IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
+                                                          ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
+  IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
+                                                          ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
+                                                          ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
+
+  // Expert Level Customization
+  IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
+                                                     ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
+  IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
+                                                     ///< The hardware socket naming method is preferred,
+                                                     ///<  If it can't be used, this provides a software method.
+                                                     ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
+} AMD_HT_INTERFACE;
+
+//-----------------------------------------------------------------------------
+//
+// HT Recovery Interface
+//
+
+
+/*-----------------------------------------------------------------------------
+ *              HT Recovery DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+// BBHT subfunction events
+#define HT_EVENT_BB_EVENTS         0x10005000ul
+#define HT_EVENT_BB_BUID_EXCEED    0x10015000ul
+#define HT_EVENT_BB_DEVICE_FAILED  0x10055000ul
+#define HT_EVENT_BB_AUTO_DEPTH     0x10065000ul
+
+/*----------------------------------------------------------------------------
+ *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/// The Interface structure to Recovery HT.
+
+typedef struct {
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
+                                                       ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+     OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
+                                   ///< else, for manual init unmodified.
+} AMD_HT_RESET_INTERFACE;
+
+
+//-----------------------------------------------------------------------------
+//                     FCH DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+/// Configuration values for SdConfig
+typedef enum {
+  SdDisable = 0,                      ///< Disabled
+  SdAmda,                             ///< AMDA,  set 24,18,16,  default
+  SdDma,                              ///< DMA clear 24, 16, set 18
+  SdPio                               ///< PIO clear 24,18,16
+} SD_MODE;
+
+/// Configuration values for SdClockControl
+typedef enum {
+  Sd50MhzTraceCableLengthWithinSixInches = 4,           ///< 50Mhz, default
+  Sd40MhzTraceCableLengthSix2ElevenInches = 6,          ///< 40Mhz
+  Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7,   ///< 25Mhz
+} SD_CLOCK_CONTROL;
+
+/// Configuration values for IrConfig
+typedef enum {
+  IrDisable  = 0,                     ///< Disable
+  IrRxTx0    = 1,                     ///< Rx and Tx0
+  IrRxTx1    = 2,                     ///< Rx and Tx1
+  IrRxTx0Tx1 = 3                      ///< Rx and both Tx0,Tx1
+} IR_CONFIG;
+
+/// Configuration values for SataClass
+typedef enum {
+  SataNativeIde = 0,                  ///< Native IDE mode
+  SataRaid,                           ///< RAID mode
+  SataAhci,                           ///< AHCI mode
+  SataLegacyIde,                      ///< Legacy IDE mode
+  SataIde2Ahci,                       ///< IDE->AHCI mode
+  SataAhci7804,                       ///< AHCI mode as 7804 ID (AMD driver)
+  SataIde2Ahci7804                    ///< IDE->AHCI mode as 7804 ID (AMD driver)
+} SATA_CLASS;
+
+/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
+typedef enum {
+  PortA4       = 0,                   ///< 4:0:0:0
+  PortA2B2     = 2,                   ///< 2:2:0:0
+  PortA2B1C1   = 3,                   ///< 2:1:1:0
+  PortA1B1C1D1 = 4                    ///< 1:1:1:1
+} GPP_LINKMODE;
+
+/// Configuration values for FchPowerFail
+typedef enum {
+  AlwaysOff   = 0,                    ///< Always power off after power resumes
+  AlwaysOn    = 1,                    ///< Always power on after power resumes
+  UsePrevious = 3,                    ///< Resume to same setting when power fails
+} POWER_FAIL;
+
+
+/// Configuration values for SATA Link Speed
+typedef enum {
+  Gen1   = 1,                         ///< SATA port GEN1 speed
+  Gen2   = 2,                         ///< SATA port GEN2 speed
+  Gen3   = 3,                         ///< SATA port GEN3 speed
+} SATA_SPEED;
+
+
+/// Configuration values for GPIO function
+typedef enum {
+  Function0   = 0,                    ///< GPIO Function 1
+  Function1   = 1,                    ///< GPIO Function 1
+  Function2   = 2,                    ///< GPIO Function 2
+  Function3   = 3,                    ///< GPIO Function 3
+} GPIO_FUN;
+
+
+/// Configuration values for GPIO_CFG
+typedef enum {
+  OwnedByEc   = 1 << 0,               ///< This bit can only be written by EC
+  OwnedByHost = 1 << 1,               ///< This bit can only be written by host (BIOS)
+  Sticky      = 1 << 2,               ///< If set, [6:3] are sticky
+  PullUpB     = 1 << 3,               ///< 0: Pullup enable; 1: Pullup disabled
+  PullDown    = 1 << 4,               ///< 0: Pulldown disabled; 1: Pulldown enable
+  GpioOutEnB  = 1 << 5,               ///< 0: Output enable; 1: Output disable
+  GpioOut     = 1 << 6,               ///< Output state when GpioOutEnB is 0
+  GpioIn      = 1 << 7,               ///< This bit is read only - current pin state
+} CFG_BYTE;
+
+/// FCH GPIO CONTROL
+typedef struct {
+  IN         UINT8        GpioPin;               ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
+  IN         GPIO_FUN     PinFunction;           ///< Multi-function selection
+  IN         CFG_BYTE     CfgByte;               ///< GPIO Register value
+} GPIO_CONTROL;
+
+///
+/// FCH SCI MAP CONTROL
+///
+typedef struct {
+  IN         UINT8        InputPin;              ///< Input Pin, valid range 0-63
+  IN         UINT8        GpeMap;                ///< Gpe Map, valid range 0-31
+} SCI_MAP_CONTROL;
+
+///
+/// FCH SATA PHY CONTROL
+///
+typedef struct {
+  IN         BOOLEAN      CommonPhy;             ///< Common PHY or not
+                                      ///<   @li <b>FALSE</b> - Only applied to specified port
+                                      ///<   @li <b>TRUE</b>  - Apply to all SATA ports
+  IN         SATA_SPEED   Gen;                   ///< SATA speed
+  IN         UINT8        Port;                  ///< Port number, valid range: 0-7
+  IN         UINT32       PhyData;               ///< SATA PHY data, valid range: 0-0xFFFFFFFF
+} SATA_PHY_CONTROL;
+
+///
+/// FCH Component Data Structure in InitReset stage
+///
+typedef struct {
+  IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
+                                             ///<   @li <b>FALSE</b> - Disable Gen2
+                                             ///<   @li <b>TRUE</b>  - Enable Gen2
+
+  IN       BOOLEAN      SataEnable;          ///< SATA controller function
+                                             ///<   @li <b>FALSE</b> - SATA controller is disabled
+                                             ///<   @li <b>TRUE</b> - SATA controller is enabled
+
+  IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
+                                             ///<   @li <b>FALSE</b> - IDE controller is disabled
+                                             ///<   @li <b>TRUE</b> - IDE controller is enabled
+
+  IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
+                                             ///<   @li <b>FALSE</b> - GPP disabled
+                                             ///<   @li <b>TRUE</b> - GPP enabled
+
+  IN       BOOLEAN      Xhci0Enable;         ///< XHCI0 controller function
+                                             ///<   @li <b>FALSE</b> - XHCI0 controller disabled
+                                             ///<   @li <b>TRUE</b> - XHCI0 controller enabled
+
+  IN       BOOLEAN      Xhci1Enable;         ///< XHCI1 controller function
+                                             ///<   @li <b>FALSE</b> - XHCI1 controller disabled
+                                             ///<   @li <b>TRUE</b> - XHCI1 controller enabled
+} FCH_RESET_INTERFACE;
+
+
+///
+/// FCH Component Data Structure from InitEnv stage
+///
+typedef struct {
+  IN       SD_MODE      SdConfig;            ///< Secure Digital (SD) controller mode
+  IN       UINT8        AzaliaController;
+
+  IN       IR_CONFIG    IrConfig;            ///< Infrared (IR) Configuration
+  IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
+                                             ///<   @li <b>FALSE</b> - Disable Gen2
+                                             ///<   @li <b>TRUE</b>  - Enable Gen2
+
+  IN       SATA_CLASS   SataClass;           ///< SATA controller mode
+  IN       BOOLEAN      SataEnable;          ///< SATA controller function
+                                             ///<   @li <b>FALSE</b> - SATA controller is disabled
+                                             ///<   @li <b>TRUE</b> - SATA controller is enabled
+
+  IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
+                                             ///<   @li <b>FALSE</b> - IDE controller is disabled
+                                             ///<   @li <b>TRUE</b> - IDE controller is enabled
+
+  IN       BOOLEAN      SataIdeMode;         ///< Native mode of SATA IDE controller
+                                             ///<   @li <b>FALSE</b> - Legacy IDE mode
+                                             ///<   @li <b>TRUE</b> - Native IDE mode
+
+  IN       BOOLEAN      Ohci1Enable;         ///< OHCI controller #1 Function
+                                             ///<   @li <b>FALSE</b> - OHCI1 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI1 is enabled
+
+  IN       BOOLEAN      Ohci2Enable;         ///< OHCI controller #2 Function
+                                             ///<   @li <b>FALSE</b> - OHCI2 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI2 is enabled
+
+  IN       BOOLEAN      Ohci3Enable;         ///< OHCI controller #3 Function
+                                             ///<   @li <b>FALSE</b> - OHCI3 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI3 is enabled
+
+  IN       BOOLEAN      Ohci4Enable;         ///< OHCI controller #4 Function
+                                             ///<   @li <b>FALSE</b> - OHCI4 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI4 is enabled
+
+  IN       BOOLEAN      XhciSwitch;          ///< XHCI controller Function
+                                             ///<   @li <b>FALSE</b> - XHCI is disabled
+                                             ///<   @li <b>TRUE</b> - XHCI is enabled
+
+  IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
+                                             ///<   @li <b>FALSE</b> - GPP disabled
+                                             ///<   @li <b>TRUE</b> - GPP enabled
+
+  IN       POWER_FAIL   FchPowerFail;        ///< FCH power failure option
+} FCH_INTERFACE;
+
+
+/*----------------------------------------------------------------------------
+ *   CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+
+/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+typedef enum {
+  C1eModeDisabled                   = 0,   ///< Disabled
+  C1eModeAuto                       = 1,   ///< Auto mode enables the best C1e method for the
+                                           ///< currently installed processor
+  C1eModeHardware                   = 2,   ///< Hardware method
+  C1eModeMsgBased                   = 3,   ///< Message-based method
+  C1eModeSoftwareDeprecated         = 4,   ///< Deprecated software SMI method.
+                                           ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
+                                           ///< example host BIOS SMM Handler implementation
+  C1eModeHardwareSoftwareDeprecated = 5,   ///< Hardware or deprecated software SMI method
+  MaxC1eMode                        = 6    ///< Not a valid value, used for verifying input
+} PLATFORM_C1E_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+  CStateModeDisabled = 0,           ///< Disabled
+  CStateModeC6       = 1,           ///< C6 State
+  MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+  CpbModeAuto     = 0,           ///< Auto
+  CpbModeDisabled = 1,           ///< Disabled
+  MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
+typedef enum {
+  LOW_POWER_PSTATE_FOR_PROCHOT_AUTO      = 0,           ///< Auto
+  LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE   = 1,           ///< Disabled
+  MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE  = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_LOW_POWER_PSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY
+#define PsdPolicyProcessorDefault  0       ///< PSD is dependent or independent per processor default
+#define PsdPolicyDependent         1       ///< PSD is forced dependent
+#define PsdPolicyIndependent       2       ///< PSD is forced independent
+#define PsdPolicyMax               3       ///< Not a valid value, used for verifying input
+
+/*----------------------------------------------------------------------------
+ *   GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+#define GNB_EVENT_INVALID_CONFIGURATION               0x20010000ul   // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul   // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002ul   // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003ul   // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004ul   // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005ul   // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006ul   // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000ul   // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000ul   // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000ul   // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
+#define DESCRIPTOR_IGNORE                   0x40000000ull
+
+/// PCIe link initialization
+typedef enum {
+  EndpointDetect = 0,                                     ///< Detect endpoint presence
+  EndpointNotPresent                                      ///< Endpoint not present (or connected). Used in case there is alternative way to determine
+                                                          ///< if device present on board or in slot. For example GPIO can be used to determine device presence.
+} PCIE_ENDPOINT_STATUS;
+
+
+/// PCIe port misc extended controls
+typedef struct  {
+  IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+  IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+                                                             *  @li @b 0 - port can advertize muximum supported capability
+                                                             *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+                                                             */
+  IN      UINT8                     SbLink             :1;  /**< PCIe link type
+                                                             *  @li @b 0 - General purpose port
+                                                             *  @li @b 1 - Port connected to SB
+                                                             */
+  IN      UINT8                     ClkPmSupport       :1;  /**< Clock Power Management Support
+                                                             *  @li @b 0 - Clock Power Management not configured
+                                                             *  @li @b 1 - Clock Power Management configured according to PCIe device capability
+                                                             */
+} PCIe_PORT_MISC_CONTROL;
+
+/// The IO APIC Interrupt Mapping Info
+typedef struct {
+  IN      UINT8                     GroupMap;               /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
+                                                             *  @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS
+                                                             *  @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3   of IO APIC redirection table)
+                                                             *  @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7   of IO APIC redirection table)
+                                                             *  @li ...
+                                                             *  @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
+                                                             */
+  IN      UINT8                     Swizzle;                /**< Swizzle interrupt in the Group.
+                                                             *  @li <b>0</b> - ABCD
+                                                             *  @li <b>1</b> - BCDA
+                                                             *  @li <b>2</b> - CDAB
+                                                             *  @li <b>3</b> - DABC
+                                                             */
+  IN      UINT8                     BridgeInt;              /**< IOAPIC redirection table entry for PCIE bridge interrupt
+                                                             *  @li <b>0</b>  - Entry 0  of IO APIC redirection table
+                                                             *  @li <b>1</b>  - Entry 1  of IO APIC redirection table
+                                                             *  @li ...
+                                                             *  @li <b>31</b> - Entry 31 of IO APIC redirection table
+                                                             */
+} APIC_DEVICE_INFO;
+
+/// PCIe port configuration data
+typedef struct  {
+  IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
+  IN       UINT8                   ChannelType;              /**< Channel type.
+                                                               *  @li @b 0 - "lowLoss",
+                                                               *  @li @b 1 - "highLoss",
+                                                               *  @li @b 2 - "mob0db",
+                                                               *  @li @b 3 - "mob3db",
+                                                               *  @li @b 4 - "extnd6db"
+                                                               *  @li @b 5 - "extnd8db"
+                                                               */
+  IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
+                                                               *   @li @b 0 - Native port device number
+                                                               *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14ONLaneConfigurations "Family 0x14(ON)")
+                                                               */
+  IN       UINT8                   FunctionNumber;           ///< Reserved for future use
+  IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
+                                                               *  @li @b 0 - Maximum supported by silicon
+                                                               *  @li @b 1 - Gen1
+                                                               *  @li @b 2 - Gen2
+                                                               *  @li @b 3 - Gen3
+                                                               */
+  IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - L0s only
+                                                               *  @li @b 2 - L1 only
+                                                               *  @li @b 3 - L0s and L1
+                                                               */
+  IN       UINT8                   LinkHotplug;              /**< Hotplug control.
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - Basic
+                                                               *  @li @b 2 - Server
+                                                               *  @li @b 3 - Enhanced
+                                                               */
+  IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                               *   identification which control reset for given port.
+                                                               *   Each port with unique GPIO should have unique ResetId assigned.
+                                                               *   All ports use same GPIO to control reset should have same ResetId assigned.
+                                                               *   see AgesaPcieSlotResetContol.
+                                                               */
+  IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
+  IN       APIC_DEVICE_INFO        ApicDeviceInfo;           ///< IOAPIC device programming info
+  IN       PCIE_ENDPOINT_STATUS    EndpointStatus;           ///< PCIe endpoint (device connected to PCIe port) status
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct {                                          ///< Structure that discribe lane mapping
+  IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
+                                                           *  @li @b 0 - Map to lane 0
+                                                           *  @li @b 1 - Map to lane 1
+                                                           *  @li @b 2 - Map to lane 2
+                                                           *  @li @b 2 - Map to lane 3
+                                                           */
+  IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING;                                        ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+  IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
+  IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct  {
+  IN       UINT8                ConnectorType;            /**< Display Connector Type
+                                                            *  @li @b 0 - DP
+                                                            *  @li @b 1 - eDP
+                                                            *  @li @b 2 - Single Link DVI-D
+                                                            *  @li @b 3 - Dual  Link DVI-D
+                                                            *  @li @b 4 - HDMI
+                                                            *  @li @b 5 - DP-to-VGA
+                                                            *  @li @b 6 - DP-to-LVDS
+                                                            *  @li @b 8 - Single Link DVI-I
+                                                            *  @li @b 9 - Native CRT (Family 0x14)
+                                                            *  @li @b 10 - Native LVDS (Family 0x14)
+                                                            *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or DP-to-LVDS
+                                                            *              The auto detection method only support panel with EDID.
+                                                            */
+  IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
+                                                            *  @li @b 0 - AUX1
+                                                            *  @li @b 1 - AUX2
+                                                            *  @li @b 2 - AUX3
+                                                            *  @li @b 3 - AUX4
+                                                            *  @li @b 4 - AUX5
+                                                            *  @li @b 5 - AUX6
+                                                            */
+  IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
+                                                            *  @li @b 0 - HDP1
+                                                            *  @li @b 1 - HDP2
+                                                            *  @li @b 2 - HDP3
+                                                            *  @li @b 3 - HDP4
+                                                            *  @li @b 4 - HDP5
+                                                            *  @li @b 5 - HDP6
+                                                            */
+  IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
+                                                            *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+                                                            *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+                                                            *  if Mapping[x] set to 0 than default mapping assumed
+                                                            */
+  IN       UINT8                LanePnInversionMask;      /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
+                                                            *  @li 0 - Do not invert (default)
+                                                            *  @li 1 - Invert P and N on this lane
+                                                            */
+  IN       UINT8                Flags;                    /**< Capabilities flags
+                                                            *  @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
+                                                            *  @li Flags bit[7:1] Reserved
+                                                            */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+  IN       UINT8                EngineType;               /**< Engine type
+                                                           *  @li @b 0 -  Ignore engine configuration
+                                                           *  @li @b 1 -  PCIe port
+                                                           *  @li @b 2 -  DDI
+                                                           */
+  IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12"
+                                                           * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14ONLaneConfigurations "Family 0x14(ON)".
+                                                           */
+  IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12",
+                                                           * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14ONLaneConfigurations "Family 0x14(ON)".
+                                                           */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in topology
+                                                           */
+  IN       UINT32               SocketId;                 ///< Socket Id
+  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       VOID                 *Reserved;                ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+  AssertSlotReset,                                        ///< Assert slot reset
+  DeassertSlotReset                                       ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
+  IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+#define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST  0x1
+
+///VBIOS image info
+typedef struct {
+  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
+  OUT     VOID                  *ImagePtr;                ///< Pointer to VBIOS image
+  IN      PCI_ADDR              GfxPciAddress;            ///< PCI address of integrated graphics controller
+  IN      UINT32                Flags;                    ///< BIT[0] - special repost requred
+} GFX_VBIOS_IMAGE_INFO;
+
+/// Engine descriptor type
+typedef enum {
+  PcieUnusedEngine = 0,                                   ///< Unused descriptor
+  PciePortEngine = 1,                                     ///< PCIe port
+  PcieDdiEngine = 2,                                      ///< DDI
+  MaxPcieEngine                                           ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum  {
+  PcieGenMaxSupported,                                    ///< Maximum supported
+  PcieGen1 = 1,                                           ///< Gen1
+  PcieGen2,                                               ///< Gen2
+  PcieGen3,                                               ///< Gen3
+  MaxPcieGen                                              ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum  {
+  PsppDisabled,                                           ///< PSPP disabled
+  PsppPerformance = 1,                                    ///< Performance
+  PsppBalanceHigh,                                        ///< Balance-High
+  PsppBalanceLow,                                         ///< Balance-Low
+  PsppPowerSaving,                                        ///< Power Saving
+  MaxPspp                                                 ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+  ConnectorTypeDP,                                        ///< DP
+  ConnectorTypeEDP,                                       ///< eDP
+  ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
+  ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
+  ConnectorTypeHDMI,                                      ///< HDMI
+  ConnectorTypeDpToVga,                                   ///< DP-to-VGA
+  ConnectorTypeDpToLvds,                                  ///< DP-to-LVDS
+  ConnectorTypeStub,
+  ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
+  ConnectorTypeCrt,                                       ///< CRT (VGA)
+  ConnectorTypeLvds,                                      ///< LVDS
+  ConnectorTypeEDPToLvds,                                 ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init
+  ConnectorTypeEDPToLvdsSwInit,                           ///< 3rd party eDP-to-LVDS translator which requires AMD SW init
+  ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS)
+  MaxConnectorType                                        ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+  ChannelTypeLowLoss,                                     ///< Low Loss
+  ChannelTypeHighLoss,                                    ///< High Loss
+  ChannelTypeMob0db,                                      ///< Mobile 0dB
+  ChannelTypeMob3db,                                      ///< Mobile 3dB
+  ChannelTypeExt6db,                                      ///< Extended 6dB
+  ChannelTypeExt8db,                                      ///< Extended 8dB
+  MaxChannelType                                          ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+  AspmDisabled,                                           ///< Disabled
+  AspmL0s,                                                ///< PCIe L0s link state
+  AspmL1,                                                 ///< PCIe L1 link state
+  AspmL0sL1,                                              ///< PCIe L0s & L1 link state
+  MaxAspm                                                 ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+  HotplugDisabled,                                        ///< Hotplug disable
+  HotplugBasic,                                           ///< Basic Hotplug
+  HotplugServer,                                          ///< Server Hotplug
+  HotplugEnhanced,                                        ///< Enhanced
+  HotplugInboard,                                         ///< Inboard
+  MaxHotplug                                              ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+  PortDisabled,                                           ///< Disable
+  PortEnabled                                             ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// PCIe ACS capability - Access Control Services
+typedef enum  {
+  PcieAcsDisabled,                                        ///< Disabled
+  PcieAcsEnabled,                                         ///< Enabled
+} PCIE_ACS_CAP;
+
+/// PCIe ClkPmSupport initialization
+typedef enum {
+  ClkPmSupportDisabled,                                   ///< Disable
+  ClkPmSupportEnabled                                     ///< Enable
+} CLKPM_SUPPORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+  Aux1,                                                   ///< Aux1
+  Aux2,                                                   ///< Aux2
+  Aux3,                                                   ///< Aux3
+  Aux4,                                                   ///< Aux4
+  Aux5,                                                   ///< Aux5
+  Aux6,                                                   ///< Aux6
+  MaxAux                                                  ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+  Hdp1,                                                   ///< Hdp1
+  Hdp2,                                                   ///< Hdp2
+  Hdp3,                                                   ///< Hdp3
+  Hdp4,                                                   ///< Hdp4
+  Hdp5,                                                   ///< Hdp5
+  Hdp6,                                                   ///< Hdp6
+  MaxHdp                                                  ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+/// PCIe_DDI_DATA.Flags definitions
+#define DDI_DATA_FLAGS_DP1_1_ONLY   0x01                  ///< BIT[0] Selects downgrade PHY link to DP1.1
+#define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02         ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training
+/// DP receiver definitions with fixed voltage swing
+typedef enum {
+  DP_VS_0_4V_0DB,                                         ///< 0x00
+  DP_VS_0_6V_0DB,                                         ///< 0x01
+  DP_VS_0_8V_0DB,                                         ///< 0x02
+  DP_VS_1_2V_0DB,                                         ///< 0x03
+  DP_VS_0_4V_3_5DB = 0x8,                                 ///< 0x08
+  DP_VS_0_6V_3_5DB,                                       ///< 0x09
+  DP_VS_0_8V_3_5DB,                                       ///< 0x0a
+  DP_VS_0_4V_6DB = 0x10,                                  ///< 0x10
+  DP_VS_0_6V_6DB,                                         ///< 0x11
+  DP_VS_0_4V_9_5DB = 0x18                                 ///< 0x18
+} DP_FIXED_VOLT_SWING_TYPE;
+
+// Macro for statically initialization of various structures
+#define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect}
+#define  PCIE_PORT_DATA_INITIALIZER_V2(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect}
+#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0}
+#define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0}
+#define  PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags}
+
+///IOMMU requestor ID
+typedef struct {
+  IN       UINT16     Bus       :8;                                ///< Bus
+  IN       UINT16     Device    :5;                                ///< Device
+  IN       UINT16     Function  :3;                                ///< Function
+} IOMMU_REQUESTOR_ID;
+
+/// IVMD exclusion range descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Flags[31] - Terminate descriptor array.
+                                                           * @li @b Flags[30] - Ignore descriptor.
+                                                           */
+  IN       IOMMU_REQUESTOR_ID   RequestorIdStart;         ///< Requestor ID start
+  IN       IOMMU_REQUESTOR_ID   RequestorIdEnd;           ///< Requestor ID end (use same as start for single ID)
+  IN       UINT64               RangeBaseAddress;         ///< Phisical base address of exclusion range
+  IN       UINT64               RangeLength;              ///< Length of exclusion range in bytes
+} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
+
+/*----------------------------------------------------------------------------
+ *   GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// LVDS Misc Control Field
+typedef struct {
+  IN  UINT8     FpdiMode:1;          ///< This item configures LVDS 888bit panel mode
+                                     ///< @li FALSE = LVDS 888 panel in LDI mode
+                                     ///< @li TRUE =  LVDS 888 panel in FPDI mode
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+  IN  UINT8     DlChSwap:1;          ///< This item configures LVDS panel lower and upper link mapping
+                                     ///< @li FALSE = Lower link and upper link not swap
+                                     ///< @li TRUE = Lower link and upper link are swapped
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+  IN  UINT8     VsyncActiveLow:1;    ///< This item configures polarity of frame pulse encoded in lvds data stream
+                                     ///< @li FALSE = Active high Frame Pulse/Vsync
+                                     ///< @li TRUE = Active low Frame Pulse/Vsync
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
+  IN  UINT8     HsyncActiveLow:1;    ///< This item configures polarity of line pulse encoded in lvds data
+                                     ///< @li FALSE = Active high Line Pulse
+                                     ///< @li TRUE = Active low Line Pulse / Hsync
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
+  IN  UINT8     BLONActiveLow:1;     ///< This item configures polarity of signal sent to digital BLON output pin
+                                     ///< @li FALSE = Not inverted(active high)
+                                     ///< @li TRUE = Inverted (active low)
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+  IN  UINT8     LvdsVoltOverwriteEn:1;  ///< This item configures polarity of DP-to-LVDS output voltage overwrite
+                                        ///< @li FALSE = DP-to-LVDS output voltage overwrite disable, use VBIOS default setting.
+                                        ///< @li TRUE = Use ucLVDSVolAdjust value to program register LVDS_CTRL_4
+                                        ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE}
+  IN  UINT8     Reserved:2;          ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+  IN LVDS_MISC_CONTROL_FIELD Field;  ///< LVDS_MISC_CONTROL_FIELD
+  IN UINT8   Value;                  ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
+/// Display Misc Control Field
+typedef struct {
+  IN  UINT8     Reserved1:3;                  ///< Reserved
+  IN  UINT8     VbiosFastBootEn:1;            ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open.
+                                              ///< @li FALSE = VBIOS fast boot is disable.
+                                              ///< @li TRUE = VBIOS fast boot is enable.
+                                              ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE}
+  IN  UINT8     Reserved2:4;                  ///< Reserved
+} DISPLAY_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _DISPLAY_MISC_CONTROL {
+  IN DISPLAY_MISC_CONTROL_FIELD Field;  ///< DISPLAY_MISC_CONTROL_FIELD
+  IN UINT8   Value;                     ///< Display Misc Control Value
+} DISPLAY_MISC_CONTROL;
+
+/// POST Configuration settings for GNB.
+typedef struct {
+  IN UINT8       IgpuEnableDisablePolicy;   ///< This item defines the iGPU Enable/Disable policy
+                                            ///< @li 0 = Auto - use existing default -
+                                            ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present
+                                            ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+} GNB_POST_CONFIGURATION;
+
+/// iGPU Enable/Disable Policy values
+#define IGPU_DISABLE_AUTO        0        ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
+#define IGPU_DISABLE_ANY_PCIE    1        ///< Disable iGPU if any PCI or PCIE graphics card is present
+
+/// ENV Configuration settings for GNB.
+typedef struct {
+  IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
+                                          ///< @li 0 = Stereo 3D is disabled (default).
+                                          ///< @li 1 = Use processor pin HPD1.
+                                          ///< @li 2 = Use processor pin HPD2
+                                          ///< @li 3 = Use processor pin HPD3
+                                          ///< @li 4 = Use processor pin HPD4
+                                          ///< @li 5 = Use processor pin HPD5
+                                          ///< @li 6 = Use processor pin HPD6
+                                          ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+  IN  BOOLEAN    IommuSupport;            ///< IOMMU support.
+                                          ///< @li FALSE = Disabled. Disable and hide IOMMU device.
+                                          ///< @li TRUE  = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+                                          ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
+  IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN  UINT8      LvdsPowerOnSeqDigonToDe;    ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
+  IN  UINT8      LvdsPowerOnSeqDeToVaryBl;   ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
+  IN  UINT8      LvdsPowerOnSeqDeToDigon;    ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
+  IN  UINT8      LvdsPowerOnSeqVaryBlToDe;   ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
+  IN  UINT8      LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
+  IN  UINT8      LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
+  IN  UINT8      LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
+  IN  UINT16     LvdsMaxPixelClockFreq;      ///< This item configures the maximum pixel clock frequency supported.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
+  IN  UINT32     LcdBitDepthControlValue;    ///< This item configures the LCD bit depth control settings.
+                                             ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
+  IN  UINT8      Lvds24bbpPanelMode;         ///< This item configures the LVDS 24 BBP mode.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
+  IN  LVDS_MISC_CONTROL      LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+  IN  UINT16     PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
+                                             ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+  IN  BOOLEAN    GnbRemoteDisplaySupport;    ///< This item enables Wireless Display Support
+                                             ///< @li TRUE  = Enable Wireless Display Support
+                                             ///< @li FALSE = Disable Wireless Display Support
+                                             ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
+  IN UINT8       LvdsMiscVoltAdjustment;     ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+                                             ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+  IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control
+  IN DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType;///< To indicate fixed voltage swing value
+                                                   ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+} GNB_ENV_CONFIGURATION;
+
+/// Configuration settings for GNB.
+typedef struct {
+  IN  UINT8     iGpuVgaMode;                 ///< VGA resources decoding configuration for iGPU
+                                             ///< @li 0 = iGPU decode all VGA resources (must be primary VGA adapter)
+                                             ///< @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter)
+  IN  UINT8     PcieAcsCapability;           ///< Pcie ACS Capability support
+                                             ///< @li 0 = Disabled
+                                             ///< @li 1 = Enabled
+  IN  UINT64    GnbIoapicAddress;            ///< GNB IOAPIC Base Address(NULL if platform configured)
+                                             ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+} GNB_MID_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+                                                        * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
+                                                        * Example of topology definition for single socket system:
+                                                        * @code
+                                                        *  PCIe_PORT_DESCRIPTOR PortList [] = {
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    }
+                                                        *  };
+                                                        *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+                                                        *    },
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+                                                        *    }
+                                                        *  };
+                                                        * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+                                                        *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
+                                                        *   0,  //Socket ID
+                                                        *   &PortList[0],
+                                                        *   &DdiList[0],
+                                                        * }
+                                                        * @endcode
+                                                        */
+  IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
+                                                         *  @li @b 0 - Disabled
+                                                         *  @li @b 1 - Performance
+                                                         *  @li @b 2 - Balance-High
+                                                         *  @li @b 3 - Balance-Low
+                                                         *  @li @b 4 - Power Saving
+                                                         */
+
+} GNB_CONFIGURATION;
+
+/// Late Configuration settings for GNB.
+typedef struct {
+  IN        BOOLEAN                 DockedTdpHeadroom;  ///< Docked TDP headroom
+                                                        ///< @li TRUE  = Enable docked TDP headroom
+                                                        ///< @li FALSE = Disable docked TDP headroom
+                                                        ///< @BldCfgItem{BLDCFG_DOCKED_TDP_HEADROOM}
+} GNB_LATE_CONFIGURATION;
+
+//
+//  MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+//   These Max values are used to define array sizes and associated loop
+//   counts in the code.  They reflect the maximum values that AGESA
+//   currently supports and does not necessarily reflect the hardware
+//   capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
+                                    ///< Eg: UINT16  *RcvEnDlys;
+                                    ///<     UINT8   *WrDqsDlys;
+                                    ///<     UINT8   *RdDqsDlys;
+                                    ///<     UINT8   *WrDatDlys;
+                                    ///<     UINT8   *RdDqsMinDlys;
+                                    ///<     UINT8   *RdDqsMaxDlys;
+                                    ///<     UINT8   *WrDatMinDlys;
+                                    ///<     UINT8   *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES     16   ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START  0x00004000ul    ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END    0x00007FFFul    ///< base [39:8]
+#define DATAEYE_VREF_RANGE     31   ///< Number of VREF steps in Data Eye Bitmap
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul   ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0    0x40000000ul   ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1    0x20000000ul   ///< UMA resides on memory that belongs to DCT1
+#define UMA_ATTRIBUTE_ON_DCT2    0x10000000ul   ///< UMA resides on memory that belongs to DCT2
+#define UMA_ATTRIBUTE_ON_DCT3    0x08000000ul   ///< UMA resides on memory that belongs to DCT3
+
+typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
+
+//        AGESA DEFINITIONS
+//
+//        Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
+/// CPU Package Type
+#define PT_L1       0                 ///< L1 Package type
+#define PT_M2       1                 ///< AM Package type
+#define PT_S1       2                 ///< S1 Package type
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+#define DDR400_FREQUENCY  200     ///< DDR 400
+#define DDR533_FREQUENCY  266     ///< DDR 533
+#define DDR667_FREQUENCY  333     ///< DDR 667
+#define DDR800_FREQUENCY  400     ///< DDR 800
+#define DDR1066_FREQUENCY 533     ///< DDR 1066
+#define DDR1333_FREQUENCY 667     ///< DDR 1333
+#define DDR1600_FREQUENCY 800     ///< DDR 1600
+#define DDR1866_FREQUENCY 933     ///< DDR 1866
+#define DDR2100_FREQUENCY 1050    ///< DDR 2100
+#define DDR2133_FREQUENCY 1066    ///< DDR 2133
+#define DDR2400_FREQUENCY 1200    ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+#define TIMING_MODE_AUTO     0  ///< Use best rate possible
+#define TIMING_MODE_LIMITED  1  ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2  ///< Set user specified speed
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+#define QUADRANK_REGISTERED  0  ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED  1  ///< Quadrank unbuffered DIMM
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+#define POWER_DOWN_BY_CHANNEL      0  ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT  1  ///< Chip select power down mode
+#define POWER_DOWN_MODE_AUTO       2  ///< AGESA to select power down mode
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+  IN OUT   UINT64 Family;             ///< Indicates logical ID Family
+  IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Structures use to report AMP status
+typedef struct {
+  OUT   BOOLEAN AmpVoltageValid;                 ///< Indicates if Amp voltage is valid
+  OUT   BOOLEAN AmpSupportDetectedButNotEnabled; ///< Indicates if Amp support is detected but not enabled
+  OUT   BOOLEAN AmpSelectedButNotEnabled;        ///< Indicates if Amp is selected but not enabled
+} AMP_STATUS;
+
+/// Normalized Critical Composite Data Eye
+///  Bit 15 represents trained eye Center
+///  Bit 0  represents eye center -15 delay steps
+///  Bit 31 represents eye center +16 delay steps
+///  Offset 0  represents +15 Vref Steps
+///  Offset 31  represents -15 Vref Steps
+typedef UINT32 COMPOSITE_DATAEYE[DATAEYE_VREF_RANGE];
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+  AMD_PLATFORM_SERVER = 0x8000,     ///< Server
+  AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
+  AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+  DDR2_TECHNOLOGY,        ///< DDR2 technology
+  DDR3_TECHNOLOGY,        ///< DDR3 technology
+  STUB_TECHNOLOGY,       ///<
+  UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology
+} TECHNOLOGY_TYPE;
+
+/// Low voltage support
+typedef enum {
+  VOLT_INITIAL,              ///< Initial value for VDDIO
+  VOLT1_5,                   ///< 1.5 Volt
+  VOLT1_35,                  ///< 1.35 Volt
+  VOLT1_25,                  ///< 1.25 Volt
+  VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// AMP voltage support
+typedef enum {
+  AMP_VOLT_RSVD,             ///< Reserved
+  AMP_VOLT1_5,               ///< 1.5 Volt
+  AMP_VOLT1_55,              ///< 1.55 Volt
+  AMP_VOLT1_6,               ///< 1.6 Volt
+  AMP_VOLT1_65,              ///< 1.65 Volt
+  AMP_VOLT1_7,               ///< 1.7 Volt
+  AMP_VOLT1_75,              ///< 1.75 Volt
+  AMP_VOLT1_8,               ///< 1.8 Volt
+  AMP_VOLT1_85,              ///< 1.85 Volt
+  AMP_VOLT1_9,               ///< 1.9 Volt
+  AMP_VOLT1_45 = 0x10,       ///< 1.45 Volt
+  AMP_VOLT1_4  = 0x20,       ///< 1.4 Volt
+  AMP_VOLT1_35 = 0x30,       ///< 1.35 Volt
+  AMP_VOLT1_3  = 0x40,       ///< 1.3 Volt
+  AMP_VOLT1_25 = 0x50,       ///< 1.25 Volt
+  AMP_VOLT1_2  = 0x60        ///< 1.2 Volt
+} AMP_DIMM_VOLTAGE;
+
+/// UMA Mode
+typedef enum {
+  UMA_NONE = 0,              ///< UMA None
+  UMA_SPECIFIED = 1,         ///< UMA Specified
+  UMA_AUTO = 2               ///< UMA Auto
+} UMA_MODE;
+
+/// Force Training Mode
+typedef enum {
+  FORCE_TRAIN_1D = 0,              ///< 1D Training only
+  FORCE_TRAIN_AUTO = 2             ///<  Auto - 1D or 2D depending on configuration
+} FORCE_TRAIN_MODE;
+
+///  The possible DRAM prefetch mode settings.
+typedef enum  {
+  DRAM_PREFETCHER_AUTO,                         ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_DRAM_PREFETCH_FOR_IO,                 ///< Disable DRAM prefetching for I/O requests only.
+  DISABLE_DRAM_PREFETCH_FOR_CPU,                ///< Disable DRAM prefetching for requests from processor cores only.
+  DISABLE_DRAM_PREFETCHER,                      ///< Disable DRAM prefetching.
+  MAX_DRAM_FREFETCH_MODE                        ///< Not a DRAM prefetch mode, use for limit checking.
+} DRAM_PREFETCH_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+  NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
+  UMA_4MB_ALIGNED = 0x00FFFFC0,          ///< UMA 4MB aligned
+  UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
+  UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
+  UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+///   Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+  GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
+  GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
+  GsbDramECCDis,             ///< Dram ECC requested but not enabled.
+  GsbSoftHole,               ///< A Node Base gap was created
+  GsbHWHole,                 ///< A HW dram remap was created
+  GsbNodeIntlv,              ///< Node Memory interleaving was enabled
+  GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                     ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+  EsbNoDimms,                  ///< No DIMMs
+  EsbSpdChkSum,                ///< SPD Checksum fail
+  EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
+  EsbDimmMismatchT,            ///< dimm CL/T mismatch
+  EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
+  EsbNoCycTime,                ///< SPD missing byte 23 or 25
+  EsbBkIntDis,                 ///< Bank interleave requested but not enabled
+  EsbDramECCDis,               ///< Dram ECC requested but not enabled
+  EsbSpareDis,                 ///< Online spare requested but not enabled
+  EsbMinimumMode,              ///< Running in Minimum Mode
+  EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
+  EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos,                 ///< No DQS-DQ passing positions
+  EsbSmallDqs,                 ///< DQS-DQ passing window too small
+  EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
+
+  EsbEMPNotSupported,          ///< Processor is not capable for EMP.
+  EsbEMPConflict,               ///< EMP requested but cannot be enabled since
+                               ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis,                   ///< EMP requested but cannot be enabled since
+                               ///< memory size of each DCT is not a power of two.
+
+  EsbEOL                       ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+///  Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+  SbRegistered,                ///< All DIMMs are Registered
+  SbEccDimms,                  ///< All banks ECC capable
+  SbParDimms,                  ///< All banks Addr/CMD Parity capable
+  SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
+  Sb128bitmode,                ///< DCT in 128-bit mode operation
+  Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
+  Sb2TMode,                    ///< 2T CMD timing mode is enabled.
+  SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
+  SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
+  SbLrdimms,                   ///< All DIMMs are LRDIMMs
+
+  SbEOL                        ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG     0xC0010010ul
+#ifndef TOP_MEM
+#define TOP_MEM     0xC001001Aul
+#endif
+#ifndef TOP_MEM2
+#define TOP_MEM2    0xC001001Dul
+#endif
+#define HWCR        0xC0010015ul
+#define NB_CFG      0xC001001Ful
+
+#define FS_BASE     0xC0000100ul
+#define IORR0_BASE  0xC0010016ul
+#define IORR0_MASK  0xC0010017ul
+#define BU_CFG      0xC0011023ul
+#define BU_CFG2     0xC001102Aul
+#define COFVID_STAT 0xC0010071ul
+#define TSC         0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+  IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
+  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+  OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
+  OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
+                                 ///<  DIMM#  Select Signal
+                                 ///<  0      MA0_CS_L[0, 1]
+                                 ///<  1      MB0_CS_L[0, 1]
+                                 ///<  2      MA1_CS_L[0, 1]
+                                 ///<  3      MB1_CS_L[0, 1]
+                                 ///<  4      MA2_CS_L[0, 1]
+                                 ///<  5      MB2_CS_L[0, 1]
+                                 ///<  6      MA3_CS_L[0, 1]
+                                 ///<  7      MB3_CS_L[0, 1]
+
+  OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+  OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+  OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+                                 ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+                                 ///<
+  OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+  OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+  OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+  OUT UINT8   Loads;             ///< Number of devices loading bus
+  OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
+  OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
+  OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
+                                 ///< FALSE = 1T
+                                 ///< TRUE = 2T
+  ///< The following pointers will be pointed to dynamically allocated buffers.
+  ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ///< Example: If DIMM and Byte based training, then
+  ///< XX is a value in Hex
+  ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
+  OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
+  OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
+  OUT UINT8   *WrDatDlys;       ///< Write Data delays
+  OUT UINT8   *RdDqs2dDlys;     ///< 2d Read DQS data
+  OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
+  OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
+  OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
+  OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
+  OUT UINT16  *RcvEnDlysMemPs1;       ///< DQS Receiver Enable Delays for Mem Pstate 1
+  OUT UINT8   *WrDqsDlysMemPs1;       ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
+  OUT UINT8   *RdDqsDlysMemPs1;       ///< Read Dqs delays for Memory Pstate 1
+  OUT UINT8   *WrDatDlysMemPs1;       ///< Write Data delays for Memory Pstate 1
+  OUT UINT8   *RdDqs2dDlysMemPs1;     ///< 2d Read DQS data for Memory Pstate 1
+  OUT UINT8   *RdDqsMinDlysMemPs1;    ///< Minimum Window for Read DQS for Memory Pstate 1
+  OUT UINT8   *RdDqsMaxDlysMemPs1;    ///< Maximum Window for Read DQS for Memory Pstate 1
+  OUT UINT8   *WrDatMinDlysMemPs1;    ///< Minimum Window for Write data for Memory Pstate 1
+  OUT UINT8   *WrDatMaxDlysMemPs1;    ///< Maximum Window for Write data for Memory Pstate 1
+  OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
+  OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
+  OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
+  OUT UINT8   *FailingBitMaskMemPs1;    ///< Table of masks to Track Failing bits for Memory Pstate 1
+  OUT VOID    *RdDataEyes;        ///< Pointer to Read Data Eye Bitmaps
+  OUT VOID    *WrDataEyes;        ///< Pointer to Write Data Eye Bitmaps
+  OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 230h)
+  OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 234h)
+  OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 238h)
+  OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 23Ch)
+  OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
+  OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
+  OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
+  OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
+  OUT UINT8   Pattern;            ///< Current pattern
+  OUT UINT8   DqsDelay;           ///< Current DQS delay value
+  OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT16  DctMaxRdLat[4];     ///< Max Read Latency (ns) for the DCT
+                                  ///< DctMaxRdLat [i] is for NBPstate i
+  OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
+  OUT UINT8   MaxCh;              ///< Max number of CH in system
+  OUT UINT8   Dct;                ///< Dct pointer
+  OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
+  OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
+
+  OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
+  OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
+  OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
+  OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
+  OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+  OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
+  OUT UINT32  NodeSysBase;        ///< for channel interleave usage
+  OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
+  OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
+  OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
+  OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
+  OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
+  OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
+
+  OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
+  OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
+  OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+  OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+  OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+  OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+  OUT UINT8   DimmNibbleAccess;   ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+  OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ///<  base on this array to disable unused MemClk to save power.
+                                  ///<
+                                  ///<  The array must have 8 entries. Each entry, which associates with
+                                  ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+
+  OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of CKE pins to the DIMMs' ranks.
+                                  ///<  The array must have 2 entries. Each entry, which associates with
+                                  ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ///<  AGESA will base on this array to disable unused CKE pins to save power.
+
+  OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of ODT pins to the DIMMs' ranks.
+                                  ///<  The array must have 4 entries. Each entry, which associates with
+                                  ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ///<  AGESA will base on this array to disable unused ODT pins to save power.
+
+  OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of chip select pins to the DIMMs' ranks.
+                                  ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ///<  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
+
+  OUT UINT8   MaxVref;            ///<  Maximum Vref Value for channel
+
+  OUT UINT8   Reserved[100];      ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+  OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+  OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
+  OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
+  OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+  OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
+  OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+  OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+  OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+  OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
+  OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
+  OUT UINT16  Speed;              ///< DRAM bus speed in MHz
+                                  ///<  400 (MHz)
+                                  ///<  533 (MHz)
+                                  ///<  667 (MHz)
+                                  ///<  800 (MHz)
+                                  ///<  and so on...
+  OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
+  OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
+  OUT UINT8   Trp;                ///< DCT Trp (busclocks)
+  OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
+  OUT UINT8   Tras;               ///< DCT Tras (busclocks)
+  OUT UINT8   Trc;                ///< DCT Trc (busclocks)
+  OUT UINT8   Twr;                ///< DCT Twr (busclocks)
+  OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
+  OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
+  OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
+  OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
+                                  ///<  0 = 75ns (for 256Mb devs)
+                                  ///<  1 = 105ns (for 512Mb devs)
+                                  ///<  2 = 127.5ns (for 1Gb devs)
+                                  ///<  3 = 195ns (for 2Gb devs)
+                                  ///<  4 = 327.5ns (for 4Gb devs)
+  OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
+                                  ///<
+  OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
+                                  ///< FALSE = 1T
+                                  ///< TRUE = 2T
+  OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
+  OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
+  OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
+  OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
+  OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
+  OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
+  OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
+  OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
+  OUT UINT16  MaxRdLat;           ///< Max Read Latency
+  OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
+  OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+  OUT UINT8   Dct;                ///< Current Dct
+  OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
+  OUT CH_TIMING_STRUCT *TimingsMemPs1;   ///< Pointed to channel timing structure for memory Pstate 1
+  OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
+  OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
+  OUT BOOLEAN BkIntDis;           ///< Bank interleave requested but not enabled on current DCT
+  OUT UINT8 BankAddrMap;          ///< Bank Address Mapping
+  OUT UINT8 EnabledChipSels;      ///< Number of enabled chip selects on current DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+  /// Advanced:
+
+  OUT UINT8   NodeId;              ///< Node ID of current controller
+  OUT UINT8   SocketId;            ///< Socket ID of this Die
+  OUT UINT8   DieId;               ///< ID of this die relative to the socket
+  OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
+  OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
+                                   ///<  0x0 = AGESA_SUCCESS
+                                   ///<  0x1 = AGESA_UNSUPPORTED
+                                   ///<  0x2 = AGESA_BOUNDS_CHK
+                                   ///<  0x3 = AGESA_ALERT
+                                   ///<  0x4 = AGESA_WARNING
+                                   ///<  0x5 = AGESA_ERROR
+                                   ///<  0x6 = AGESA_CRITICAL
+                                   ///<  0x7 = AGESA_FATAL
+                                   ///<
+  OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
+                                   ///<
+  OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
+                                   ///<
+  OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+                                   ///<
+  OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
+                                   ///<
+  OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+                                   ///<
+  OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
+                                   ///<
+  OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
+                                   ///<   DIMM#  Select Signal
+                                   ///<   0      MA0_CS_L[0, 1]
+                                   ///<   1      MB0_CS_L[0, 1]
+                                   ///<   2      MA1_CS_L[0, 1]
+                                   ///<   3      MB1_CS_L[0, 1]
+                                   ///<   4      MA2_CS_L[0, 1]
+                                   ///<   5      MB2_CS_L[0, 1]
+                                   ///<   6      MA3_CS_L[0, 1]
+                                   ///<   7      MB3_CS_L[0, 1]
+                                   ///<
+  OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+  OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+  OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+  OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+                                   ///<
+  OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
+  OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
+                                   ///<  0 in any bit field indicates Channel 0
+                                   ///<  1 in any bit field indicates Channel 1
+  OUT UINT8   Dct;                 ///<  Need to be removed
+                                   ///<  DCT pointer
+  OUT BOOLEAN GangedMode;          ///< Ganged mode
+                                   ///<  0 = disabled
+                                   ///<  1 = enabled
+  OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+                                   ///<
+  OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT8   MLoad;               ///< Need to be removed
+                                   ///< Number of devices loading MAA bus
+                                   ///<
+  OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
+                                   ///<
+  OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
+                                   ///<
+  OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
+                                   ///<
+  OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+  OUT UINT8   DctCount;            ///< Number of DCTs per this Die
+  OUT UINT8   Reserved[16];        ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+     OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
+     OUT   UINT16 Version;             ///< S3 Params version number
+  IN OUT   UINT32 Flags;               ///< Indicates operation
+  IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
+  IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
+  IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
+  IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+  // Basic (Return parameters)
+  // (This section contains the outbound parameters from the memory init code)
+
+  OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
+                                  ///<
+  OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+                                  ///<
+  OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
+                                  ///<
+  OUT UINT32 Sub1THoleBase;       ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+                                  ///<
+  OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
+                                  ///<
+  OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
+                                  ///<
+  OUT UINT8 ExternalVrefValue;    ///< Target reference voltage for external Vref for 2D training
+                                  ///<
+  OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
+
+  //  Advanced (Optional parameters)
+  //  Optional (all defaults values will be initialized by the
+  //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
+  //  to the IBV/OEM to change the defaults after initialization
+  //  but prior to the main entry to the memory code):
+
+  // Memory Map/Mgt.
+
+  IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
+                                   ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
+                                   ///<
+  IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+  IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+
+  // Dram Timing
+
+  IN UINT32  UserTimingMode;       ///< User Memclock Mode.
+                                                ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+  IN UINT32  MemClockValue;        ///< Memory Clock Value.
+                                                ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+  // Dram Configuration
+
+  IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
+                                   ///<  - FALSE =disable (default)
+                                   ///<  - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+  IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+  IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+  // ECC
+
+  IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+  // Dram Power
+
+  IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
+                                   ///<   - FALSE =disable (default)
+                                   ///<   - TRUE =enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+  // Online Spare
+
+  IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+                                   ///<  - FALSE = disable Spare (default)
+                                   ///<  - TRUE = enable Spare
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+  IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+  IN PSO_TABLE *PlatformMemoryConfiguration;
+                                   ///< A table that contains platform specific settings.
+                                   ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+                                   ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ///< contains default conservative settings. Platform BIOS can either tweak
+                                   ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ///<
+  IN BOOLEAN EnableParity;         ///< Parity control.
+                                   ///<  - TRUE = enable
+                                   ///<  - FALSE = disable (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+  IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+                                   ///<
+
+  IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+
+  // Uma Configuration
+
+  IN UMA_MODE UmaMode;             ///<  Uma Mode
+                                   ///<  0 = None
+                                   ///<  1 = Specified
+                                   ///<  2 = Auto
+  IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
+                                   ///<  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ///<
+  OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
+                                   ///<  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ///<
+
+  /// Memory Restore Feature
+
+  IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
+                                   ///<   FALSE = perform memory init as normal (AMD default)
+                                   ///<   TRUE = restore memory context and skip training. This requires
+                                   ///<          MemContext is valid before AmdInitPost
+                                   ///<
+  IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
+                                   ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ///<   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ///<           expected to call S3Save later in POST if it wants to
+                                   ///<           use memory context restore feature.
+                                   ///<
+  IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+                                   ///< save and restore for memory context restore feature to work.
+                                   ///< It uses the subset of S3Save block to save/restore. Hence platform
+                                   ///< may save only S3 block and uses it for both S3 resume and
+                                   ///< memory context restore.
+                                   ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ///<    before AmdInitPost.
+                                   ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ///<    right after AmdInitPost.
+                                   ///<
+  IN BOOLEAN IsCapsuleMode;        ///< Capsule reboot control
+                                   ///<   FALSE = This is not a capsule reboot.
+                                   ///<   TRUE = This is a capsule reboot.
+                                   ///<
+  IN BOOLEAN ExternalVrefCtl;      ///< Control the use of external Vref
+                                   ///<   TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
+                                   ///<          to change the vref
+                                   ///<   FALSE = AGESA will will use the internal vref control.
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
+                                   ///<
+  IN FORCE_TRAIN_MODE ForceTrainMode;   ///<  Training Mode
+                                   ///<  0 = Force 1D Training for all configurations
+                                   ///<  1 = Force 2D Training for all configurations
+                                   ///<  2 = Auto - AGESA will control 1D or 2D
+  IN TECHNOLOGY_TYPE DimmTypeUsedInMixedConfig;   ///< Select the preferred technology type that AGESA will enable
+                                                  ///< when it is mixed with other technology types.
+                                                  ///<   DDR3_TECHNOLOGY = Use DDR3 DIMMs
+                                                  ///< @BldCfgItem{BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG}
+  IN BOOLEAN AmpEnable;            ///< AMP functionality control
+                                   ///<   TRUE = Enable, platform BIOS requests to enable memory overclocking function, and AGESA
+                                   ///<          detects if memory is capable of it
+                                   ///<   FALSE = Disable, there is no request to enable memory overclocking function
+                                   ///<
+  IN BOOLEAN AmpWarningMsgEnable;  ///< AMP warning messages control
+                                   ///<   TRUE = Enable to log the warning messages of AMP
+                                   ///<   FALSE = Disable
+                                   ///<
+  OUT AMP_STATUS AmpStatus;        ///< AMP status allows platform BIOS to check which voltage or warning message it should
+                                   ///< use/apply.
+                                   ///<
+                                   ///<   AmpVoltageValid :
+                                   ///<       TRUE - AGESA does enable AMP function, so use AmpVoltage for voltage adjustment
+                                   ///<       FALSE - AGESA does not enable AMP function, so use DDR3Voltage for voltage adjustment
+                                   ///<
+                                   ///<   AmpSupportDetectedButNotEnabled :
+                                   ///<       TRUE - Display warning message of "AMP support detected but not enabled"
+                                   ///<       FALSE - No corresponding message should be displayed
+                                   ///<
+                                   ///<   AmpSelectedButNotEnabled :
+                                   ///<       TRUE - Display warning message of "AMP selected but not enabled"
+                                   ///<       FALSE - No corresponding message should be displayed
+                                   ///<
+                                   ///<   Note that both of warning message status reports are controlled by AmpWarningMsgEnable
+                                   ///<
+  OUT AMP_DIMM_VOLTAGE AmpVoltage; ///< AMP voltage which will be sent back to platform BIOS, and
+                                   ///< the value in AmpVoltage is valid only if AmpStatus is TRUE returned
+  IN BOOLEAN DataEyeEn;            ///< Get 2D training data eye
+                                   ///<   TRUE  = Enable to get the 2D data eye
+                                   ///<   FALSE = The 2D data eye is not enabled
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_DATA_EYE}
+  IN BOOLEAN DramDoubleRefreshRate;///< Specify the average time between refresh requests to all DRAM devices.
+                                   ///<   TRUE  = 2x refresh rate.
+                                   ///<   FALSE = 1x refresh rate.
+                                   ///< @BldCfgItem{BLDCFG_DRAM_DOUBLE_REFRESH_RATE}
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+  // PUBLIC required Internal functions
+
+  IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
+  IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
+
+  // PUBLIC optional functions
+
+  IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
+  IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+  IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
+  IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
+  IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
+  IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
+  IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
+  IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
+  IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
+  IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
+  IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);               ///< NB code for LRDIMMs
+  IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+  OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
+
+  OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+  IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+
+  IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
+
+  OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
+
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+  OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
+                                   ///< SocketList is a shortcut for IBVs to retrieve training
+                                   ///< and timing data for each channel indexed by socket/channel,
+                                   ///< eliminating their need to parse die/dct/channel etc.
+                                   ///< It contains pointers to the populated data structures for
+                                   ///< each channel and skips the channel structures that are
+                                   ///< unpopulated. In the case of channels sharing the same DCT,
+                                   ///< the pTimings pointers will point to the same DCT Timing data.
+
+  OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
+  OUT UINT8      DieCount;        ///< Number of MCTs in the system.
+
+  IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
+
+  IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
+
+  IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
+
+  OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
+
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+  OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
+  OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
+  OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
+  OUT UINT8  UmaMode;          ///< Indicate the mode of Uma
+  OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
+  OUT UINT8  MemType;          ///< Indicate the DRAM technology type that is being used
+  OUT UINT8  Reserved[2];      ///< Reserved for future usage
+} UMA_INFO;
+
+/// Bitfield for ID
+typedef struct {
+  OUT UINT16 SocketId:8;       ///< Socket ID
+  OUT UINT16 ModuleId:8;       ///< Module ID
+} ID_FIELD;
+///
+/// Union for ID of socket and module that will be passed out in call out
+///
+typedef union {
+  OUT ID_FIELD IdField;         ///< Bitfield for ID
+  OUT UINT16 IdInformation;     ///< ID information for call out
+} ID_INFO;
+
+//  AGESA MEMORY ERRORS
+
+// AGESA_SUCCESS memory events
+#define MEM_EVENT_CAPSULE_IN_EFFECT      0x04013600ul          ///< Capsule is in effect
+#define MEM_EVENT_CONTEXT_RESTORE_IN_EFFECT     0x04023600ul   ///< Context restore is in effect
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000ul       ///< TIMING_MODE_SPECIFIC is requested but
+                                                               ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul               ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200ul                      ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul            ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul         ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul            ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul         ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul        ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul         ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul       ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul           ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul        ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul         ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul   ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul         ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul       ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul          ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul           ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul            ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul  ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul           ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul            ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul               ///< Time out when polling FlushWr bit
+#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul    ///< Time out when polling CurNBPstate bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul               ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul   ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul      ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul              ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200ul       ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300ul                   ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul        ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul             ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_NO_2D_RDDQS_WINDOW 0x040D0300ul              ///< No 2D RdDqs Window
+#define MEM_ERROR_NO_2D_RDDQS_HEIGHT 0x040E0300ul              ///< No 2D RdDqs Height
+#define MEM_ERROR_2D_DQS_ERROR  0x040F0300ul                   ///< 2d RdDqs Error
+#define MEM_ERROR_INVALID_2D_RDDQS_VALUE  0x04022400ul         ///< 2d RdDqs invalid value found
+#define MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR  0x04023400ul       ///< 2d RdDqs Vef Margin error found
+#define MEM_ERROR_LR_IBT_NOT_FOUND  0x04013500ul               ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND  0x04023500ul                  ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND  0x04033500ul          ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND  0x04043500ul              ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND  0x04053500ul        ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND  0x04063500ul                  ///< No RTT value is found
+#define MEM_ERROR_P2D_NOT_FOUND  0x04073500ul                  ///< No 2D training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND  0x04083500ul                  ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND  0x04093500ul          ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND  0x040A3500ul          ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND  0x040B3500ul          ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND  0x040C3500ul           ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND  0x040D3500ul        ///< No training seed is found
+#define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul              ///< No 2D WrDat Window
+#define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul              ///< No 2D WrDat Height
+#define MEM_ERROR_2D_WRDAT_ERROR  0x040F0400ul                 ///< 2d WrDat Error
+#define MEM_ERROR_INVALID_2D_WRDAT_VALUE  0x04100400ul         ///< 2d WrDat invalid value found
+#define MEM_ERROR_2D_WRDAT_VREF_MARGIN_ERROR  0x04110400ul     ///< 2d WrDat Vef Margin error found
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600ul       ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600ul       ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600ul       ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600ul       ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600ul       ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600ul       ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700ul       ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT            0x04021700ul       ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED         0x04031700ul       ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS                 0x04041700ul       ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul  ///< Performance has been enabled, but battery life is preferred.
+                                                                             ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND               0x04011900ul ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED    0x04012300ul ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO      0x04012400ul ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO   0x04012500ul ///< Cannot find a commonly supported VDDIO
+#define MEM_WARNING_AMP_SUPPORT_DETECTED_BUT_NOT_ENABLED 0x04012900ul ///< AMP support detected but not enabled
+#define MEM_WARNING_AMP_SELECTED_BUT_NOT_ENABLED  0x04022900ul ///< AMP selected but not enabled
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE              0x04011A00ul       ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul       ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM   0x04011C00ul       ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS      0x04011D00ul       ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME               0x04011E00ul       ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS     0x04011F00ul  ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs  0x04021F00ul  ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00ul           ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD               0x04041F00ul    ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00ul    ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00ul   ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00ul    ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK    0x04081F00ul   ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM    0x04022300ul    ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED                   0x04022500ul    ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D                0x040B1F00ul    ///< Heap allocation error for 2D training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D              0x040C1F00ul    ///< Heap de-allocation error for 2D training data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DATAEYE           0x040F1F00ul    ///< Heap allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_DATAEYE         0x040E1F00ul    ///< Heap de-allocation error for DATAEYE Storage
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3    0x04091F00ul    ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2    0x040A1F00ul    ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG             0x04011400ul    ///< Dimm population is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul    ///< Heap allocation error for CRAT memory affinity info
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                    CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00ul
+#define CPU_EVENT_PM_EVENT_CLASS                        0x08000400ul
+
+//================================================================
+// CPU General events
+//    Heap allocation                     (AppFunction =      01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100ul
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100ul
+#define CPU_ERROR_HEAP_IS_FULL                          0x08020100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100ul
+//    BrandId                             (AppFunction =      02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200ul
+//    Micro code patch                    (AppFunction =      03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300ul
+//    Power management                    (AppFunction =      04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400ul
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400ul
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400ul
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400ul
+//    TDP Limiting
+#define CPU_EVENT_TDP_LIMIT_FORCE_TO_50_PERCENTAGE      0x08060100ul
+#define CPU_ERROR_TDP_LIMIT_SAVE_PSTATE_FAIL            0x08060200ul
+#define CPU_ERROR_TDP_LIMIT_RESTORE_PSTATE_FAIL         0x08060201ul
+#define CPU_ERROR_TDP_LIMIT_TDP2WATT_IS_ZERO            0x08060202ul
+#define CPU_ERROR_TDP_LIMIT_INVALID_INPUT               0x08060203ul
+//    Other CPU events                    (AppFunction =      05h)
+#define CPU_EVENT_BIST_ERROR                            0x08000500ul
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY              0x08010500ul
+#define CPU_EVENT_STACK_REENTRY                         0x08020500ul
+#define CPU_EVENT_CORE_NOT_IDENTIFIED                   0x08030500ul
+
+//=================================================================
+// CPU Feature events
+//    Execution cache                     (AppFunction =      21h)
+//        AGESA_CACHE_SIZE_REDUCED                            2101
+//        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
+//        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
+//        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
+//        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
+//        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
+//        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100ul
+//    Core Leveling                       (AppFunction =      22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200ul
+//    HT Assist                           (AppFunction =      23h)
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300ul
+//    SCS initialization                  (AppFunction =      24h)
+//        AGESA_SCS_HEAP_ENTRY_MISSING                        2401
+//        AGESA_SCS_BUFFER_EMPTY                              2402
+//        AGESA_SCS_WEIGHTS_MISMATCH                          2403
+#define CPU_EVENT_SCS_INITIALIZATION_ERROR              0x08002400ul
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+  IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
+  IN  UINT64 MsrData;     ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000    0x00000250ul
+#define AMD_AP_MTRR_FIX16k_80000    0x00000258ul
+#define AMD_AP_MTRR_FIX16k_A0000    0x00000259ul
+#define AMD_AP_MTRR_FIX4k_C0000     0x00000268ul
+#define AMD_AP_MTRR_FIX4k_C8000     0x00000269ul
+#define AMD_AP_MTRR_FIX4k_D0000     0x0000026Aul
+#define AMD_AP_MTRR_FIX4k_D8000     0x0000026Bul
+#define AMD_AP_MTRR_FIX4k_E0000     0x0000026Cul
+#define AMD_AP_MTRR_FIX4k_E8000     0x0000026Dul
+#define AMD_AP_MTRR_FIX4k_F0000     0x0000026Eul
+#define AMD_AP_MTRR_FIX4k_F8000     0x0000026Ful
+#define CPU_LIST_TERMINAL           0xFFFFFFFFul
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+  IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
+  OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+  IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
+  IN OUT UINTN Reserved;              ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
+  IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
+  OUT       VOID                *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
+  IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
+  IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
+  IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN        UINT8               SocketId;       ///< Address of SPD - socket ID
+  IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
+  IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
+  IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
+  IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// VoltageType values
+typedef enum {
+  VTYPE_CPU_VREF,                                    ///< Cpu side Vref
+  VTYPE_DIMM_VREF,                                   ///< Dimm Side Vref
+  VTYPE_VDDIO                                        ///< Vddio
+} VTYPE;
+
+/// Parameters structure for the interface call-out AgesaExternalVoltageAdjust
+typedef struct _VOLTAGE_ADJUST {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;     ///< Standard configuration header
+  IN OUT    MEM_DATA_STRUCT     *MemData;      ///< Location of the MemData structure, for reference
+  IN        VTYPE               VoltageType;   ///< Which Voltage Type to adjust
+  IN        INT8                AdjustValue;   ///< Positive/Negative Adjust Value
+} VOLTAGE_ADJUST;
+
+/// Buffer Handles
+typedef enum {
+  AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
+  AMD_ACPI_ALIB_BUFFER_HANDLE,                  ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+  AMD_ACPI_IVRS_BUFFER_HANDLE,                  ///< Assign 0x000D00A buffer handle to IOMMU IVRS table
+  AMD_CRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D00B buffer handle to CRAT function
+  AMD_ACPI_CDIT_BUFFER_HANDLE                   ///< Assign 0x000D00C buffer handle to CDIT function
+} AMD_BUFFER_HANDLE;
+
+
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+  IN        UINTN               ResetType,
+  IN OUT    AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
+  );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
+  );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
+  );
+
+AGESA_STATUS
+AgesaReadSpd (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN               ApicIdOfCore,
+  IN        AP_EXE_PARAMS       *LaunchApParams
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+ );
+
+AGESA_STATUS
+AgesaGetVbiosImage (
+  IN       UINTN                 FcnData,
+  IN OUT   GFX_VBIOS_IMAGE_INFO *VbiosImageInfo
+  );
+
+AGESA_STATUS
+AgesaFchOemCallout (
+  IN      VOID                  *FchData
+ );
+
+AGESA_STATUS
+AgesaExternal2dTrainVrefChange (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  );
+
+AGESA_STATUS
+AgesaExternalVoltageAdjust (
+  IN       UINTN           SocketIdModuleId,
+  IN OUT   VOLTAGE_ADJUST *AdjustValue
+  );
+/************************************************************************
+ *
+ *  AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration:  The parameters in boot branch function
+ **********************************************************************/
+
+///  The possible platform control flow settings.
+typedef enum  {
+  Nfcm,                                          ///< Normal Flow Control Mode.
+  UmaDr,                                         ///< UMA using Display Refresh flow control.
+  UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
+  Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
+  Iommu,                                         ///< An IOMMU is in use in the system.
+  MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+///  Platform Deemphasis Levels.
+///
+/// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
+/// set based on the level of the far transmitter.
+typedef enum {
+  DeemphasisLevelNone,                           ///< No Deemphasis.
+  DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
+  DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
+  DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
+  DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone = 16,                             ///< No DCV Deemphasis.
+  DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
+  DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
+  DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
+  DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
+  DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
+  DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
+  DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
+  DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
+} PLATFORM_DEEMPHASIS_LEVEL;
+
+///  Provide Deemphasis Levels for HT Links.
+///
+///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
+///  is in the inclusive range HighFreq:LoFreq.
+///  AGESA does not set deemphasis in IO devices, only in processors.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
+  IN       UINT8 Link;                                          ///< The Link on this Processor.
+  IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
+  IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
+  // Value fields
+  IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
+  IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
+} CPU_HT_DEEMPHASIS_LEVEL;
+
+
+///  The possible hardware prefetch mode settings.
+typedef enum  {
+  HARDWARE_PREFETCHER_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+  DISABLE_L1_PREFETCHER,                        ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching and above.
+  DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< (deprecated) - This setting is deprecated; it has the same effect as DISABLE_L1_PREFETCHER
+  DISABLE_L2_STRIDE_PREFETCHER,                 ///< Use the recommended settings for the hardware prefetcher, but disable the L2 stride prefetcher and above
+  DISABLE_HARDWARE_PREFETCH,                    ///< Disable hardware prefetching.
+  MAX_HARDWARE_PREFETCH_MODE                    ///< Not a hardware prefetch mode, use for limit checking.
+} HARDWARE_PREFETCH_MODE;
+
+///  The possible software prefetch mode settings.
+typedef enum  {
+  SOFTWARE_PREFETCHES_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_SOFTWARE_PREFETCHES,                  ///< Disable software prefetches (convert software prefetch instructions to NOP).
+  MAX_SOFTWARE_PREFETCH_MODE                    ///< Not a software prefetch mode, use for limit checking.
+} SOFTWARE_PREFETCH_MODE;
+
+/// Advanced performance tunings, prefetchers.
+/// These settings provide for performance tuning to optimize for specific workloads.
+typedef struct {
+  IN HARDWARE_PREFETCH_MODE  HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+  IN SOFTWARE_PREFETCH_MODE  SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
+  IN DRAM_PREFETCH_MODE      DramPrefetchMode;     ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+} ADVANCED_PERFORMANCE_PROFILE;
+
+///  The possible platform power policy settings.
+typedef enum  {
+  Performance,                                   ///< Optimize for performance.
+  BatteryLife,                                   ///< Optimize for battery life.
+  MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+///  Platform performance settings for optimized settings.
+///  Several configuration settings for the processor depend upon other parts and
+///  general designer choices for the system. The determination of these data points
+///  is not standard for all platforms, so the host environment needs to provide these
+///  to specify how the system is to be configured.
+typedef struct {
+  IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+  IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
+  IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
+  IN BOOLEAN               UseNeighborCache;           ///< Neighbor cache mode.
+                                                       ///< @BldCfgItem{BLDCFG_USE_NEIGHBOR_CACHE}
+  IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
+                                                       ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+  IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+                                                       ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+  IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile;   ///< The advanced platform performance settings.
+  IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+  IN BOOLEAN               NbPstatesSupported;         ///< The Nb-Pstates is supported or not
+                                                       ///< @BldCfgItem{BLDCFG_NB_PSTATES_SUPPORTED}
+} PERFORMANCE_PROFILE;
+
+///  Platform settings that describe the voltage regulator modules of the system.
+///  Many power management settings are dependent upon the characteristics of the
+///  on-board voltage regulator module (VRM).  The host environment needs to provide
+///  these to specify how the system is to be configured.
+typedef struct {
+  IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+  IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+  IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+  IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+  IN UINT32  MaximumCurrentLimit;                  ///< Vrm Maximum Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT}
+  IN UINT32  SviOcpLevel;                          ///< SVI OCP Level.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL}
+} PLATFORM_VRM_CONFIGURATION;
+
+///  The VRM types to characterize.
+typedef enum  {
+  CoreVrm,                                       ///< VDD plane.
+  NbVrm,                                         ///< VDDNB plane.
+  MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// FCH Platform Configuration Policy
+typedef struct {
+  IN UINT16     CfgSmbus0BaseAddress;             ///< SMBUS0 Controller Base Address
+  IN UINT16     CfgSmbus1BaseAddress;             ///< SMBUS1 Controller Base Address
+  IN UINT16     CfgSioPmeBaseAddress;             ///< I/O base address for LPC I/O target range
+  IN UINT16     CfgAcpiPm1EvtBlkAddr;             ///< I/O base address of ACPI power management Event Block
+  IN UINT16     CfgAcpiPm1CntBlkAddr;             ///< I/O base address of ACPI power management Control Block
+  IN UINT16     CfgAcpiPmTmrBlkAddr;              ///< I/O base address of ACPI power management Timer Block
+  IN UINT16     CfgCpuControlBlkAddr;             ///< I/O base address of ACPI power management CPU Control Block
+  IN UINT16     CfgAcpiGpe0BlkAddr;               ///< I/O base address of ACPI power management General Purpose Event Block
+  IN UINT16     CfgSmiCmdPortAddr;                ///< I/O base address of ACPI SMI Command Block
+  IN UINT16     CfgAcpiPmaCntBlkAddr;             ///< I/O base address of ACPI power management additional control block
+  IN UINT32     CfgGecShadowRomBase;              ///< 32-bit base address to the GEC shadow ROM
+  IN UINT32     CfgWatchDogTimerBase;             ///< Watchdog Timer base address
+  IN UINT32     CfgSpiRomBaseAddress;             ///< Base address for the SPI ROM controller
+  IN UINT32     CfgHpetBaseAddress;               ///< HPET MMIO base address
+  IN UINT32     CfgAzaliaSsid;
+  IN UINT32     CfgSmbusSsid;                     ///< Subsystem ID of SMBUS controller
+  IN UINT32     CfgIdeSsid;                       ///< Subsystem ID of IDE controller
+  IN UINT32     CfgSataAhciSsid;                  ///< Subsystem ID of SATA controller in AHCI mode
+  IN UINT32     CfgSataIdeSsid;                   ///< Subsystem ID of SATA controller in IDE mode
+  IN UINT32     CfgSataRaid5Ssid;                 ///< Subsystem ID of SATA controller in RAID5 mode
+  IN UINT32     CfgSataRaidSsid;                  ///< Subsystem ID of SATA controller in RAID mode
+  IN UINT32     CfgEhciSsid;                      ///< Subsystem ID of EHCI
+  IN UINT32     CfgOhciSsid;                      ///< Subsystem ID of OHCI
+  IN UINT32     CfgLpcSsid;                       ///< Subsystem ID of LPC ISA Bridge
+  IN UINT32     CfgSdSsid;                        ///< Subsystem ID of SecureDigital controller
+  IN UINT32     CfgXhciSsid;                      ///< Subsystem ID of XHCI
+  IN BOOLEAN    CfgFchPort80BehindPcib;           ///< Is port80 cycle going to the PCI bridge
+  IN BOOLEAN    CfgFchEnableAcpiSleepTrap;        ///< ACPI sleep SMI enable/disable
+  IN GPP_LINKMODE CfgFchGppLinkConfig;            ///< GPP link configuration
+  IN BOOLEAN    CfgFchGppPort0Present;            ///< Is FCH GPP port 0 present
+  IN BOOLEAN    CfgFchGppPort1Present;            ///< Is FCH GPP port 1 present
+  IN BOOLEAN    CfgFchGppPort2Present;            ///< Is FCH GPP port 2 present
+  IN BOOLEAN    CfgFchGppPort3Present;            ///< Is FCH GPP port 3 present
+  IN BOOLEAN    CfgFchGppPort0HotPlug;            ///< Is FCH GPP port 0 hotplug capable
+  IN BOOLEAN    CfgFchGppPort1HotPlug;            ///< Is FCH GPP port 1 hotplug capable
+  IN BOOLEAN    CfgFchGppPort2HotPlug;            ///< Is FCH GPP port 2 hotplug capable
+  IN BOOLEAN    CfgFchGppPort3HotPlug;            ///< Is FCH GPP port 3 hotplug capable
+
+  IN UINT8   CfgFchEsataPortBitMap;               ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+  IN UINT8   CfgFchIrPinControl;                  ///< Register bitfield describing Infrared Pin Control:
+                                                  ///<   [0] - IR Enable 0
+                                                  ///<   [1] - IR Enable 1
+                                                  ///<   [2] - IR Tx0
+                                                  ///<   [3] - IR Tx1
+                                                  ///<   [4] - IR Open Drain
+                                                  ///<   [5] - IR Enable LED
+  IN SD_CLOCK_CONTROL CfgFchSdClockControl;       ///< FCH SD Clock Control
+  IN SCI_MAP_CONTROL  *CfgFchSciMapControl;       ///< FCH SCI Mapping Control
+  IN SATA_PHY_CONTROL *CfgFchSataPhyControl;      ///< FCH SATA PHY Control
+  IN GPIO_CONTROL     *CfgFchGpioControl;         ///< FCH GPIO Control
+} FCH_PLATFORM_POLICY;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+  IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
+
+  //Build Option Area
+  IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+  IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+  IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+  IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+  IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+  IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+  IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+  IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+  IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+  IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+  IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+  IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+  IN BOOLEAN OptionPStatesInHpcMode;              ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE"
+  IN BOOLEAN OptionCrat;                          ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT"
+  IN BOOLEAN OptionCdit;                          ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT"
+  IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+  IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+  IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+  IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+  IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+  IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+  IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+  IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
+  IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
+  IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
+  IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData3;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+  IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
+  IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+  IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
+  IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode
+  IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
+  IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
+  IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+
+  IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
+  IN UINT32 CfgAmdPowerCeiling;                   ///< PowerCeiling, specifies a maximum power usage limit for the platform
+  IN UINT16 CfgHtcTemperatureLimit;               ///< Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+  IN UINT16 CfgLhtcTemperatureLimit;              ///< Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+
+  IN UINT32 CfgMemoryBusFrequencyLimit;           ///< Memory Bus Frequency Limit.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+  IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+  IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+  IN UINT32 CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+  IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
+  IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
+  IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
+  IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+  IN BOOLEAN CfgLimitMemoryToBelow1Tb;            ///< Limit memory address space to below 1TB
+  IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
+  IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
+  IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
+  IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+  IN UINT32  CfgPowerDownMode;                    ///< Power Down Mode.
+  IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
+  IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
+  IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
+  IN UINT32  CfgTimingModeSelect;                 ///< Timing Mode Select.
+  IN UINT32  CfgMemoryClockSelect;                ///< Memory Clock Select.
+  IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+  IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+  IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+  IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+  IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+  IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+  IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+  IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
+  IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
+  IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
+  IN UINT32  CfgAcpiPstatesPsdPolicy;             ///< PSD policy
+  IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+  IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
+  IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
+  IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
+  IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
+  IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
+  IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
+  IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
+  IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
+  IN UINT8   CfgAbmSupport;                       ///< Abm Support
+  IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
+  IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
+  IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
+  IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+  IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+  IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN FCH_PLATFORM_POLICY  *FchBldCfg;             ///< FCH platform build configuration policy
+
+  IN BOOLEAN    CfgIommuSupport;                  ///< IOMMU support
+  IN UINT8      CfgLvdsPowerOnSeqDigonToDe;       ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqDeToVaryBl;      ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqDeToDigon;       ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqVaryBlToDe;      ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqOnToOffDelay;    ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqVaryBlToBlon;    ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqBlonToVaryBl;    ///< Panel initialization timing
+  IN UINT16     CfgLvdsMaxPixelClockFreq;         ///< The maximum pixel clock frequency supported
+  IN UINT32     CfgLcdBitDepthControlValue;       ///< The LCD bit depth control settings
+  IN UINT8      CfgLvds24bbpPanelMode;            ///< The LVDS 24 BBP mode
+  IN LVDS_MISC_CONTROL CfgLvdsMiscControl;        ///< THe LVDS Misc control
+  IN UINT16     CfgPcieRefClkSpreadSpectrum;      ///< PCIe Reference Clock Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+  IN BOOLEAN    CfgExternalVrefCtlFeature;        ///< External Vref control
+  IN FORCE_TRAIN_MODE   CfgForceTrainMode;        ///< Force Train Mode
+  IN BOOLEAN    CfgGnbRemoteDisplaySupport;       ///< Wireless Display Support
+  IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
+  IN BOOLEAN    CfgGnbSyncFloodPinAsNmi;          ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI"
+  IN UINT8      CfgIgpuEnableDisablePolicy;       ///< This item defines the iGPU Enable/Disable policy
+                                                  ///< @li 0 = Auto - use current default
+                                                  ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present
+                                                  ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+  IN UINT8      CfgGnbSwTjOffset;                 ///< Software-writeable TjOffset to account for changes in junction temperature
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION}
+  IN UINT8      CfgLvdsMiscVoltAdjustment;        ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+  IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl;  ///< The Display Misc control
+  IN DP_FIXED_VOLT_SWING_TYPE CfgDpFixedVoltSwingType;///< To indicate fixed voltage swing value
+                                                      ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+  IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+                                                   ///< when it is mixed with other technology types.
+  IN BOOLEAN CfgHybridBoostEnable;                ///< HyBrid Boost support
+                                                  ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE}
+  IN UINT64  CfgGnbIoapicAddress;                 ///< GNB IOAPIC Base Address(NULL if platform configured)
+                                                  ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+  IN BOOLEAN CfgDataEyeEn;                        ///< Enable get 2D Data Eye
+  IN BOOLEAN CfgDockedTdpHeadroom;                ///< @BldCfgItem{BLDCFG_DOCKED_TDP_HEADROOM}
+  IN BOOLEAN CfgDramDoubleRefreshRateEn;          ///< Double DRAM refresh rate
+  IN BOOLEAN Reserved;                            ///< reserved...
+} BUILD_OPT_CFG;
+
+///  A structure containing platform specific operational characteristics. This
+///  structure is initially populated by the initializer with a copy of the same
+///  structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+  IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
+  IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
+                                                      ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
+  IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
+                                                      ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+  IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
+  IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
+  IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
+  IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
+  IN UINT32              C1ePlatformData3;            ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3}
+  IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+  IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+                                                      ///< If CStateMode is CStateModeC6, this item is reserved
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+  IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+                                                      ///< can be used to allow the CPU to enter Cstates.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+  IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+  IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
+  IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
+  IN BOOLEAN             UserOptionCrat;              ///< When set to TRUE, the CRAT data table is generated.
+  IN BOOLEAN             UserOptionCdit;              ///< When set to TRUE, the CDIT data table is generated.
+  IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
+  IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
+  IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
+  IN PLATFORM_LOW_POWER_PSTATE_MODES  LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
+  IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+  IN BOOLEAN             ForcePstateIndependent;      ///< Deprecated in favor of PstatesPsdPolicy.
+                                                      ///< P-State _PSD is forced independent.
+                                                      ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+  IN UINT32              PstatesPsdPolicy;            ///< PSD policy
+                                                      ///< @BldCfgItem{BLDCFG_ACPI_PSTATES_PSD_POLICY}
+  IN BOOLEAN             PStatesInHpcMode;            ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE}
+  IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+  IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+  IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+  IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+  IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                      ///< essentially it enables function 1 of graphics device.
+                                                      ///< @li 0 = HD Audio disable
+                                                      ///< @li 1 = HD Audio enable
+                                                      ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+  IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
+                                                      ///< characteristic specific to display panel which used by platform design.
+                                                      ///< @li 0 = ABM support disabled
+                                                      ///< @li 1 = ABM support enabled
+                                                      ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+  IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
+                                                      ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+  IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
+                                                      ///< If equal to 0 backlight not controlled by iGPU
+                                                      ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+  IN UINT16              HtcTemperatureLimit;         ///< The Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+                                                      ///< If equal to 0, use hardware defaults.
+                                                      ///< @BldCfgItem{BLDCFG_HTC_TEMPERATURE_LIMIT}
+  IN UINT16              LhtcTemperatureLimit;        ///< The Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+                                                      ///< If equal to 0, use hardware defaults.
+                                                      ///< @BldCfgItem{BLDCFG_LHTC_TEMPERATURE_LIMIT}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH  48
+#define MAX_DIMMS_PER_SOCKET 16
+#define PROC_MANU_LENGTH     29
+
+/*  Interface Parameter Structures  */
+/// DMI Type4 - Processor ID
+typedef struct {
+  OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
+  OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+  OUT UINT8                     T4ProcType;             ///< CPU Type
+  OUT UINT8                     T4ProcFamily;           ///< Family 1
+  OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
+  OUT UINT8                     T4Voltage;              ///< Voltage
+  OUT UINT16                    T4ExternalClock;        ///< External clock
+  OUT UINT16                    T4MaxSpeed;             ///< Max speed
+  OUT UINT16                    T4CurrentSpeed;         ///< Current speed
+  OUT UINT8                     T4Status;               ///< Status
+  OUT UINT8                     T4ProcUpgrade;          ///< Up grade
+  OUT UINT8                     T4CoreCount;            ///< Core count
+  OUT UINT8                     T4CoreEnabled;          ///< Core Enable
+  OUT UINT8                     T4ThreadCount;          ///< Thread count
+  OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
+  OUT UINT16                    T4ProcFamily2;          ///< Family 2
+  OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+  OUT CHAR8                     T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+  OUT UINT16                    T7CacheCfg;             ///< Cache cfg
+  OUT UINT16                    T7MaxCacheSize;         ///< Max size
+  OUT UINT16                    T7InstallSize;          ///< Install size
+  OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
+  OUT UINT16                    T7CurrentSramType;      ///< Current type
+  OUT UINT8                     T7CacheSpeed;           ///< Speed
+  OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
+  OUT UINT8                     T7SystemCacheType;      ///< Cache type
+  OUT UINT8                     T7Associativity;        ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+  OtherLocation = 0x01,                                 ///< Assign 01 to Other
+  UnknownLocation,                                      ///< Assign 02 to Unknown
+  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
+  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
+  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
+  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
+  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
+  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
+  NuBus,                                                ///< Assign 0A to NuBus
+  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+  OtherUse = 0x01,                                      ///< Assign 01 to Other
+  UnknownUse,                                           ///< Assign 02 to Unknown
+  SystemMemory,                                         ///< Assign 03 to system memory
+  VideoMemory,                                          ///< Assign 04 to video memory
+  FlashMemory,                                          ///< Assign 05 to flash memory
+  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
+  CacheMemory                                           ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
+  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
+  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
+  Dmi16Parity,                                          ///< Assign 04 to parity
+  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
+  Dmi16Crc                                              ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
+                                                        ///< whether on the system board or an add-in board.
+  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
+                                                        ///< is used.
+  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                        ///< detection method supported by this memory array.
+  OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
+                                                        ///< for the array.
+  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
+                                                        ///< for memory devices in this array.
+  OUT UINT64                    ExtMaxCapacity;         ///< The maximum memory capacity, in bytes,
+                                                        ///< for this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
+  UnknowFormFactor,                                     ///< Assign 02 to Unknown
+  SimmFormFactor,                                       ///< Assign 03 to SIMM
+  SipFormFactor,                                        ///< Assign 04 to SIP
+  ChipFormFactor,                                       ///< Assign 05 to Chip
+  DipFormFactor,                                        ///< Assign 06 to DIP
+  ZipFormFactor,                                        ///< Assign 07 to ZIP
+  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
+  TsopFormFactor,                                       ///< Assign 10 to TSOP
+  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
+  RimmFormFactor,                                       ///< Assign 12 to RIMM
+  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
+  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
+  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+  OtherMemType = 0x01,                                  ///< Assign 01 to Other
+  UnknownMemType,                                       ///< Assign 02 to Unknown
+  DramMemType,                                          ///< Assign 03 to DRAM
+  EdramMemType,                                         ///< Assign 04 to EDRAM
+  VramMemType,                                          ///< Assign 05 to VRAM
+  SramMemType,                                          ///< Assign 06 to SRAM
+  RamMemType,                                           ///< Assign 07 to RAM
+  RomMemType,                                           ///< Assign 08 to ROM
+  FlashMemType,                                         ///< Assign 09 to Flash
+  EepromMemType,                                        ///< Assign 10 to EEPROM
+  FepromMemType,                                        ///< Assign 11 to FEPROM
+  EpromMemType,                                         ///< Assign 12 to EPROM
+  CdramMemType,                                         ///< Assign 13 to CDRAM
+  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
+  SdramMemType,                                         ///< Assign 15 to SDRAM
+  SgramMemType,                                         ///< Assign 16 to SGRAM
+  RdramMemType,                                         ///< Assign 17 to RDRAM
+  DdrMemType,                                           ///< Assign 18 to DDR
+  Ddr2MemType,                                          ///< Assign 19 to DDR2
+  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
+  Fbd2MemType                                           ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
+  OUT UINT16                    StaticColumn:1;         ///< Static column
+  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
+  OUT UINT16                    Rambus:1;               ///< RAMBUS
+  OUT UINT16                    Synchronous:1;          ///< Synchronous
+  OUT UINT16                    Cmos:1;                 ///< CMOS
+  OUT UINT16                    Edo:1;                  ///< EDO
+  OUT UINT16                    WindowDram:1;           ///< Window DRAM
+  OUT UINT16                    CacheDram:1;            ///< Cache Dram
+  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
+  OUT UINT16                    Registered:1;           ///< Registered (Buffered)
+  OUT UINT16                    Unbuffered:1;           ///< Unbuffered (Unregistered)
+  OUT UINT16                    Reserved2:1;            ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+  OUT UINT16                    Handle;                 ///< The temporary handle, or instance number, associated with the structure
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
+                                                        ///< Memory Devices that must be populated with all devices of
+                                                        ///< the same type and size, and the set to which this device belongs.
+  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
+  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
+  OUT CHAR8                     PartNumber[19];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 - for memory use
+typedef struct {
+  OUT UINT8                     Socket:3;               ///< Socket ID
+  OUT UINT8                     Channel:2;              ///< Channel ID
+  OUT UINT8                     Dimm:2;                 ///< DIMM ID
+  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
+  OUT UINT16                    Handle;                 ///< The temporary handle, or instance number, associated with the structure
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT UINT8                     SerialNumber[4];        ///< Serial Number.
+  OUT UINT8                     PartNumber[18];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+} MEM_DMI_PHYSICAL_DIMM_INFO;
+
+/// Memory DMI Type 20 - for memory use
+typedef struct {
+  OUT UINT8                     Socket:3;               ///< Socket ID
+  OUT UINT8                     Channel:2;              ///< Channel ID
+  OUT UINT8                     Dimm:2;                 ///< DIMM ID
+  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} MEM_DMI_LOGICAL_DIMM_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                        ///< of a range of memory mapped to the
+                                                        ///< specified physical memory array.
+  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                        ///< last kilobyte of a range of addresses
+                                                        ///< mapped to the specified physical memory array.
+  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                        ///< with the physical memory array to which this
+                                                        ///< address range is mapped.
+  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                        ///< form a single row of memory for the address
+                                                        ///< partition defined by this structure.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+                                                        ///< with the Memory Array Mapped Address structure to
+                                                        ///< which this device address range is mapped.
+  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
+                                                        ///< Device in a row of the address partition.
+  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
+                                                        ///< an interleave.
+  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
+                                                        ///< referenced Memory Device that are accessed in a
+                                                        ///< single interleaved transfer.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+  OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
+  OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
+  OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
+  OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
+  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
+  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+  OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
+  OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call:  AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS    3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+  IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
+  IN OUT   UINT32               ExeCacheSize;           ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call:  AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
+     OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  );
+
+/// Selection type for core leveling
+typedef enum {
+  CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
+  CORE_LEVEL_TWO,               ///< Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
+  CORE_LEVEL_NONE,              ///< Do no leveling
+  CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
+  CORE_LEVEL_COMPUTE_UNIT_TWO,  ///< Level cores to two cores per compute unit
+  CORE_LEVEL_COMPUTE_UNIT_THREE,  ///< Level cores to three cores per compute unit
+  CORE_LEVEL_ONE,               ///< Level to 1 core
+  CORE_LEVEL_THREE,             ///< Level to 3 cores
+  CORE_LEVEL_FOUR,              ///< Level to 4 cores
+  CORE_LEVEL_FIVE,              ///< Level to 5 cores
+  CORE_LEVEL_SIX,               ///< Level to 6 cores
+  CORE_LEVEL_SEVEN,             ///< Level to 7 cores
+  CORE_LEVEL_EIGHT,             ///< Level to 8 cores
+  CORE_LEVEL_NINE,              ///< Level to 9 cores
+  CORE_LEVEL_TEN,               ///< Level to 10 cores
+  CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
+  CORE_LEVEL_TWELVE,            ///< Level to 12 cores
+  CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
+  CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
+  CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
+  CoreLevelModeMax              ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ *  AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call:  AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+  IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
+  IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
+  IN       FCH_RESET_INTERFACE       FchInterface;     ///< Interface for FCH configuration
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS     *ResetParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
+  IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS     *EarlyParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
+  IN       GNB_POST_CONFIGURATION GnbPostConfig;    ///< GNB post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
+  IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< GNB configuration
+  IN       FCH_INTERFACE          FchInterface;         ///< FCH configuration
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS       *EnvParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       GNB_MID_CONFIGURATION  GnbMidConfiguration;  ///< GNB configuration
+  IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS       *MidParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
+  IN       IOMMU_EXCLUSION_RANGE_DESCRIPTOR  *IvrsExclusionRangeList;   ///< Pointer to array of exclusion ranges
+     OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
+     OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
+     OUT   VOID                   *AcpiSrat;              ///< SRAT Table
+     OUT   VOID                   *AcpiSlit;              ///< SLIT Table
+     OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
+     OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
+     OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
+     OUT   VOID                   *AcpiIvrs;              ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+     OUT   VOID                   *AcpiCrat;              ///< Component Resource Affinity Table table
+     OUT   VOID                   *AcpiCdit;              ///< Component Locality Distance Information table
+  IN       GNB_LATE_CONFIGURATION GnbLateConfiguration;   ///< GNB configuration
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS      *LateParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
+  IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
+  IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
+  IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+  IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS    *ResumeParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+     OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
+  IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call:  AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Core's Socket.
+  IN       UINT8             Core;             ///< The Core id.
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
+     OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call:  AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Processor's socket
+  IN       UINT8             Module;           ///< The Module in that Processor
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
+     OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT8             Socket;            ///< The current Core's Socket
+     OUT   UINT8             Module;            ///< The current Core's Processor Module
+     OUT   UINT8             Core;              ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call:  AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
+     OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
+     OUT   UINT32            DataParam1;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam2;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam3;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam4;        ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
+  IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
+  OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
+  OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
+  OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  );
+
+/// Request the 2D Data Eye Training Data
+#define RD_DATAEYE  0
+#define WR_DATAEYE  1
+
+/**********************************************************************
+ * Interface service call:  AmdGet2DDataEye
+ **********************************************************************/
+/// Request the training data eye on Socket, Channel, Dimm.
+
+typedef struct _AMD_GET_DATAEYE {
+  IN OUT AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
+  IN OUT AMD_POST_PARAMS *PostParamsPtr;         ///< Pointer to AMD_POST_PARAMS
+  IN  UINT8 SocketId;                            ///< The socket number to get the 2D data eye
+  IN  UINT8 MemChannelId;                        ///< The channel number to get the 2D data eye
+  IN  UINT8 DimmId;                              ///< The dimm number to get the 2D data eye
+  IN  UINT8 DataEyeType;                         ///< Get the 2D data eye on read or write training
+  OUT UINT8* DataEyeBuffer;                      ///< The buffer to stores the 2D data eye
+} AMD_GET_DATAEYE;
+
+AGESA_STATUS
+AmdGet2DDataEye (
+  IN OUT   AMD_GET_DATAEYE *AmdGetDataEye
+  );
+
+#define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+  AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
+  AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
+  AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
+  AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+  AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
+  AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
+
+  AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
+
+  AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
+
+  AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
+  AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
+  AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
+  AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
+  AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
+
+  AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
+  AGESA_IDS_NV_DRAMCON,                             ///< 0x0027                                                  Specify the mode for controller initialization
+  AGESA_IDS_EXT_ID_END,                             ///< 0x0028                                                               specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/AMD.h b/src/vendorcode/amd/agesa/f16kb/AMD.h
new file mode 100644
index 0000000..bfce993
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/AMD.h
@@ -0,0 +1,476 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define AGESA_REVISION  "Arch2008"
+#define AGESA_ID        "AGESA"
+
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY          0xFFFFFFFFul
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+  AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
+                                 ///<  Not logged.
+  AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
+                                 ///< Example, memory address not installed, heap buffer handle not found.
+                                 ///< Not Logged.
+  // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT,                   ///< An observed condition, but no loss of function.
+                                 ///<  See log.  Example, HT CRC.
+  AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
+  AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
+  AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
+                                 ///< may not be able to reliably produce log events.
+  AgesaStatusMax                 ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in]        Function      The specific callout function being invoked.
+ * @param[in]        FcnData       Function specific data item.
+ * @param[in,out]    ConfigPtr     Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+  IN       UINT32  Function,
+  IN       UINTN   FcnData,
+  IN OUT   VOID    *ConfigPtr
+  );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+  // AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY = 0x00020000,                           ///< AmdInitRecovery entry point handle
+  AMD_CREATE_STRUCT,                                        ///< AmdCreateStruct handle
+  AMD_INIT_EARLY,                                           ///< AmdInitEarly entry point handle
+  AMD_INIT_ENV,                                             ///< AmdInitEnv entry point handle
+  AMD_INIT_LATE,                                            ///< AmdInitLate entry point handle
+  AMD_INIT_MID,                                             ///< AmdInitMid entry point handle
+  AMD_INIT_POST,                                            ///< AmdInitPost entry point handle
+  AMD_INIT_RESET,                                           ///< AmdInitReset entry point handle
+  AMD_INIT_RESUME,                                          ///< AmdInitResume entry point handle
+  AMD_RELEASE_STRUCT,                                       ///< AmdReleaseStruct handle
+  AMD_S3LATE_RESTORE,                                       ///< AmdS3LateRestore entry point handle
+  AMD_S3_SAVE,                                              ///< AmdS3Save entry point handle
+  AMD_GET_APIC_ID,                                          ///< AmdGetApicId entry point handle
+  AMD_GET_PCI_ADDRESS,                                      ///< AmdGetPciAddress entry point handle
+  AMD_IDENTIFY_CORE,                                        ///< AmdIdentifyCore general service handle
+  AMD_READ_EVENT_LOG,                                       ///< AmdReadEventLog general service handle
+  AMD_GET_EXECACHE_SIZE,                                    ///< AmdGetAvailableExeCacheSize general service handle
+  AMD_LATE_RUN_AP_TASK,                                     ///< AmdLateRunApTask entry point handle
+  AMD_IDENTIFY_DIMMS,                                       ///< AmdIdentifyDimm general service handle
+  AMD_GET_2D_DATA_EYE                                       ///< AmdGet2DDataEye general service handle
+} AGESA_STRUCT_NAME;
+
+  /*  ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       UINT32          Func;             ///< The service desired
+  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
+  IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
+  IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
+  IN       UINT64          HeapBasePtr;      ///< Location of the heap
+  IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
+  IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
+  IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
+  IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
+                                                   ///< The struct to init for ByHost allocation,
+                                                   ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+/// AGESA Binary module header structure
+typedef struct {
+  IN  UINT32  Signature;                          ///< Binary Signature
+  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
+  IN  CHAR8   Version[12];                        ///< 12 characters version
+  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
+  IN  UINT32  EntryPointAddress;                  ///< Entry address
+  IN  UINT32  ImageBase;                          ///< Image base
+  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
+  IN  UINT32  ImageSize;                          ///< Size
+  IN  UINT16  Checksum;                           ///< Checksum
+  IN  UINT8   ImageType;                          ///< Type
+  IN  UINT8   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
+  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
+  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
+  IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
+  IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE  {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+  IN  CHAR8   Signature[8];                       ///< code header Signature
+  IN  CHAR8   ComponentName[16];                  ///< 16 character name of the code module
+  IN  CHAR8   Version[12];                        ///< 12 character version string
+  IN  CHAR8   TerminatorNull;                     ///< null terminated string
+  IN  CHAR8   VerReserved[7];                     ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+  IN OUT  UINT32      Register:12;                ///< Register offset
+  IN OUT  UINT32      Function:3;                 ///< Function number
+  IN OUT  UINT32      Device:5;                   ///< Device number
+  IN OUT  UINT32      Bus:8;                      ///< Bus number
+  IN OUT  UINT32      Segment:4;                  ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+  IN  UINT32          AddressValue;               ///< Formal address
+  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
+} PCI_ADDR;
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function(3-bits)
+//   11:00   Offset  (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFFul
+
+/// CPUID data received registers format
+typedef struct {
+  OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
+  OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
+  OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
+  OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19,                ///< HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX                                ///< Limit check.
+} HT_FREQUENCIES;
+// The minimum HT3 frequency
+#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Dispatcher.h b/src/vendorcode/amd/agesa/f16kb/Dispatcher.h
new file mode 100644
index 0000000..eecdd0e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Dispatcher.h
@@ -0,0 +1,51 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ***************************************************************************
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h
new file mode 100644
index 0000000..43794e3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h
@@ -0,0 +1,166 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Advanced API Interface for HT, Memory and CPU
+ *
+ * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
+ * would be required by the basic interface implementations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _ADVANCED_API_H_
+#define _ADVANCED_API_H_
+
+/*----------------------------------------------------------------------------
+ *                           HT FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  );
+
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  );
+
+/*----------------------------------------------------------------------------
+ *                        HT Recovery   FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ */
+AGESA_STATUS
+AmdHtResetConstructor (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+/**
+ * Initialize HT at Reset for both Normal and Recovery.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+///----------------------------------------------------------------------------
+///                          MEMORY FUNCTIONS PROTOTYPE
+///
+///----------------------------------------------------------------------------
+
+AGESA_STATUS
+AmdMemRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT  PLATFORM_CONFIGURATION   *PlatFormConfig
+  );
+
+VOID
+memDefRet ( VOID );
+
+BOOLEAN
+memDefTrue ( VOID );
+
+BOOLEAN
+memDefFalse ( VOID );
+
+VOID
+MemRecDefRet ( VOID );
+
+BOOLEAN
+MemRecDefTrue ( VOID );
+
+#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f16kb/Include/CommonReturns.h
new file mode 100644
index 0000000..539acbc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/CommonReturns.h
@@ -0,0 +1,159 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * Routines which do nothing, returning a result (preferably some version of zero) which
+ * is consistent with "do nothing" or "default".  Useful for function pointer tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _COMMON_RETURNS_H_
+#define _COMMON_RETURNS_H_
+
+
+/**
+* Return True
+*
+* @retval True    Default case, no special action
+*/
+BOOLEAN
+CommonReturnTrue ( VOID );
+
+/**
+* Return False.
+*
+* @retval FALSE    Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse ( VOID );
+
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 ( VOID );
+
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 ( VOID );
+
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 ( VOID );
+
+/**
+ * Return (UINT8)one.
+ *
+ *
+ * @retval one     None, or only case one.
+ */
+UINT8
+CommonReturnOne8 ( VOID );
+
+/**
+ * Return (UINT32)one.
+ *
+ *
+ * @retval one     None, or only case one.
+ */
+UINT32
+CommonReturnOne32 ( VOID );
+
+/**
+ * Return (UINT64)one.
+ *
+ *
+ * @retval one     None, or only case one.
+ */
+UINT64
+CommonReturnOne64 ( VOID );
+
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL ( VOID );
+
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess ( VOID );
+
+/**
+* Return AGESA_ERROR.
+*
+* @retval AGESA_ERROR Error.
+*/
+AGESA_STATUS
+CommonReturnAgesaError ( VOID );
+
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid ( VOID );
+
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert ( VOID );
+
+#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h
new file mode 100644
index 0000000..a3b3472
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h
@@ -0,0 +1,581 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 86079 $   @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE                                         (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE                               (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE                          (0xA001)
+#define PROC_GNB_GNBINITATEARLY_FILECODE                                 (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE                                   (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE                                  (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE                                   (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE                                  (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE                                 (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE                    (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE              (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE                (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE               (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE              (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE                 (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE              (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE            (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE      (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE      (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE          (0xA034)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE           (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE            (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE          (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE          (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE     (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE   (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE       (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE       (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE        (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE      (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE         (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE   (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE             (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE  (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE        (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE     (0xA049)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE              (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE             (0xA08F)
+#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE                      (0xA090)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE        (0xA091)
+#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE                  (0xA0A8)
+#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE          (0xA0A9)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE   (0xA0AA)
+
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE                     (0xA0BA)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE                      (0xA0BB)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE               (0xA0BD)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE             (0xA0C0)
+#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE                   (0xA0C2)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE     (0xA0C5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE     (0xA0C6)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE    (0xA0C7)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE       (0xA0C8)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
+#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE          (0xA0CB)
+
+
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE       (0xA0DB)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE       (0xA0DC)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE    (0xA0DD)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE              (0xA0E0)
+
+#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE                    (0xA0EE)
+
+#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE       (0xA0F4)
+#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE                 (0xA0F5)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE        (0xA101)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE     (0xA102)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE                           (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE                        (0xAE02)
+#define PROC_GNB_GNBINITATS3SAVE_FILECODE                                (0xAE03)
+#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE                      (0xAE04)
+
+
+#define PROC_GNB_MODULES_GNBINITKB_GFXENVINITKB_FILECODE                 (0xAE20)
+#define PROC_GNB_MODULES_GNBINITKB_GFXINTEGRATEDINFOTABLEKB_FILECODE     (0xAE21)
+#define PROC_GNB_MODULES_GNBINITKB_GFXMIDINITKB_FILECODE                 (0xAE22)
+#define PROC_GNB_MODULES_GNBINITKB_GFXPOSTINITKB_FILECODE                (0xAE23)
+#define PROC_GNB_MODULES_GNBINITKB_GFXLIBKB_FILECODE                     (0xAE24)
+#define PROC_GNB_MODULES_GNBINITKB_GNBEARLYINITKB_FILECODE               (0xAE25)
+#define PROC_GNB_MODULES_GNBINITKB_GNBENVINITKB_FILECODE                 (0xAE26)
+#define PROC_GNB_MODULES_GNBINITKB_GNBMIDINITKB_FILECODE                 (0xAE27)
+#define PROC_GNB_MODULES_GNBINITKB_GNBPOSTINITKB_FILECODE                (0xAE28)
+#define PROC_GNB_MODULES_GNBINITKB_GNBREGISTERACCKB_FILECODE             (0xAE29)
+#define PROC_GNB_MODULES_GNBINITKB_PCIECOMPLEXDATAKB_FILECODE            (0xAE2A)
+#define PROC_GNB_MODULES_GNBINITKB_PCIECONFIGKB_FILECODE                 (0xAE2B)
+#define PROC_GNB_MODULES_GNBINITKB_PCIEEARLYINITKB_FILECODE              (0xAE2C)
+#define PROC_GNB_MODULES_GNBINITKB_PCIEENVINITKB_FILECODE                (0xAE2D)
+#define PROC_GNB_MODULES_GNBINITKB_PCIEMIDINITKB_FILECODE                (0xAE2F)
+#define PROC_GNB_MODULES_GNBINITKB_PCIEPOSTINITKB_FILECODE               (0xAE30)
+#define PROC_GNB_MODULES_GNBINITKB_PCIELIBKB_FILECODE                    (0xAE31)
+#define PROC_GNB_MODULES_GNBINITKB_GFXGMCINITKB_FILECODE                 (0xAE32)
+#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE               (0xAE33)
+#define PROC_GNB_MODULES_GNBINITKV_ALIBKVD_FILECODE                      (0xAE34)
+#define PROC_GNB_MODULES_GNBINITKV_GNBREGISTERXLATKV_FILECODE            (0xAE37)
+#define PROC_GNB_MODULES_GNBINITKV_GNBFUSETABLEKV_FILECODE               (0xAE39)
+#define PROC_GNB_MODULES_GNBINITKV_GNBURAKV_FILECODE                     (0xAE3B)
+#define PROC_GNB_MODULES_GNBINITKB_GNBURATOKENMAPKB_FILECODE             (0xAE3E)
+#define PROC_GNB_MODULES_GNBINITBK_GNBURABK_FILECODE                     (0xAE3F)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXINTEGRATEDINFOTABLE_FILECODE (0xAE42)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXPWRPLAYTABLE_FILECODE       (0xAE43)
+#define PROC_GNB_MODULES_GNBSCSLIBV1_GNBSCSLIBV1_FILECODE                (0xAE44)
+#define PROC_GNB_MODULES_GNBINITKB_GFXSAMUINITKB_FILECODE                (0xAE45)
+
+#define PROC_GNB_MODULES_GNBINITML_GFXENVINITML_FILECODE                 (0xAE50)
+
+// FCH
+#define PROC_FCH_AZALIA_AZALIARESET_FILECODE                             (0xB001)
+#define PROC_FCH_AZALIA_AZALIAENV_FILECODE                               (0xB002)
+#define PROC_FCH_AZALIA_AZALIAMID_FILECODE                               (0xB003)
+#define PROC_FCH_AZALIA_AZALIALATE_FILECODE                              (0xB004)
+#define PROC_FCH_COMMON_ACPILIB_FILECODE                                 (0xB010)
+#define PROC_FCH_COMMON_FCHLIB_FILECODE                                  (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE                               (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE                            (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE                                  (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE                                  (0xB015)
+#define PROC_FCH_COMMON_FCHPELIB_FILECODE                                (0xB016)
+#define PROC_FCH_GEC_GECRESET_FILECODE                                   (0xB020)
+#define PROC_FCH_GEC_GECENV_FILECODE                                     (0xB021)
+#define PROC_FCH_GEC_GECMID_FILECODE                                     (0xB022)
+#define PROC_FCH_GEC_GECLATE_FILECODE                                    (0xB023)
+#define PROC_FCH_GEC_FAMILY_YANGTZE_YANGTZEGECSERVICE_FILECODE           (0xB028)
+#define PROC_FCH_GEC_FAMILY_YANGTZE_YANGTZEGECENVSERVICE_FILECODE        (0xB029)
+#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE                             (0xB030)
+#define PROC_FCH_HWACPI_HWACPIENV_FILECODE                               (0xB031)
+#define PROC_FCH_HWACPI_HWACPIMID_FILECODE                               (0xB032)
+#define PROC_FCH_HWACPI_HWACPILATE_FILECODE                              (0xB033)
+#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPIENVSERVICE_FILECODE  (0xB03C)
+#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPIMIDSERVICE_FILECODE  (0xB03D)
+#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPILATESERVICE_FILECODE (0xB03E)
+#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZESSSERVICE_FILECODE         (0xB03F)
+#define PROC_FCH_HWM_HWMRESET_FILECODE                                   (0xB050)
+#define PROC_FCH_HWM_HWMENV_FILECODE                                     (0xB051)
+#define PROC_FCH_HWM_HWMMID_FILECODE                                     (0xB052)
+#define PROC_FCH_HWM_HWMLATE_FILECODE                                    (0xB053)
+#define PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMENVSERVICE_FILECODE        (0xB05A)
+#define PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMMIDSERVICE_FILECODE        (0xB05B)
+#define PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMLATESERVICE_FILECODE       (0xB05C)
+#define PROC_FCH_IMC_IMCENV_FILECODE                                     (0xB060)
+#define PROC_FCH_IMC_IMCMID_FILECODE                                     (0xB061)
+#define PROC_FCH_IMC_IMCLATE_FILECODE                                    (0xB062)
+#define PROC_FCH_IMC_IMCLIB_FILECODE                                     (0xB063)
+#define PROC_FCH_IMC_IMCRESET_FILECODE                                   (0xB064)
+#define PROC_FCH_IMC_FCHECENV_FILECODE                                   (0xB065)
+#define PROC_FCH_IMC_FCHECMID_FILECODE                                   (0xB066)
+#define PROC_FCH_IMC_FCHECLATE_FILECODE                                  (0xB067)
+#define PROC_FCH_IMC_FCHECRESET_FILECODE                                 (0xB068)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE           (0xB069)
+#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE                 (0xB06A)
+#define PROC_FCH_IMC_FAMILY_YANGTZE_YANGTZEIMCSERVICE_FILECODE           (0xB06B)
+#define PROC_FCH_IMC_FAMILY_AVALON_AVALONIMCSERVICE_FILECODE             (0xB36B)
+#define PROC_FCH_IDE_IDEENV_FILECODE                                     (0xB06D)
+#define PROC_FCH_IDE_IDEMID_FILECODE                                     (0xB06E)
+#define PROC_FCH_IDE_IDELATE_FILECODE                                    (0xB06F)
+#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE                         (0xB070)
+#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE                           (0xB071)
+#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE                         (0xB072)
+#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE                           (0xB073)
+#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE                          (0xB074)
+#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE                           (0xB075)
+#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE                            (0xB076)
+#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE                      (0xB077)
+#define PROC_FCH_IR_IRENV_FILECODE                                       (0xB080)
+#define PROC_FCH_IR_IRMID_FILECODE                                       (0xB081)
+#define PROC_FCH_IR_IRLATE_FILECODE                                      (0xB082)
+#define PROC_FCH_PCIB_PCIBRESET_FILECODE                                 (0xB090)
+#define PROC_FCH_PCIB_PCIBENV_FILECODE                                   (0xB091)
+#define PROC_FCH_PCIB_PCIBMID_FILECODE                                   (0xB092)
+#define PROC_FCH_PCIB_PCIBLATE_FILECODE                                  (0xB093)
+#define PROC_FCH_PCIE_ABRESET_FILECODE                                   (0xB0A0)
+#define PROC_FCH_PCIE_ABENV_FILECODE                                     (0xB0A1)
+#define PROC_FCH_PCIE_ABMID_FILECODE                                     (0xB0A2)
+#define PROC_FCH_PCIE_ABLATE_FILECODE                                    (0xB0A3)
+#define PROC_FCH_PCIE_GPPHP_FILECODE                                     (0xB0A4)
+#define PROC_FCH_PCIE_GPPLIB_FILECODE                                    (0xB0A5)
+#define PROC_FCH_PCIE_GPPRESET_FILECODE                                  (0xB0A6)
+#define PROC_FCH_PCIE_GPPENV_FILECODE                                    (0xB0A7)
+#define PROC_FCH_PCIE_GPPMID_FILECODE                                    (0xB0A8)
+#define PROC_FCH_PCIE_GPPLATE_FILECODE                                   (0xB0A9)
+#define PROC_FCH_PCIE_PCIERESET_FILECODE                                 (0xB0AA)
+#define PROC_FCH_PCIE_PCIEENV_FILECODE                                   (0xB0AB)
+#define PROC_FCH_PCIE_PCIEMID_FILECODE                                   (0xB0AC)
+#define PROC_FCH_PCIE_PCIELATE_FILECODE                                  (0xB0AD)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE      (0xB0AE)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE        (0xB0AF)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE           (0xB0B0)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE     (0xB0B1)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE          (0xB0B2)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE      (0xB0B3)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE         (0xB0B4)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE            (0xB0B5)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE              (0xB0B6)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE                 (0xB0B7)
+#define PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABRESETSERVICE_FILECODE      (0xB0B8)
+#define PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABENVSERVICE_FILECODE        (0xB0B9)
+#define PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABSERVICE_FILECODE           (0xB0BA)
+#define PROC_FCH_PCIE_FAMILY_AVALON_AVALONABRESETSERVICE_FILECODE        (0xB3B8)
+#define PROC_FCH_PCIE_FAMILY_AVALON_AVALONABENVSERVICE_FILECODE          (0xB3B9)
+#define PROC_FCH_PCIE_FAMILY_AVALON_AVALONABSERVICE_FILECODE             (0xB3BA)
+#define PROC_FCH_SATA_AHCIENV_FILECODE                                   (0xB0C0)
+#define PROC_FCH_SATA_AHCIMID_FILECODE                                   (0xB0C1)
+#define PROC_FCH_SATA_AHCILATE_FILECODE                                  (0xB0C2)
+#define PROC_FCH_SATA_AHCILIB_FILECODE                                   (0xB0C3)
+#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE                               (0xB0C4)
+#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE                               (0xB0C5)
+#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE                              (0xB0C6)
+#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE                               (0xB0C7)
+#define PROC_FCH_SATA_RAIDENV_FILECODE                                   (0xB0C8)
+#define PROC_FCH_SATA_RAIDMID_FILECODE                                   (0xB0C9)
+#define PROC_FCH_SATA_RAIDLATE_FILECODE                                  (0xB0CA)
+#define PROC_FCH_SATA_RAIDLIB_FILECODE                                   (0xB0CB)
+#define PROC_FCH_SATA_SATAENV_FILECODE                                   (0xB0CC)
+#define PROC_FCH_SATA_SATAENVLIB_FILECODE                                (0xB0CD)
+#define PROC_FCH_SATA_SATAIDEENV_FILECODE                                (0xB0CE)
+#define PROC_FCH_SATA_SATAIDEMID_FILECODE                                (0xB0CF)
+#define PROC_FCH_SATA_SATAIDELATE_FILECODE                               (0xB0D0)
+#define PROC_FCH_SATA_SATAIDELIB_FILECODE                                (0xB0D1)
+#define PROC_FCH_SATA_SATAMID_FILECODE                                   (0xB0D2)
+#define PROC_FCH_SATA_SATALATE_FILECODE                                  (0xB0D3)
+#define PROC_FCH_SATA_SATALIB_FILECODE                                   (0xB0D4)
+#define PROC_FCH_SATA_SATARESET_FILECODE                                 (0xB0D5)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE    (0xB0D6)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE      (0xB0D7)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE         (0xB0D8)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE          (0xB0D9)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE            (0xB0DA)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE               (0xB0DB)
+#define PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATARESETSERVICE_FILECODE    (0xB0DC)
+#define PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATAENVSERVICE_FILECODE      (0xB0DD)
+#define PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATASERVICE_FILECODE         (0xB0DE)
+#define PROC_FCH_SD_SDENV_FILECODE                                       (0xB0E0)
+#define PROC_FCH_SD_SDMID_FILECODE                                       (0xB0E1)
+#define PROC_FCH_SD_SDLATE_FILECODE                                      (0xB0E2)
+#define PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDSERVICE_FILECODE             (0xB0E9)
+#define PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDRESETSERVICE_FILECODE        (0xB0EA)
+#define PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDENVSERVICE_FILECODE          (0xB0EB)
+#define PROC_FCH_SPI_LPCRESET_FILECODE                                   (0xB0F0)
+#define PROC_FCH_SPI_LPCENV_FILECODE                                     (0xB0F1)
+#define PROC_FCH_SPI_LPCMID_FILECODE                                     (0xB0F2)
+#define PROC_FCH_SPI_LPCLATE_FILECODE                                    (0xB0F3)
+#define PROC_FCH_SPI_SPIRESET_FILECODE                                   (0xB0F4)
+#define PROC_FCH_SPI_SPIENV_FILECODE                                     (0xB0F5)
+#define PROC_FCH_SPI_SPIMID_FILECODE                                     (0xB0F6)
+#define PROC_FCH_SPI_SPILATE_FILECODE                                    (0xB0F7)
+#define PROC_FCH_SPI_FAMILY_YANGTZE_YANGTZELPCENVSERVICE_FILECODE        (0xB0FE)
+#define PROC_FCH_SPI_FAMILY_YANGTZE_YANGTZELPCRESETSERVICE_FILECODE      (0xB0FF)
+#define PROC_FCH_USB_EHCIRESET_FILECODE                                  (0xB100)
+#define PROC_FCH_USB_EHCIENV_FILECODE                                    (0xB101)
+#define PROC_FCH_USB_EHCIMID_FILECODE                                    (0xB102)
+#define PROC_FCH_USB_EHCILATE_FILECODE                                   (0xB103)
+#define PROC_FCH_USB_OHCIRESET_FILECODE                                  (0xB104)
+#define PROC_FCH_USB_OHCIENV_FILECODE                                    (0xB105)
+#define PROC_FCH_USB_OHCIMID_FILECODE                                    (0xB106)
+#define PROC_FCH_USB_OHCILATE_FILECODE                                   (0xB107)
+#define PROC_FCH_USB_USBRESET_FILECODE                                   (0xB108)
+#define PROC_FCH_USB_USBENV_FILECODE                                     (0xB109)
+#define PROC_FCH_USB_USBMID_FILECODE                                     (0xB10A)
+#define PROC_FCH_USB_USBLATE_FILECODE                                    (0xB10B)
+#define PROC_FCH_USB_XHCIRESET_FILECODE                                  (0xB10C)
+#define PROC_FCH_USB_XHCIENV_FILECODE                                    (0xB10D)
+#define PROC_FCH_USB_XHCIMID_FILECODE                                    (0xB10E)
+#define PROC_FCH_USB_XHCILATE_FILECODE                                   (0xB10F)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEEHCIENVSERVICE_FILECODE       (0xB124)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEEHCIMIDSERVICE_FILECODE       (0xB125)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEEHCILATESERVICE_FILECODE      (0xB126)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEOHCIENVSERVICE_FILECODE       (0xB127)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEOHCIMIDSERVICE_FILECODE       (0xB128)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEOHCILATESERVICE_FILECODE      (0xB129)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCIRESETSERVICE_FILECODE     (0xB12A)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCIENVSERVICE_FILECODE       (0xB12B)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCIMIDSERVICE_FILECODE       (0xB12C)
+#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCILATESERVICE_FILECODE      (0xB12D)
+#define PROC_FCH_USB_XHCIRECOVERY_FILECODE                               (0xB12E)
+#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE                               (0xB12F)
+#define PROC_FCH_PCIE_GPPALLINONE_FILECODE                               (0xB2C0)
+
+#define LIB_AMDLIB_FILECODE                                              (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE                               (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE                                 (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE                                  (0xC012)
+
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE                                (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE                                  (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE                                 (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE                                  (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE                                 (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE                             (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE                                (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE                               (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE                            (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE                                   (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE                            (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE                               (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE                                (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE                                 (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE                              (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE                                 (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE                               (0xC401)
+#define PROC_CPU_TABLE_FILECODE                                          (0xC403)
+#define PROC_CPU_TABLEHT_FILECODE                                        (0xC404)
+#define PROC_CPU_CPUEARLYINIT_FILECODE                                   (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE                                    (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE                           (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE                             (0xC408)
+#define PROC_CPU_CPULATEINIT_FILECODE                                    (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE                              (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE                                   (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE                                    (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE                                        (0xC40E)
+#define PROC_CPU_MMIOMAPMANAGER_FILECODE                                 (0xC40F)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE                                    (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE                                   (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE                        (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE                       (0xC432)
+#define PROC_CPU_S3_FILECODE                                             (0xC460)
+
+// Family 15h
+
+
+
+// Family 16h
+#define PROC_CPU_FAMILY_0X16_CPUF16BRANDID_FILECODE                      (0xCC00)
+#define PROC_CPU_FAMILY_0X16_CPUF16UTILITIES_FILECODE                    (0xCC01)
+#define PROC_CPU_FAMILY_0X16_CPUF16WHEAINITDATATABLES_FILECODE           (0xCC02)
+#define PROC_CPU_FAMILY_0X16_CPUF16CACHEDEFAULTS_FILECODE                (0xCC03)
+#define PROC_CPU_FAMILY_0X16_CPUF16DMI_FILECODE                          (0xCC04)
+#define PROC_CPU_FAMILY_0X16_CPUF16PCIUNKNOWNTABLES_FILECODE             (0xCC05)
+#define PROC_CPU_FAMILY_0X16_CPUF16MSRUNKNOWNTABLES_FILECODE             (0xCC06)
+#define PROC_CPU_FAMILY_0X16_CPUF16PSTATEHPCMODE_FILECODE                (0xCC07)
+#define PROC_CPU_FAMILY_0X16_CPUF16MMIOMAP_FILECODE                      (0xCC08)
+#define PROC_CPU_FAMILY_0X16_CPUF16PREFETCHMODE_FILECODE                 (0xCC09)
+#define PROC_CPU_FAMILY_0X16_CPUF16APM_FILECODE                          (0xCC0A)
+#define PROC_CPU_FAMILY_0X16_CPUF16CRAT_FILECODE                         (0xCC0B)
+
+#define PROC_CPU_FAMILY_0X16_KB_F16KBLOGICALIDTABLES_FILECODE            (0xCC20)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE             (0xCC21)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBEQUIVALENCETABLE_FILECODE           (0xCC22)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBMICROCODEPATCHTABLES_FILECODE       (0xCC23)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBPCITABLES_FILECODE                  (0xCC24)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBMSRTABLES_FILECODE                  (0xCC25)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBSHAREDMSRTABLE_FILECODE             (0xCC26)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBUTILITIES_FILECODE                  (0xCC27)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBC6STATE_FILECODE                    (0xCC28)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBCOREAFTERRESET_FILECODE             (0xCC29)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBCPB_FILECODE                        (0xCC2A)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBDMI_FILECODE                        (0xCC2B)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBIOCSTATE_FILECODE                   (0xCC2C)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBNBAFTERRESET_FILECODE               (0xCC2D)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBPOWERCHECK_FILECODE                 (0xCC2E)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBPSTATE_FILECODE                     (0xCC2F)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBPSI_FILECODE                        (0xCC30)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBHTC_FILECODE                        (0xCC31)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBPOWERMGMTSYSTEMTABLES_FILECODE      (0xCC32)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBSCS_FILECODE                        (0xCC33)
+#define PROC_CPU_FAMILY_0X16_KB_F16KBCACHEFLUSHONHALT_FILECODE           (0xCC34)
+
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE                    (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE                           (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE                                 (0xDC10)
+#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE                     (0xDC20)
+#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE                          (0xDC30)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE                        (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE                      (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE                        (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE                                (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE                                (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE                                (0xDC70)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE                             (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE                                 (0xDC83)
+#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE                        (0xDC84)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE                            (0xDC85)
+#define PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE                       (0xDC86)
+#define PROC_CPU_FEATURE_CPUAPM_FILECODE                                 (0xDC87)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE                            (0xDC90)
+#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE                         (0xDCA0)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE                        (0xDCB0)
+#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE                        (0xDCC0)
+#define PROC_CPU_FEATURE_CPUPSI_FILECODE                                 (0xDCC1)
+#define PROC_CPU_FEATURE_CPUHTC_FILECODE                                 (0xDCC2)
+#define PROC_CPU_FEATURE_CPUCRAT_FILECODE                                (0xDCD0)
+#define PROC_CPU_FEATURE_CPUCDIT_FILECODE                                (0xDCD1)
+#define PROC_CPU_FEATURE_CPUTDPLIMITING_FILECODE                         (0xDCD2)
+#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE                        (0xDCD3)
+#define PROC_CPU_FEATURE_CPUSCS_FILECODE                                 (0xDCD4)
+
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE                                (0xE801)
+#define PROC_IDS_LIBRARY_IDSLIB_FILECODE                                 (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE                                 (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE                                   (0xE804)
+#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE                              (0xE810)
+#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE                              (0xE811)
+#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE                            (0xE812)
+#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE                              (0xE813)
+#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE                          (0xE814)
+#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE                                 (0xE815)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE                              (0xE81E)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE                            (0xE81F)
+#define PROC_IDS_FAMILY_0X16_KB_IDSF16KBALLSERVICE_FILECODE              (0xE821)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE                                    (0xF001)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE                         (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE                         (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE                             (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE                             (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE                (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE                   (0xF088)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE                       (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE                       (0xF08B)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE                 (0xF08D)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE             (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE             (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE                               (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE                           (0xF093)
+#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE                           (0xF095)
+#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE                   (0xF097)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE         (0xF098)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE      (0xF099)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE         (0xF09A)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE          (0xF09B)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_KB_MFRDWR2DKB_FILECODE             (0xF09D)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_ML_MFRDWR2DML_FILECODE             (0xF09E)
+#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE                    (0xF09F)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE                                  (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE                                 (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE                                    (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE                             (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE                                 (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE                         (0xF106)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE                      (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE                         (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE                    (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE                    (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE                                   (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE                              (0xF110)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE                                (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE                               (0xF113)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE                              (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE                            (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE                          (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE                      (0xF118)
+#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE                           (0xF119)
+#define PROC_MEM_MAIN_KB_MMFLOWKB_FILECODE                           (0xF124)
+
+#define PROC_MEM_NB_MN_FILECODE                                      (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE                                   (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE                                   (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE                                   (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE                                    (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE                                  (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE                                  (0XF282)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE                                (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE                                   (0XF285)
+#define PROC_MEM_NB_MNPMU_FILECODE                                   (0xF2B7)
+#define PROC_MEM_NB_KB_MNREGKB_FILECODE                              (0XF2B8)
+#define PROC_MEM_NB_KB_MNKB_FILECODE                                 (0XF2B9)
+#define PROC_MEM_NB_KB_MNMCTKB_FILECODE                              (0XF2BA)
+#define PROC_MEM_NB_KB_MNOTKB_FILECODE                               (0XF2BB)
+#define PROC_MEM_NB_KB_MNDCTKB_FILECODE                              (0XF2BC)
+#define PROC_MEM_NB_KB_MNPHYKB_FILECODE                              (0XF2BD)
+#define PROC_MEM_NB_KB_MNS3KB_FILECODE                               (0XF2BE)
+#define PROC_MEM_NB_KB_MNIDENDIMMKB_FILECODE                         (0XF2BF)
+#define PROC_MEM_NB_KB_MNFLOWKB_FILECODE                             (0XF2C0)
+#define PROC_MEM_NB_KB_MNPROTOKB_FILECODE                            (0XF2C1)
+
+
+#define PROC_MEM_PS_MP_FILECODE                                      (0XF401)
+#define PROC_MEM_PS_MPRTT_FILECODE                                   (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE                               (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE                                (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE                                   (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE                                   (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE                                (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE                             (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE                                 (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE                                 (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE                                 (0XF42B)
+#define PROC_MEM_PS_MPS2D_FILECODE                                   (0XF436)
+#define PROC_MEM_PS_MPSEEDS_FILECODE                                 (0XF437)
+#define PROC_MEM_PS_KB_MPSKB3_FILECODE                               (0XF438)
+#define PROC_MEM_PS_KB_MPKB3_FILECODE                                (0XF439)
+#define PROC_MEM_PS_KB_MPUKB3_FILECODE                               (0XF43A)
+#define PROC_MEM_PS_KB_FT3_MPSKBFT3_FILECODE                         (0XF43B)
+#define PROC_MEM_PS_MPCADCFG_FILECODE                                (0XF43C)
+#define PROC_MEM_PS_MPDATACFG_FILECODE                               (0XF43D)
+
+#define PROC_MEM_TECH_MT_FILECODE                                    (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE                                 (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE                              (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE                                (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE                                (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE                                 (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE                             (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE                                (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE                         (0XF50C)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE                              (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE                            (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE                           (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE                           (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE                           (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE                           (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE                          (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE                        (0XF589)
+#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE                       (0XF58A)
+#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE                    (0XF58B)
+#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE                (0XF58C)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h
new file mode 100644
index 0000000..d07db77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h
@@ -0,0 +1,201 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components.  Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+  AGESA_STATUS EventClass;   ///< The severity of the event, its associated AGESA_STATUS.
+  UINT32   EventInfo;        ///< Uniquely identifies the event.
+  UINT32   DataParam1;       ///< Event specific additional data
+  UINT32   DataParam2;       ///< Event specific additional data
+  UINT32   DataParam3;       ///< Event specific additional data
+  UINT32   DataParam4;       ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f16kb/Include/GnbInterface.h
new file mode 100644
index 0000000..314383d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/GnbInterface.h
@@ -0,0 +1,123 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB API definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84514 $   @e \$Date: 2012-12-17 10:44:17 -0600 (Mon, 17 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBINTERFACE_H_
+#define _GNBINTERFACE_H_
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT  AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtPostDef (
+  IN OUT  GNB_POST_CONFIGURATION  *GnbPostConfigPtr,
+  IN      AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtMidDef (
+  IN OUT  GNB_MID_CONFIGURATION   *GnbMidConfigPtr,
+  IN      AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtLateDef (
+  IN OUT  GNB_LATE_CONFIGURATION  *GnbLateConfigPtr,
+  IN      AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS       *AmdS3SaveParams
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h
new file mode 100644
index 0000000..69bb6da
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h
@@ -0,0 +1,1426 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 87651 $   @e \$Date: 2013-02-06 13:31:52 -0600 (Wed, 06 Feb 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+  /* Macros to aid debugging */
+  /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE  1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS;  ///< Status of IDS function.
+#define IDS_SUCCESS         ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED     ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+#ifndef IDS_DEADLOOP
+  #define IDS_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+/**
+ *  IDS Option Hook Points
+ *
+ *  These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum {                        //vv- for debug reference only
+  IDS_INIT_EARLY_BEFORE,              ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+                                          ///<   IDS Object is initialized.
+                                          ///<   Override CPU Core Leveling Mode.
+                                          ///<   Set P-State in Post
+  IDS_INIT_EARLY_AFTER,               ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+  IDS_INIT_LATE_BEFORE,               ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+                                          ///< It will be used to control the following tables.
+                                          ///<   ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+                                          ///<   ACPI SRAT Table
+                                          ///<   ACPI SLIT Table
+                                          ///<   ACPI WHEA Table
+                                          ///<   DMI Table
+  IDS_INIT_LATE_AFTER,                ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+  IDS_INIT_MID_BEFORE,                ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+  IDS_INIT_MID_AFTER,                 ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+  IDS_INIT_POST_BEFORE,               ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+                                          ///<   Control Interleaving and DRAM memory hole
+                                          ///<   Override the setting of ECC Control
+                                          ///<   Override the setting of Online Spare Rank
+  IDS_INIT_POST_AFTER,                ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_INIT_RESET_BEFORE,              ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+  IDS_INIT_RESET_AFTER,               ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+  IDS_INIT_POST_MID,                  ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_BEFORE_S3_SAVE,                 ///< 0b override any settings before S3 save.
+  IDS_BEFORE_S3_RESTORE,              ///< 0c  override any settings before S3 restore
+  IDS_AFTER_S3_SAVE,                  ///< 0d Override any settings after S3 save
+  IDS_AFTER_S3_RESTORE,               ///< 0e Override any settings after S3 restore
+  IDS_BEFORE_DQS_TRAINING,            ///< 0f override any settings before DQS training
+  IDS_BEFORE_DRAM_INIT,               ///< 10 override any settings before Dram initialization
+  IDS_BEFORE_MEM_FREQ_CHG,            ///< 11 override settings before MemClk frequency change
+  IDS_BEFORE_WARM_RESET ,             ///< 12 Override PCI or MSR Registers Before Warm Reset
+  IDS_BEFORE_PCI_INIT,                ///< 13 Override PCI or MSR Registers Before PCI Init
+  IDS_BEFORE_AP_EARLY_HALT,           ///< 14 Option Hook Point before AP early halt
+  IDS_BEFORE_S3_RESUME,               ///< 15 Option Hook Point before s3 resume
+  IDS_AFTER_S3_RESUME,                ///< 16 Option Hook Point after s3 resume
+  IDS_BEFORE_PM_INIT,                 ///< 17 Option Hook Point Before Pm Init
+
+  IDS_MT_BASE = 0x20,                 ///< 0x20 ~ 0x38 24 time points reserved for MTTime
+
+  IDS_PLATFORM_RSVD1 = 0x38,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD2 = 0x39,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD3 = 0x3a,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD4 = 0x3b,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD5 = 0x3c,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD6 = 0x3d,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD7 = 0x3e,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD8 = 0x3f,          ///< from 0x38 to 0x3f will reserved for platform used
+
+  IDS_HT_CONTROL,                     ///< 40 Override the setting of HT Link Control
+  IDS_HT_TRISTATE,                    ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
+  IDS_INIT_DRAM_TABLE,                ///< 42 Generate override table for Dram Timing
+                                          ///< Dram Controller, Drive Strength and DQS Timing
+  IDS_GET_DRAM_TABLE,                 ///< 43 Generate override table for Dram Timing
+  IDS_GANGING_MODE,                   ///< 44 override Memory Mode Unganged
+  IDS_POWERDOWN_MODE,                 ///< 45 override Power Down Mode
+  IDS_BURST_LENGTH32,                 ///< 46 override Burst Length32
+  IDS_ALL_MEMORY_CLOCK,               ///< 47 override All Memory Clks Enable
+  IDS_ECC,                            ///< 48 override ECC parameter
+  IDS_ECCSYMBOLSIZE,                  ///< 49 override ECC symbol size
+  IDS_CPU_Early_Override,             ///< 4a override CPU early parameter
+  IDS_CACHE_FLUSH_HLT,                ///< 4b override Cache Flush Hlt
+  IDS_CHANNEL_INTERLEAVE,             ///< 4c override Channel Interleave
+  IDS_MEM_ERROR_RECOVERY,             ///< 4d override memory error recovery
+  IDS_MEM_RETRAIN_TIMES,              ///< 4e override memory retrain times
+  IDS_MEM_SIZE_OVERLAY,               ///< 4f Override the syslimit
+  IDS_HT_ASSIST,                      ///< 50 Override Probe Filter
+  IDS_CHECK_NEGATIVE_WL,              ///< 51 Check for negative write leveling result
+  IDS_DLL_SHUT_DOWN,                  ///< 52 Check for Dll Shut Down
+  IDS_POR_MEM_FREQ,                   ///< 53 Entry to enable/disable MemClk frequency enforcement
+  IDS_PHY_DLL_STANDBY_CTRL,           ///< 54 Enable/Disable Phy DLL standby feature
+  IDS_PLATFORMCFG_OVERRIDE,           ///< 55 Hook for Override PlatformConfig structure
+  IDS_LOADCARD_ERROR_RECOVERY,        ///< 56 Special error handling for load card support
+  IDS_MEM_IGNORE_ERROR,               ///< 57 Ignore error and do not do fatal exit in memory
+  IDS_GNB_SMU_SERVICE_CONFIG,         ///< 58 Config GNB SMU service
+  IDS_GNB_ORBDYNAMIC_WAKE,            ///< 59 config GNB dynamic wake
+  IDS_GNB_PLATFORMCFG_OVERRIDE,       ///< 5a override ids gnb platform config
+  IDS_GNB_LCLK_DPM_EN,                ///< 5b override GNB LCLK DPM configuration
+  IDS_GNB_LCLK_DEEP_SLEEP,            ///< 5c override GNB LCLK DPM deep sleep
+  IDS_GNB_CLOCK_GATING,               ///< 5d Override GNB Clock gating config
+  IDS_NB_PSTATE_DIDVID,               ///< 5e Override NB P-state settings
+  IDS_CPB_CTRL,                       ///< 5f Config the Core peformance boost feature
+  IDS_HTC_CTRL,                       ///< 60 Hook for Hardware Thermal Control
+  IDS_RESERVED_1,                 ///< 61
+  IDS_MEM_MR0,                        ///< 62 Hook for override Memory Mr0 register
+  IDS_TRAP_TABLE,                     ///< 63 Hook for add IDS register table to the loop
+  IDS_NBBUFFERALLOCATIONATEARLY,      ///< 64 Hook for override North bridge bufer allocation
+  IDS_BEFORE_S3_SPECIAL,              ///< 65 Hook to bypass S3 special functions
+  IDS_SET_PCI_REGISTER_ENTRY,         ///< 66 Hook to SetRegisterForPciEntry
+  IDS_RESERVED_2,          ///< 67
+  IDS_BEFORE_MEMCLR,                  ///< 68 Hook before set Memclr bit
+  IDS_OVERRIDE_IO_CSTATE,             ///< 69 Hook for override io C-state setting
+  IDS_NBPSDIS_OVERRIDE,               ///< 6a Hook for override NB pstate disable setting
+  IDS_NBPS_REG_OVERRIDE,              ///< 6b Hook for override Memory NBps reg
+  IDS_LOW_POWER_PSTATE,               ///< 6c Hook for disable Low power_Pstates feature
+  IDS_CST_CREATE,                     ///< 6d Hook for create _CST
+  IDS_CST_SIZE,                       ///< 6e Hook for get _CST size
+  IDS_ENFORCE_VDDIO,                  ///< 6f Hook to override VDDIO
+  IDS_STRETCH_FREQUENCY_LIMIT,        ///< 70 Hook for enforcing memory stretch frequency limit
+  IDS_INIT_MEM_REG_TABLE,             ///< 71 Hook for init memory register table
+  IDS_STUB1,            ///< 72 Hook to skip fused max rate cap
+  IDS_FCH_INIT_AT_RESET,              ///< 73 Hook for FCH reset parameter
+  IDS_FCH_INIT_AT_ENV,                ///< 74 Hook for FCH ENV parameter
+  IDS_ENFORCE_PLAT_TABLES,            ///< 75 Hook to enforce platform specific tables
+  IDS_NBPS_MIN_FREQ,                  ///< 76 Hook for override MIN nb ps freq
+  IDS_GNB_FORCE_CABLESAFE,            ///< 77 Hook for override Force Cable Safe
+  IDS_SKIP_PM_TRANSITION_STEP,        ///< 78 Hook for provide IDS ability to skip this PM step
+  IDS_GNB_PROPERTY,                   ///< 79 Hook for GNB Property
+  IDS_GNB_PCIE_POWER_GATING,          ///< 7A Hook for GNB PCIe Power Gating
+  IDS_MEM_DYN_DRAM_TERM,              ///< 7B Hook for Override Dynamic Dram Term
+  IDS_MEM_DRAM_TERM,                  ///< 7C Hook for Override Dram Term
+  IDS_HT_TRACE_MODE,                     ///< 7D Trace Mode
+  IDS_GNB_ALTVDDNB,                   ///< 7E Hook for Override AltVddNB
+  IDS_UCODE,                          ///< 7F Enable or Disable microcode patching
+  dummy210,
+  IDS_MEMORY_POWER_POLICY,            ///< 81 Memory power policy
+  IDS_GET_STRETCH_FREQUENCY_LIMIT,    ///< 82 Hook for enforcing memory stretch frequency limit
+  IDS_CPU_FEAT,                       ///< 83 Hook for runtime force cpu feature disable
+  IDS_AFTER_DCT_PHY_ACCESS,           ///< 84 Hook for DctAccessDone check
+  IDS_FORCE_PHY_TO_M0,                ///< 85 Hook to bypass M0 enforcement
+  IDS_GNB_PMM_SWTJOFFSET,             ///< 86 Hook to GNBSWTJOFFSET
+  IDS_LOCK_DRAM_CFG,                  ///< 87 Hook to BFLockDramCfg
+  IDS_BEFORE_GEN2_INIT,               ///< 88 Hook to Before Gen2 Init
+  IDS_BEFORE_GPP_TRAINING,            ///< 89 Hook to Before Gpp training
+  IDS_BEFORE_RECONFIGURATION,         ///< 8A Hook to Before Reconfiguration
+  IDS_BEFORE_GEN3_INIT,               ///< 8B Hook to Before Gen3 Init
+  IDS_BEFORE_POWER_GATING,            ///< 8C Hook to Before Power Gating
+  IDS_AFTER_EARLY_INIT_ONCORE,        ///< 8D Hook to after EarlyInit On Core
+  IDS_GNB_PCIE_PORT_REMAP,            ///< 8E Hook to change mapping of PCIe devices
+  IDS_ECC_CONTROL,                    ///< 8F Enable/Disable ECC feature
+  IDS_GNB_PCIE_PHY_ISOLATION,         ///< 90 Enable/Disable PCIE PHY ISOLATION
+  IDS_AFTER_RESTORING_PCI_REG,        ///< 91 Hook after restoring PCI register during S3 resume
+  IDS_MSR_ACCESS_OVERRIDE,            ///< 92 Hook to disable MSR access
+  IDS_REPORT_SMU_FW_VERSION,          ///< 93 Hook to report SMU firmware version
+  IDS_GNB_LOAD_SAMU_PATCH,            ///< 94 Hook to Load SAMU patch
+  IDS_DLLSTAGGERDLY_OVERRIDE,         ///< 95 Hook to skip Dll Stagger Delay
+  IDS_CSAMPLE_TIMER,                  ///< 96 Hook to override CSampleTimer
+  IDS_GNB_PMM_NATIVEGEN1PLL,          ///< 97 Enable/Disable Native Gen1 PLL
+  IDS_BEFORE_PLAT_TABLES,             ///< 98 Hook before processing platform specific tables
+  IDS_GNB_PCIE_MASTERPLL_SELECTION,   ///< 99 Hook to override PCIe Master PLL selection
+  IDS_OPTION_END,                     ///< 100 End of IDS option
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+#include "IdsPerf.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+  #define IDSOPT_IDS_ENABLED        FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_NV_TO_CMOS
+  #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+  #define IDSOPT_TRACING_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+  #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+  #define IDSOPT_HEAP_CHECKING           FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+  #define IDSOPT_ASSERT_ENABLED         FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+  #define IDSOPT_DEBUG_CODE_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_IDT_EXCEPTION_TRAP
+  #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+  #define IDSOPT_C_OPTIMIZATION_DISABLED   FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT
+  #define IDSOPT_TRACING_CONSOLE_HDTOUT   TRUE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT
+  #define IDSOPT_TRACING_CONSOLE_SERIALPORT   FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+  #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO  FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_RAM
+  #define IDSOPT_TRACING_CONSOLE_RAM  FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef  IDSOPT_CONTROL_ENABLED
+  #undef  IDSOPT_TRACING_ENABLED
+  #undef  IDSOPT_PERF_ANALYSIS
+  #undef  IDSOPT_HEAP_CHECKING
+  #undef  IDSOPT_ASSERT_ENABLED
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #undef  IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #undef  IDSOPT_DEBUG_CODE_ENABLED
+  #undef  IDSOPT_TRACE_USER_OPTIONS
+  #undef  IDSOPT_TRACING_CONSOLE_HDTOUT
+  #undef  IDSOPT_TRACING_CONSOLE_SERIALPORT
+  #undef  IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+  #undef  IDSOPT_TRACING_CONSOLE_RAM
+
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+  #define IDSOPT_TRACING_ENABLED    FALSE
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+  #define IDSOPT_HEAP_CHECKING      FALSE
+  #define IDSOPT_ASSERT_ENABLED     FALSE
+  #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+  #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+  #define IDSOPT_TRACE_USER_OPTIONS FALSE
+  #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+  #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+  #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+  #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable when master token Tracing is set to FALSE
+#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE))
+  #undef  IDSOPT_TRACING_CONSOLE_HDTOUT
+  #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+
+  #undef  IDSOPT_TRACING_CONSOLE_SERIALPORT
+  #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+
+  #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+  #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+
+  #undef IDSOPT_TRACING_CONSOLE_RAM
+  #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable Tracing if all support HW layer set to FALSE
+#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE))
+  #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+    #undef  IDSOPT_TRACING_ENABLED
+    #define IDSOPT_TRACING_ENABLED FALSE
+  #endif
+#endif
+/**
+ *  Make a Progress Report to the User.
+ *
+ *  This Macro is always enabled. The default action is to write the TestPoint value
+ *  to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ *  IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ *  in OptionsIds.h in their build tip.
+ *
+ *  @param[in]      TestPoint       The value for display indicating progress
+ *  @param[in,out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
+
+#ifndef IDS_DEBUG_PORT
+  #define IDS_DEBUG_PORT  0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ *  (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ *  Causes the program to halt and display the file number of the source of the
+ *  halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+  #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+  #define STOP_HERE  STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ *  Test an assertion that the given statement is True.
+ *
+ *  The statement is evaluated to a boolean value. If the statement is True,
+ *  then no action is taken (no error). If the statement is False, a error stop
+ *  is generated to halt the program. Used for testing for fatal errors that
+ *  must be resolved before production. This is used to do parameter checks,
+ *  bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in]   conditional    Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+  #if IDSOPT_ASSERT_ENABLED == TRUE
+    #ifdef STOP_CODE
+      #undef STOP_CODE
+    #endif
+    #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+    #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
+  #else
+    #define ASSERT(conditional)
+  #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)  IdsCarCorruptionCheck(StdHeader)
+#else
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+/**
+ * @def DEBUG_CODE
+ * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
+ *
+ */
+#ifndef DEBUG_CODE
+  #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+    #define  DEBUG_CODE(Code) Code
+  #else
+    #define  DEBUG_CODE(Code)
+  #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+  #define IDS_ERROR_TRAP  IdsErrorStop (STOP_CODE)
+#else
+  #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+  #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+  #define IDS_TRACE_DEFAULT (0)
+  #define IDS_INITIAL_F16_KB_PM_STEP
+  #define IDS_F16_KB_PM_CUSTOM_STEP
+  #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+  #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+  #define IDS_EXTENDED_HEAP_SIZE 0
+  #define IDS_EXT_INCLUDE_F15(file)
+  #define IDS_EXT_INCLUDE(file)
+  #define IDS_PAD_4K
+  #define IDS_EXTENDED_CODE(code)
+  #define SMU_FIRMWARE_PADS_1K
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+  #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#define IDS_CMOS_INDEX_PORT 0x70
+#define IDS_CMOS_DATA_PORT 0x71
+#define IDS_CMOS_REGION_START 0x20
+#define IDS_CMOS_REGION_END 0x7F
+#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
+          AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \
+          IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader))
+  #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+    #undef IDS_AP_GET_NV_FROM_CMOS
+    #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x)
+    #ifdef IDS_OPT_CMOS_INDEX_PORT
+      #undef IDS_CMOS_INDEX_PORT
+      #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
+    #endif
+
+    #ifdef IDS_OPT_CMOS_DATA_PORT
+      #undef IDS_CMOS_DATA_PORT
+      #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
+    #endif
+
+    #ifdef IDS_OPT_CMOS_REGION_START
+      #undef IDS_CMOS_REGION_START
+      #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
+    #endif
+
+    #ifdef IDS_OPT_CMOS_REGION_END
+      #undef IDS_CMOS_REGION_END
+      #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
+    #endif
+  #endif
+#else
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) //AGESA_SUCCESS
+#endif
+
+/**
+ *  Macro to add a *skip* hook for IDS options
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, IDS dispatcher function will be called to perform
+ *  the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in]       IdsOption       IDS Option ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
+          if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
+#else
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a heap manager routine
+ *
+ *  when memory is allocated the heap manager actually allocates two extra dwords of data,
+ *  one dword buffer before the actual memory, and one dword afterwards.
+ *  a complete heap walk and check to be performed at any time.
+ *  it would ASSERT if the heap is corrupt
+ *
+ * @param[in]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548ul    // "Head"
+#define SENTINEL_AFTER_VALUE  0x6C696154ul    // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_HEAP_CHECKING == TRUE
+    #define SIZE_OF_SENTINEL  4
+    #define NUM_OF_SENTINEL   2             // Before ("Head") and After ("Tail")
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
+    #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
+    #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
+  #else
+    #define SIZE_OF_SENTINEL  0
+    #define NUM_OF_SENTINEL   0
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+    #define SET_SENTINEL_AFTER(NodePtr)
+    #define Heap_Check(stdheader)
+  #endif
+#else
+  #define SIZE_OF_SENTINEL    0
+  #define NUM_OF_SENTINEL     0
+  #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+  #define SET_SENTINEL_AFTER(NodePtr)
+  #define Heap_Check(stdheader)
+#endif
+
+/**
+ *  Macro to add IDT for debugging exception.
+ *
+ *  A debug feature. Adding a 'jmp $' into every exception handler.
+ *  So debugger could use HDT to skip 'jmp $' and execute the iret,
+ *  then they could find which instruction cause the exception.
+ *
+ * @param[in]       FunctionId      IDS Function ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
+    #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader)
+  #else
+    #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+  #endif
+#else
+  #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+#endif
+
+
+ //Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a)   ((UINT64)1 << a)
+//Memory Masks
+#define MEM_SETREG                                  DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG                                  DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW                                    DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS                                  DEBUG_PRINT_SHIFT (3)
+#define MEM_UNDEF_BF                                DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2                           DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3                           DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4                           DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5                           DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6                           DEBUG_PRINT_SHIFT (9)
+
+//CPU Masks
+#define CPU_TRACE                                   DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1                              DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2                              DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3                              DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4                              DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5                              DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6                              DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7                              DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8                              DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9                              DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE                                   DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC                                   DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE                          DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE                          DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2                              DEBUG_PRINT_SHIFT (24)
+#define NB_MISC                                     DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3                              DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC                                    DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE                             DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1                              DEBUG_PRINT_SHIFT (29)
+
+//HT Masks
+#define HT_TRACE                                    DEBUG_PRINT_SHIFT (30)
+#define HT_TRACE_RSV1                               DEBUG_PRINT_SHIFT (31)
+#define HT_TRACE_RSV2                               DEBUG_PRINT_SHIFT (32)
+#define HT_TRACE_RSV3                               DEBUG_PRINT_SHIFT (33)
+#define HT_TRACE_RSV4                               DEBUG_PRINT_SHIFT (34)
+#define HT_TRACE_RSV5                               DEBUG_PRINT_SHIFT (35)
+#define HT_TRACE_RSV6                               DEBUG_PRINT_SHIFT (36)
+#define HT_TRACE_RSV7                               DEBUG_PRINT_SHIFT (37)
+#define HT_TRACE_RSV8                               DEBUG_PRINT_SHIFT (38)
+#define HT_TRACE_RSV9                               DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE                                    DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1                               DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2                               DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3                               DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4                               DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5                               DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6                               DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7                               DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8                               DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9                               DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW                                    DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG                                    DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE                          DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE                                    DEBUG_PRINT_SHIFT (53)
+#define IDS_TRACE_RSV2                               DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3                               DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE                                     DEBUG_PRINT_SHIFT (57)
+
+//Library function to read/write PCI/MSR registers
+#define LIB_PCI_RD                                   DEBUG_PRINT_SHIFT (58)
+#define LIB_PCI_WR                                   DEBUG_PRINT_SHIFT (59)
+
+//AGESA test points
+#define TEST_POINT                                   DEBUG_PRINT_SHIFT (60)
+
+//Reserved for platform log
+#define PLAT_RSV1                                    DEBUG_PRINT_SHIFT (61)
+#define PLAT_RSV2                                    DEBUG_PRINT_SHIFT (62)
+#define PLAT_RSV3                                    DEBUG_PRINT_SHIFT (63)
+
+#define GNB_TRACE_DEFAULT\
+      (\
+      GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \
+      )
+
+#define GNB_TRACE_REG\
+      (\
+      PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \
+      NB_SMUREG_TRACE | GNB_TRACE_RSV1 \
+      )
+
+#define GNB_TRACE_ALL\
+      (\
+      GNB_TRACE_DEFAULT | GNB_TRACE_REG \
+      )
+
+#define CPU_TRACE_ALL\
+      (\
+      CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \
+      CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \
+      CPU_TRACE_RSV8 | CPU_TRACE_RSV9\
+      )
+
+#define MEMORY_TRACE_ALL\
+      (\
+      MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \
+      MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \
+      MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\
+      )
+
+#define HT_TRACE_ALL\
+      (\
+      HT_TRACE | HT_TRACE_RSV1 | HT_TRACE_RSV2 | HT_TRACE_RSV3 | \
+      HT_TRACE_RSV4 | HT_TRACE_RSV5 | HT_TRACE_RSV6 | HT_TRACE_RSV7 | \
+      HT_TRACE_RSV8 | HT_TRACE_RSV9\
+      )
+
+#define FCH_TRACE_ALL\
+      (\
+      FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \
+      FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \
+      FCH_TRACE_RSV8 | FCH_TRACE_RSV9\
+      )
+
+#define IDS_TRACE_ALL\
+      (\
+      IDS_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\
+      )
+
+#define OTHER_TRACE_ALL\
+      (\
+      MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\
+      )
+
+
+#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull)
+#ifndef IDS_DEBUG_PRINT_MASK
+  #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT  | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | HT_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
+#endif
+
+/// if no specific define INIT & EXIT will be NULL
+#define IDS_HDT_CONSOLE_INIT(x)
+#define IDS_HDT_CONSOLE_EXIT(x)
+
+/// AGESA tracing service
+#if IDSOPT_TRACING_ENABLED == TRUE
+  #ifdef VA_ARGS_SUPPORTED
+    #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
+      #define IDS_HDT_CONSOLE(f, s, ...)        AmdIdsDebugPrint (f, s, __VA_ARGS__)
+    #else
+      #pragma warning(disable: 4127)
+      #define IDS_HDT_CONSOLE(f, s, ...)        if      (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \
+                                                 else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \
+                                                  else if (f == HT_TRACE) AmdIdsDebugPrintHt (s, __VA_ARGS__); \
+                                                  else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \
+                                                 else AmdIdsDebugPrint (f, s, __VA_ARGS__)
+    #endif
+  #else
+    #define IDS_HDT_CONSOLE    AmdIdsDebugPrint
+  #endif
+  #define CONSOLE            AmdIdsDebugPrintAll
+  #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)  Code
+  #define IDS_TIMEOUT_CTL(t)                IdsMemTimeOut (t)
+#else
+  #define IDS_HDT_CONSOLE           1 ? (VOID) 0 : AmdIdsDebugPrint
+  #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+  #define CONSOLE   CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+  #define IDS_TIMEOUT_CTL(t)
+#endif
+
+/// Macros for serial port tracing
+#ifdef IDSOPT_SERIAL_PORT
+  #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT
+#endif
+
+#ifndef IDS_SERIAL_PORT
+  #define IDS_SERIAL_PORT 0x3F8
+#endif
+
+// Macros for redirect IO tracing
+#ifdef IDSOPT_DEBUG_PRINT_IO_PORT
+  #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT
+#endif
+
+#ifndef IDS_DEBUG_PRINT_IO_PORT
+  #define IDS_DEBUG_PRINT_IO_PORT 0x80
+#endif
+
+#define IDS_DPRAM_BASE 0
+#define IDS_DPRAM_SIZE 0
+///Default policy, shift the old data when buffer full
+#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE
+#if IDSOPT_TRACING_CONSOLE_RAM  == TRUE
+  #ifdef IDSOPT_DPRAM_BASE
+    #undef IDS_DPRAM_BASE
+    #define IDS_DPRAM_BASE  IDSOPT_DPRAM_BASE
+  #else
+    #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h"
+  #endif
+
+  #ifdef IDSOPT_DPRAM_SIZE
+    #undef IDS_DPRAM_SIZE
+    #define IDS_DPRAM_SIZE  IDSOPT_DPRAM_SIZE
+  #else
+    #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h"
+  #endif
+
+  #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+    #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+  #endif
+#endif
+/**
+ *  Macros to add HDT OUT
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, the debug information can be displayed in HDT or other
+ *  devices.
+ *
+ **/
+#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
+  #undef IDS_HDT_CONSOLE_INIT
+  #undef IDS_HDT_CONSOLE_EXIT
+  #define IDS_HDT_CONSOLE_INIT(x)           AmdIdsHdtOutInit (x)
+  #define IDS_HDT_CONSOLE_EXIT(x)           AmdIdsHdtOutExit (x)
+  #define IDS_HDT_CONSOLE_S3_EXIT(x)        AmdIdsHdtOutS3Exit (x)
+  #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)     AmdIdsHdtOutS3ApExit (x)
+
+  #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)   AmdIdsHdtOutBufferFlush (x)
+  #define IDS_HDT_CONSOLE_ASSERT(x)   AmdIdsDebugPrintAssert (x)
+  #define IDS_FUNCLIST_ADDR                 ScriptFuncList
+  #define IDS_FUNCLIST_EXTERN()             extern SCRIPT_FUNCTION ScriptFuncList[]
+#else
+  #define IDS_HDT_CONSOLE_S3_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+  #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+  #define IDS_HDT_CONSOLE_ASSERT(x)
+  #define IDS_FUNCLIST_ADDR                 NULL
+  #define IDS_FUNCLIST_EXTERN()
+#endif
+
+#if IDSOPT_TRACING_ENABLED == TRUE
+  #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+    #undef  IDS_HDT_CONSOLE
+    #define IDS_HDT_CONSOLE        IDSOPT_CUSTOMIZE_TRACING_SERVICE
+  #endif
+  #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
+    #undef IDS_HDT_CONSOLE_INIT
+    #define IDS_HDT_CONSOLE_INIT(x)           IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x)
+  #endif
+  #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
+    #undef IDS_HDT_CONSOLE_EXIT
+    #define IDS_HDT_CONSOLE_EXIT(x)           IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x)
+  #endif
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG  IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+  #include "IdsPerf.h"
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+  #define IDS_PERF_TIMESTAMP(ID, StdHeader)  IdsPerfTimestamp (STOP_CODE, ID, (StdHeader))
+  #define IDS_PERF_ANALYSE(StdHeader)   IdsPerfAnalyseTimestamp (StdHeader)
+#else
+  #define IDS_PERF_TIMESTAMP(ID, StdHeader)
+  #define IDS_PERF_ANALYSE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL  0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY    TRUE
+#define IDS_ALL_CORES   FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID     PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT      0x01                             ///< The function data of IDS callout function of initialization.
+
+#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG   0x84        ///< The function data of IDS callout function of GNB integrated table.
+#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG       0x85        ///< The function data of IDS callout function of GNB NB power gate config.
+#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG     0x86        ///< The function data of IDS callout function of GNB PCIE power gateconfig.
+#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG      0x87        ///< The function data of IDS callout function of GNB pcie platform config.
+#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG           0x88        ///< The function data of IDS callout function of GNB pcie PHY config.
+#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE     0x89        ///< The function data of IDS callout function of GNB GMM register override
+#define IDS_CALLOUT_MTC1E_PLATFORM_CONFIG         0x8A        ///< The function data of IDS callout function of Message Triggered C1e platform config.
+#define IDS_CALLOUT_FCH_INIT_RESET                0x8B        ///< The function data of IDS callout function of FchInitReset
+#define IDS_CALLOUT_FCH_INIT_ENV                  0x8C        ///< The function data of IDS callout function of FchInitEnv.
+#define IDS_CALLOUT_GET_PERF_BUFFER               0x8E        ///< The function data of IDS callout function of get platform performance buffer.
+#define IDS_CALLOUT_SMU_PORT80_LOGGING_BUFFER     0x90        ///< The function data of IDS callout function of SMU port80 logging buffer.
+#define IDS_CALLOUT_GNB_BEFORE_EARLY_INIT         0x91        ///< The function data of IDS callout function of GNB before early init.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+  UINT32  FuncAddr;       ///< Function address in ROM
+  CHAR8   FuncName[40];   ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ *  AGESA Test Points
+ *
+ *  These are the values displayed to the user to indicate progress through boot.
+ *  These can be used in a debug environment to stop the debugger at a specific
+ *  test point:
+ *  For SimNow!, this command
+ *      bi 81 w vb 49
+ *  will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+  StartProcessorTestPoints,           ///< 00 Entry used for range testing for @b Processor related TPs
+
+  // Memory test points
+  TpProcMemBeforeMemDataInit,         ///< 01 .. Memory structure initialization (Public interface)
+  TpProcMemBeforeSpdProcessing,       ///< 02 .. SPD Data processing  (Public interface)
+  TpProcMemAmdMemAuto,                ///< 03 .. Memory configuration  (Public interface)
+  TpProcMemDramInit,                  ///< 04 .. DRAM initialization
+  TpProcMemSPDChecking,               ///< 05 ..
+  TpProcMemModeChecking,              ///< 06 ..
+  TpProcMemSpeedTclConfig,            ///< 07 .. Speed and TCL configuration
+  TpProcMemSpdTiming,                 ///< 08 ..
+  TpProcMemDramMapping,               ///< 09 ..
+  TpProcMemPlatformSpecificConfig,    ///< 0A ..
+  TPProcMemPhyCompensation,           ///< 0B ..
+  TpProcMemStartDcts,                 ///< 0C ..
+  TpProcMemBeforeDramInit,            ///< 0D .. (Public interface)
+  TpProcMemPhyFenceTraining,          ///< 0E ..
+  TpProcMemSynchronizeDcts,           ///< 0F ..
+  TpProcMemSystemMemoryMapping,       ///< 10 ..
+  TpProcMemMtrrConfiguration,         ///< 11 ..
+  TpProcMemDramTraining,              ///< 12 ..
+  TpProcMemBeforeAnyTraining,         ///< 13 .. (Public interface)
+  TpProcMemWriteLevelizationTraining, ///< 14 ..
+  TpProcMemWlFirstPass,               ///< 15 .. Below 800Mhz first pass start
+  TpProcMemWlSecondPass,              ///< 16 .. Above 800Mhz second pass start
+  TpProcMemWlTrainTargetDimm,         ///< 17 .. Target DIMM configured
+  TpProcMemWlPrepDimms,               ///< 18 ..  Prepare DIMMS for WL
+  TpProcMemWlConfigDimms,             ///< 19 ..  Configure DIMMS for WL
+  TpProcMemReceiverEnableTraining,    ///< 1A ..
+  TpProcMemRcvrStartSweep,            ///< 1B .. Start sweep loop
+  TpProcMemRcvrSetDelay,              ///< 1C .. Set receiver Delay
+  TpProcMemRcvrWritePattern,          ///< 1D .. Write test pattern
+  TpProcMemRcvrReadPattern,           ///< 1E .. Read test pattern
+  TpProcMemRcvrTestPattern,           ///< 1F .. Compare test pattern
+  TpProcMemRcvrCalcLatency,           ///< 20 .. Calculate MaxRdLatency per channel
+  TpProcMemReceiveDqsTraining,        ///< 21 ..
+  TpProcMemRcvDqsSetDelay,            ///< 22 .. Set Write Data delay
+  TpProcMemRcvDqsWritePattern,        ///< 23 .. Write test pattern
+  TpProcMemRcvDqsStartSweep,          ///< 24 .. Start read sweep
+  TpProcMemRcvDqsSetRcvDelay,         ///< 25 .. Set Receive DQS delay
+  TpProcMemRcvDqsReadPattern,         ///< 26 .. Read Test pattern
+  TpProcMemRcvDqsTstPattern,          ///< 27 .. Compare Test pattern
+  TpProcMemRcvDqsResults,             ///< 28 .. Update results
+  TpProcMemRcvDqsFindWindow,          ///< 29 .. Start Find passing window
+  TpProcMemTransmitDqsTraining,       ///< 2A ..
+  TpProcMemTxDqStartSweep,            ///< 2B .. Start write sweep
+  TpProcMemTxDqSetDelay,              ///< 2C .. Set Transmit DQ delay
+  TpProcMemTxDqWritePattern,          ///< 2D .. Write test pattern
+  TpProcMemTxDqReadPattern,           ///< 2E .. Read Test pattern
+  TpProcMemTxDqTestPattern,           ///< 2F .. Compare Test pattern
+  TpProcMemTxDqResults,               ///< 30 .. Update results
+  TpProcMemTxDqFindWindow,            ///< 31 .. Start Find passing window
+  TpProcMemMaxRdLatencyTraining,      ///< 32 ..
+  TpProcMemMaxRdLatStartSweep,        ///< 33 .. Start sweep
+  TpProcMemMaxRdLatSetDelay,          ///< 34 .. Set delay
+  TpProcMemMaxRdLatWritePattern,      ///< 35 .. Write test pattern
+  TpProcMemMaxRdLatReadPattern,       ///< 36 .. Read Test pattern
+  TpProcMemMaxRdLatTestPattern,       ///< 37 .. Compare Test pattern
+  TpProcMemOnlineSpareInit,           ///< 38 .. Online Spare init
+  TpProcMemBankInterleaveInit,        ///< 39 .. Bank Interleave Init
+  TpProcMemNodeInterleaveInit,        ///< 3A .. Node Interleave Init
+  TpProcMemChannelInterleaveInit,     ///< 3B .. Channel Interleave Init
+  TpProcMemEccInitialization,         ///< 3C .. ECC initialization
+  TpProcMemPlatformSpecificInit,      ///< 3D .. Platform Specific Init
+  TpProcMemBeforeAgesaReadSpd,        ///< 3E .. Before callout for "AgesaReadSpd"
+  TpProcMemAfterAgesaReadSpd,         ///< 3F .. After callout for "AgesaReadSpd"
+  TpProcMemBeforeAgesaHookBeforeDramInit,    ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeDramInit,     ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemAfterAgesaHookBeforeDQSTraining,  ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeExitSelfRef,  ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterMemDataInit,          ///< 46 .. After MemDataInit
+  TpProcMemInitializeMCT,             ///< 47 .. Before InitializeMCT
+  TpProcMemLvDdr3,                    ///< 48 .. Before LV DDR3
+  TpProcMemInitMCT,                   ///< 49 .. Before InitMCT
+  TpProcMemOtherTiming,               ///< 4A.. Before OtherTiming
+  TpProcMemUMAMemTyping,              ///< 4B .. Before UMAMemTyping
+  TpProcMemSetDqsEccTmgs,             ///< 4C .. Before SetDqsEccTmgs
+  TpProcMemMemClr,                    ///< 4D .. Before MemClr
+  TpProcMemOnDimmThermal,             ///< 4E .. Before On DIMM Thermal
+  TpProcMemDmi,                       ///< 4F .. Before DMI
+  TpProcMemEnd,                       ///< 50 .. End of memory code
+
+  // CPU test points
+  TpProcCpuEntryDmi,                  ///< 51 .. Entry point CreateDmiRecords
+  TpProcCpuEntryPstate,               ///< 52 .. Entry point GenerateSsdt
+  TpProcCpuEntryPstateLeveling,       ///< 53 .. Entry point PStateLeveling
+  TpProcCpuEntryPstateGather,         ///< 54 .. Entry point PStateGatherData
+  TpProcCpuEntryWhea,                 ///< 55 .. Entry point CreateAcpiWhea
+  TpProcCpuEntrySrat,                 ///< 56 .. Entry point CreateAcpiSrat
+  TpProcCpuEntrySlit,                 ///< 57 .. Entry point CreateAcpiSlit
+  TpProcCpuProcessRegisterTables,     ///< 58 .. Register table processing
+  TpProcCpuSetBrandID,                ///< 59 .. Set brand ID
+  TpProcCpuLocalApicInit,             ///< 5A .. Initialize local APIC
+  TpProcCpuLoadUcode,                 ///< 5B .. Load microcode patch
+  TpProcCpuBeforePMFeatureInit,       ///< 5C .. BeforePM feature dispatch point
+  TpProcCpuPowerMgmtInit,             ///< 5D .. Power Management table processing
+  TpProcCpuEarlyFeatureInit,          ///< 5E .. Early feature dispatch point
+  TpProcCpuCoreLeveling,              ///< 5F .. Core Leveling
+  TpProcCpuApMtrrSync,                ///< 60 .. AP MTRR sync up
+  TpProcCpuPostFeatureInit,           ///< 61 .. POST feature dispatch point
+  TpProcCpuFeatureLeveling,           ///< 62 .. CPU Feature Leveling
+  TpProcCpuBeforeRelinquishAPsFeatureInit,   ///< 63 .. Before Relinquishing control of APs feature dispatch point
+  TpProcCpuBeforeAllocateWheaBuffer,  ///< 64 .. Before the WHEA init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateWheaBuffer,   ///< 65 .. After the WHEA init code calls out to allocate a buffer
+  TpProcCpuBeforeAllocateSratBuffer,  ///< 66 .. Before the SRAT init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSratBuffer,   ///< 67 .. After the SRAT init code calls out to allocate a buffer
+  TpProcCpuBeforeLocateSsdtBuffer,    ///< 68 .. Before the P-state init code calls out to locate a buffer
+  TpProcCpuAfterLocateSsdtBuffer,     ///< 69 .. After the P-state init code calls out to locate a buffer
+  TpProcCpuBeforeAllocateSsdtBuffer,  ///< 6A .. Before the P-state init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSsdtBuffer,   ///< 6B .. After the P-state init code calls out to allocate a buffer
+  TpProcCpuEntryCrat,                 ///< 6C .. Entry point CreateAcpiCrat
+  TpProcCpuEntryCdit,                 ///< 6D .. Entry point CreateAcpiCdit
+  TpProcCpuEntryScs,                  ///< 6E .. Entry point InitializeScsFeature
+
+  // HT test points
+  TpProcHtEntry = 0x71,               ///< 71 .. Coherent Discovery begin (Public interface)
+  TpProcHtTopology,                   ///< 72 .. Topology match, routing, begin
+  TpProcHtManualNc,                   ///< 73 .. Manual Non-coherent Init begin
+  TpProcHtAutoNc,                     ///< 74 .. Automatic Non-coherent init begin
+  TpProcHtOptGather,                  ///< 75 .. Optimization: Gather begin
+  TpProcHtOptRegang,                  ///< 76 .. Optimization: Regang begin
+  TpProcHtOptLinks,                   ///< 77 .. Optimization: Link Begin
+  TpProcHtOptSubLinks,                ///< 78 .. Optimization: Sublinks begin
+  TpProcHtOptFinish,                  ///< 79 .. Optimization: Set begin
+  TpProcHtTrafficDist,                ///< 7A .. Traffic Distribution begin
+  TpProcHtTuning,                     ///< 7B .. Misc Tuning Begin
+  TpProcHtDone,                       ///< 7C .. HT Init complete
+  TpProcHtApMapEntry,                 ///< 7D .. AP HT: Init Maps begin
+  TpProcHtApMapDone,                  ///< 7E .. AP HT: Complete
+
+  // Extended memory test point
+  TpProcMemSendMRS2 = 0x80,           ///< 80 .. Sending MRS2
+  TpProcMemSendMRS3,                  ///< 81 .. Sedding MRS3
+  TpProcMemSendMRS1,                  ///< 82 .. Sending MRS1
+  TpProcMemSendMRS0,                  ///< 83 .. Sending MRS0
+  TpProcMemContinPatternGenRead,      ///< 84 .. Continuous Pattern Read
+  TpProcMemContinPatternGenWrite,     ///< 85 .. Continuous Pattern Write
+  TpProcMem2dRdDqsTraining,           ///< 86 .. Mem: 2d RdDqs Training begin
+  TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
+  TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training
+  TpProcMemConfigureDCTForGeneral,    ///< 89 .. Configure DCT For General use begin
+  TpProcMemProcConfigureDCTForTraining,    ///< 8A .. Configure DCT For training begin
+  TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit
+  TpProcMemSynchronizeChannels,       ///< 8C .. Configure to Sync channels
+  TpProcMemC6StorageAllocation,       ///< 8D .. Allocate C6 Storage
+
+  // Gnb Earlier init
+  TpGnbEarlierPcieConfigurationInit = 0x90,           ///< 90 .. GNB earlier PCIE configuration init
+  TpGnbEarlierInterface = 0x91,                       ///< 91 .. GNB earlier interface
+  // Gnb Early init
+  TpGnbEarlyInterface = 0x92,                         ///< 92 .. GNB early interface
+  TpNbSmuInitFeatureAtEarly,                          ///< 93 .. GNB early SMU service init
+  TpGnbPcieConfigurationMap,                          ///< 94 .. GNB early PCIE configuration map
+  TpGnbPcieEarlyInterface,                            ///< 95 .. GNB early PCIE interface
+  //Gnb post init
+  TpGnbPciePostEarlyInterface = 0x96,                 ///< 96 .. GNB post early interface
+  TpGnbGfxConfigPostInterface,                        ///< 97 .. GNB post GFX config interface
+  TpGnbGfxPostInterface,                              ///< 98 .. GNB post GFX interface
+  // Gnb post after DRAM init
+  TpGnbPostInterface = 0x99,                          ///< 99 .. GNB post after DRAM interface
+  TpGnbPciePostInterface,                             ///< 9A .. GNB post after DRAM PCIE interface
+  // Gnb Env init
+  TpNbF1Feature = 0x9B,                        ///< 9B
+  TpGnbEnvInterface,                                  ///< 9C .. GNB Env Nb interface
+  TpGnbPcieEnvInterface,                              ///< 9D .. GNB Env PCIE interface
+  TpGnbGfxConfigEnvInterface,                         ///< 9E .. GNB Env GFX Config interface
+  TpGnbGfxEnvInterface,                               ///< 9F .. GNB Env GFX interface
+  TpNbPowerGateFeature,                               ///< A0 .. GNB Env NB power gating feature
+  // Gnb Mid init
+  TpGnbGfxConfigMidInterface = 0xA1,                  ///< A1 .. GNB Mid GFX config interface
+  TpGnbGfxMidInterface,                               ///< A2 .. GNB Mid GFX interface
+  TpGnbCableSafeEntry,                                ///< A3 .. GNB Mid cable safe
+  TpPcieMidInterface,                                 ///< A4 .. GNB Mid PCIE interface
+  TpGnbMidInterface,                                  ///< A5 .. GNB Mid interface
+  TpNbLclkFeature,                                    ///< A6 .. GNB Mid Nclk feature
+  TpPciePowerGateFeature,                             ///< A7 .. GNB Mid pcie power gate feature
+  TpGnbPcieMaxPayloadInterface,                       ///< A8 .. GNB Mid pcie max payload interface
+  TpGnbPcieClkPmInterface,                            ///< A8 .. GNB Mid pcie clk pm port interface
+  TpGnbPcieAspmInterface,                             ///< A9 .. GNB Mid pcie ASPM interface
+  TpGnbNbIoapicInterface,                             ///< AA .. GNB Mid IOAPIC interface
+  // Gnb Late init
+  TpGnbPcieAlibFeature = 0xAB,                        ///< AB .. GNB Late pcie ALIB feature
+  TpGnbIommuIvrsTable,                                ///< AC .. GNB Late pcie IOMMU
+  // Gnb S3 Save
+  TpGnbGfxInitSview = 0xAD,                           ///< AD .. GNB S3SAVE GFX sview init
+
+  EndGnbTestPoints = 0xAF,                            ///< AF End of TP range for GNB
+
+  StartFchTestPoints = 0xB0,          ///< B0 Entry used for range testing for @b FCH related TPs
+  TpFchInitResetDispatching,          ///< B1 .. FCH InitReset dispatch point
+  TpFchGppBeforePortTraining,         ///< B2 .. Before FCH GPP port training
+  TpFchGppGen1PortPolling,            ///< B3 .. FCH GPP port polling with GEN1 speed
+  TpFchGppGen2PortPolling,            ///< B4 .. FCH GPP port polling with GEN2 speed
+  TpFchGppAfterPortTraining,          ///< B5 .. After FCH GPP port training
+  TpFchInitEnvDispatching,            ///< B6 .. FCH InitEnv dispatch point
+  TpFchInitMidDispatching,            ///< B7 .. FCH InitMid dispatch point
+  TpFchInitLateDispatching,           ///< B8 .. FCH InitLate dispatch point
+  TpFchGppHotPlugging,                ///< B9 .. FCH GPP hot plug event
+  TpFchGppHotUnplugging,              ///< BA .. AFCH GPP hot unplug event
+  TpFchInitS3EarlyDispatching,        ///< BB .. FCH InitS3Early dispatch point
+  TpFchInitS3LateDispatching,         ///< BC .. FCH InitS3Late dispatch point
+  EndFchTestPoints,                   ///< BF End of TP range for FCH
+
+  // Interface test points
+  TpIfAmdInitResetEntry = 0xC0,       ///< C0 .. Entry to AmdInitReset
+  TpIfAmdInitResetExit,               ///< C1 .. Exiting from AmdInitReset
+  TpIfAmdInitRecoveryEntry,           ///< C2 .. Entry to AmdInitRecovery
+  TpIfAmdInitRecoveryExit,            ///< C3 .. Exiting from AmdInitRecovery
+  TpIfAmdInitEarlyEntry,              ///< C4 .. Entry to AmdInitEarly
+  TpIfAmdInitEarlyExit,               ///< C5 .. Exiting from AmdInitEarly
+  TpIfAmdInitPostEntry,               ///< C6 .. Entry to AmdInitPost
+  TpIfAmdInitPostExit,                ///< C7 .. Exiting from AmdInitPost
+  TpIfAmdInitEnvEntry,                ///< C8 .. Entry to AmdInitEnv
+  TpIfAmdInitEnvExit,                 ///< C9 .. Exiting from AmdInitEnv
+  TpIfAmdInitMidEntry,                ///< CA .. Entry to AmdInitMid
+  TpIfAmdInitMidExit,                 ///< CB .. Exiting from AmdInitMid
+  TpIfAmdInitLateEntry,               ///< CC .. Entry to AmdInitLate
+  TpIfAmdInitLateExit,                ///< CD .. Exiting from AmdInitLate
+  TpIfAmdS3SaveEntry,                 ///< CE .. Entry to AmdS3Save
+  TpIfAmdS3SaveExit,                  ///< CF .. Exiting from AmdS3Save
+  TpIfAmdInitResumeEntry,             ///< D0 .. Entry to AmdInitResume
+  TpIfAmdInitResumeExit,              ///< D1 .. Exiting from AmdInitResume
+  TpIfAmdS3LateRestoreEntry,          ///< D2 .. Entry to AmdS3LateRestore
+  TpIfAmdS3LateRestoreExit,           ///< D3 .. Exiting from AmdS3LateRestore
+  TpIfAmdLateRunApTaskEntry,          ///< D4 .. Entry to AmdS3LateRestore
+  TpIfAmdLateRunApTaskExit,           ///< D5 .. Exiting from AmdS3LateRestore
+  TpIfAmdReadEventLogEntry,           ///< D6 .. Entry to AmdReadEventLog
+  TpIfAmdReadEventLogExit,            ///< D7 .. Exiting from AmdReadEventLog
+  TpIfAmdGetApicIdEntry,              ///< D8 .. Entry to AmdGetApicId
+  TpIfAmdGetApicIdExit,               ///< D9 .. Exiting from AmdGetApicId
+  TpIfAmdGetPciAddressEntry,          ///< DA .. Entry to AmdGetPciAddress
+  TpIfAmdGetPciAddressExit,           ///< DB .. Exiting from AmdGetPciAddress
+  TpIfAmdIdentifyCoreEntry,           ///< DC .. Entry to AmdIdentifyCore
+  TpIfAmdIdentifyCoreExit,            ///< DD .. Exiting from AmdIdentifyCore
+  TpIfBeforeRunApFromIds,             ///< DE .. After IDS calls out to run code on an AP
+  TpIfAfterRunApFromIds,              ///< DF .. After IDS calls out to run code on an AP
+  TpIfBeforeGetIdsData,               ///< E0 .. Before IDS calls out to get IDS data
+  TpIfAfterGetIdsData,                ///< E1 .. After IDS calls out to get IDS data
+  TpIfBeforeAllocateHeapBuffer,       ///< E2 .. Before the heap manager calls out to allocate a buffer
+  TpIfAfterAllocateHeapBuffer,        ///< E3 .. After the heap manager calls out to allocate a buffer
+  TpIfBeforeDeallocateHeapBuffer,     ///< E4 .. Before the heap manager calls out to deallocate a buffer
+  TpIfAfterDeallocateHeapBuffer,      ///< E5 .. After the heap manager calls out to deallocate a buffer
+  TpIfBeforeLocateHeapBuffer,         ///< E6 .. Before the heap manager calls out to locate a buffer
+  TpIfAfterLocateHeapBuffer,          ///< E7 .. After the heap manager calls out to locate a buffer
+  TpIfBeforeRunApFromAllAps,          ///< E8 .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllAps,           ///< E9 .. After the BSP calls out to run code on an AP
+  TpIfBeforeRunApFromAllCore0s,       ///< EA .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllCore0s,        ///< EB .. After the BSP calls out to run code on an AP
+  TpIfBeforeAllocateS3SaveBuffer,     ///< EC .. Before the S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateS3SaveBuffer,      ///< ED .. After the S3 save code calls out to allocate a buffer
+  TpIfBeforeAllocateMemoryS3SaveBuffer,  ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateMemoryS3SaveBuffer,   ///< EF .. After the memory S3 save code calls out to allocate a buffer
+  TpIfBeforeLocateS3PciBuffer,        ///< F0 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3PciBuffer,         ///< F1 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CPciBuffer,       ///< F2 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CPciBuffer,        ///< F3 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3MsrBuffer,        ///< F4 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3MsrBuffer,         ///< F5 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CMsrBuffer,       ///< F6 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CMsrBuffer,        ///< F7 .. After the memory code calls out to locate a buffer
+  TpReadyToBoot,                      ///< F8 .. Ready to boot event
+  EndAgesaTps = 0xFF,                 ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+  IDS_FEAT_UCODE_UPDATE = 0x0000,   ///< Feat for Ucode Update
+  IDS_FEAT_TARGET_PSTATE,           ///< Feat for Target Pstate
+  IDS_FEAT_POSTPSTATE,              ///< Feat for Post Pstate
+  IDS_FEAT_ECC_CTRL,                ///< Feat for Ecc Control
+  IDS_FEAT_ECC_SYMBOL_SIZE,         ///< Feat for Ecc symbol size
+  IDS_FEAT_DCT_ALLMEMCLK,           ///< Feat for all memory clock
+  IDS_FEAT_DCT_GANGMODE,            ///< Feat for Dct gang mode
+  IDS_FEAT_DCT_BURSTLENGTH,         ///< Feat for dct burst length
+  IDS_FEAT_DCT_POWERDOWN,           ///< Feat for dct power down
+  IDS_FEAT_DCT_DLLSHUTDOWN,         ///< Feat for dct dll shut down
+  IDS_FEAT_PROBE_FILTER,            ///< Feat for probe filter
+  IDS_FEAT_HDTOUT,                  ///< Feat for hdt out
+  IDS_FEAT_HT_SETTING,              ///< Feat for Ht setting
+  IDS_FEAT_GNB_PLATFORMCFG,         ///< Feat for override GNB platform config
+  IDS_FEAT_CPB_CTRL,                ///< Feat for Config the Core peformance boost feature
+  IDS_FEAT_HTC_CTRL,                ///< Feat for Hardware Thermal Control
+  IDS_FEAT_MEMORY_MAPPING,          ///< Feat for Memory Mapping
+  IDS_FEAT_POWER_POLICY,            ///< Feat for Power Policy
+  IDS_FEAT_NV_TO_CMOS,              ///< Feat for Save BSP Nv to CMOS
+  IDS_FEAT_COMMON,                  ///< Common Feat
+  IDS_FEAT_END = 0xFF               ///< End of Common feat
+} IDS_FEAT;
+
+///Ids IDT table function ID
+typedef enum {
+  IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000,   ///< Function ID for saving IDTR for BSC
+  IDS_IDT_RESTORE_IDTR_FOR_BSC,            ///< Function ID for restoring IDTR for BSC
+  IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP,  ///< Function ID for updating exception vector
+} IDS_IDT_FUNC_ID;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef  struct _IDS_FAMILY_FEAT_STRUCT {
+  IDS_FEAT  IdsFeat;      ///< Ids Feat ID
+  BOOLEAN IsBsp;          ///< swith for Bsp check
+  AGESA_IDS_OPTION IdsOption;   ///< IDS option
+  UINT64 CpuFamily;       ///<
+  PIDS_COMMON_FUNC  pf_idsoption;   ///<pointer to function
+} IDS_FAMILY_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef  struct _IDS_OPTION_STRUCT {
+  AGESA_IDS_OPTION idsoption;       ///< IDS option
+  PIDS_COMMON_FUNC  pf_idsoption;   ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+  UINT8 version;      ///<Version of IDS option table
+  UINT16 size;        ///<Size of IDS option table
+  CONST IDS_OPTION_STRUCT  *pIdsOptionStruct; ///<pointer to array of  structure
+} IDS_OPTION_STRUCT_TBL;
+
+#define IDS_NV_TO_CMOS_LEN_BYTE   1
+#define IDS_NV_TO_CMOS_LEN_WORD   2
+#define IDS_NV_TO_CMOS_LEN_END   0xFF
+#define IDS_NV_TO_CMOS_ID_END   0xFFFF
+
+/// Data struct of set/get NV to/from CMOS
+typedef struct _IDS_NV_TO_CMOS {
+  UINT8 Length;       ///< Length of NV
+  UINT16 IDS_NV_ID; ///< IDS id
+} IDS_NV_TO_CMOS;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsOptionCallout (
+  IN       UINTN                CallOutId,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsHdtOutInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsHdtOutExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsHdtOutS3Exit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsHdtOutS3ApExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrint (
+  IN       UINT64 Flag,
+  IN       CONST CHAR8 *Format,
+  IN       ...
+  );
+
+VOID
+AmdIdsDebugPrintHt (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintCpu (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintMem (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintGnb (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintAll (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsHdtOutBufferFlush (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsMemTimeOut (
+  IN OUT   VOID *DataPtr
+  );
+
+VOID
+IdsAgesaTestPoint (
+  IN      AGESA_TP TestPoint,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval         TRUE     No error
+**/
+BOOLEAN
+IdsAssert (
+  IN      UINT32 FileCode
+  );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+  IN      UINT32 FileCode
+  );
+
+VOID
+IdsDelay (
+VOID);
+
+BOOLEAN
+AmdHeapIntactCheck (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsCarCorruptionCheck (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsExceptionTrap (
+  IN       IDS_IDT_FUNC_ID IdsIdtFuncId,
+  IN       VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsPerfTimestamp (
+  IN       UINT32 LineInFile,
+  IN       UINT32 Description,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef IEM_SKIP_CODE
+  #undef IEM_INSERT_CODE
+#endif
+#ifndef IEM_SKIP_CODE
+  #define IEM_SKIP_CODE(L)
+#endif
+#ifndef IEM_INSERT_CODE
+  #define IEM_INSERT_CODE(L, Fn, Parm)
+#endif
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h b/src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h
new file mode 100644
index 0000000..1d597c6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h
@@ -0,0 +1,123 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Definitions
+ *
+ * Contains AMD AGESA Integrated Debug HT related items.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_HT_H_
+#define _IDS_HT_H_
+
+// Frequency equates for call backs which take an actual frequency setting
+#define HT_FREQUENCY_200M            0
+#define HT_FREQUENCY_400M            2
+#define HT_FREQUENCY_600M            4
+#define HT_FREQUENCY_800M            5
+#define HT_FREQUENCY_1000M           6
+#define HT_FREQUENCY_1200M           7
+#define HT_FREQUENCY_1400M           8
+#define HT_FREQUENCY_1600M           9
+#define HT_FREQUENCY_1800M           10
+#define HT_FREQUENCY_2000M           11
+#define HT_FREQUENCY_2200M           12
+#define HT_FREQUENCY_2400M           13
+#define HT_FREQUENCY_2600M           14
+#define HT_FREQUENCY_2800M           17
+#define HT_FREQUENCY_3000M           18
+#define HT_FREQUENCY_3200M           19
+#define HT_FREQUENCY_3600M           20
+
+/**
+ * HT IDS: HT Link Port Override params.
+ *
+ * Provide an absolute override of HT Link Port settings.  No checking is done that
+ * the settings obey limits or capabilities, this responsibility rests with the user.
+ *
+ * Rules for values of structure items:
+ * - Socket
+ *   - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
+ *   - HT_LIST_MATCH_ANY == Match Any Socket
+ *   - 0 .. 7 == The matching socket
+ * - Link
+ *   - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
+ *   - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
+ *   - 0 .. 7 == The matching package link.  0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
+ * - Frequency
+ *   - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
+ *   - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
+ * - Widthin
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ * - Widthout
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ */
+typedef struct {
+  // Match Fields
+  UINT8       Socket;      ///< The Socket which this port is on.
+  UINT8       Link;        ///< The port for this package link on that socket.
+  // Override fields
+  UINT8       Frequency;   ///< Absolutely override the port's frequency.
+  UINT8       WidthIn;     ///< Absolutely override the port's width.
+  UINT8       WidthOut;    ///< Absolutely override the port's width.
+} HTIDS_PORT_OVERRIDE;
+
+/**
+ * A list of port overrides to search.
+ */
+typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+
+typedef
+VOID
+F_HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
+#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/IdsPerf.h b/src/vendorcode/amd/agesa/f16kb/Include/IdsPerf.h
new file mode 100644
index 0000000..1282085
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/IdsPerf.h
@@ -0,0 +1,139 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Routines for performance analysis
+ *
+ * Contains AMD AGESA debug macros and functions for performance analysis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+#ifndef _IDS_PERFORMANCE_DATA_POINT
+
+  #define _IDS_PERFORMANCE_DATA_POINT
+  #define IDS_PERF_VERSION 0x00010000ul  //version number 0.1.0.0
+/// Time points performance function used
+  typedef enum {
+    TP_BEGINPROCAMDINITEARLY             = 0x100,  ///< BeginProcAmdInitEarly
+    TP_ENDPROCAMDINITEARLY               = 0x101,  ///< EndProcAmdInitEarly
+    TP_BEGINAMDHTINITIALIZE              = 0x102,  ///< BeginAmdHtInitialize
+    TP_ENDAMDHTINITIALIZE                = 0x103,  ///< EndAmdHtInitialize
+    TP_BEGINGNBINITATEARLIER             = 0x104,  ///< BeginGnbInitAtEarlier
+    TP_ENDGNBINITATEARLIER               = 0x105,  ///< EndGnbInitAtEarlier
+    TP_BEGINAMDCPUEARLY                  = 0x106,  ///< BeginAmdCpuEarly
+    TP_ENDAMDCPUEARLY                    = 0x107,  ///< EndAmdCpuEarly
+    TP_BEGINGNBINITATEARLY               = 0x108,  ///< BeginGnbInitAtEarly
+    TP_ENDGNBINITATEARLY                 = 0x109,  ///< EndGnbInitAtEarly
+    TP_BEGINPROCAMDINITENV               = 0x10A,  ///< BeginProcAmdInitEnv
+    TP_ENDPROCAMDINITENV                 = 0x10B,  ///< EndProcAmdInitEnv
+    TP_BEGININITENV                      = 0x10C,  ///< BeginInitEnv
+    TP_ENDINITENV                        = 0x10D,  ///< EndInitEnv
+    TP_BEGINGNBINITATENV                 = 0x10E,  ///< BeginGnbInitAtEnv
+    TP_ENDGNBINITATENV                   = 0x10F,  ///< EndGnbInitAtEnv
+    TP_BEGINPROCAMDINITLATE              = 0x110,  ///< BeginProcAmdInitLate
+    TP_ENDPROCAMDINITLATE                = 0x111,  ///< EndProcAmdInitLate
+    TP_BEGINCREATSYSTEMTABLE             = 0x112,  ///< BeginCreatSystemTable
+    TP_ENDCREATSYSTEMTABLE               = 0x113,  ///< EndCreatSystemTable
+    TP_BEGINDISPATCHCPUFEATURESLATE      = 0x114,  ///< BeginDispatchCpuFeaturesLate
+    TP_ENDDISPATCHCPUFEATURESLATE        = 0x115,  ///< EndDispatchCpuFeaturesLate
+    TP_BEGINAMDCPULATE                   = 0x116,  ///< BeginAmdCpuLate
+    TP_ENDAMDCPULATE                     = 0x117,  ///< EndAmdCpuLate
+    TP_BEGINGNBINITATLATE                = 0x118,  ///< BeginGnbInitAtLate
+    TP_ENDGNBINITATLATE                  = 0x119,  ///< EndGnbInitAtLate
+    TP_BEGINPROCAMDINITMID               = 0x11A,  ///< BeginProcAmdInitMid
+    TP_ENDPROCAMDINITMID                 = 0x11B,  ///< EndProcAmdInitMid
+    TP_BEGINDISPATCHCPUFEATURESMID       = 0x11C,  ///< BeginDispatchCpuFeaturesMid
+    TP_ENDDISPATCHCPUFEATURESMID         = 0x11D,  ///< EndDispatchCpuFeaturesMid
+    TP_BEGININITMID                      = 0x11E,  ///< BeginInitMid
+    TP_ENDINITMID                        = 0x11F,  ///< EndInitMid
+    TP_BEGINGNBINITATMID                 = 0x120,  ///< BeginGnbInitAtMid
+    TP_ENDGNBINITATMID                   = 0x121,  ///< EndGnbInitAtMid
+    TP_BEGINPROCAMDINITPOST              = 0x122,  ///< BeginProcAmdInitPost
+    TP_ENDPROCAMDINITPOST                = 0x123,  ///< EndProcAmdInitPost
+    TP_BEGINGNBINITATPOST                = 0x124,  ///< BeginGnbInitAtPost
+    TP_ENDGNBINITATPOST                  = 0x125,  ///< EndGnbInitAtPost
+    TP_BEGINAMDMEMAUTO                   = 0x126,  ///< BeginAmdMemAuto
+    TP_ENDAMDMEMAUTO                     = 0x127,  ///< EndAmdMemAuto
+    TP_BEGINAMDCPUPOST                   = 0x128,  ///< BeginAmdCpuPost
+    TP_ENDAMDCPUPOST                     = 0x129,  ///< EndAmdCpuPost
+    TP_BEGINGNBINITATPOSTAFTERDRAM       = 0x12A,  ///< BeginGnbInitAtPostAfterDram
+    TP_ENDGNBINITATPOSTAFTERDRAM         = 0x12B,  ///< EndGnbInitAtPostAfterDram
+    TP_BEGINPROCAMDINITRESET             = 0x12C,  ///< BeginProcAmdInitReset
+    TP_ENDPROCAMDINITRESET               = 0x12D,  ///< EndProcAmdInitReset
+    TP_BEGININITRESET                    = 0x12E,  ///< BeginInitReset
+    TP_ENDINITRESET                      = 0x12F,  ///< EndInitReset
+    TP_BEGINHTINITRESET                  = 0x130,  ///< BeginHtInitReset
+    TP_ENDHTINITRESET                    = 0x131,  ///< EndHtInitReset
+    TP_BEGINPROCAMDINITRESUME            = 0x132,  ///< BeginProcAmdInitResume
+    TP_ENDPROCAMDINITRESUME              = 0x133,  ///< EndProcAmdInitResume
+    TP_BEGINAMDMEMS3RESUME               = 0x134,  ///< BeginAmdMemS3Resume
+    TP_ENDAMDMEMS3RESUME                 = 0x135,  ///< EndAmdMemS3Resume
+    TP_BEGINDISPATCHCPUFEATURESS3RESUME  = 0x136,  ///< BeginDispatchCpuFeaturesS3Resume
+    TP_ENDDISPATCHCPUFEATURESS3RESUME    = 0x137,  ///< EndDispatchCpuFeaturesS3Resume
+    TP_BEGINSETCORESTSCFREQSEL           = 0x138,  ///< BeginSetCoresTscFreqSel
+    TP_ENDSETCORESTSCFREQSEL             = 0x139,  ///< EndSetCoresTscFreqSel
+    TP_BEGINMEMFMCTMEMCLR_INIT           = 0x13A,  ///< BeginMemFMctMemClr_Init
+    TP_ENDNMEMFMCTMEMCLR_INIT            = 0x13B,  ///< EndnMemFMctMemClr_Init
+    TP_BEGINMEMBEFOREMEMDATAINIT         = 0x13C,  ///< BeginMemBeforeMemDataInit
+    TP_ENDMEMBEFOREMEMDATAINIT           = 0x13D,  ///< EndMemBeforeMemDataInit
+    TP_BEGINPROCAMDMEMAUTO               = 0x13E,  ///< BeginProcAmdMemAuto
+    TP_ENDPROCAMDMEMAUTO                 = 0x13F,  ///< EndProcAmdMemAuto
+    TP_BEGINMEMMFLOWC32                  = 0x140,  ///< BeginMemMFlowC32
+    TP_ENDMEMMFLOWC32                    = 0x141,  ///< EndMemMFlowC32
+    TP_BEGINMEMINITIALIZEMCT             = 0x142,  ///< BeginMemInitializeMCT
+    TP_ENDMEMINITIALIZEMCT               = 0x143,  ///< EndMemInitializeMCT
+    TP_BEGINMEMSYSTEMMEMORYMAPPING       = 0x144,  ///< BeginMemSystemMemoryMapping
+    TP_ENDMEMSYSTEMMEMORYMAPPING         = 0x145,  ///< EndMemSystemMemoryMapping
+    TP_BEGINMEMDRAMTRAINING              = 0x146,  ///< BeginMemDramTraining
+    TP_ENDMEMDRAMTRAINING                = 0x147,  ///< EndMemDramTraining
+    TP_BEGINMEMOTHERTIMING               = 0x148,  ///< BeginMemOtherTiming
+    TP_ENDMEMOTHERTIMING                 = 0x149,  ///< EndMemOtherTiming
+    TP_BEGINMEMUMAMEMTYPING              = 0x14A,  ///< BeginMemUMAMemTyping
+    TP_ENDMEMUMAMEMTYPING                = 0x14B,  ///< EndMemUMAMemTyping
+    TP_BEGINMEMMEMCLR                    = 0x14C,  ///< BeginMemMemClr
+    TP_ENDMEMMEMCLR                      = 0x14D,  ///< EndMemMemClr
+    TP_BEGINMEMMFLOWTN                   = 0x14E,  ///< BeginMemMFlowTN
+    TP_ENDMEMMFLOWTN                     = 0x14F,  ///< EndMemMFlowTN
+    TP_BEGINAGESAHOOKBEFOREDRAMINIT      = 0x150,  ///< BeginAgesaHookBeforeDramInit
+    TP_ENDAGESAHOOKBEFOREDRAMINIT        = 0x151,  ///< EndAgesaHookBeforeDramInit
+    TP_BEGINPROCMEMDRAMTRAINING          = 0x152,  ///< BeginProcMemDramTraining
+    TP_ENDPROCMEMDRAMTRAINING            = 0x153,  ///< EndProcMemDramTraining
+    TP_BEGINGNBINITATS3SAVE              = 0x154,  ///< BeginGnbInitAtS3Save
+    TP_ENDGNBINITATS3SAVE                = 0x155,  ///< EndGnbInitAtS3Save
+    TP_BEGINGNBLOADSCSDATA               = 0x156,  ///< BeginGnbLoadScsData
+    TP_ENDGNBLOADSCSDATA                 = 0x157,  ///< EndGnbLoadScsData
+    TP_BEGINGNBPCIETRAINING              = 0x158,  ///< BeginGnbPcieTraining
+    TP_ENDGNBPCIETRAINING                = 0x159,  ///< EndGnbPcieTraining
+    IDS_TP_END                                     ///< End of IDS TP list
+  } IDS_PERF_DATA;
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h
new file mode 100644
index 0000000..6b16a6c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h
@@ -0,0 +1,143 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Kerala platform solution
+ *
+ * This file generates the defaults tables for the "Kerala" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 69377 $   @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "KabiniPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '1', '.', '0', ' ', ' ', ' ', ' '}
+
+
+// The Kerala solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets.
+#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
+
+#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
+  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
+    #undef INSTALL_FT3_SOCKET_SUPPORT
+    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+
+#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
+#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x420
+#define DFLT_SPI_BASE_ADDRESS               0xFEC10000ul
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0ul
+#define DFLT_HPET_BASE_ADDRESS              0xFED00000ul
+#define DFLT_SMI_CMD_PORT                   0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
+#define DFLT_GEC_BASE_ADDRESS               0xFED61000ul
+#define DFLT_AZALIA_SSID                    0x780D1022ul
+#define DFLT_SMBUS_SSID                     0x780B1022ul
+#define DFLT_IDE_SSID                       0x780C1022ul
+#define DFLT_SATA_AHCI_SSID                 0x78011022ul
+#define DFLT_SATA_IDE_SSID                  0x78001022ul
+#define DFLT_SATA_RAID5_SSID                0x78031022ul
+#define DFLT_SATA_RAID_SSID                 0x78021022ul
+#define DFLT_EHCI_SSID                      0x78081022ul
+#define DFLT_OHCI_SSID                      0x78071022ul
+#define DFLT_LPC_SSID                       0x780E1022ul
+#define DFLT_SD_SSID                        0x78061022ul
+#define DFLT_XHCI_SSID                      0x78121022ul
+#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionApmInstall.h
new file mode 100644
index 0000000..1624859
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionApmInstall.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Application Power Management (APM).
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_APM_INSTALL_H_
+#define _OPTION_APM_INSTALL_H_
+
+#include "cpuApm.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_APM_FEAT
+#define F16_APM_SUPPORT
+
+#if OPTION_CPU_APM == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 16H
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
+        #undef OPTION_CPU_APM_FEAT
+        #define OPTION_CPU_APM_FEAT &CpuFeatureApm,
+        extern CONST APM_FAMILY_SERVICES ROMDATA F16ApmSupport;
+        #undef F16_APM_SUPPORT
+        #define F16_APM_SUPPORT {AMD_FAMILY_16, &F16ApmSupport},
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
+{
+  F16_APM_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
+{
+  (sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &ApmFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_APM_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionC6Install.h
new file mode 100644
index 0000000..53256ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionC6Install.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: C6 C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_C6_STATE_INSTALL_H_
+#define _OPTION_C6_STATE_INSTALL_H_
+
+#include "cpuC6State.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_C6_STATE_FEAT
+#define F15_TN_C6_STATE_SUPPORT
+#define F16_KB_C6_STATE_SUPPORT
+
+#if OPTION_C6_STATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_TN == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support;
+          #undef F15_TN_C6_STATE_SUPPORT
+          #define F15_TN_C6_STATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnC6Support},
+        #endif
+
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F16KbC6Support;
+          #undef F16_KB_C6_STATE_SUPPORT
+          #define F16_KB_C6_STATE_SUPPORT {AMD_FAMILY_16_KB, &F16KbC6Support},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
+{
+  F15_TN_C6_STATE_SUPPORT
+  F16_KB_C6_STATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
+{
+  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &C6FamilyServiceArray[0]
+};
+
+#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCdit.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCdit.h
new file mode 100644
index 0000000..19afc75
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCdit.h
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CDIT option API.
+ *
+ * Contains structures and values used to control the CDIT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_CDIT_H_
+#define _OPTION_CDIT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Create the ACPI Component Locality Distance Information Table.
+ *
+ */
+typedef AGESA_STATUS OPTION_CDIT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   VOID                   **CditPtr
+  );
+
+#define CDIT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of CDIT
+typedef struct  {
+  UINT16              OptCditVersion;       ///< The version number of CDIT
+  OPTION_CDIT_FEATURE  *CditFeature;        ///< The Option Feature of CDIT
+  UINT8               OemIdString[6];       ///< Configurable OEM Id
+  UINT8               OemTableIdString[8];  ///< Configurable OEM Table Id
+} OPTION_CDIT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_CDIT_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCditInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCditInstall.h
new file mode 100644
index 0000000..96ee782
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCditInstall.h
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CDIT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CDIT_INSTALL_H_
+#define _OPTION_CDIT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+OPTION_CDIT_FEATURE          GetAcpiCditStub;
+#define USER_CDIT_OPTION     &GetAcpiCditStub
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_CDIT
+    #error  BLDOPT: Option not defined: "OPTION_CDIT"
+  #endif
+  #if OPTION_CDIT == TRUE
+    OPTION_CDIT_FEATURE        GetAcpiCditMain;
+    #undef USER_CDIT_OPTION
+    #define USER_CDIT_OPTION   &GetAcpiCditMain
+  #endif
+#endif
+
+/*  Declare the instance of the CDIT option configuration structure  */
+CONST OPTION_CDIT_CONFIGURATION ROMDATA OptionCditConfiguration = {
+  CDIT_STRUCT_VERSION,
+  USER_CDIT_OPTION,
+  {CFG_ACPI_SET_OEM_ID},
+  {CFG_ACPI_SET_OEM_TABLE_ID}
+};
+
+#endif  // _OPTION_CDIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpbInstall.h
new file mode 100644
index 0000000..42a9ff5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpbInstall.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Core Performance Boost
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPB_INSTALL_H_
+#define _OPTION_CPB_INSTALL_H_
+
+#include "cpuCpb.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPB_FEAT
+#define F15_TN_CPB_SUPPORT
+#define F16_KB_CPB_SUPPORT
+
+#if OPTION_CPB == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_TN == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport;
+          #undef F15_TN_CPB_SUPPORT
+          #define F15_TN_CPB_SUPPORT {AMD_FAMILY_15_TN, &F15TnCpbSupport},
+        #endif
+
+      #endif
+    #endif
+
+
+    // Family 16h
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F16KbCpbSupport;
+          #undef F16_KB_CPB_SUPPORT
+          #define F16_KB_CPB_SUPPORT {AMD_FAMILY_16_KB, &F16KbCpbSupport},
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
+{
+  F15_TN_CPB_SUPPORT
+  F16_KB_CPB_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
+{
+  (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpbFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCacheFlushOnHaltInstall.h
new file mode 100644
index 0000000..9e094ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Cache Flush On Halt
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+
+#include "cpuPostInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+#define F15_TN_CPU_CFOH_SUPPORT
+#define F16_KB_CPU_CFOH_SUPPORT
+
+#if OPTION_CPU_CFOH == TRUE
+  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
+          #undef F15_TN_CPU_CFOH_SUPPORT
+          #define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
+        #endif
+
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F16KbCacheFlushOnHalt;
+          #undef F16_KB_CPU_CFOH_SUPPORT
+          #define F16_KB_CPU_CFOH_SUPPORT {AMD_FAMILY_16_KB, &F16KbCacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
+{
+  F16_KB_CPU_CFOH_SUPPORT
+  F15_TN_CPU_CFOH_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
+{
+  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CacheFlushOnHaltFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCoreLevelingInstall.h
new file mode 100644
index 0000000..4b29b73
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCoreLevelingInstall.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Core Leveling
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
+#define _OPTION_CPU_CORELEVELING_INSTALL_H_
+
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CORE_LEVELING_FEAT
+#define F15_TN_CPU_CORELEVELING_SUPPORT
+#define F16_KB_CPU_CORELEVELING_SUPPORT
+
+#if OPTION_CPU_CORELEVELING == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+    // Family 15h
+    #if OPTION_FAMILY15H == TRUE
+      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+      #undef OPTION_CPU_CORE_LEVELING_FEAT
+      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+
+      #if (OPTION_FAMILY15H_TN == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
+        #undef F15_TN_CPU_CORELEVELING_SUPPORT
+        #define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
+      #endif
+
+    #endif
+
+    // Family 16h
+    #if OPTION_FAMILY16H == TRUE
+      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+      #undef OPTION_CPU_CORE_LEVELING_FEAT
+      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+
+      #if (OPTION_FAMILY16H_KB == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F16KbCoreLeveling;
+        #undef F16_KB_CPU_CORELEVELING_SUPPORT
+        #define F16_KB_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_16_KB, &F16KbCoreLeveling},
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
+{
+  F16_KB_CPU_CORELEVELING_SUPPORT
+  F15_TN_CPU_CORELEVELING_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
+{
+  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CoreLevelingFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFamiliesInstall.h
new file mode 100644
index 0000000..8e61eff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFamiliesInstall.h
@@ -0,0 +1,228 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of all appropriate CPU family specific support.
+ *
+ * This file generates the defaults tables for all family specific
+ * combinations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+/*  Default all CPU Specific Service members to off.  They
+    will be enabled as needed by cross referencing families
+    with entry points in the family / model install files.  */
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define BASE_FAMILY_WORKAROUNDS     FALSE
+
+/*
+ * Pull in family specific services based on entry point
+ */
+#if AGESA_ENTRY_INIT_RESET == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef BASE_FAMILY_WORKAROUNDS
+  #define BASE_FAMILY_WORKAROUNDS     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RESUME == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+#endif
+
+/*
+ * Initialize PCI MMIO mask to 0
+ */
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+
+/*
+ * Initialize all families to disabled
+ */
+#define OPT_F15_TABLE
+#define OPT_F16_TABLE
+
+#define OPT_F15_ID_TABLE
+#define OPT_F16_ID_TABLE
+
+
+/*
+ * Install family specific support
+ */
+#if (OPTION_FAMILY15H_TN == TRUE)
+  #include  "OptionFamily15hInstall.h"
+#endif
+
+#if (OPTION_FAMILY16H_KB == TRUE)
+  #include  "OptionFamily16hInstall.h"
+#endif
+/*
+ * Process PCI MMIO mask
+ */
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000ul * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+/*
+ * Process sockets / modules
+ */
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+/*
+ * Instantiate global data needed for processor identification
+ */
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
+{
+  OPT_F15_TABLE
+  OPT_F16_TABLE
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
+{
+  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpuSupportedFamiliesArray[0]
+};
+
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F15_ID_TABLE
+  OPT_F16_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFeaturesInstall.h
new file mode 100644
index 0000000..61c750a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFeaturesInstall.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of multiple CPU features.
+ *
+ * Aggregates enabled CPU features into a list for the dispatcher to process.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
+#define _OPTION_CPU_FEATURES_INSTALL_H_
+
+#include "OptionMsgBasedC1eInstall.h"
+#include "OptionL3FeaturesInstall.h"
+#include "OptionCpuCoreLevelingInstall.h"
+#include "OptionIoCstateInstall.h"
+#include "OptionC6Install.h"
+#include "OptionCpbInstall.h"
+#include "OptionApmInstall.h"
+#include "OptionCpuCacheFlushOnHaltInstall.h"
+#include "OptionPstateHpcModeInstall.h"
+#include "OptionLowPwrPstateInstall.h"
+#include "OptionTdpLimitingInstall.h"
+#include "OptionPsiInstall.h"
+#include "OptionHtcInstall.h"
+#include "OptionPrefetchModeInstall.h"
+#include "OptionPreserveMailboxInstall.h"
+
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+{
+  OPTION_MSG_BASED_C1E_FEAT
+  OPTION_L3_FEAT
+  OPTION_CPU_CORE_LEVELING_FEAT
+  OPTION_IO_CSTATE_FEAT
+  OPTION_C6_STATE_FEAT
+  OPTION_CPU_APM_FEAT
+  OPTION_CPB_FEAT
+  OPTION_TDP_LIMIT_FEAT
+  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+  OPTION_CPU_PSTATE_HPC_MODE_FEAT             // this function should be run before low power pstate for prochot
+  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT  // this function should be run before creating ACPI objects and after Pstate initialization
+  OPTION_CPU_PSI_FEAT
+  OPTION_CPU_HTC_FEAT
+  OPTION_PREFETCH_MODE_FEAT
+  OPTION_PRESERVE_MAILBOX_FEAT
+  NULL
+};
+
+
+#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
new file mode 100644
index 0000000..987677e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
@@ -0,0 +1,1297 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of CPU specific services support
+ *
+ * This file generates the CPU specific services tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 85962 $   @e \$Date: 2013-01-14 20:12:29 -0600 (Mon, 14 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+/*
+
+NOTE:
+
+1. This file is designed to be included multiple times in one file. So there's no includsion guard like below.
+
+#ifndef _OPTION_CPU_FAMILY_SERVICE_INSTALL_DEFAULT_H_
+#define _OPTION_CPU_FAMILY_SERVICE_INSTALL_DEFAULT_H_
+#endif // _OPTION_CPU_FAMILY_SERVICE_INSTALL_DEFAULT_H_
+
+
+2. This file is designed to be included in below form.
+
+//
+// 1st family model specific definitions
+//
+#include "OptionCpuSpecificServicesInstallReset.h"
+#define CpuSrvcTableName                                        cpuFamilyModelServices
+// Put your service definitions "CpuSrvc<ServiceName>" here.
+#define CpuSrvcDisablePstate                                    cpuF1stM1stDisablePstate
+#include "OptionCpuSpecificServicesInstall.h"
+INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
+
+//
+// 2nd family model specific definitions
+//
+#include "OptionCpuSpecificServicesInstallReset.h"
+#define CpuSrvcTableName                                        cpuFamilyModelServices
+// Put your service definitions "CpuSrvc<ServiceName>" here.
+#define CpuSrvcDisablePstate                                    cpuF2ndM2ndDisablePstate
+#include "OptionCpuSpecificServicesInstall.h"
+INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
+
+
+Example of CPU specific services definitions:
+
+NOTE: Members with type casting should use OvrdDfltCpuSrvc<ServiceName> instead due to automatical "extern" limitation.
+
+#define CpuSrvcRevision                                        (UINT16)                                           Revision
+#define CpuSrvcDisablePstate                                   (PF_CPU_DISABLE_PSTATE)                            DisablePstate
+#define CpuSrvcTransitionPstate                                (PF_CPU_TRANSITION_PSTATE)                         TransitionPstate
+#define CpuSrvcGetProcIddMax                                   (PF_CPU_GET_IDD_MAX)                               GetProcIddMax
+#define CpuSrvcGetTscRate                                      (PF_CPU_GET_TSC_RATE)                              GetTscRate
+#define CpuSrvcGetCurrentNbFrequency                           (PF_CPU_GET_NB_FREQ)                               GetCurrentNbFrequency
+#define CpuSrvcGetMinMaxNbFrequency                            (PF_CPU_GET_MIN_MAX_NB_FREQ)                       GetMinMaxNbFrequency
+#define CpuSrvcGetNbPstateInfo                                 (PF_CPU_GET_NB_PSTATE_INFO)                        GetNbPstateInfo
+#define CpuSrvcIsNbCofInitNeeded                               (PF_CPU_IS_NBCOF_INIT_NEEDED)                      IsNbCofInitNeeded
+#define CpuSrvcGetNbIddMax                                     (PF_CPU_GET_NB_IDD_MAX)                            GetNbIddMax
+#define CpuSrvcLaunchApCore                                    (PF_CPU_AP_INITIAL_LAUNCH)                         LaunchApCore
+#define CpuSrvcGetNumberOfPhysicalCores                        (PF_CPU_NUMBER_OF_PHYSICAL_CORES)                  GetNumberOfPhysicalCores
+#define CpuSrvcGetApMailboxFromHardware                        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE)          GetApMailboxFromHardware
+#define CpuSrvcSetApCoreNumber                                 (PF_CPU_SET_AP_CORE_NUMBER)                        SetApCoreNumber
+#define CpuSrvcGetApCoreNumber                                 (PF_CPU_GET_AP_CORE_NUMBER)                        GetApCoreNumber
+#define CpuSrvcTransferApCoreNumber                            (PF_CPU_TRANSFER_AP_CORE_NUMBER)                   TransferApCoreNumber
+#define CpuSrvcGetStoredNodeNumber                             (PF_CPU_GET_STORED_NODE_NUMBER)                    GetStoredNodeNumber
+#define CpuSrvcCoreIdPositionInInitialApicId                   (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID)           CoreIdPositionInInitialApicId
+#define CpuSrvcSaveFeatures                                    (PF_CPU_SAVE_FEATURES)                             SaveFeatures
+#define CpuSrvcWriteFeatures                                   (PF_CPU_WRITE_FEATURES)                            WriteFeatures
+#define CpuSrvcSetWarmResetFlag                                (PF_CPU_SET_WARM_RESET_FLAG)                       SetWarmResetFlag
+#define CpuSrvcGetWarmResetFlag                                (PF_CPU_GET_WARM_RESET_FLAG)                       GetWarmResetFlag
+#define CpuSrvcGetBrandString1                                 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetBrandString1
+#define CpuSrvcGetBrandString2                                 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetBrandString2
+#define CpuSrvcGetMicroCodePatchesStruct                       (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetMicroCodePatchesStruct
+#define CpuSrvcGetMicrocodeEquivalenceTable                    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetMicrocodeEquivalenceTable
+#define CpuSrvcGetCacheInfo                                    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetCacheInfo
+#define CpuSrvcGetSysPmTableStruct                             (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetSysPmTableStruct
+#define CpuSrvcGetWheaInitData                                 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetWheaInitData
+#define CpuSrvcGetPlatformTypeSpecificInfo                     (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO)           GetPlatformTypeSpecificInfo
+#define CpuSrvcIsNbPstateEnabled                               (PF_IS_NB_PSTATE_ENABLED)                          IsNbPstateEnabled
+#define CpuSrvcNextLinkHasHtPhyFeats                           (PF_NEXT_LINK_HAS_HTFPY_FEATS)                     NextLinkHasHtPhyFeats
+#define CpuSrvcSetHtPhyRegister                                (PF_SET_HT_PHY_REGISTER)                           SetHtPhyRegister
+#define CpuSrvcGetNextHtLinkFeatures                           (PF_GET_NEXT_HT_LINK_FEATURES)                     GetNextHtLinkFeatures
+#define CpuSrvcRegisterTableList                               (REGISTER_TABLE **)                                RegisterTableList
+#define CpuSrvcTableEntryTypeDescriptors                       (TABLE_ENTRY_TYPE_DESCRIPTOR *)                    TableEntryTypeDescriptors
+#define CpuSrvcPackageLinkMap                                  (PACKAGE_HTLINK_MAP)                               PackageLinkMap
+#define CpuSrvcComputeUnitMap                                  (COMPUTE_UNIT_MAP *)                               ComputeUnitMap
+#define CpuSrvcInitCacheDisabled                               (FAMILY_CACHE_INIT_POLICY)                         InitCacheDisabled
+#define CpuSrvcGetEarlyBeforeApLaunchInitOnCoreTable           (PF_GET_EARLY_INIT_TABLE)                          GetEarlyInitBeforeApLaunchOnCoreTable
+#define CpuSrvcGetEarlyAfterApLaunchInitOnCoreTable            (PF_GET_EARLY_INIT_TABLE)                          GetEarlyInitAfterApLaunchOnCoreTable
+#define CpuSrvcPatchLoaderIsSharedByCU                         (BOOLEAN)                                          TRUE
+
+  USAGE MODEL:
+
+  //
+  // If BUILD_CONFIG_SWITCH = TRUE
+  //   If override service is defined, use it as the final service definition.
+  //   If override service is not define, use default service (DlftCpuSrvc) as the final service definition.
+  //
+  // If BUILD_CONFIG_SWITCH = FALSE
+  //   Use default assert service (AssertCpuSrvc) as the final service definition for making a assertion when unsupported service is called.
+  //
+  // "extern" will be used for function pointer (exclude data) type serive members automatically when CpuSrvc<ServiceName> is defined.
+  //
+
+// Member: (MEMBER_TYPE) ServiceName
+#if BUILD_CONFIG_SWITCH == TRUE
+  #ifdef CpuSrvcServiceName
+    #define FinalCpuSrvcServiceName           CpuSrvcServiceName
+    extern  MEMBER_TYPE                       FinalCpuSrvcServiceName;
+  #else
+    #define FinalCpuSrvcServiceName           DfltCpuSrvcServiceName
+    #pragma message( STRING_MACRO_DEFAULT_USED(CpuSrvcServiceName) )
+  #endif
+#else
+  #define FinalCpuSrvcServiceName           DfltAssertCpuSrvcServiceName
+  #pragma message( STRING_MACRO_DEFAULT_ASSERT_USED(CpuSrvcServiceName) )
+#endif
+
+*/
+
+
+#define STRING2(x)                                #x
+#define STRING(x)                                 STRING2(x)
+#define CAT_STRING(a, b)                          a##b
+#define STRING_ARROW                              " --> "
+
+//
+// Verbose control for messaging CPU services at build time
+//
+#ifndef VERBOSE_CPU_SERVICES
+  #define VERBOSE_CPU_SERVICES                    1 // 0 - disable messaging, 1 - enable debugging.
+#endif
+
+#if VERBOSE_CPU_SERVICES
+  #define STRING_MACRO_VALUE(Name)                " " #Name " = " STRING(Name)
+  #define STRING_OVERRIDE_MACRO_VALUE(Name)       "  OVERRIDE: " #Name " : " STRING(Name) STRING_ARROW STRING(Ovrd##Name)
+  #define STRING_MACRO_DEFAULT_USED(Name)         "  NOT DEFINED: "  #Name STRING_ARROW " DEFAULT: " STRING(FinalDflt##Name)
+  #define STRING_MACRO_DEFAULT_ASSERT_USED(Name)  "  DISABLED: " #Name ", assertion is used."
+
+  #define STRING_SEPARATOR1                       "-----------------------------------------------------------------------------------------------"
+  #define STRING_SEPARATOR2                       "==============================================================================================="
+  #define STRING_SEPARATOR_POUND                  "###############################################################################################"
+#else // VERBOSE_CPU_SERVICES
+  #define STRING_MACRO_VALUE(Name)                NULL_STRING
+  #define STRING_OVERRIDE_MACRO_VALUE(Name)       NULL_STRING
+  #define STRING_MACRO_DEFAULT_USED(Name)         NULL_STRING
+  #define STRING_MACRO_DEFAULT_ASSERT_USED(Name)  NULL_STRING
+
+
+  #define NULL_STRING                             ""
+  #define STRING_SEPARATOR1                       NULL_STRING
+  #define STRING_SEPARATOR2                       NULL_STRING
+  #define STRING_SEPARATOR_POUND                  NULL_STRING
+#endif // VERBOSE_CPU_SERVICES
+
+//
+// Handle override definitions on DfltAssertCpuSrvc<ServiceName>
+//
+
+#ifdef OvrdDfltAssertCpuSrvcRevision
+  #define FinalDfltAssertCpuSrvcRevision                              OvrdDfltAssertCpuSrvcRevision
+#else
+  #define FinalDfltAssertCpuSrvcRevision                              DfltAssertCpuSrvcRevision
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcDisablePstate
+  #define FinalDfltAssertCpuSrvcDisablePstate                         OvrdDfltAssertCpuSrvcDisablePstate
+#else
+  #define FinalDfltAssertCpuSrvcDisablePstate                         DfltAssertCpuSrvcDisablePstate
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcTransitionPstate
+  #define FinalDfltAssertCpuSrvcTransitionPstate                      OvrdDfltAssertCpuSrvcTransitionPstate
+#else
+  #define FinalDfltAssertCpuSrvcTransitionPstate                      DfltAssertCpuSrvcTransitionPstate
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetProcIddMax
+  #define FinalDfltAssertCpuSrvcGetProcIddMax                         OvrdDfltAssertCpuSrvcGetProcIddMax
+#else
+  #define FinalDfltAssertCpuSrvcGetProcIddMax                         DfltAssertCpuSrvcGetProcIddMax
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetTscRate
+  #define FinalDfltAssertCpuSrvcGetTscRate                            OvrdDfltAssertCpuSrvcGetTscRate
+#else
+  #define FinalDfltAssertCpuSrvcGetTscRate                            DfltAssertCpuSrvcGetTscRate
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetCurrentNbFrequency
+  #define FinalDfltAssertCpuSrvcGetCurrentNbFrequency                 OvrdDfltAssertCpuSrvcGetCurrentNbFrequency
+#else
+  #define FinalDfltAssertCpuSrvcGetCurrentNbFrequency                 DfltAssertCpuSrvcGetCurrentNbFrequency
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetMinMaxNbFrequency
+  #define FinalDfltAssertCpuSrvcGetMinMaxNbFrequency                  OvrdDfltAssertCpuSrvcGetMinMaxNbFrequency
+#else
+  #define FinalDfltAssertCpuSrvcGetMinMaxNbFrequency                  DfltAssertCpuSrvcGetMinMaxNbFrequency
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetNbPstateInfo
+  #define FinalDfltAssertCpuSrvcGetNbPstateInfo                       OvrdDfltAssertCpuSrvcGetNbPstateInfo
+#else
+  #define FinalDfltAssertCpuSrvcGetNbPstateInfo                       DfltAssertCpuSrvcGetNbPstateInfo
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcIsNbCofInitNeeded
+  #define FinalDfltAssertCpuSrvcIsNbCofInitNeeded                     OvrdDfltAssertCpuSrvcIsNbCofInitNeeded
+#else
+  #define FinalDfltAssertCpuSrvcIsNbCofInitNeeded                     DfltAssertCpuSrvcIsNbCofInitNeeded
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetNbIddMax
+  #define FinalDfltAssertCpuSrvcGetNbIddMax                           OvrdDfltAssertCpuSrvcGetNbIddMax
+#else
+  #define FinalDfltAssertCpuSrvcGetNbIddMax                           DfltAssertCpuSrvcGetNbIddMax
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcLaunchApCore
+  #define FinalDfltAssertCpuSrvcLaunchApCore                          OvrdDfltAssertCpuSrvcLaunchApCore
+#else
+  #define FinalDfltAssertCpuSrvcLaunchApCore                          DfltAssertCpuSrvcLaunchApCore
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetNumberOfPhysicalCores
+  #define FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores              OvrdDfltAssertCpuSrvcGetNumberOfPhysicalCores
+#else
+  #define FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores              DfltAssertCpuSrvcGetNumberOfPhysicalCores
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetApMailboxFromHardware
+  #define FinalDfltAssertCpuSrvcGetApMailboxFromHardware              OvrdDfltAssertCpuSrvcGetApMailboxFromHardware
+#else
+  #define FinalDfltAssertCpuSrvcGetApMailboxFromHardware              DfltAssertCpuSrvcGetApMailboxFromHardware
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcSetApCoreNumber
+  #define FinalDfltAssertCpuSrvcSetApCoreNumber                       OvrdDfltAssertCpuSrvcSetApCoreNumber
+#else
+  #define FinalDfltAssertCpuSrvcSetApCoreNumber                       DfltAssertCpuSrvcSetApCoreNumber
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetApCoreNumber
+  #define FinalDfltAssertCpuSrvcGetApCoreNumber                       OvrdDfltAssertCpuSrvcGetApCoreNumber
+#else
+  #define FinalDfltAssertCpuSrvcGetApCoreNumber                       DfltAssertCpuSrvcGetApCoreNumber
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcTransferApCoreNumber
+  #define FinalDfltAssertCpuSrvcTransferApCoreNumber                  OvrdDfltAssertCpuSrvcTransferApCoreNumber
+#else
+  #define FinalDfltAssertCpuSrvcTransferApCoreNumber                  DfltAssertCpuSrvcTransferApCoreNumber
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetStoredNodeNumber
+  #define FinalDfltAssertCpuSrvcGetStoredNodeNumber                   OvrdDfltAssertCpuSrvcGetStoredNodeNumber
+#else
+  #define FinalDfltAssertCpuSrvcGetStoredNodeNumber                   DfltAssertCpuSrvcGetStoredNodeNumber
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcCoreIdPositionInInitialApicId
+  #define FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId         OvrdDfltAssertCpuSrvcCoreIdPositionInInitialApicId
+#else
+  #define FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId         DfltAssertCpuSrvcCoreIdPositionInInitialApicId
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcSaveFeatures
+  #define FinalDfltAssertCpuSrvcSaveFeatures                          OvrdDfltAssertCpuSrvcSaveFeatures
+#else
+  #define FinalDfltAssertCpuSrvcSaveFeatures                          DfltAssertCpuSrvcSaveFeatures
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcWriteFeatures
+  #define FinalDfltAssertCpuSrvcWriteFeatures                         OvrdDfltAssertCpuSrvcWriteFeatures
+#else
+  #define FinalDfltAssertCpuSrvcWriteFeatures                         DfltAssertCpuSrvcWriteFeatures
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcSetWarmResetFlag
+  #define FinalDfltAssertCpuSrvcSetWarmResetFlag                      OvrdDfltAssertCpuSrvcSetWarmResetFlag
+#else
+  #define FinalDfltAssertCpuSrvcSetWarmResetFlag                      DfltAssertCpuSrvcSetWarmResetFlag
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetWarmResetFlag
+  #define FinalDfltAssertCpuSrvcGetWarmResetFlag                      OvrdDfltAssertCpuSrvcGetWarmResetFlag
+#else
+  #define FinalDfltAssertCpuSrvcGetWarmResetFlag                      DfltAssertCpuSrvcGetWarmResetFlag
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetBrandString1
+  #define FinalDfltAssertCpuSrvcGetBrandString1                       OvrdDfltAssertCpuSrvcGetBrandString1
+#else
+  #define FinalDfltAssertCpuSrvcGetBrandString1                       DfltAssertCpuSrvcGetBrandString1
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetBrandString2
+  #define FinalDfltAssertCpuSrvcGetBrandString2                       OvrdDfltAssertCpuSrvcGetBrandString2
+#else
+  #define FinalDfltAssertCpuSrvcGetBrandString2                       DfltAssertCpuSrvcGetBrandString2
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetMicroCodePatchesStruct
+  #define FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct             OvrdDfltAssertCpuSrvcGetMicroCodePatchesStruct
+#else
+  #define FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct             DfltAssertCpuSrvcGetMicroCodePatchesStruct
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+  #define FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable          OvrdDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+#else
+  #define FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable          DfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetCacheInfo
+  #define FinalDfltAssertCpuSrvcGetCacheInfo                          OvrdDfltAssertCpuSrvcGetCacheInfo
+#else
+  #define FinalDfltAssertCpuSrvcGetCacheInfo                          DfltAssertCpuSrvcGetCacheInfo
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetSysPmTableStruct
+  #define FinalDfltAssertCpuSrvcGetSysPmTableStruct                   OvrdDfltAssertCpuSrvcGetSysPmTableStruct
+#else
+  #define FinalDfltAssertCpuSrvcGetSysPmTableStruct                   DfltAssertCpuSrvcGetSysPmTableStruct
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetWheaInitData
+  #define FinalDfltAssertCpuSrvcGetWheaInitData                       OvrdDfltAssertCpuSrvcGetWheaInitData
+#else
+  #define FinalDfltAssertCpuSrvcGetWheaInitData                       DfltAssertCpuSrvcGetWheaInitData
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+  #define FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo           OvrdDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+#else
+  #define FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo           DfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcIsNbPstateEnabled
+  #define FinalDfltAssertCpuSrvcIsNbPstateEnabled                     OvrdDfltAssertCpuSrvcIsNbPstateEnabled
+#else
+  #define FinalDfltAssertCpuSrvcIsNbPstateEnabled                     DfltAssertCpuSrvcIsNbPstateEnabled
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcNextLinkHasHtPhyFeats
+  #define FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats                 OvrdDfltAssertCpuSrvcNextLinkHasHtPhyFeats
+#else
+  #define FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats                 DfltAssertCpuSrvcNextLinkHasHtPhyFeats
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcSetHtPhyRegister
+  #define FinalDfltAssertCpuSrvcSetHtPhyRegister                      OvrdDfltAssertCpuSrvcSetHtPhyRegister
+#else
+  #define FinalDfltAssertCpuSrvcSetHtPhyRegister                      DfltAssertCpuSrvcSetHtPhyRegister
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetNextHtLinkFeatures
+  #define FinalDfltAssertCpuSrvcGetNextHtLinkFeatures                 OvrdDfltAssertCpuSrvcGetNextHtLinkFeatures
+#else
+  #define FinalDfltAssertCpuSrvcGetNextHtLinkFeatures                 DfltAssertCpuSrvcGetNextHtLinkFeatures
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcRegisterTableList
+  #define FinalDfltAssertCpuSrvcRegisterTableList                     OvrdDfltAssertCpuSrvcRegisterTableList
+#else
+  #define FinalDfltAssertCpuSrvcRegisterTableList                     DfltAssertCpuSrvcRegisterTableList
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcTableEntryTypeDescriptors
+  #define FinalDfltAssertCpuSrvcTableEntryTypeDescriptors             OvrdDfltAssertCpuSrvcTableEntryTypeDescriptors
+#else
+  #define FinalDfltAssertCpuSrvcTableEntryTypeDescriptors             DfltAssertCpuSrvcTableEntryTypeDescriptors
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcPackageLinkMap
+  #define FinalDfltAssertCpuSrvcPackageLinkMap                        OvrdDfltAssertCpuSrvcPackageLinkMap
+#else
+  #define FinalDfltAssertCpuSrvcPackageLinkMap                        DfltAssertCpuSrvcPackageLinkMap
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcComputeUnitMap
+  #define FinalDfltAssertCpuSrvcComputeUnitMap                        OvrdDfltAssertCpuSrvcComputeUnitMap
+#else
+  #define FinalDfltAssertCpuSrvcComputeUnitMap                        DfltAssertCpuSrvcComputeUnitMap
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcInitCacheDisabled
+  #define FinalDfltAssertCpuSrvcInitCacheDisabled                     OvrdDfltAssertCpuSrvcInitCacheDisabled
+#else
+  #define FinalDfltAssertCpuSrvcInitCacheDisabled                     DfltAssertCpuSrvcInitCacheDisabled
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+  #define FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable OvrdDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#else
+  #define FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable DfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+  #define FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable  OvrdDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#else
+  #define FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable  DfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#endif
+
+#ifdef OvrdDfltAssertCpuSrvcPatchLoaderIsSharedByCU
+  #define FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU               OvrdDfltAssertCpuSrvcPatchLoaderIsSharedByCU
+#else
+  #define FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU               DfltAssertCpuSrvcPatchLoaderIsSharedByCU
+#endif
+
+//
+// Handle override definitions on DfltCpuSrvc<ServiceName>
+//
+
+#ifdef OvrdDfltCpuSrvcRevision
+  #define FinalDfltCpuSrvcRevision                                    OvrdDfltCpuSrvcRevision
+#else
+  #define FinalDfltCpuSrvcRevision                                    DfltCpuSrvcRevision
+#endif
+
+#ifdef OvrdDfltCpuSrvcDisablePstate
+  #define FinalDfltCpuSrvcDisablePstate                               OvrdDfltCpuSrvcDisablePstate
+#else
+  #define FinalDfltCpuSrvcDisablePstate                               DfltCpuSrvcDisablePstate
+#endif
+
+#ifdef OvrdDfltCpuSrvcTransitionPstate
+  #define FinalDfltCpuSrvcTransitionPstate                            OvrdDfltCpuSrvcTransitionPstate
+#else
+  #define FinalDfltCpuSrvcTransitionPstate                            DfltCpuSrvcTransitionPstate
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetProcIddMax
+  #define FinalDfltCpuSrvcGetProcIddMax                               OvrdDfltCpuSrvcGetProcIddMax
+#else
+  #define FinalDfltCpuSrvcGetProcIddMax                               DfltCpuSrvcGetProcIddMax
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetTscRate
+  #define FinalDfltCpuSrvcGetTscRate                                  OvrdDfltCpuSrvcGetTscRate
+#else
+  #define FinalDfltCpuSrvcGetTscRate                                  DfltCpuSrvcGetTscRate
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetCurrentNbFrequency
+  #define FinalDfltCpuSrvcGetCurrentNbFrequency                       OvrdDfltCpuSrvcGetCurrentNbFrequency
+#else
+  #define FinalDfltCpuSrvcGetCurrentNbFrequency                       DfltCpuSrvcGetCurrentNbFrequency
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetMinMaxNbFrequency
+  #define FinalDfltCpuSrvcGetMinMaxNbFrequency                        OvrdDfltCpuSrvcGetMinMaxNbFrequency
+#else
+  #define FinalDfltCpuSrvcGetMinMaxNbFrequency                        DfltCpuSrvcGetMinMaxNbFrequency
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetNbPstateInfo
+  #define FinalDfltCpuSrvcGetNbPstateInfo                             OvrdDfltCpuSrvcGetNbPstateInfo
+#else
+  #define FinalDfltCpuSrvcGetNbPstateInfo                             DfltCpuSrvcGetNbPstateInfo
+#endif
+
+#ifdef OvrdDfltCpuSrvcIsNbCofInitNeeded
+  #define FinalDfltCpuSrvcIsNbCofInitNeeded                           OvrdDfltCpuSrvcIsNbCofInitNeeded
+#else
+  #define FinalDfltCpuSrvcIsNbCofInitNeeded                           DfltCpuSrvcIsNbCofInitNeeded
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetNbIddMax
+  #define FinalDfltCpuSrvcGetNbIddMax                                 OvrdDfltCpuSrvcGetNbIddMax
+#else
+  #define FinalDfltCpuSrvcGetNbIddMax                                 DfltCpuSrvcGetNbIddMax
+#endif
+
+#ifdef OvrdDfltCpuSrvcLaunchApCore
+  #define FinalDfltCpuSrvcLaunchApCore                                OvrdDfltCpuSrvcLaunchApCore
+#else
+  #define FinalDfltCpuSrvcLaunchApCore                                DfltCpuSrvcLaunchApCore
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetNumberOfPhysicalCores
+  #define FinalDfltCpuSrvcGetNumberOfPhysicalCores                    OvrdDfltCpuSrvcGetNumberOfPhysicalCores
+#else
+  #define FinalDfltCpuSrvcGetNumberOfPhysicalCores                    DfltCpuSrvcGetNumberOfPhysicalCores
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetApMailboxFromHardware
+  #define FinalDfltCpuSrvcGetApMailboxFromHardware                    OvrdDfltCpuSrvcGetApMailboxFromHardware
+#else
+  #define FinalDfltCpuSrvcGetApMailboxFromHardware                    DfltCpuSrvcGetApMailboxFromHardware
+#endif
+
+#ifdef OvrdDfltCpuSrvcSetApCoreNumber
+  #define FinalDfltCpuSrvcSetApCoreNumber                             OvrdDfltCpuSrvcSetApCoreNumber
+#else
+  #define FinalDfltCpuSrvcSetApCoreNumber                             DfltCpuSrvcSetApCoreNumber
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetApCoreNumber
+  #define FinalDfltCpuSrvcGetApCoreNumber                             OvrdDfltCpuSrvcGetApCoreNumber
+#else
+  #define FinalDfltCpuSrvcGetApCoreNumber                             DfltCpuSrvcGetApCoreNumber
+#endif
+
+#ifdef OvrdDfltCpuSrvcTransferApCoreNumber
+  #define FinalDfltCpuSrvcTransferApCoreNumber                        OvrdDfltCpuSrvcTransferApCoreNumber
+#else
+  #define FinalDfltCpuSrvcTransferApCoreNumber                        DfltCpuSrvcTransferApCoreNumber
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetStoredNodeNumber
+  #define FinalDfltCpuSrvcGetStoredNodeNumber                         OvrdDfltCpuSrvcGetStoredNodeNumber
+#else
+  #define FinalDfltCpuSrvcGetStoredNodeNumber                         DfltCpuSrvcGetStoredNodeNumber
+#endif
+
+#ifdef OvrdDfltCpuSrvcCoreIdPositionInInitialApicId
+  #define FinalDfltCpuSrvcCoreIdPositionInInitialApicId               OvrdDfltCpuSrvcCoreIdPositionInInitialApicId
+#else
+  #define FinalDfltCpuSrvcCoreIdPositionInInitialApicId               DfltCpuSrvcCoreIdPositionInInitialApicId
+#endif
+
+#ifdef OvrdDfltCpuSrvcSaveFeatures
+  #define FinalDfltCpuSrvcSaveFeatures                                OvrdDfltCpuSrvcSaveFeatures
+#else
+  #define FinalDfltCpuSrvcSaveFeatures                                DfltCpuSrvcSaveFeatures
+#endif
+
+#ifdef OvrdDfltCpuSrvcWriteFeatures
+  #define FinalDfltCpuSrvcWriteFeatures                               OvrdDfltCpuSrvcWriteFeatures
+#else
+  #define FinalDfltCpuSrvcWriteFeatures                               DfltCpuSrvcWriteFeatures
+#endif
+
+#ifdef OvrdDfltCpuSrvcSetWarmResetFlag
+  #define FinalDfltCpuSrvcSetWarmResetFlag                            OvrdDfltCpuSrvcSetWarmResetFlag
+#else
+  #define FinalDfltCpuSrvcSetWarmResetFlag                            DfltCpuSrvcSetWarmResetFlag
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetWarmResetFlag
+  #define FinalDfltCpuSrvcGetWarmResetFlag                            OvrdDfltCpuSrvcGetWarmResetFlag
+#else
+  #define FinalDfltCpuSrvcGetWarmResetFlag                            DfltCpuSrvcGetWarmResetFlag
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetBrandString1
+  #define FinalDfltCpuSrvcGetBrandString1                             OvrdDfltCpuSrvcGetBrandString1
+#else
+  #define FinalDfltCpuSrvcGetBrandString1                             DfltCpuSrvcGetBrandString1
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetBrandString2
+  #define FinalDfltCpuSrvcGetBrandString2                             OvrdDfltCpuSrvcGetBrandString2
+#else
+  #define FinalDfltCpuSrvcGetBrandString2                             DfltCpuSrvcGetBrandString2
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetMicroCodePatchesStruct
+  #define FinalDfltCpuSrvcGetMicroCodePatchesStruct                   OvrdDfltCpuSrvcGetMicroCodePatchesStruct
+#else
+  #define FinalDfltCpuSrvcGetMicroCodePatchesStruct                   DfltCpuSrvcGetMicroCodePatchesStruct
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetMicrocodeEquivalenceTable
+  #define FinalDfltCpuSrvcGetMicrocodeEquivalenceTable                OvrdDfltCpuSrvcGetMicrocodeEquivalenceTable
+#else
+  #define FinalDfltCpuSrvcGetMicrocodeEquivalenceTable                DfltCpuSrvcGetMicrocodeEquivalenceTable
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetCacheInfo
+  #define FinalDfltCpuSrvcGetCacheInfo                                OvrdDfltCpuSrvcGetCacheInfo
+#else
+  #define FinalDfltCpuSrvcGetCacheInfo                                DfltCpuSrvcGetCacheInfo
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetSysPmTableStruct
+  #define FinalDfltCpuSrvcGetSysPmTableStruct                         OvrdDfltCpuSrvcGetSysPmTableStruct
+#else
+  #define FinalDfltCpuSrvcGetSysPmTableStruct                         DfltCpuSrvcGetSysPmTableStruct
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetWheaInitData
+  #define FinalDfltCpuSrvcGetWheaInitData                             OvrdDfltCpuSrvcGetWheaInitData
+#else
+  #define FinalDfltCpuSrvcGetWheaInitData                             DfltCpuSrvcGetWheaInitData
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetPlatformTypeSpecificInfo
+  #define FinalDfltCpuSrvcGetPlatformTypeSpecificInfo                 OvrdDfltCpuSrvcGetPlatformTypeSpecificInfo
+#else
+  #define FinalDfltCpuSrvcGetPlatformTypeSpecificInfo                 DfltCpuSrvcGetPlatformTypeSpecificInfo
+#endif
+
+#ifdef OvrdDfltCpuSrvcIsNbPstateEnabled
+  #define FinalDfltCpuSrvcIsNbPstateEnabled                           OvrdDfltCpuSrvcIsNbPstateEnabled
+#else
+  #define FinalDfltCpuSrvcIsNbPstateEnabled                           DfltCpuSrvcIsNbPstateEnabled
+#endif
+
+#ifdef OvrdDfltCpuSrvcNextLinkHasHtPhyFeats
+  #define FinalDfltCpuSrvcNextLinkHasHtPhyFeats                       OvrdDfltCpuSrvcNextLinkHasHtPhyFeats
+#else
+  #define FinalDfltCpuSrvcNextLinkHasHtPhyFeats                       DfltCpuSrvcNextLinkHasHtPhyFeats
+#endif
+
+#ifdef OvrdDfltCpuSrvcSetHtPhyRegister
+  #define FinalDfltCpuSrvcSetHtPhyRegister                            OvrdDfltCpuSrvcSetHtPhyRegister
+#else
+  #define FinalDfltCpuSrvcSetHtPhyRegister                            DfltCpuSrvcSetHtPhyRegister
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetNextHtLinkFeatures
+  #define FinalDfltCpuSrvcGetNextHtLinkFeatures                       OvrdDfltCpuSrvcGetNextHtLinkFeatures
+#else
+  #define FinalDfltCpuSrvcGetNextHtLinkFeatures                       DfltCpuSrvcGetNextHtLinkFeatures
+#endif
+
+#ifdef OvrdDfltCpuSrvcRegisterTableList
+  #define FinalDfltCpuSrvcRegisterTableList                           OvrdDfltCpuSrvcRegisterTableList
+#else
+  #define FinalDfltCpuSrvcRegisterTableList                           DfltCpuSrvcRegisterTableList
+#endif
+
+#ifdef OvrdDfltCpuSrvcTableEntryTypeDescriptors
+  #define FinalDfltCpuSrvcTableEntryTypeDescriptors                   OvrdDfltCpuSrvcTableEntryTypeDescriptors
+#else
+  #define FinalDfltCpuSrvcTableEntryTypeDescriptors                   DfltCpuSrvcTableEntryTypeDescriptors
+#endif
+
+#ifdef OvrdDfltCpuSrvcPackageLinkMap
+  #define FinalDfltCpuSrvcPackageLinkMap                              OvrdDfltCpuSrvcPackageLinkMap
+#else
+  #define FinalDfltCpuSrvcPackageLinkMap                              DfltCpuSrvcPackageLinkMap
+#endif
+
+#ifdef OvrdDfltCpuSrvcComputeUnitMap
+  #define FinalDfltCpuSrvcComputeUnitMap                              OvrdDfltCpuSrvcComputeUnitMap
+#else
+  #define FinalDfltCpuSrvcComputeUnitMap                              DfltCpuSrvcComputeUnitMap
+#endif
+
+#ifdef OvrdDfltCpuSrvcInitCacheDisabled
+  #define FinalDfltCpuSrvcInitCacheDisabled                           OvrdDfltCpuSrvcInitCacheDisabled
+#else
+  #define FinalDfltCpuSrvcInitCacheDisabled                           DfltCpuSrvcInitCacheDisabled
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+  #define FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable       OvrdDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#else
+  #define FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable       DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#endif
+
+#ifdef OvrdDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+  #define FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable        OvrdDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#else
+  #define FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable        DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#endif
+
+#ifdef OvrdDfltCpuSrvcPatchLoaderIsSharedByCU
+  #define FinalDfltCpuSrvcPatchLoaderIsSharedByCU                     OvrdDfltCpuSrvcPatchLoaderIsSharedByCU
+#else
+  #define FinalDfltCpuSrvcPatchLoaderIsSharedByCU                     DfltCpuSrvcPatchLoaderIsSharedByCU
+#endif
+
+
+//
+// Make final service definition with considerations of below:
+// 1. Common build config swich control
+// 2. Override service definition
+//
+
+// Member: (UINT16) Revision
+#ifdef CpuSrvcRevision
+  #define FinalCpuSrvcRevision                                CpuSrvcRevision
+#else
+  #define FinalCpuSrvcRevision                                FinalDfltCpuSrvcRevision
+#endif
+
+// Member: (PF_CPU_DISABLE_PSTATE) DisablePstate
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcDisablePstate
+    #define FinalCpuSrvcDisablePstate                           CpuSrvcDisablePstate
+    #ifndef EXTERN_FINALCPUSRVCDISABLEPSTATE
+    #define EXTERN_FINALCPUSRVCDISABLEPSTATE
+        extern  F_CPU_DISABLE_PSTATE                                FinalCpuSrvcDisablePstate;
+    #endif
+  #else
+    #define FinalCpuSrvcDisablePstate                           FinalDfltCpuSrvcDisablePstate
+  #endif
+#else
+  #define FinalCpuSrvcDisablePstate                           FinalDfltAssertCpuSrvcDisablePstate
+#endif
+
+// Member: (PF_CPU_TRANSITION_PSTATE) TransitionPstate
+#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcTransitionPstate
+    #define FinalCpuSrvcTransitionPstate                        CpuSrvcTransitionPstate
+    #ifndef EXTERN_FINALCPUSRVCTRANSITIONPSTATE
+    #define EXTERN_FINALCPUSRVCTRANSITIONPSTATE
+        extern  F_CPU_TRANSITION_PSTATE                             FinalCpuSrvcTransitionPstate;
+    #endif
+  #else
+    #define FinalCpuSrvcTransitionPstate                        FinalDfltCpuSrvcTransitionPstate
+  #endif
+#else
+  #define FinalCpuSrvcTransitionPstate                        FinalDfltAssertCpuSrvcTransitionPstate
+#endif
+
+// Member: (PF_CPU_GET_IDD_MAX) GetProcIddMax
+#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
+  #ifdef CpuSrvcGetProcIddMax
+    #define FinalCpuSrvcGetProcIddMax                           CpuSrvcGetProcIddMax
+    extern  F_CPU_GET_IDD_MAX                                   FinalCpuSrvcGetProcIddMax;
+  #else
+    #define FinalCpuSrvcGetProcIddMax                           FinalDfltCpuSrvcGetProcIddMax
+  #endif
+#else
+  #define FinalCpuSrvcGetProcIddMax                           FinalDfltAssertCpuSrvcGetProcIddMax
+#endif
+
+// Member: (PF_CPU_GET_TSC_RATE) GetTscRate
+#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcGetTscRate
+    #define FinalCpuSrvcGetTscRate                              CpuSrvcGetTscRate
+    #ifndef EXTERN_FINALCPUSRVCGETTSCRATE
+    #define EXTERN_FINALCPUSRVCGETTSCRATE
+        extern  F_CPU_GET_TSC_RATE                                  FinalCpuSrvcGetTscRate;
+    #endif
+  #else
+    #define FinalCpuSrvcGetTscRate                              FinalDfltCpuSrvcGetTscRate
+  #endif
+#else
+  #define FinalCpuSrvcGetTscRate                              FinalDfltAssertCpuSrvcGetTscRate
+#endif
+
+// Member: (PF_CPU_GET_NB_FREQ) GetCurrentNbFrequency
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetCurrentNbFrequency
+    #define FinalCpuSrvcGetCurrentNbFrequency                   CpuSrvcGetCurrentNbFrequency
+    extern  F_CPU_GET_NB_FREQ                                   FinalCpuSrvcGetCurrentNbFrequency;
+  #else
+    #define FinalCpuSrvcGetCurrentNbFrequency                   FinalDfltCpuSrvcGetCurrentNbFrequency
+  #endif
+#else
+  #define FinalCpuSrvcGetCurrentNbFrequency                   FinalDfltAssertCpuSrvcGetCurrentNbFrequency
+#endif
+
+
+// Member: (PF_CPU_GET_MIN_MAX_NB_FREQ) GetMinMaxNbFrequency
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetMinMaxNbFrequency
+    #define FinalCpuSrvcGetMinMaxNbFrequency                    CpuSrvcGetMinMaxNbFrequency
+    extern  F_CPU_GET_MIN_MAX_NB_FREQ                           FinalCpuSrvcGetMinMaxNbFrequency;
+  #else
+    #define FinalCpuSrvcGetMinMaxNbFrequency                    FinalDfltCpuSrvcGetMinMaxNbFrequency
+  #endif
+#else
+  #define FinalCpuSrvcGetMinMaxNbFrequency                    FinalDfltAssertCpuSrvcGetMinMaxNbFrequency
+#endif
+
+// Member: (PF_CPU_GET_NB_PSTATE_INFO) GetNbPstateInfo
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetNbPstateInfo
+    #define FinalCpuSrvcGetNbPstateInfo                         CpuSrvcGetNbPstateInfo
+    extern  F_CPU_GET_NB_PSTATE_INFO                            FinalCpuSrvcGetNbPstateInfo;
+  #else
+    #define FinalCpuSrvcGetNbPstateInfo                         FinalDfltCpuSrvcGetNbPstateInfo
+  #endif
+#else
+  #define FinalCpuSrvcGetNbPstateInfo                         FinalDfltAssertCpuSrvcGetNbPstateInfo
+#endif
+
+// Member: (PF_CPU_IS_NBCOF_INIT_NEEDED) IsNbCofInitNeeded
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcIsNbCofInitNeeded
+    #define FinalCpuSrvcIsNbCofInitNeeded                       CpuSrvcIsNbCofInitNeeded
+    extern  F_CPU_IS_NBCOF_INIT_NEEDED                          FinalCpuSrvcIsNbCofInitNeeded;
+  #else
+    #define FinalCpuSrvcIsNbCofInitNeeded                       FinalDfltCpuSrvcIsNbCofInitNeeded
+  #endif
+#else
+  #define FinalCpuSrvcIsNbCofInitNeeded                       FinalDfltAssertCpuSrvcIsNbCofInitNeeded
+#endif
+
+// Member:    (PF_CPU_GET_NB_IDD_MAX) GetNbIddMax
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetNbIddMax
+    #define FinalCpuSrvcGetNbIddMax                             CpuSrvcGetNbIddMax
+    extern  F_CPU_GET_NB_IDD_MAX                                FinalCpuSrvcGetNbIddMax;
+  #else
+    #define FinalCpuSrvcGetNbIddMax                             FinalDfltCpuSrvcGetNbIddMax
+  #endif
+#else
+  #define FinalCpuSrvcGetNbIddMax                             FinalDfltAssertCpuSrvcGetNbIddMax
+#endif
+
+// Member:  (PF_CPU_AP_INITIAL_LAUNCH) LaunchApCore
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcLaunchApCore
+    #define FinalCpuSrvcLaunchApCore                            CpuSrvcLaunchApCore
+    #ifndef EXTERN_FINALCPUSRVCLAUNCHAPCORE
+    #define EXTERN_FINALCPUSRVCLAUNCHAPCORE
+        extern  F_CPU_AP_INITIAL_LAUNCH                             FinalCpuSrvcLaunchApCore;
+    #endif
+  #else
+    #define FinalCpuSrvcLaunchApCore                            FinalDfltCpuSrvcLaunchApCore
+  #endif
+#else
+  #define FinalCpuSrvcLaunchApCore                            FinalDfltAssertCpuSrvcLaunchApCore
+#endif
+
+// Member:(PF_CPU_NUMBER_OF_PHYSICAL_CORES) GetNumberOfPhysicalCores
+#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcGetNumberOfPhysicalCores
+    #define FinalCpuSrvcGetNumberOfPhysicalCores                CpuSrvcGetNumberOfPhysicalCores
+    extern  F_CPU_NUMBER_OF_PHYSICAL_CORES                      FinalCpuSrvcGetNumberOfPhysicalCores;
+  #else
+    #define FinalCpuSrvcGetNumberOfPhysicalCores                FinalDfltCpuSrvcGetNumberOfPhysicalCores
+  #endif
+#else
+  #define FinalCpuSrvcGetNumberOfPhysicalCores                FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores
+#endif
+
+// Member: (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) GetApMailboxFromHardware
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcGetApMailboxFromHardware
+    #define FinalCpuSrvcGetApMailboxFromHardware                CpuSrvcGetApMailboxFromHardware
+    extern  F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE              FinalCpuSrvcGetApMailboxFromHardware;
+  #else
+    #define FinalCpuSrvcGetApMailboxFromHardware                FinalDfltCpuSrvcGetApMailboxFromHardware
+  #endif
+#else
+  #define FinalCpuSrvcGetApMailboxFromHardware                FinalDfltAssertCpuSrvcGetApMailboxFromHardware
+#endif
+
+// Member: (PF_CPU_SET_AP_CORE_NUMBER) SetApCoreNumber
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcSetApCoreNumber
+    #define FinalCpuSrvcSetApCoreNumber                         CpuSrvcSetApCoreNumber
+    extern  F_CPU_SET_AP_CORE_NUMBER                            FinalCpuSrvcSetApCoreNumber;
+  #else
+    #define FinalCpuSrvcSetApCoreNumber                         FinalDfltCpuSrvcSetApCoreNumber
+  #endif
+#else
+  #define FinalCpuSrvcSetApCoreNumber                         FinalDfltAssertCpuSrvcSetApCoreNumber
+#endif
+
+// Member: (PF_CPU_GET_AP_CORE_NUMBER) GetApCoreNumber
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || \
+    (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcGetApCoreNumber
+    #define FinalCpuSrvcGetApCoreNumber                         CpuSrvcGetApCoreNumber
+    extern  F_CPU_GET_AP_CORE_NUMBER                            FinalCpuSrvcGetApCoreNumber;
+  #else
+    #define FinalCpuSrvcGetApCoreNumber                         FinalDfltCpuSrvcGetApCoreNumber
+  #endif
+#else
+  #define FinalCpuSrvcGetApCoreNumber                         FinalDfltAssertCpuSrvcGetApCoreNumber
+#endif
+
+// Member: (PF_CPU_TRANSFER_AP_CORE_NUMBER) TransferApCoreNumber
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcTransferApCoreNumber
+    #define FinalCpuSrvcTransferApCoreNumber                    CpuSrvcTransferApCoreNumber
+    extern  F_CPU_TRANSFER_AP_CORE_NUMBER                       FinalCpuSrvcTransferApCoreNumber;
+  #else
+    #define FinalCpuSrvcTransferApCoreNumber                    FinalDfltCpuSrvcTransferApCoreNumber
+  #endif
+#else
+  #define FinalCpuSrvcTransferApCoreNumber                    FinalDfltAssertCpuSrvcTransferApCoreNumber
+#endif
+
+// Member: (PF_CPU_GET_STORED_NODE_NUMBER) GetStoredNodeNumber
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || \
+    (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || \
+    (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || \
+    (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) || (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+  #ifdef CpuSrvcGetStoredNodeNumber
+    #define FinalCpuSrvcGetStoredNodeNumber                     CpuSrvcGetStoredNodeNumber
+    extern  F_CPU_GET_STORED_NODE_NUMBER                        FinalCpuSrvcGetStoredNodeNumber;
+  #else
+    #define FinalCpuSrvcGetStoredNodeNumber                     FinalDfltCpuSrvcGetStoredNodeNumber
+  #endif
+#else
+  #define FinalCpuSrvcGetStoredNodeNumber                     FinalDfltAssertCpuSrvcGetStoredNodeNumber
+#endif
+
+// Member: (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CoreIdPositionInInitialApicId
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || \
+    (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+  #ifdef CpuSrvcCoreIdPositionInInitialApicId
+    #define FinalCpuSrvcCoreIdPositionInInitialApicId           CpuSrvcCoreIdPositionInInitialApicId
+    #ifndef EXTERN_FINALCPUSRVCCOREIDPOSITIONININITIALAPICID
+    #define EXTERN_FINALCPUSRVCCOREIDPOSITIONININITIALAPICID
+        extern  F_CORE_ID_POSITION_IN_INITIAL_APIC_ID               FinalCpuSrvcCoreIdPositionInInitialApicId;
+    #endif
+  #else
+    #define FinalCpuSrvcCoreIdPositionInInitialApicId           FinalDfltCpuSrvcoreIdPositionInInitialApicId
+  #endif
+#else
+  #define FinalCpuSrvcCoreIdPositionInInitialApicId           FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId
+#endif
+
+// Member: (PF_CPU_SAVE_FEATURES) SaveFeatures
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+  #ifdef CpuSrvcSaveFeatures
+    #define FinalCpuSrvcSaveFeatures                            CpuSrvcSaveFeatures
+    extern  F_CPU_SAVE_FEATURES                                 FinalCpuSrvcSaveFeatures;
+  #else
+    #define FinalCpuSrvcSaveFeatures                            FinalDfltCpuSrvcSaveFeatures
+  #endif
+#else
+  #define FinalCpuSrvcSaveFeatures                            FinalDfltAssertCpuSrvcSaveFeatures
+#endif
+
+// Member: (PF_CPU_WRITE_FEATURES) WriteFeatures
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+  #ifdef CpuSrvcWriteFeatures
+    #define FinalCpuSrvcWriteFeatures                           CpuSrvcWriteFeatures
+    extern  F_CPU_WRITE_FEATURES                                FinalCpuSrvcWriteFeatures;
+  #else
+    #define FinalCpuSrvcWriteFeatures                           FinalDfltCpuSrvcWriteFeatures
+  #endif
+#else
+  #define FinalCpuSrvcWriteFeatures                           FinalDfltAssertCpuSrvcWriteFeatures
+#endif
+
+// Member: (PF_CPU_SET_WARM_RESET_FLAG) SetWarmResetFlag
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
+  #ifdef CpuSrvcSetWarmResetFlag
+    #define FinalCpuSrvcSetWarmResetFlag                        CpuSrvcSetWarmResetFlag
+    #ifndef EXTERN_FINALCPUSRVCSETWARMRESETFLAG
+    #define EXTERN_FINALCPUSRVCSETWARMRESETFLAG
+        extern  F_CPU_SET_WARM_RESET_FLAG                           FinalCpuSrvcSetWarmResetFlag;
+    #endif
+  #else
+    #define FinalCpuSrvcSetWarmResetFlag                        FinalDfltCpuSrvcSetWarmResetFlag
+  #endif
+#else
+  #define FinalCpuSrvcSetWarmResetFlag                        FinalDfltAssertCpuSrvcSetWarmResetFlag
+#endif
+
+// Member: (PF_CPU_GET_WARM_RESET_FLAG) GetWarmResetFlag
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
+  #ifdef CpuSrvcGetWarmResetFlag
+    #define FinalCpuSrvcGetWarmResetFlag                        CpuSrvcGetWarmResetFlag
+    #ifndef EXTERN_FINALCPUSRVCGETWARMRESETFLAG
+    #define EXTERN_FINALCPUSRVCGETWARMRESETFLAG
+        extern  F_CPU_GET_WARM_RESET_FLAG                           FinalCpuSrvcGetWarmResetFlag;
+    #endif
+  #else
+    #define FinalCpuSrvcGetWarmResetFlag                        FinalDfltCpuSrvcGetWarmResetFlag
+  #endif
+#else
+  #define FinalCpuSrvcGetWarmResetFlag                        FinalDfltAssertCpuSrvcGetWarmResetFlag
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetBrandString1
+#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcGetBrandString1
+    #define FinalCpuSrvcGetBrandString1                         CpuSrvcGetBrandString1
+    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetBrandString1;
+  #else
+    #define FinalCpuSrvcGetBrandString1                         FinalDfltCpuSrvcGetBrandString1
+  #endif
+#else
+  #define FinalCpuSrvcGetBrandString1                         FinalDfltAssertCpuSrvcGetBrandString1
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetBrandString2
+#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcGetBrandString2
+    #define FinalCpuSrvcGetBrandString2                         CpuSrvcGetBrandString2
+    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetBrandString2;
+  #else
+    #define FinalCpuSrvcGetBrandString2                         FinalDfltCpuSrvcGetBrandString2
+  #endif
+#else
+  #define FinalCpuSrvcGetBrandString2                         FinalDfltAssertCpuSrvcGetBrandString2
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetMicroCodePatchesStruct
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcGetMicroCodePatchesStruct
+    #define FinalCpuSrvcGetMicroCodePatchesStruct               CpuSrvcGetMicroCodePatchesStruct
+    #ifndef EXTERN_FINALCPUSRVCGETMICROCODEPATCHESSTRUCT
+    #define EXTERN_FINALCPUSRVCGETMICROCODEPATCHESSTRUCT
+        extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetMicroCodePatchesStruct;
+    #endif
+  #else
+    #define FinalCpuSrvcGetMicroCodePatchesStruct               FinalDfltCpuSrvcGetMicroCodePatchesStruct
+  #endif
+#else
+  #define FinalCpuSrvcGetMicroCodePatchesStruct               FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetMicrocodeEquivalenceTable
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcGetMicrocodeEquivalenceTable
+    #define FinalCpuSrvcGetMicrocodeEquivalenceTable            CpuSrvcGetMicrocodeEquivalenceTable
+    #ifndef EXTERN_FINALCPUSRVCGETMICROCODEEQUIVALENCETABLE
+    #define EXTERN_FINALCPUSRVCGETMICROCODEEQUIVALENCETABLE
+        extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetMicrocodeEquivalenceTable;
+    #endif
+  #else
+    #define FinalCpuSrvcGetMicrocodeEquivalenceTable            FinalDfltCpuSrvcGetMicrocodeEquivalenceTable
+  #endif
+#else
+  #define FinalCpuSrvcGetMicrocodeEquivalenceTable            FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetCacheInfo
+#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcGetCacheInfo
+    #define FinalCpuSrvcGetCacheInfo                            CpuSrvcGetCacheInfo
+    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetCacheInfo;
+  #else
+    #define FinalCpuSrvcGetCacheInfo                            FinalDfltCpuSrvcGetCacheInfo
+  #endif
+#else
+  #define FinalCpuSrvcGetCacheInfo                            FinalDfltAssertCpuSrvcGetCacheInfo
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetSysPmTableStruct
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetSysPmTableStruct
+    #define FinalCpuSrvcGetSysPmTableStruct                     CpuSrvcGetSysPmTableStruct
+    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetSysPmTableStruct;
+  #else
+    #define FinalCpuSrvcGetSysPmTableStruct                     FinalDfltCpuSrvcGetSysPmTableStruct
+  #endif
+#else
+  #define FinalCpuSrvcGetSysPmTableStruct                     FinalDfltAssertCpuSrvcGetSysPmTableStruct
+#endif
+
+// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetWheaInitData
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifdef CpuSrvcGetWheaInitData
+    #define FinalCpuSrvcGetWheaInitData                         CpuSrvcGetWheaInitData
+    #ifndef EXTERN_FINALCPUSRVCGETWHEAINITDATA
+    #define EXTERN_FINALCPUSRVCGETWHEAINITDATA
+        extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetWheaInitData;
+    #endif
+  #else
+    #define FinalCpuSrvcGetWheaInitData                         FinalDfltCpuSrvcGetWheaInitData
+  #endif
+#else
+  #define FinalCpuSrvcGetWheaInitData                         FinalDfltAssertCpuSrvcGetWheaInitData
+#endif
+
+// Member: (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) GetPlatformTypeSpecificInfo
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #ifdef CpuSrvcGetPlatformTypeSpecificInfo
+    #define FinalCpuSrvcGetPlatformTypeSpecificInfo             CpuSrvcGetPlatformTypeSpecificInfo
+    extern  F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO               FinalCpuSrvcGetPlatformTypeSpecificInfo;
+  #else
+    #define FinalCpuSrvcGetPlatformTypeSpecificInfo             FinalDfltCpuSrvcGetPlatformTypeSpecificInfo
+  #endif
+#else
+  #define FinalCpuSrvcGetPlatformTypeSpecificInfo             FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+#endif
+
+// Member: (PF_IS_NB_PSTATE_ENABLED) IsNbPstateEnabled
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
+  #ifdef CpuSrvcIsNbPstateEnabled
+    #define FinalCpuSrvcIsNbPstateEnabled                       CpuSrvcIsNbPstateEnabled
+    extern  F_IS_NB_PSTATE_ENABLED                              FinalCpuSrvcIsNbPstateEnabled;
+  #else
+    #define FinalCpuSrvcIsNbPstateEnabled                       FinalDfltCpuSrvcIsNbPstateEnabled
+  #endif
+#else
+  #define FinalCpuSrvcIsNbPstateEnabled                       FinalDfltAssertCpuSrvcIsNbPstateEnabled
+#endif
+
+// Member: (PF_NEXT_LINK_HAS_HTFPY_FEATS) NextLinkHasHtPhyFeats
+#if BASE_FAMILY_HT_PCI == TRUE
+  #ifdef CpuSrvcNextLinkHasHtPhyFeats
+    #define FinalCpuSrvcNextLinkHasHtPhyFeats                   CpuSrvcNextLinkHasHtPhyFeats
+    extern  F_NEXT_LINK_HAS_HTPHY_FEATS                         FinalCpuSrvcNextLinkHasHtPhyFeats;
+  #else
+    #define FinalCpuSrvcNextLinkHasHtPhyFeats                   FinalDfltCpuSrvcNextLinkHasHtPhyFeats
+  #endif
+#else
+  #define FinalCpuSrvcNextLinkHasHtPhyFeats                   FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats
+#endif
+
+// Member: (PF_SET_HT_PHY_REGISTER) SetHtPhyRegister
+#if BASE_FAMILY_HT_PCI == TRUE
+  #ifdef CpuSrvcSetHtPhyRegister
+    #define FinalCpuSrvcSetHtPhyRegister                        CpuSrvcSetHtPhyRegister
+    extern  F_SET_HT_PHY_REGISTER                               FinalCpuSrvcSetHtPhyRegister;
+  #else
+    #define FinalCpuSrvcSetHtPhyRegister                        FinalDfltCpuSrvcSetHtPhyRegister
+  #endif
+#else
+  #define FinalCpuSrvcSetHtPhyRegister                        FinalDfltAssertCpuSrvcSetHtPhyRegister
+#endif
+
+// Member: (PF_GET_NEXT_HT_LINK_FEATURES) GetNextHtLinkFeatures
+#if BASE_FAMILY_PCI == TRUE
+  #ifdef CpuSrvcGetNextHtLinkFeatures
+    #define FinalCpuSrvcGetNextHtLinkFeatures                   CpuSrvcGetNextHtLinkFeatures
+    extern  F_GET_NEXT_HT_LINK_FEATURES                         FinalCpuSrvcGetNextHtLinkFeatures;
+  #else
+    #define FinalCpuSrvcGetNextHtLinkFeatures                   FinalDfltCpuSrvcGetNextHtLinkFeatures
+  #endif
+#else
+  #define FinalCpuSrvcGetNextHtLinkFeatures                   FinalDfltAssertCpuSrvcGetNextHtLinkFeatures
+#endif
+
+// Member: (REGISTER_TABLE **) RegisterTableList
+#if USES_REGISTER_TABLES == TRUE // (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcRegisterTableList
+    #define FinalCpuSrvcRegisterTableList                       CpuSrvcRegisterTableList
+  #else
+    #define FinalCpuSrvcRegisterTableList                       FinalDfltCpuSrvcRegisterTableList
+  #endif
+#else
+  #define FinalCpuSrvcRegisterTableList                       FinalDfltAssertCpuSrvcRegisterTableList
+#endif
+
+// Member: (TABLE_ENTRY_TYPE_DESCRIPTOR *) TableEntryTypeDescriptors
+#if USES_REGISTER_TABLES == TRUE // (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcTableEntryTypeDescriptors
+    #define FinalCpuSrvcTableEntryTypeDescriptors               CpuSrvcTableEntryTypeDescriptors
+  #else
+    #define FinalCpuSrvcTableEntryTypeDescriptors               FinalDfltCpuSrvcTableEntryTypeDescriptors
+  #endif
+#else
+  #define FinalCpuSrvcTableEntryTypeDescriptors               FinalDfltAssertCpuSrvcTableEntryTypeDescriptors
+#endif
+
+// Member: (PACKAGE_HTLINK_MAP) PackageLinkMap
+#if MODEL_SPECIFIC_HT_PCI == TRUE
+  #ifdef CpuSrvcPackageLinkMap
+    #define FinalCpuSrvcPackageLinkMap                          CpuSrvcPackageLinkMap
+  #else
+    #define FinalCpuSrvcPackageLinkMap                          FinalDfltCpuSrvcPackageLinkMap
+  #endif
+#else
+  #define FinalCpuSrvcPackageLinkMap                          FinalDfltAssertCpuSrvcPackageLinkMap
+#endif
+
+// Member: (COMPUTE_UNIT_MAP *) ComputeUnitMap
+#ifdef CpuSrvcComputeUnitMap
+  #define FinalCpuSrvcComputeUnitMap                            CpuSrvcComputeUnitMap
+#else
+  #define FinalCpuSrvcComputeUnitMap                            FinalDfltCpuSrvcComputeUnitMap
+#endif
+
+// Member: (FAMILY_CACHE_INIT_POLICY) InitCacheDisabled
+#ifdef CpuSrvcInitCacheDisabled
+  #define FinalCpuSrvcInitCacheDisabled                         CpuSrvcInitCacheDisabled
+#else
+  #define FinalCpuSrvcInitCacheDisabled                         FinalDfltCpuSrvcInitCacheDisabled
+#endif
+
+// Member: (PF_GET_EARLY_INIT_TABLE) GetEarlyInitBeforeApLaunchOnCoreTable
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+    #define FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable                 CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+    extern  F_GET_EARLY_INIT_TABLE                              FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable;
+  #else
+    #define FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable                 FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+  #endif
+#else
+  #define FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable                   FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#endif
+
+// Member: (PF_GET_EARLY_INIT_TABLE) GetEarlyInitAfterApLaunchOnCoreTable
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+    #define FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable                 CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+    extern  F_GET_EARLY_INIT_TABLE                              FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable;
+  #else
+    #define FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable                 FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+  #endif
+#else
+  #define FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable                   FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#endif
+
+// Member: (BOOLEAN) PatchLoaderIsSharedByCU
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #ifdef CpuSrvcPatchLoaderIsSharedByCU
+    #define FinalCpuSrvcPatchLoaderIsSharedByCU                 CpuSrvcPatchLoaderIsSharedByCU
+  #else
+    #define FinalCpuSrvcPatchLoaderIsSharedByCU                 FinalDfltCpuSrvcPatchLoaderIsSharedByCU
+  #endif
+#else
+  #define FinalCpuSrvcPatchLoaderIsSharedByCU                 FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU
+#endif
+
+//
+// NOTE: All CPU family specific service members should be all defined now.
+//
+
+//
+// Define CPU specific services installation macro
+//
+#ifndef _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME_
+  #define _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME_
+
+  #define INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME(MacroPrefix, TableName) \
+  CONST CPU_SPECIFIC_SERVICES ROMDATA TableName =           \
+  {                                                         \
+    MacroPrefix##CpuSrvcRevision,                           \
+    MacroPrefix##CpuSrvcDisablePstate,                      \
+    MacroPrefix##CpuSrvcTransitionPstate,                   \
+    MacroPrefix##CpuSrvcGetProcIddMax,                      \
+    MacroPrefix##CpuSrvcGetTscRate,                         \
+    MacroPrefix##CpuSrvcGetCurrentNbFrequency,              \
+    MacroPrefix##CpuSrvcGetMinMaxNbFrequency,               \
+    MacroPrefix##CpuSrvcGetNbPstateInfo,                    \
+    MacroPrefix##CpuSrvcIsNbCofInitNeeded,                  \
+    MacroPrefix##CpuSrvcGetNbIddMax,                        \
+    MacroPrefix##CpuSrvcLaunchApCore,                       \
+    MacroPrefix##CpuSrvcGetNumberOfPhysicalCores,           \
+    MacroPrefix##CpuSrvcGetApMailboxFromHardware,           \
+    MacroPrefix##CpuSrvcSetApCoreNumber,                    \
+    MacroPrefix##CpuSrvcGetApCoreNumber,                    \
+    MacroPrefix##CpuSrvcTransferApCoreNumber,               \
+    MacroPrefix##CpuSrvcGetStoredNodeNumber,                \
+    MacroPrefix##CpuSrvcCoreIdPositionInInitialApicId,      \
+    MacroPrefix##CpuSrvcSaveFeatures,                       \
+    MacroPrefix##CpuSrvcWriteFeatures,                      \
+    MacroPrefix##CpuSrvcSetWarmResetFlag,                   \
+    MacroPrefix##CpuSrvcGetWarmResetFlag,                   \
+    MacroPrefix##CpuSrvcGetBrandString1,                    \
+    MacroPrefix##CpuSrvcGetBrandString2,                    \
+    MacroPrefix##CpuSrvcGetMicroCodePatchesStruct,          \
+    MacroPrefix##CpuSrvcGetMicrocodeEquivalenceTable,       \
+    MacroPrefix##CpuSrvcGetCacheInfo,                       \
+    MacroPrefix##CpuSrvcGetSysPmTableStruct,                \
+    MacroPrefix##CpuSrvcGetWheaInitData,                    \
+    MacroPrefix##CpuSrvcGetPlatformTypeSpecificInfo,        \
+    MacroPrefix##CpuSrvcIsNbPstateEnabled,                  \
+    MacroPrefix##CpuSrvcNextLinkHasHtPhyFeats,              \
+    MacroPrefix##CpuSrvcSetHtPhyRegister,                   \
+    MacroPrefix##CpuSrvcGetNextHtLinkFeatures,              \
+    MacroPrefix##CpuSrvcRegisterTableList,                  \
+    MacroPrefix##CpuSrvcTableEntryTypeDescriptors,          \
+    MacroPrefix##CpuSrvcPackageLinkMap,                     \
+    MacroPrefix##CpuSrvcComputeUnitMap,                     \
+    MacroPrefix##CpuSrvcInitCacheDisabled,                  \
+    MacroPrefix##CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable, \
+    MacroPrefix##CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable, \
+    MacroPrefix##CpuSrvcPatchLoaderIsSharedByCU             \
+  }
+#endif // _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME_
+
+#ifndef _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_
+  #define _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_
+
+  #define INSTALL_CPU_SPECIFIC_SERVICES_TABLE(TableName) \
+            INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME (Final, TableName)
+#endif // _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_
+
+//
+// Message out the final table definitions
+//
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h
new file mode 100644
index 0000000..923b621
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h
@@ -0,0 +1,545 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of CPU specific services support
+ *
+ * This file resets and generates default services of CPU specific services.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 85962 $   @e \$Date: 2013-01-14 20:12:29 -0600 (Mon, 14 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+//
+// Undefine service table name
+//
+#undef CpuSrvcTableName
+
+//
+// Definitions types of a service to undefine
+//
+// * CpuSrvc<ServiceName>
+// * DfltCpuSrvc<ServiceName>
+// * DfltAssertCpuSrvc<ServiceName>
+// * OvrdDfltCpuSrvc<ServiceName>
+// * OvrdDfltAssertCpuSrvc<ServiceName>
+// * FinalDfltCpuSrvc<ServiceName>
+// * FinalDfltAssertCpuSrvc<ServiceName>
+// * FinalCpuSrvc<ServiceName>
+//
+
+//
+// Reset default services definitions
+//
+#undef CpuSrvcRevision
+#undef CpuSrvcDisablePstate
+#undef CpuSrvcTransitionPstate
+#undef CpuSrvcGetProcIddMax
+#undef CpuSrvcGetTscRate
+#undef CpuSrvcGetCurrentNbFrequency
+#undef CpuSrvcGetMinMaxNbFrequency
+#undef CpuSrvcGetNbPstateInfo
+#undef CpuSrvcIsNbCofInitNeeded
+#undef CpuSrvcGetNbIddMax
+#undef CpuSrvcLaunchApCore
+#undef CpuSrvcGetNumberOfPhysicalCores
+#undef CpuSrvcGetApMailboxFromHardware
+#undef CpuSrvcSetApCoreNumber
+#undef CpuSrvcGetApCoreNumber
+#undef CpuSrvcTransferApCoreNumber
+#undef CpuSrvcGetStoredNodeNumber
+#undef CpuSrvcCoreIdPositionInInitialApicId
+#undef CpuSrvcSaveFeatures
+#undef CpuSrvcWriteFeatures
+#undef CpuSrvcSetWarmResetFlag
+#undef CpuSrvcGetWarmResetFlag
+#undef CpuSrvcGetBrandString1
+#undef CpuSrvcGetBrandString2
+#undef CpuSrvcGetMicroCodePatchesStruct
+#undef CpuSrvcGetMicrocodeEquivalenceTable
+#undef CpuSrvcGetCacheInfo
+#undef CpuSrvcGetSysPmTableStruct
+#undef CpuSrvcGetWheaInitData
+#undef CpuSrvcGetPlatformTypeSpecificInfo
+#undef CpuSrvcIsNbPstateEnabled
+#undef CpuSrvcNextLinkHasHtPhyFeats
+#undef CpuSrvcSetHtPhyRegister
+#undef CpuSrvcGetNextHtLinkFeatures
+#undef CpuSrvcRegisterTableList
+#undef CpuSrvcTableEntryTypeDescriptors
+#undef CpuSrvcPackageLinkMap
+#undef CpuSrvcComputeUnitMap
+#undef CpuSrvcInitCacheDisabled
+#undef CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef CpuSrvcPatchLoaderIsSharedByCU
+
+#undef DfltCpuSrvcRevision
+#undef DfltCpuSrvcDisablePstate
+#undef DfltCpuSrvcTransitionPstate
+#undef DfltCpuSrvcGetProcIddMax
+#undef DfltCpuSrvcGetTscRate
+#undef DfltCpuSrvcGetCurrentNbFrequency
+#undef DfltCpuSrvcGetMinMaxNbFrequency
+#undef DfltCpuSrvcGetNbPstateInfo
+#undef DfltCpuSrvcIsNbCofInitNeeded
+#undef DfltCpuSrvcGetNbIddMax
+#undef DfltCpuSrvcLaunchApCore
+#undef DfltCpuSrvcGetNumberOfPhysicalCores
+#undef DfltCpuSrvcGetApMailboxFromHardware
+#undef DfltCpuSrvcSetApCoreNumber
+#undef DfltCpuSrvcGetApCoreNumber
+#undef DfltCpuSrvcTransferApCoreNumber
+#undef DfltCpuSrvcGetStoredNodeNumber
+#undef DfltCpuSrvcCoreIdPositionInInitialApicId
+#undef DfltCpuSrvcSaveFeatures
+#undef DfltCpuSrvcWriteFeatures
+#undef DfltCpuSrvcSetWarmResetFlag
+#undef DfltCpuSrvcGetWarmResetFlag
+#undef DfltCpuSrvcGetBrandString1
+#undef DfltCpuSrvcGetBrandString2
+#undef DfltCpuSrvcGetMicroCodePatchesStruct
+#undef DfltCpuSrvcGetMicrocodeEquivalenceTable
+#undef DfltCpuSrvcGetCacheInfo
+#undef DfltCpuSrvcGetSysPmTableStruct
+#undef DfltCpuSrvcGetWheaInitData
+#undef DfltCpuSrvcGetPlatformTypeSpecificInfo
+#undef DfltCpuSrvcIsNbPstateEnabled
+#undef DfltCpuSrvcNextLinkHasHtPhyFeats
+#undef DfltCpuSrvcSetHtPhyRegister
+#undef DfltCpuSrvcGetNextHtLinkFeatures
+#undef DfltCpuSrvcRegisterTableList
+#undef DfltCpuSrvcTableEntryTypeDescriptors
+#undef DfltCpuSrvcPackageLinkMap
+#undef DfltCpuSrvcComputeUnitMap
+#undef DfltCpuSrvcInitCacheDisabled
+#undef DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef DfltCpuSrvcPatchLoaderIsSharedByCU
+
+#undef DfltAssertCpuSrvcRevision
+#undef DfltAssertCpuSrvcDisablePstate
+#undef DfltAssertCpuSrvcTransitionPstate
+#undef DfltAssertCpuSrvcGetProcIddMax
+#undef DfltAssertCpuSrvcGetTscRate
+#undef DfltAssertCpuSrvcGetCurrentNbFrequency
+#undef DfltAssertCpuSrvcGetMinMaxNbFrequency
+#undef DfltAssertCpuSrvcGetNbPstateInfo
+#undef DfltAssertCpuSrvcIsNbCofInitNeeded
+#undef DfltAssertCpuSrvcGetNbIddMax
+#undef DfltAssertCpuSrvcLaunchApCore
+#undef DfltAssertCpuSrvcGetNumberOfPhysicalCores
+#undef DfltAssertCpuSrvcGetApMailboxFromHardware
+#undef DfltAssertCpuSrvcSetApCoreNumber
+#undef DfltAssertCpuSrvcGetApCoreNumber
+#undef DfltAssertCpuSrvcTransferApCoreNumber
+#undef DfltAssertCpuSrvcGetStoredNodeNumber
+#undef DfltAssertCpuSrvcCoreIdPositionInInitialApicId
+#undef DfltAssertCpuSrvcSaveFeatures
+#undef DfltAssertCpuSrvcWriteFeatures
+#undef DfltAssertCpuSrvcSetWarmResetFlag
+#undef DfltAssertCpuSrvcGetWarmResetFlag
+#undef DfltAssertCpuSrvcGetBrandString1
+#undef DfltAssertCpuSrvcGetBrandString2
+#undef DfltAssertCpuSrvcGetMicroCodePatchesStruct
+#undef DfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+#undef DfltAssertCpuSrvcGetCacheInfo
+#undef DfltAssertCpuSrvcGetSysPmTableStruct
+#undef DfltAssertCpuSrvcGetWheaInitData
+#undef DfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+#undef DfltAssertCpuSrvcIsNbPstateEnabled
+#undef DfltAssertCpuSrvcNextLinkHasHtPhyFeats
+#undef DfltAssertCpuSrvcSetHtPhyRegister
+#undef DfltAssertCpuSrvcGetNextHtLinkFeatures
+#undef DfltAssertCpuSrvcRegisterTableList
+#undef DfltAssertCpuSrvcTableEntryTypeDescriptors
+#undef DfltAssertCpuSrvcPackageLinkMap
+#undef DfltAssertCpuSrvcComputeUnitMap
+#undef DfltAssertCpuSrvcInitCacheDisabled
+#undef DfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef DfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef DfltAssertCpuSrvcPatchLoaderIsSharedByCU
+
+#undef OvrdDfltCpuSrvcRevision
+#undef OvrdDfltCpuSrvcDisablePstate
+#undef OvrdDfltCpuSrvcTransitionPstate
+#undef OvrdDfltCpuSrvcGetProcIddMax
+#undef OvrdDfltCpuSrvcGetTscRate
+#undef OvrdDfltCpuSrvcGetCurrentNbFrequency
+#undef OvrdDfltCpuSrvcGetMinMaxNbFrequency
+#undef OvrdDfltCpuSrvcGetNbPstateInfo
+#undef OvrdDfltCpuSrvcIsNbCofInitNeeded
+#undef OvrdDfltCpuSrvcGetNbIddMax
+#undef OvrdDfltCpuSrvcLaunchApCore
+#undef OvrdDfltCpuSrvcGetNumberOfPhysicalCores
+#undef OvrdDfltCpuSrvcGetApMailboxFromHardware
+#undef OvrdDfltCpuSrvcSetApCoreNumber
+#undef OvrdDfltCpuSrvcGetApCoreNumber
+#undef OvrdDfltCpuSrvcTransferApCoreNumber
+#undef OvrdDfltCpuSrvcGetStoredNodeNumber
+#undef OvrdDfltCpuSrvcCoreIdPositionInInitialApicId
+#undef OvrdDfltCpuSrvcSaveFeatures
+#undef OvrdDfltCpuSrvcWriteFeatures
+#undef OvrdDfltCpuSrvcSetWarmResetFlag
+#undef OvrdDfltCpuSrvcGetWarmResetFlag
+#undef OvrdDfltCpuSrvcGetBrandString1
+#undef OvrdDfltCpuSrvcGetBrandString2
+#undef OvrdDfltCpuSrvcGetMicroCodePatchesStruct
+#undef OvrdDfltCpuSrvcGetMicrocodeEquivalenceTable
+#undef OvrdDfltCpuSrvcGetCacheInfo
+#undef OvrdDfltCpuSrvcGetSysPmTableStruct
+#undef OvrdDfltCpuSrvcGetWheaInitData
+#undef OvrdDfltCpuSrvcGetPlatformTypeSpecificInfo
+#undef OvrdDfltCpuSrvcIsNbPstateEnabled
+#undef OvrdDfltCpuSrvcNextLinkHasHtPhyFeats
+#undef OvrdDfltCpuSrvcSetHtPhyRegister
+#undef OvrdDfltCpuSrvcGetNextHtLinkFeatures
+#undef OvrdDfltCpuSrvcRegisterTableList
+#undef OvrdDfltCpuSrvcTableEntryTypeDescriptors
+#undef OvrdDfltCpuSrvcPackageLinkMap
+#undef OvrdDfltCpuSrvcComputeUnitMap
+#undef OvrdDfltCpuSrvcInitCacheDisabled
+#undef OvrdDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef OvrdDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef OvrdDfltCpuSrvcPatchLoaderIsSharedByCU
+
+#undef OvrdDfltAssertCpuSrvcRevision
+#undef OvrdDfltAssertCpuSrvcDisablePstate
+#undef OvrdDfltAssertCpuSrvcTransitionPstate
+#undef OvrdDfltAssertCpuSrvcGetProcIddMax
+#undef OvrdDfltAssertCpuSrvcGetTscRate
+#undef OvrdDfltAssertCpuSrvcGetCurrentNbFrequency
+#undef OvrdDfltAssertCpuSrvcGetMinMaxNbFrequency
+#undef OvrdDfltAssertCpuSrvcGetNbPstateInfo
+#undef OvrdDfltAssertCpuSrvcIsNbCofInitNeeded
+#undef OvrdDfltAssertCpuSrvcGetNbIddMax
+#undef OvrdDfltAssertCpuSrvcLaunchApCore
+#undef OvrdDfltAssertCpuSrvcGetNumberOfPhysicalCores
+#undef OvrdDfltAssertCpuSrvcGetApMailboxFromHardware
+#undef OvrdDfltAssertCpuSrvcSetApCoreNumber
+#undef OvrdDfltAssertCpuSrvcGetApCoreNumber
+#undef OvrdDfltAssertCpuSrvcTransferApCoreNumber
+#undef OvrdDfltAssertCpuSrvcGetStoredNodeNumber
+#undef OvrdDfltAssertCpuSrvcCoreIdPositionInInitialApicId
+#undef OvrdDfltAssertCpuSrvcSaveFeatures
+#undef OvrdDfltAssertCpuSrvcWriteFeatures
+#undef OvrdDfltAssertCpuSrvcSetWarmResetFlag
+#undef OvrdDfltAssertCpuSrvcGetWarmResetFlag
+#undef OvrdDfltAssertCpuSrvcGetBrandString1
+#undef OvrdDfltAssertCpuSrvcGetBrandString2
+#undef OvrdDfltAssertCpuSrvcGetMicroCodePatchesStruct
+#undef OvrdDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+#undef OvrdDfltAssertCpuSrvcGetCacheInfo
+#undef OvrdDfltAssertCpuSrvcGetSysPmTableStruct
+#undef OvrdDfltAssertCpuSrvcGetWheaInitData
+#undef OvrdDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+#undef OvrdDfltAssertCpuSrvcIsNbPstateEnabled
+#undef OvrdDfltAssertCpuSrvcNextLinkHasHtPhyFeats
+#undef OvrdDfltAssertCpuSrvcSetHtPhyRegister
+#undef OvrdDfltAssertCpuSrvcGetNextHtLinkFeatures
+#undef OvrdDfltAssertCpuSrvcRegisterTableList
+#undef OvrdDfltAssertCpuSrvcTableEntryTypeDescriptors
+#undef OvrdDfltAssertCpuSrvcPackageLinkMap
+#undef OvrdDfltAssertCpuSrvcComputeUnitMap
+#undef OvrdDfltAssertCpuSrvcInitCacheDisabled
+#undef OvrdDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef OvrdDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef OvrdDfltAssertCpuSrvcPatchLoaderIsSharedByCU
+
+#undef FinalDfltCpuSrvcRevision
+#undef FinalDfltCpuSrvcDisablePstate
+#undef FinalDfltCpuSrvcTransitionPstate
+#undef FinalDfltCpuSrvcGetProcIddMax
+#undef FinalDfltCpuSrvcGetTscRate
+#undef FinalDfltCpuSrvcGetCurrentNbFrequency
+#undef FinalDfltCpuSrvcGetMinMaxNbFrequency
+#undef FinalDfltCpuSrvcGetNbPstateInfo
+#undef FinalDfltCpuSrvcIsNbCofInitNeeded
+#undef FinalDfltCpuSrvcGetNbIddMax
+#undef FinalDfltCpuSrvcLaunchApCore
+#undef FinalDfltCpuSrvcGetNumberOfPhysicalCores
+#undef FinalDfltCpuSrvcGetApMailboxFromHardware
+#undef FinalDfltCpuSrvcSetApCoreNumber
+#undef FinalDfltCpuSrvcGetApCoreNumber
+#undef FinalDfltCpuSrvcTransferApCoreNumber
+#undef FinalDfltCpuSrvcGetStoredNodeNumber
+#undef FinalDfltCpuSrvcCoreIdPositionInInitialApicId
+#undef FinalDfltCpuSrvcSaveFeatures
+#undef FinalDfltCpuSrvcWriteFeatures
+#undef FinalDfltCpuSrvcSetWarmResetFlag
+#undef FinalDfltCpuSrvcGetWarmResetFlag
+#undef FinalDfltCpuSrvcGetBrandString1
+#undef FinalDfltCpuSrvcGetBrandString2
+#undef FinalDfltCpuSrvcGetMicroCodePatchesStruct
+#undef FinalDfltCpuSrvcGetMicrocodeEquivalenceTable
+#undef FinalDfltCpuSrvcGetCacheInfo
+#undef FinalDfltCpuSrvcGetSysPmTableStruct
+#undef FinalDfltCpuSrvcGetWheaInitData
+#undef FinalDfltCpuSrvcGetPlatformTypeSpecificInfo
+#undef FinalDfltCpuSrvcIsNbPstateEnabled
+#undef FinalDfltCpuSrvcNextLinkHasHtPhyFeats
+#undef FinalDfltCpuSrvcSetHtPhyRegister
+#undef FinalDfltCpuSrvcGetNextHtLinkFeatures
+#undef FinalDfltCpuSrvcRegisterTableList
+#undef FinalDfltCpuSrvcTableEntryTypeDescriptors
+#undef FinalDfltCpuSrvcPackageLinkMap
+#undef FinalDfltCpuSrvcComputeUnitMap
+#undef FinalDfltCpuSrvcInitCacheDisabled
+#undef FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef FinalDfltCpuSrvcPatchLoaderIsSharedByCU
+
+#undef FinalDfltAssertCpuSrvcRevision
+#undef FinalDfltAssertCpuSrvcDisablePstate
+#undef FinalDfltAssertCpuSrvcTransitionPstate
+#undef FinalDfltAssertCpuSrvcGetProcIddMax
+#undef FinalDfltAssertCpuSrvcGetTscRate
+#undef FinalDfltAssertCpuSrvcGetCurrentNbFrequency
+#undef FinalDfltAssertCpuSrvcGetMinMaxNbFrequency
+#undef FinalDfltAssertCpuSrvcGetNbPstateInfo
+#undef FinalDfltAssertCpuSrvcIsNbCofInitNeeded
+#undef FinalDfltAssertCpuSrvcGetNbIddMax
+#undef FinalDfltAssertCpuSrvcLaunchApCore
+#undef FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores
+#undef FinalDfltAssertCpuSrvcGetApMailboxFromHardware
+#undef FinalDfltAssertCpuSrvcSetApCoreNumber
+#undef FinalDfltAssertCpuSrvcGetApCoreNumber
+#undef FinalDfltAssertCpuSrvcTransferApCoreNumber
+#undef FinalDfltAssertCpuSrvcGetStoredNodeNumber
+#undef FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId
+#undef FinalDfltAssertCpuSrvcSaveFeatures
+#undef FinalDfltAssertCpuSrvcWriteFeatures
+#undef FinalDfltAssertCpuSrvcSetWarmResetFlag
+#undef FinalDfltAssertCpuSrvcGetWarmResetFlag
+#undef FinalDfltAssertCpuSrvcGetBrandString1
+#undef FinalDfltAssertCpuSrvcGetBrandString2
+#undef FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct
+#undef FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
+#undef FinalDfltAssertCpuSrvcGetCacheInfo
+#undef FinalDfltAssertCpuSrvcGetSysPmTableStruct
+#undef FinalDfltAssertCpuSrvcGetWheaInitData
+#undef FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
+#undef FinalDfltAssertCpuSrvcIsNbPstateEnabled
+#undef FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats
+#undef FinalDfltAssertCpuSrvcSetHtPhyRegister
+#undef FinalDfltAssertCpuSrvcGetNextHtLinkFeatures
+#undef FinalDfltAssertCpuSrvcRegisterTableList
+#undef FinalDfltAssertCpuSrvcTableEntryTypeDescriptors
+#undef FinalDfltAssertCpuSrvcPackageLinkMap
+#undef FinalDfltAssertCpuSrvcComputeUnitMap
+#undef FinalDfltAssertCpuSrvcInitCacheDisabled
+#undef FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU
+
+#undef FinalCpuSrvcRevision
+#undef FinalCpuSrvcDisablePstate
+#undef FinalCpuSrvcTransitionPstate
+#undef FinalCpuSrvcGetProcIddMax
+#undef FinalCpuSrvcGetTscRate
+#undef FinalCpuSrvcGetCurrentNbFrequency
+#undef FinalCpuSrvcGetMinMaxNbFrequency
+#undef FinalCpuSrvcGetNbPstateInfo
+#undef FinalCpuSrvcIsNbCofInitNeeded
+#undef FinalCpuSrvcGetNbIddMax
+#undef FinalCpuSrvcLaunchApCore
+#undef FinalCpuSrvcGetNumberOfPhysicalCores
+#undef FinalCpuSrvcGetApMailboxFromHardware
+#undef FinalCpuSrvcSetApCoreNumber
+#undef FinalCpuSrvcGetApCoreNumber
+#undef FinalCpuSrvcTransferApCoreNumber
+#undef FinalCpuSrvcGetStoredNodeNumber
+#undef FinalCpuSrvcCoreIdPositionInInitialApicId
+#undef FinalCpuSrvcSaveFeatures
+#undef FinalCpuSrvcWriteFeatures
+#undef FinalCpuSrvcSetWarmResetFlag
+#undef FinalCpuSrvcGetWarmResetFlag
+#undef FinalCpuSrvcGetBrandString1
+#undef FinalCpuSrvcGetBrandString2
+#undef FinalCpuSrvcGetMicroCodePatchesStruct
+#undef FinalCpuSrvcGetMicrocodeEquivalenceTable
+#undef FinalCpuSrvcGetCacheInfo
+#undef FinalCpuSrvcGetSysPmTableStruct
+#undef FinalCpuSrvcGetWheaInitData
+#undef FinalCpuSrvcGetPlatformTypeSpecificInfo
+#undef FinalCpuSrvcIsNbPstateEnabled
+#undef FinalCpuSrvcNextLinkHasHtPhyFeats
+#undef FinalCpuSrvcSetHtPhyRegister
+#undef FinalCpuSrvcGetNextHtLinkFeatures
+#undef FinalCpuSrvcRegisterTableList
+#undef FinalCpuSrvcTableEntryTypeDescriptors
+#undef FinalCpuSrvcPackageLinkMap
+#undef FinalCpuSrvcComputeUnitMap
+#undef FinalCpuSrvcInitCacheDisabled
+#undef FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#undef FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#undef FinalCpuSrvcPatchLoaderIsSharedByCU
+
+//
+// Define null CPU specific services - no redefinition is expected.
+//
+#define NullCpuSrvcRevision                                   (UINT16)                                      0
+#define NullCpuSrvcDisablePstate                              (PF_CPU_DISABLE_PSTATE)                       CommonReturnAgesaSuccess
+#define NullCpuSrvcTransitionPstate                           (PF_CPU_TRANSITION_PSTATE)                    CommonReturnAgesaSuccess
+#define NullCpuSrvcGetProcIddMax                              (PF_CPU_GET_IDD_MAX)                          CommonReturnFalse
+#define NullCpuSrvcGetTscRate                                 (PF_CPU_GET_TSC_RATE)                         CommonReturnAgesaSuccess
+#define NullCpuSrvcGetCurrentNbFrequency                      (PF_CPU_GET_NB_FREQ)                          CommonReturnAgesaError
+#define NullCpuSrvcGetMinMaxNbFrequency                       (PF_CPU_GET_MIN_MAX_NB_FREQ)                  CommonReturnAgesaError
+#define NullCpuSrvcGetNbPstateInfo                            (PF_CPU_GET_NB_PSTATE_INFO)                   CommonReturnFalse
+#define NullCpuSrvcIsNbCofInitNeeded                          (PF_CPU_IS_NBCOF_INIT_NEEDED)                 CommonReturnAgesaSuccess
+#define NullCpuSrvcGetNbIddMax                                (PF_CPU_GET_NB_IDD_MAX)                       CommonReturnFalse
+#define NullCpuSrvcLaunchApCore                               (PF_CPU_AP_INITIAL_LAUNCH)                    CommonReturnFalse
+#define NullCpuSrvcGetNumberOfPhysicalCores                   (PF_CPU_NUMBER_OF_PHYSICAL_CORES)             CommonReturnZero8
+#define NullCpuSrvcGetApMailboxFromHardware                   (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE)     CommonReturnAgesaSuccess
+#define NullCpuSrvcSetApCoreNumber                            (PF_CPU_SET_AP_CORE_NUMBER)                   CommonVoid
+#define NullCpuSrvcGetApCoreNumber                            (PF_CPU_GET_AP_CORE_NUMBER)                   CommonReturnOne32
+#define NullCpuSrvcTransferApCoreNumber                       (PF_CPU_TRANSFER_AP_CORE_NUMBER)              CommonVoid
+#define NullCpuSrvcGetStoredNodeNumber                        (PF_CPU_GET_STORED_NODE_NUMBER)               CommonReturnZero32
+#define NullCpuSrvcCoreIdPositionInInitialApicId              (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID)      CommonReturnAgesaSuccess
+#define NullCpuSrvcSaveFeatures                               (PF_CPU_SAVE_FEATURES)                        CommonVoid
+#define NullCpuSrvcWriteFeatures                              (PF_CPU_WRITE_FEATURES)                       CommonVoid
+#define NullCpuSrvcSetWarmResetFlag                           (PF_CPU_SET_WARM_RESET_FLAG)                  CommonReturnAgesaSuccess
+#define NullCpuSrvcGetWarmResetFlag                           (PF_CPU_GET_WARM_RESET_FLAG)                  CommonReturnAgesaSuccess
+#define NullCpuSrvcGetBrandString1                            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetBrandString2                            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetMicroCodePatchesStruct                  (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetMicrocodeEquivalenceTable               (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetCacheInfo                               (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetSysPmTableStruct                        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetWheaInitData                            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            GetEmptyArray
+#define NullCpuSrvcGetPlatformTypeSpecificInfo                (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO)      CommonReturnAgesaSuccess
+#define NullCpuSrvcIsNbPstateEnabled                          (PF_IS_NB_PSTATE_ENABLED)                     CommonReturnFalse
+#define NullCpuSrvcNextLinkHasHtPhyFeats                      (PF_NEXT_LINK_HAS_HTPHY_FEATS)                CommonReturnFalse
+#define NullCpuSrvcSetHtPhyRegister                           (PF_SET_HT_PHY_REGISTER)                      CommonVoid
+#define NullCpuSrvcGetNextHtLinkFeatures                      (PF_GET_NEXT_HT_LINK_FEATURES)                CommonVoid
+#define NullCpuSrvcRegisterTableList                          (REGISTER_TABLE **)                           NULL
+#define NullCpuSrvcTableEntryTypeDescriptors                  (TABLE_ENTRY_TYPE_DESCRIPTOR *)               NULL
+#define NullCpuSrvcPackageLinkMap                             (PACKAGE_HTLINK_MAP)                          NULL
+#define NullCpuSrvcComputeUnitMap                             (COMPUTE_UNIT_MAP *)                          NULL
+#define NullCpuSrvcInitCacheDisabled                          (FAMILY_CACHE_INIT_POLICY)                    InitCacheDisabled
+#define NullCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable      (PF_GET_EARLY_INIT_TABLE)                     CommonVoid
+#define NullCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable       (PF_GET_EARLY_INIT_TABLE)                     CommonVoid
+#define NullCpuSrvcPatchLoaderIsSharedByCU                    (BOOLEAN)                                     FALSE
+//
+// Define default cpu specific services assertion if possible
+//
+#define DfltAssertCpuSrvcRevision                             NullCpuSrvcRevision
+#define DfltAssertCpuSrvcDisablePstate                        (PF_CPU_DISABLE_PSTATE)                       CommonAssert
+#define DfltAssertCpuSrvcTransitionPstate                     (PF_CPU_TRANSITION_PSTATE)                    CommonAssert
+#define DfltAssertCpuSrvcGetProcIddMax                        (PF_CPU_GET_IDD_MAX)                          CommonAssert
+#define DfltAssertCpuSrvcGetTscRate                           (PF_CPU_GET_TSC_RATE)                         CommonAssert
+#define DfltAssertCpuSrvcGetCurrentNbFrequency                (PF_CPU_GET_NB_FREQ)                          CommonAssert
+#define DfltAssertCpuSrvcGetMinMaxNbFrequency                 (PF_CPU_GET_MIN_MAX_NB_FREQ)                  CommonAssert
+#define DfltAssertCpuSrvcGetNbPstateInfo                      (PF_CPU_GET_NB_PSTATE_INFO)                   CommonAssert
+#define DfltAssertCpuSrvcIsNbCofInitNeeded                    (PF_CPU_IS_NBCOF_INIT_NEEDED)                 CommonAssert
+#define DfltAssertCpuSrvcGetNbIddMax                          (PF_CPU_GET_NB_IDD_MAX)                       CommonAssert
+#define DfltAssertCpuSrvcLaunchApCore                         (PF_CPU_AP_INITIAL_LAUNCH)                    CommonAssert
+#define DfltAssertCpuSrvcGetNumberOfPhysicalCores             (PF_CPU_NUMBER_OF_PHYSICAL_CORES)             CommonAssert
+#define DfltAssertCpuSrvcGetApMailboxFromHardware             (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE)     CommonAssert
+#define DfltAssertCpuSrvcSetApCoreNumber                      (PF_CPU_SET_AP_CORE_NUMBER)                   CommonAssert
+#define DfltAssertCpuSrvcGetApCoreNumber                      (PF_CPU_GET_AP_CORE_NUMBER)                   CommonAssert
+#define DfltAssertCpuSrvcTransferApCoreNumber                 (PF_CPU_TRANSFER_AP_CORE_NUMBER)              CommonAssert
+#define DfltAssertCpuSrvcGetStoredNodeNumber                  (PF_CPU_GET_STORED_NODE_NUMBER)               CommonAssert
+#define DfltAssertCpuSrvcCoreIdPositionInInitialApicId        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID)      CommonAssert
+#define DfltAssertCpuSrvcSaveFeatures                         (PF_CPU_SAVE_FEATURES)                        CommonAssert
+#define DfltAssertCpuSrvcWriteFeatures                        (PF_CPU_WRITE_FEATURES)                       CommonAssert
+#define DfltAssertCpuSrvcSetWarmResetFlag                     (PF_CPU_SET_WARM_RESET_FLAG)                  CommonAssert
+#define DfltAssertCpuSrvcGetWarmResetFlag                     (PF_CPU_GET_WARM_RESET_FLAG)                  CommonAssert
+#define DfltAssertCpuSrvcGetBrandString1                      (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetBrandString2                      (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetMicroCodePatchesStruct            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetMicrocodeEquivalenceTable         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetCacheInfo                         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetSysPmTableStruct                  (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetWheaInitData                      (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)            CommonAssert
+#define DfltAssertCpuSrvcGetPlatformTypeSpecificInfo          (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO)      CommonAssert
+#define DfltAssertCpuSrvcIsNbPstateEnabled                    (PF_IS_NB_PSTATE_ENABLED)                     CommonAssert
+#define DfltAssertCpuSrvcNextLinkHasHtPhyFeats                (PF_NEXT_LINK_HAS_HTPHY_FEATS)                CommonAssert
+#define DfltAssertCpuSrvcSetHtPhyRegister                     (PF_SET_HT_PHY_REGISTER)                      CommonAssert
+#define DfltAssertCpuSrvcGetNextHtLinkFeatures                (PF_GET_NEXT_HT_LINK_FEATURES)                CommonAssert
+#define DfltAssertCpuSrvcRegisterTableList                    NullCpuSrvcRegisterTableList
+#define DfltAssertCpuSrvcTableEntryTypeDescriptors            NullCpuSrvcTableEntryTypeDescriptors
+#define DfltAssertCpuSrvcPackageLinkMap                       NullCpuSrvcPackageLinkMap
+#define DfltAssertCpuSrvcComputeUnitMap                       NullCpuSrvcComputeUnitMap
+#define DfltAssertCpuSrvcInitCacheDisabled                    (FAMILY_CACHE_INIT_POLICY)                    InitCacheDisabled
+#define DfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable (PF_GET_EARLY_INIT_TABLE)                    CommonAssert
+#define DfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable (PF_GET_EARLY_INIT_TABLE)                     CommonAssert
+#define DfltAssertCpuSrvcPatchLoaderIsSharedByCU              NullCpuSrvcPatchLoaderIsSharedByCU
+
+//
+// Define family specific services default when feature is enabled in the build
+//
+#define DfltCpuSrvcRevision                                   NullCpuSrvcRevision
+#define DfltCpuSrvcDisablePstate                              DfltAssertCpuSrvcDisablePstate
+#define DfltCpuSrvcTransitionPstate                           DfltAssertCpuSrvcTransitionPstate
+#define DfltCpuSrvcGetProcIddMax                              NullCpuSrvcGetProcIddMax
+#define DfltCpuSrvcGetTscRate                                 DfltAssertCpuSrvcGetTscRate
+#define DfltCpuSrvcGetCurrentNbFrequency                      DfltAssertCpuSrvcGetCurrentNbFrequency
+#define DfltCpuSrvcGetMinMaxNbFrequency                       NullCpuSrvcGetMinMaxNbFrequency
+#define DfltCpuSrvcGetNbPstateInfo                            NullCpuSrvcGetNbPstateInfo
+#define DfltCpuSrvcIsNbCofInitNeeded                          (PF_CPU_IS_NBCOF_INIT_NEEDED)                 CommonReturnFalse
+#define DfltCpuSrvcGetNbIddMax                                DfltAssertCpuSrvcGetNbIddMax
+#define DfltCpuSrvcLaunchApCore                               NullCpuSrvcLaunchApCore
+#define DfltCpuSrvcGetNumberOfPhysicalCores                   (PF_CPU_NUMBER_OF_PHYSICAL_CORES)             CommonReturnOne8
+#define DfltCpuSrvcGetApMailboxFromHardware                   DfltAssertCpuSrvcGetApMailboxFromHardware
+#define DfltCpuSrvcSetApCoreNumber                            NullCpuSrvcSetApCoreNumber
+#define DfltCpuSrvcGetApCoreNumber                            NullCpuSrvcGetApCoreNumber
+#define DfltCpuSrvcTransferApCoreNumber                       NullCpuSrvcTransferApCoreNumber
+#define DfltCpuSrvcGetStoredNodeNumber                        NullCpuSrvcGetStoredNodeNumber
+#define DfltCpuSrvcCoreIdPositionInInitialApicId              (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID)      CommonReturnOne32
+#define DfltCpuSrvcSaveFeatures                               NullCpuSrvcSaveFeatures
+#define DfltCpuSrvcWriteFeatures                              NullCpuSrvcWriteFeatures
+#define DfltCpuSrvcSetWarmResetFlag                           (PF_CPU_SET_WARM_RESET_FLAG)                  CommonVoid
+#define DfltCpuSrvcGetWarmResetFlag                           DfltAssertCpuSrvcGetWarmResetFlag
+#define DfltCpuSrvcGetBrandString1                            NullCpuSrvcGetBrandString1
+#define DfltCpuSrvcGetBrandString2                            NullCpuSrvcGetBrandString2
+#define DfltCpuSrvcGetMicroCodePatchesStruct                  NullCpuSrvcGetMicroCodePatchesStruct
+#define DfltCpuSrvcGetMicrocodeEquivalenceTable               NullCpuSrvcGetMicrocodeEquivalenceTable
+#define DfltCpuSrvcGetCacheInfo                               NullCpuSrvcGetCacheInfo
+#define DfltCpuSrvcGetSysPmTableStruct                        NullCpuSrvcGetSysPmTableStruct
+#define DfltCpuSrvcGetWheaInitData                            NullCpuSrvcGetWheaInitData
+#define DfltCpuSrvcGetPlatformTypeSpecificInfo                NullCpuSrvcGetPlatformTypeSpecificInfo
+#define DfltCpuSrvcIsNbPstateEnabled                          NullCpuSrvcIsNbPstateEnabled
+#define DfltCpuSrvcNextLinkHasHtPhyFeats                      NullCpuSrvcNextLinkHasHtPhyFeats
+#define DfltCpuSrvcSetHtPhyRegister                           NullCpuSrvcSetHtPhyRegister
+#define DfltCpuSrvcGetNextHtLinkFeatures                      (PF_GET_NEXT_HT_LINK_FEATURES)                CommonReturnFalse
+#define DfltCpuSrvcRegisterTableList                          NullCpuSrvcRegisterTableList
+#define DfltCpuSrvcTableEntryTypeDescriptors                  NullCpuSrvcTableEntryTypeDescriptors
+#define DfltCpuSrvcPackageLinkMap                             NullCpuSrvcPackageLinkMap
+#define DfltCpuSrvcComputeUnitMap                             NullCpuSrvcComputeUnitMap
+// NOTE: From CPUs with compute units and moving forward, we use InitCacheEnabled.
+#define DfltCpuSrvcInitCacheDisabled                          (FAMILY_CACHE_INIT_POLICY)                    InitCacheEnabled
+#define DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable      NullCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
+#define DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable       NullCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
+#define DfltCpuSrvcPatchLoaderIsSharedByCU                    NullCpuSrvcPatchLoaderIsSharedByCU
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
new file mode 100644
index 0000000..db5588d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
@@ -0,0 +1,193 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CRAT option API.
+ *
+ * Contains structures and values used to control the CRAT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_CRAT_H_
+#define _OPTION_CRAT_H_
+
+#include "cpuLateInit.h"
+#include "cpuCrat.h"
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_CRAT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **CratPtr
+  );
+
+#define CRAT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of CRAT
+typedef struct  {
+  UINT16              OptCratVersion;       ///< The version number of CRAT
+  OPTION_CRAT_FEATURE  *CratFeature;        ///< The Option Feature of CRAT
+  UINT8               OemIdString[6];       ///< Configurable OEM Id
+  UINT8               OemTableIdString[8];  ///< Configurable OEM Table Id
+} OPTION_CRAT_CONFIGURATION;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to generat CRAT cache affinity structure.
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ *
+ */
+
+typedef VOID F_GENERATE_CRAT_CACHE (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_GENERATE_CRAT_CACHE         *PF_GENERATE_CRAT_CACHE;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to generat CRAT TLB affinity structure.
+ *
+ *    @param[in]      CratHeaderStructPtr  CRAT header pointer
+ *    @param[in, out] TableEnd             The end of CRAT
+ *    @param[in, out] StdHeader            Standard Head Pointer
+ *
+ *
+ */
+
+typedef VOID F_GENERATE_CRAT_TLB (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_GENERATE_CRAT_TLB         *PF_GENERATE_CRAT_TLB;
+
+/**
+ * Provide the interface to the CRAT Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+typedef struct _CRAT_FAMILY_SERVICES {
+  UINT16          Revision;                                        ///< Interface version
+  // Public Methods.
+  PF_GENERATE_CRAT_CACHE   generateCratCacheEntry;                 ///< Method: Family specific call to generat CRAT cache affinity structure
+  PF_GENERATE_CRAT_TLB     generateCratTLBEntry;                   ///< Method: Family specific call to generat CRAT TLB affinity structure
+
+} CRAT_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+MakeHSAProcUnitEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MakeMemoryEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MakeCacheEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MakeTLBEntry (
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// @todo
+//VOID
+//MakeFPUEntry (
+//  IN       CRAT_HEADER *CratHeaderStructPtr,
+//  IN OUT   UINT8       **TableEnd,
+//  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+//  );
+
+/// @todo
+//VOID
+//MakeIOEntry (
+//  IN       CRAT_HEADER *CratHeaderStructPtr,
+//  IN OUT   UINT8       **TableEnd,
+//  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+//  );
+
+UINT8 *
+AddOneCratEntry (
+  IN       CRAT_ENTRY_TYPE CratEntryType,
+  IN       CRAT_HEADER *CratHeaderStructPtr,
+  IN OUT   UINT8       **TableEnd,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _OPTION_CRAT_H_
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
new file mode 100644
index 0000000..2b47e15
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
@@ -0,0 +1,127 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CRAT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CRAT_INSTALL_H_
+#define _OPTION_CRAT_INSTALL_H_
+
+OPTION_CRAT_FEATURE          GetAcpiCratStub;
+#define USER_CRAT_OPTION     &GetAcpiCratStub
+
+#define F15_CRAT_SUPPORT
+#define F16_CRAT_SUPPORT
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_CRAT
+    #error  BLDOPT: Option not defined: "OPTION_CRAT"
+  #endif
+  #if OPTION_CRAT == TRUE
+    OPTION_CRAT_FEATURE          GetAcpiCratMain;
+    #undef USER_CRAT_OPTION
+    #define USER_CRAT_OPTION     &GetAcpiCratMain
+    /*
+     * Family service start
+     */
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if ((OPTION_FAMILY15H_TN == TRUE)
+          extern CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport;
+          #undef F15_CRAT_SUPPORT
+          #define F15_CRAT_SUPPORT {AMD_FAMILY_15, &F15CratSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        extern CONST CRAT_FAMILY_SERVICES ROMDATA F16CratSupport;
+        #undef F16_CRAT_SUPPORT
+        #define F16_CRAT_SUPPORT {AMD_FAMILY_16, &F16CratSupport},
+      #endif
+    #endif
+    /*
+     * Family service end
+     */
+  #endif
+#endif
+
+/*  Declare the instance of the CRAT option configuration structure  */
+CONST OPTION_CRAT_CONFIGURATION ROMDATA OptionCratConfiguration = {
+  CRAT_STRUCT_VERSION,
+  USER_CRAT_OPTION,
+  {CFG_ACPI_SET_OEM_ID},
+  {CFG_ACPI_SET_OEM_TABLE_ID}
+};
+
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CratFamilyServiceArray[] =
+{
+  F16_CRAT_SUPPORT
+  F15_CRAT_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CratFamilyServiceTable =
+{
+  (sizeof (CratFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CratFamilyServiceArray[0]
+};
+
+
+/// All entries that CRAT needs
+CONST S_MAKE_CRAT_ENTRY ROMDATA MakeCratEntryTable[] =
+{
+  {MakeHSAProcUnitEntry},
+  {MakeMemoryEntry},
+  {MakeCacheEntry},
+  {MakeTLBEntry},
+  /// @todo
+  //MakeFPUEntry,
+  //MakeIOEntry,
+  {NULL}
+};
+#endif  // _OPTION_CRAT_INSTALL_H_
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h
new file mode 100644
index 0000000..9fbc889
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI option API.
+ *
+ * Contains structures and values used to control the DMI option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_DMI_H_
+#define _OPTION_DMI_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_DMI_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   DMI_INFO             **DmiPtr
+  );
+
+typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define DMI_STRUCT_VERSION  0x01
+
+/// DMI option configuration. Determine the item of structure when compiling.
+typedef struct  {
+  UINT16              OptDmiVersion;      ///< Dmi version.
+  OPTION_DMI_FEATURE  *DmiFeature;        ///< Feature main routine, otherwise dummy.
+  OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
+  UINT16              NumEntries;         ///< Number of entry.
+  VOID                *((*FamilyList)[]); ///< Family service.
+} OPTION_DMI_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
new file mode 100644
index 0000000..ce8ef06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
@@ -0,0 +1,125 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: DMI
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_DMI_INSTALL_H_
+#define _OPTION_DMI_INSTALL_H_
+
+#include "cpuLateInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+OPTION_DMI_FEATURE                  GetDmiInfoStub;
+OPTION_DMI_RELEASE_BUFFER           ReleaseDmiBufferStub;
+#define USER_DMI_OPTION             GetDmiInfoStub
+#define USER_DMI_RELEASE_BUFFER     ReleaseDmiBufferStub
+#define CPU_DMI_AP_GET_TYPE4_TYPE7
+
+#define  FAM15_TN_DMI_TABLE
+#define  FAM16_KB_DMI_TABLE
+
+#ifndef OPTION_DMI
+  #error  BLDOPT: Option not defined: "OPTION_DMI"
+#endif
+
+#if OPTION_DMI == TRUE
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    OPTION_DMI_FEATURE          GetDmiInfoMain;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
+    #undef USER_DMI_OPTION
+    #define USER_DMI_OPTION     &GetDmiInfoMain
+    #undef USER_DMI_RELEASE_BUFFER
+    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
+
+    // This additional check keeps AP launch routines from being unnecessarily included
+    // in single socket systems.
+    #if OPTION_MULTISOCKET == TRUE
+      #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+      #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+      #undef CPU_DMI_AP_GET_TYPE4_TYPE7
+      #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
+    #endif
+
+    // Family 15
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
+          #undef FAM15_TN_DMI_TABLE
+          #define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
+        #endif
+      #endif
+    #endif
+
+    // Family 16
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        #if OPTION_FAMILY16H_KB
+          extern PROC_FAMILY_TABLE ProcFamily16KbDmiTable;
+          #undef FAM16_KB_DMI_TABLE
+          #define FAM16_KB_DMI_TABLE &ProcFamily16KbDmiTable,
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+/*  Declare the Family List. An array of pointers to tables that each describe a family  */
+CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
+  FAM15_TN_DMI_TABLE
+  FAM16_KB_DMI_TABLE
+  NULL
+};
+
+/*  Declare the instance of the DMI option configuration structure  */
+CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
+  DMI_STRUCT_VERSION,
+  USER_DMI_OPTION,
+  USER_DMI_RELEASE_BUFFER,
+  ((sizeof (ProcTables) / sizeof (PROC_FAMILY_TABLE *)) - 1),  // Including 'NULL' in above ProcTables would
+                                        // cause one more entry is counted.
+  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
+};
+
+#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hEarlySample.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hEarlySample.h
new file mode 100644
index 0000000..2c424c0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hEarlySample.h
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family 16h 'early sample' support
+ *
+ * This file defines the required structures for family 16h pre-production processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_16H_EARLY_SAMPLE_H_
+#define _OPTION_FAMILY_16H_EARLY_SAMPLE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*
+ * Install family 16h model 0x00 - 0x0F Early Sample support
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_FAMILY_16H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h
new file mode 100644
index 0000000..92dae54
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h
@@ -0,0 +1,332 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 16h support
+ *
+ * This file generates the defaults tables for family 16h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 87264 $   @e \$Date: 2013-01-31 09:26:23 -0600 (Thu, 31 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_16H_INSTALL_H_
+#define _OPTION_FAMILY_16H_INSTALL_H_
+
+#include "OptionFamily16hEarlySample.h"
+#include "cpuFamilyTranslation.h"
+
+
+/*
+ * Pull in family specific services based on entry point
+ */
+
+/*
+ * Common Family 16h routines
+ */
+
+/*
+ * Install family 16h model 00h - 0Fh support
+ */
+#ifdef OPTION_FAMILY16H_KB
+  #if OPTION_FAMILY16H_KB == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableBeforeApLaunch;
+    extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableAfterApLaunch;
+    extern CONST REGISTER_TABLE ROMDATA F16KbPciWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F16KbMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable;
+
+    /**
+     * Compute unit and Compute unit primary determination table.
+     *
+     * The four fields from the compute unit status hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST COMPUTE_UNIT_MAP ROMDATA HtFam16KbComputeUnitMapping[] =
+    {
+      {1, 'x', 'x', 1, QuadCoresMapping},                            ///< 1 Compute Unit with 4 Cores
+      {1, 'x',  1,  0, TripleCoresMapping},                          ///< 1 Compute Unit with 3 Cores
+      {1,  1,   0,  0, EvenCoresMapping},                            ///< 1 Compute Unit with 2 cores
+      {1,  0,   0,  0, AllCoresMapping},                             ///< 1 Compute Unit with 1 Cores
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F16KbRegisterTables[] =
+      {
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F16KbPciRegisterTableBeforeApLaunch,
+          &F16KbPciRegisterTableAfterApLaunch,
+          &F16KbPciWorkaroundTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F16KbMsrRegisterTable,
+          &F16KbMsrWorkaroundTable,
+          &F16KbSharedMsrRegisterTable,
+          &F16KbSharedMsrWorkaroundTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16KbTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    /**
+     * Early Init Tables
+     *
+     */
+    extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesBeforeApLaunch;
+    extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAfterApLaunch;
+    extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly;
+    extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+    extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
+
+    CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] =
+    {
+      {SetRegistersFromTablesBeforeApLaunch, PERFORM_EARLY_ANY_CONDITION},
+      {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
+      #if OPTION_EARLY_SAMPLES == TRUE
+        {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
+      #endif
+      {NULL, 0}
+    };
+
+    CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitAfterApLaunchOnCoreTable[] =
+    {
+      {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION},
+      {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
+      #if OPTION_EARLY_SAMPLES == FALSE
+        {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
+      #endif
+      {NULL, 0}
+    };
+
+    #include "OptionCpuSpecificServicesInstallReset.h"
+    #define CpuSrvcTableName                            cpuF16KbServices
+
+    #define CpuSrvcDisablePstate                        F16DisablePstate
+    #define CpuSrvcTransitionPstate                     F16TransitionPstate
+    #define CpuSrvcGetProcIddMax                        F16KbGetProcIddMax
+    #define CpuSrvcGetTscRate                           F16GetTscRate
+    #define CpuSrvcGetCurrentNbFrequency                F16KbGetCurrentNbFrequency
+    #define CpuSrvcGetMinMaxNbFrequency                 F16KbGetMinMaxNbFrequency
+    #define CpuSrvcGetNbPstateInfo                      F16KbGetNbPstateInfo
+    #define CpuSrvcIsNbCofInitNeeded                    F16GetNbCofVidUpdate
+    #define CpuSrvcGetNbIddMax                          F16KbGetNbIddMax
+    #define CpuSrvcLaunchApCore                         F16LaunchApCore
+    #define CpuSrvcGetNumberOfPhysicalCores             F16KbGetNumberOfPhysicalCores
+    #define CpuSrvcGetApMailboxFromHardware             F16KbGetApMailboxFromHardware
+    #define CpuSrvcGetApCoreNumber                      F16KbGetApCoreNumber
+    #define CpuSrvcCoreIdPositionInInitialApicId        F16CpuAmdCoreIdPositionInInitialApicId
+    #define CpuSrvcSetWarmResetFlag                     F16SetAgesaWarmResetFlag
+    #define CpuSrvcGetWarmResetFlag                     F16GetAgesaWarmResetFlag
+    #define CpuSrvcGetMicroCodePatchesStruct            GetF16KbMicroCodePatchesStruct
+    #define CpuSrvcGetMicrocodeEquivalenceTable         GetF16KbMicrocodeEquivalenceTable
+    #define CpuSrvcGetCacheInfo                         GetF16CacheInfo
+    #define CpuSrvcGetSysPmTableStruct                  GetF16KbSysPmTable
+    #define CpuSrvcGetWheaInitData                      GetF16WheaInitData
+    #define CpuSrvcIsNbPstateEnabled                    F16KbIsNbPstateEnabled
+    #define CpuSrvcRegisterTableList                    (REGISTER_TABLE **) F16KbRegisterTables
+    #define CpuSrvcTableEntryTypeDescriptors            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16KbTableEntryTypeDescriptors
+    #define CpuSrvcComputeUnitMap                       (COMPUTE_UNIT_MAP *) &HtFam16KbComputeUnitMapping
+    #define CpuSrvcInitCacheDisabled                    InitCacheEnabled
+    #define CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable GetF16KbEarlyInitBeforeApLaunchOnCoreTable
+    #define CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable GetF16KbEarlyInitAfterApLaunchOnCoreTable
+    #define CpuSrvcPatchLoaderIsSharedByCU              FALSE
+
+    #include "OptionCpuSpecificServicesInstall.h"
+    INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
+
+    #define KB_SOCKETS 1
+    #define KB_MODULES 1
+    #define KB_RECOVERY_SOCKETS 1
+    #define KB_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF16KbLogicalIdAndRev;
+    #define OPT_F16_KB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF16KbLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < KB_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES KB_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < KB_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES KB_MODULES
+      #endif
+    #endif
+
+    #if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
+      #define F16_KB_UCODE_002A
+      #define F16_KB_UCODE_0106
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+        #endif
+        extern  CONST UINT8 ROMDATA  arr1[];
+        #undef F16_KB_UCODE_002A
+        #define F16_KB_UCODE_002A arr1,
+
+        extern  CONST UINT8 ROMDATA  arr2[];
+        #undef F16_KB_UCODE_0106
+        #define F16_KB_UCODE_0106 arr2,
+      #endif
+
+      CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] =
+      {
+        F16_KB_UCODE_0106
+        F16_KB_UCODE_002A
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF16KbMicroCodePatchArray) / sizeof (CpuF16KbMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F16_KB_CPU {AMD_FAMILY_16_KB, &cpuF16KbServices},
+
+  #else  //  OPTION_FAMILY16H_KB == TRUE
+    #define OPT_F16_KB_CPU
+    #define OPT_F16_KB_ID
+  #endif  //  OPTION_FAMILY16H_KB == TRUE
+#else  //  defined (OPTION_FAMILY16H_KB)
+  #define OPT_F16_KB_CPU
+  #define OPT_F16_KB_ID
+#endif  //  defined (OPTION_FAMILY16H_KB)
+
+
+/*
+ * Install unknown family 16h support
+ */
+
+
+#if USES_REGISTER_TABLES == TRUE
+  extern CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable;
+  extern CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable;
+  CONST REGISTER_TABLE ROMDATA *F16UnknownRegisterTables[] =
+  {
+    &F16PciUnknownRegisterTable,
+    &F16MsrUnknownRegisterTable
+    // the end.
+  };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16UnknownTableEntryTypeDescriptors[] =
+  {
+    {MsrRegister, SetRegisterForMsrEntry},
+    {PciRegister, SetRegisterForPciEntry},
+    // End
+    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+  };
+#endif
+
+
+
+#include "OptionCpuSpecificServicesInstallReset.h"
+#define CpuSrvcTableName                            cpuF16UnknownServices
+
+#define CpuSrvcDisablePstate                        F16DisablePstate
+#define CpuSrvcTransitionPstate                     F16TransitionPstate
+#define CpuSrvcGetTscRate                           F16GetTscRate
+#define CpuSrvcLaunchApCore                         F16LaunchApCore
+#define CpuSrvcCoreIdPositionInInitialApicId        F16CpuAmdCoreIdPositionInInitialApicId
+#define CpuSrvcSetWarmResetFlag                     F16SetAgesaWarmResetFlag
+#define CpuSrvcGetWarmResetFlag                     F16GetAgesaWarmResetFlag
+#define CpuSrvcGetMicroCodePatchesStruct            GetEmptyArray
+#define CpuSrvcGetMicrocodeEquivalenceTable         GetEmptyArray
+#define CpuSrvcGetWheaInitData                      GetF16WheaInitData
+#define CpuSrvcIsNbPstateEnabled                    F16IsNbPstateEnabled
+#define CpuSrvcRegisterTableList                    (REGISTER_TABLE **) F16UnknownRegisterTables
+#define CpuSrvcTableEntryTypeDescriptors            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16UnknownTableEntryTypeDescriptors
+#define CpuSrvcInitCacheDisabled                    InitCacheEnabled
+#define CpuSrvcPatchLoaderIsSharedByCU              FALSE
+
+#include "OptionCpuSpecificServicesInstall.h"
+INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
+
+// Family 16h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
+
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
+
+  #undef  FAMILY_MMIO_BASE_MASK
+
+  #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
+
+#endif
+
+
+
+#undef OPT_F16_ID_TABLE
+
+#define OPT_F16_ID_TABLE {0x16, {AMD_FAMILY_16, AMD_F16_UNKNOWN}, F16LogicalIdTable, (sizeof (F16LogicalIdTable) / sizeof (F16LogicalIdTable[0]))},
+
+#define OPT_F16_UNKNOWN_CPU {AMD_FAMILY_16, &cpuF16UnknownServices},
+
+
+#undef OPT_F16_TABLE
+
+#define OPT_F16_TABLE   OPT_F16_KB_CPU OPT_F16_UNKNOWN_CPU
+
+
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F16LogicalIdTable[] =
+
+{
+
+  OPT_F16_KB_ID
+
+};
+
+
+#endif  // _OPTION_FAMILY_16H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h
new file mode 100644
index 0000000..4c927af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h
@@ -0,0 +1,1026 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 15h support
+ *
+ * This file generates the defaults tables for family 15h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*********************************************************************************
+;
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*********************************************************************************/
+
+#ifndef _OPTION_FCH_INSTALL_H_
+#define _OPTION_FCH_INSTALL_H_
+
+#include "AmdFch.h"
+
+#ifndef  FCH_SUPPORT
+  #define  FCH_SUPPORT   FALSE
+#endif
+
+
+/* ACPI block register offset definitions */
+#define PM1_STATUS_OFFSET              0x00
+#define PM1_ENABLE_OFFSET              0x02
+#define PM_CONTROL_OFFSET              0x04
+#define PM_TIMER_OFFSET                0x08
+#define CPU_CONTROL_OFFSET             0x10
+#define EVENT_STATUS_OFFSET            0x20
+#define EVENT_ENABLE_OFFSET            0x24
+
+
+#if  FCH_SUPPORT == TRUE
+  /*
+   * FCH subfunctions
+   */
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      extern FCH_TASK_ENTRY    FchInitResetHwAcpiP;
+      extern FCH_TASK_ENTRY    FchInitResetHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitResetAb;
+      extern FCH_TASK_ENTRY    FchInitResetSpi;
+      extern FCH_TASK_ENTRY    FchInitResetGec;
+      extern FCH_TASK_ENTRY    FchInitResetSata;
+      extern FCH_TASK_ENTRY    FchInitResetLpc;
+      extern FCH_TASK_ENTRY    FchInitResetPcib;
+      extern FCH_TASK_ENTRY    FchInitResetPcie;
+      extern FCH_TASK_ENTRY    FchInitResetGpp;
+      extern FCH_TASK_ENTRY    FchInitAllinoneGpp;
+      extern FCH_TASK_ENTRY    FchInitResetUsb;
+      extern FCH_TASK_ENTRY    FchInitResetEhci;
+      extern FCH_TASK_ENTRY    FchInitResetOhci;
+      extern FCH_TASK_ENTRY    FchInitResetXhci;
+      extern FCH_TASK_ENTRY    FchInitResetImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      extern FCH_TASK_ENTRY    FchInitEnvUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsb;
+      extern FCH_TASK_ENTRY    FchInitEnvAb;
+      extern FCH_TASK_ENTRY    FchInitEnvGpp;
+      extern FCH_TASK_ENTRY    FchInitEnvGppPhaseII;
+      extern FCH_TASK_ENTRY    FchInitEnvPcie;
+      extern FCH_TASK_ENTRY    FchInitEnvPcib;
+      extern FCH_TASK_ENTRY    FchInitEnvHwAcpiP;
+      extern FCH_TASK_ENTRY    FchInitEnvHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitEnvAbSpecial;
+      extern FCH_TASK_ENTRY    FchInitEnvSpi;
+      extern FCH_TASK_ENTRY    FchInitEnvGec;
+      extern FCH_TASK_ENTRY    FchInitEnvSata;
+      extern FCH_TASK_ENTRY    FchInitEnvIde;
+      extern FCH_TASK_ENTRY    FchInitEnvSd;
+      extern FCH_TASK_ENTRY    FchInitEnvIr;
+      extern FCH_TASK_ENTRY    FchInitEnvAzalia;
+      extern FCH_TASK_ENTRY    FchInitEnvHwm;
+      extern FCH_TASK_ENTRY    FchInitEnvImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      extern FCH_TASK_ENTRY    FchInitMidHwm;
+      extern FCH_TASK_ENTRY    FchInitMidAzalia;
+      extern FCH_TASK_ENTRY    FchInitMidGec;
+      extern FCH_TASK_ENTRY    FchInitMidSata;
+      extern FCH_TASK_ENTRY    FchInitMidIde;
+      extern FCH_TASK_ENTRY    FchInitMidAb;
+      extern FCH_TASK_ENTRY    FchInitMidUsb;
+      extern FCH_TASK_ENTRY    FchInitMidUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitMidUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitMidUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitMidImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      extern FCH_TASK_ENTRY    FchInitLateHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitLateSpi;
+      extern FCH_TASK_ENTRY    FchInitLateGec;
+      extern FCH_TASK_ENTRY    FchInitLateSata;
+      extern FCH_TASK_ENTRY    FchInitLateIde;
+      extern FCH_TASK_ENTRY    FchInitLatePcib;
+      extern FCH_TASK_ENTRY    FchInitLateAb;
+      extern FCH_TASK_ENTRY    FchInitLatePcie;
+      extern FCH_TASK_ENTRY    FchInitLateGpp;
+      extern FCH_TASK_ENTRY    FchInitLateUsb;
+      extern FCH_TASK_ENTRY    FchInitLateUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitLateUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitLateUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitLateImc;
+      extern FCH_TASK_ENTRY    FchInitLateAzalia;
+      extern FCH_TASK_ENTRY    FchInitLateHwm;
+    #endif
+  #endif
+
+  extern FCH_TASK_ENTRY    FchTaskDummy;
+  extern FCH_TASK_ENTRY    FchGppHotplugSmiCallback;
+  /* FCH Interface entries */
+  extern  FCH_INIT     CommonFchInitStub;
+
+  /* FCH Interface entries */
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      extern  FCH_INIT      FchInitReset;
+      extern  FCH_INIT      FchResetConstructor;
+
+      #define FP_FCH_INIT_RESET              &FchInitReset
+      #define FP_FCH_INIT_RESET_CONSTRUCT    &FchResetConstructor
+    #else
+      #define FP_FCH_INIT_RESET              &CommonFchInitStub
+      #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      extern  FCH_INIT      FchInitEnv;
+      extern  FCH_INIT      FchEnvConstructor;
+
+      #define FP_FCH_INIT_ENV                &FchInitEnv
+      #define FP_FCH_INIT_ENV_CONSTRUCT      &FchEnvConstructor
+    #else
+      #define FP_FCH_INIT_ENV                &CommonFchInitStub
+      #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      extern  FCH_INIT      FchInitMid;
+      extern  FCH_INIT      FchMidConstructor;
+
+      #define FP_FCH_INIT_MID                &FchInitMid
+      #define FP_FCH_INIT_MID_CONSTRUCT      &FchMidConstructor
+    #else
+      #define FP_FCH_INIT_MID                &CommonFchInitStub
+      #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      extern  FCH_INIT      FchInitLate;
+      extern  FCH_INIT      FchLateConstructor;
+
+      #define FP_FCH_INIT_LATE               &FchInitLate
+      #define FP_FCH_INIT_LATE_CONSTRUCT     &FchLateConstructor
+    #else
+      #define FP_FCH_INIT_LATE               &CommonFchInitStub
+      #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
+    #endif
+  #endif
+
+  /* FCH subcomponent build options */
+  #undef  FCH_NO_HWACPI_SUPPORT
+  #undef  FCH_NO_AB_SUPPORT
+  #undef  FCH_NO_SPI_SUPPORT
+  #undef  FCH_NO_GEC_SUPPORT
+  #undef  FCH_NO_SATA_SUPPORT
+  #undef  FCH_NO_IDE_SUPPORT
+  #undef  FCH_NO_LPC_SUPPORT
+  #undef  FCH_NO_PCIB_SUPPORT
+  #undef  FCH_NO_PCIE_SUPPORT
+  #undef  FCH_NO_GPP_SUPPORT
+  #undef  FCH_NO_USB_SUPPORT
+  #undef  FCH_NO_EHCI_SUPPORT
+  #undef  FCH_NO_OHCI_SUPPORT
+  #undef  FCH_NO_XHCI_SUPPORT
+  #undef  FCH_NO_IMC_SUPPORT
+  #undef  FCH_NO_SD_SUPPORT
+  #undef  FCH_NO_IR_SUPPORT
+  #undef  FCH_NO_AZALIA_SUPPORT
+  #undef  FCH_NO_HWM_SUPPORT
+
+  #define FCH_NO_GEC_SUPPORT        TRUE
+
+  // Following are determined by silicon characteristics
+  #if (FALSE)
+    #define FCH_NO_GPP_SUPPORT        TRUE
+    #define FCH_NO_PCIB_SUPPORT       TRUE
+    #define FCH_NO_PCIE_SUPPORT       TRUE
+
+    //#define FCH_NO_GEC_SUPPORT        TRUE
+  #elif (OPTION_FAMILY15H_TN == TRUE)
+    //#define FCH_NO_GEC_SUPPORT        TRUE
+  #elif (OPTION_FAMILY16H_MODEL_0x == TRUE)
+    #define FCH_NO_GPP_SUPPORT        TRUE
+    #define FCH_NO_PCIB_SUPPORT       TRUE
+    #define FCH_NO_PCIE_SUPPORT       TRUE
+  #else
+    #error FCH_SUPPORT: No chip type selected.
+  #endif
+
+
+  //
+  // Installable blocks depending on build switches
+  //
+  #ifndef FCH_NO_HWACPI_SUPPORT
+    #define BLOCK_HWACPI_SIZE           sizeof (FCH_ACPI)
+    #define InstallFchInitResetHwAcpiP  &FchInitResetHwAcpiP
+    #define InstallFchInitResetHwAcpi   &FchInitResetHwAcpi
+    #define InstallFchInitEnvHwAcpiP    &FchInitEnvHwAcpiP
+    #define InstallFchInitEnvHwAcpi     &FchInitEnvHwAcpi
+    #define InstallFchInitMidHwAcpi     &FchTaskDummy
+    #define InstallFchInitLateHwAcpi    &FchInitLateHwAcpi
+  #else
+    #define BLOCK_HWACPI_SIZE           0
+    #define InstallFchInitResetHwAcpiP  &FchTaskDummy
+    #define InstallFchInitResetHwAcpi   &FchTaskDummy
+    #define InstallFchInitEnvHwAcpi     &FchTaskDummy
+    #define InstallFchInitMidHwAcpi     &FchTaskDummy
+    #define InstallFchInitLateHwAcpi    &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_AB_SUPPORT
+    #define BLOCK_AB_SIZE               sizeof (FCH_AB)
+    #define InstallFchInitResetAb       &FchInitResetAb
+    #define InstallFchInitEnvAb         &FchInitEnvAb
+    #define InstallFchInitEnvAbS        &FchInitEnvAbSpecial
+    #define InstallFchInitMidAb         &FchInitMidAb
+    #define InstallFchInitLateAb        &FchInitLateAb
+  #else
+    #define BLOCK_AB_SIZE               0
+    #define InstallFchInitResetAb       &FchTaskDummy
+    #define InstallFchInitEnvAb         &FchTaskDummy
+    #define InstallFchInitEnvAbS        &FchTaskDummy
+    #define InstallFchInitMidAb         &FchTaskDummy
+    #define InstallFchInitLateAb        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_SPI_SUPPORT
+    #define BLOCK_SPI_SIZE              sizeof (FCH_SPI)
+    #define InstallFchInitResetSpi      &FchInitResetSpi
+    #define InstallFchInitEnvSpi        &FchInitEnvSpi
+    #define InstallFchInitMidSpi        &FchTaskDummy
+    #define InstallFchInitLateSpi       &FchInitLateSpi
+  #else
+    #define BLOCK_SPI_SIZE              0
+    #define InstallFchInitResetSpi      &FchTaskDummy
+    #define InstallFchInitEnvSpi        &FchTaskDummy
+    #define InstallFchInitMidSpi        &FchTaskDummy
+    #define InstallFchInitLateSpi       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_GEC_SUPPORT
+    #define BLOCK_GEC_SIZE              sizeof (FCH_GEC)
+    #define InstallFchInitResetGec      &FchInitResetGec
+    #define InstallFchInitEnvGec        &FchInitEnvGec
+    #define InstallFchInitMidGec        &FchInitMidGec
+    #define InstallFchInitLateGec       &FchInitLateGec
+  #else
+    #define BLOCK_GEC_SIZE              0
+    #define InstallFchInitResetGec      &FchTaskDummy
+    #define InstallFchInitEnvGec        &FchTaskDummy
+    #define InstallFchInitMidGec        &FchTaskDummy
+    #define InstallFchInitLateGec       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_SATA_SUPPORT
+    #define BLOCK_SATA_SIZE             sizeof (FCH_SATA)
+    #define InstallFchInitResetSata     &FchInitResetSata
+    #define InstallFchInitEnvSata       &FchInitEnvSata
+    #define InstallFchInitMidSata       &FchInitMidSata
+    #define InstallFchInitLateSata      &FchInitLateSata
+  #else
+    #define BLOCK_SATA_SIZE             0
+    #define InstallFchInitResetSata     &FchTaskDummy
+    #define InstallFchInitEnvSata       &FchTaskDummy
+    #define InstallFchInitMidSata       &FchTaskDummy
+    #define InstallFchInitLateSata      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IDE_SUPPORT
+    #define BLOCK_IDE_SIZE              sizeof (FCH_IDE)
+    #define InstallFchInitResetIde      &FchTaskDummy
+    #define InstallFchInitEnvIde        &FchInitEnvIde
+    #define InstallFchInitMidIde        &FchInitMidIde
+    #define InstallFchInitLateIde       &FchInitLateIde
+  #else
+    #define BLOCK_IDE_SIZE              0
+    #define InstallFchInitResetIde      &FchTaskDummy
+    #define InstallFchInitEnvIde        &FchTaskDummy
+    #define InstallFchInitMidIde        &FchTaskDummy
+    #define InstallFchInitLateIde       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_LPC_SUPPORT
+    #define BLOCK_LPC_SIZE              sizeof (FCH_LPC)
+    #define InstallFchInitResetLpc      &FchInitResetLpc
+    #define InstallFchInitEnvLpc        &FchTaskDummy
+    #define InstallFchInitMidLpc        &FchTaskDummy
+    #define InstallFchInitLateLpc       &FchTaskDummy
+  #else
+    #define BLOCK_LPC_SIZE              0
+    #define InstallFchInitResetLpc      &FchTaskDummy
+    #define InstallFchInitEnvLpc        &FchTaskDummy
+    #define InstallFchInitMidLpc        &FchTaskDummy
+    #define InstallFchInitLateLpc       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_PCIB_SUPPORT
+    #define BLOCK_PCIB_SIZE             sizeof (FCH_PCIB)
+    #define InstallFchInitResetPcib     &FchInitResetPcib
+    #define InstallFchInitEnvPcib       &FchInitEnvPcib
+    #define InstallFchInitMidPcib       &FchTaskDummy
+    #define InstallFchInitLatePcib      &FchInitLatePcib
+  #else
+    #define BLOCK_PCIB_SIZE             0
+    #define InstallFchInitResetPcib     &FchTaskDummy
+    #define InstallFchInitEnvPcib       &FchTaskDummy
+    #define InstallFchInitMidPcib       &FchTaskDummy
+    #define InstallFchInitLatePcib      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_PCIE_SUPPORT
+    #define InstallFchInitResetPcie     &FchInitResetPcie
+    #define InstallFchInitEnvPcie       &FchInitEnvPcie
+    #define InstallFchInitMidPcie       &FchTaskDummy
+    #define InstallFchInitLatePcie      &FchInitLatePcie
+  #else
+    #define InstallFchInitResetPcie     &FchTaskDummy
+    #define InstallFchInitEnvPcie       &FchTaskDummy
+    #define InstallFchInitMidPcie       &FchTaskDummy
+    #define InstallFchInitLatePcie      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_GPP_SUPPORT
+    #define BLOCK_GPP_SIZE              sizeof (FCH_GPP)
+    #define InstallFchInitResetGpp      &FchInitResetGpp
+    #define InstallFchInitAllinoneGPP   &FchTaskDummy
+    #define InstallFchInitEnvGpp        &FchInitEnvGpp
+    #define InstallFchInitEnvGppPhaseII &FchInitEnvGppPhaseII
+    #define InstallFchInitMidGpp        &FchTaskDummy
+    #define InstallFchInitLateGpp       &FchInitLateGpp
+    #define InstallHpSmiCallback        &FchGppHotplugSmiCallback
+  #else
+    #define BLOCK_GPP_SIZE              0
+    #define InstallFchInitResetGpp      &FchTaskDummy
+      #define InstallFchInitAllinoneGPP &FchTaskDummy
+    #define InstallFchInitEnvGpp        &FchTaskDummy
+    #define InstallFchInitEnvGppPhaseII &FchTaskDummy
+    #define InstallFchInitMidGpp        &FchTaskDummy
+    #define InstallFchInitLateGpp       &FchTaskDummy
+      #define InstallHpSmiCallback      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_USB_SUPPORT
+    #define BLOCK_USB_SIZE              sizeof (FCH_USB)
+    #define InstallFchInitResetUsb      &FchInitResetUsb
+    #define InstallFchInitEnvUsb        &FchInitEnvUsb
+    #define InstallFchInitMidUsb        &FchInitMidUsb
+    #define InstallFchInitLateUsb       &FchInitLateUsb
+  #else
+    #define BLOCK_USB_SIZE              0
+    #define InstallFchInitResetUsb      &FchTaskDummy
+    #define InstallFchInitEnvUsb        &FchTaskDummy
+    #define InstallFchInitMidUsb        &FchTaskDummy
+    #define InstallFchInitLateUsb       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_EHCI_SUPPORT
+    #define InstallFchInitResetUsbEhci  &FchInitResetEhci
+    #define InstallFchInitEnvUsbEhci    &FchInitEnvUsbEhci
+    #define InstallFchInitMidUsbEhci    &FchInitMidUsbEhci
+    #define InstallFchInitLateUsbEhci   &FchInitLateUsbEhci
+  #else
+    #define InstallFchInitResetUsbEhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbEhci    &FchTaskDummy
+    #define InstallFchInitMidUsbEhci    &FchTaskDummy
+    #define InstallFchInitLateUsbEhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_OHCI_SUPPORT
+    #define InstallFchInitResetUsbOhci  &FchInitResetOhci
+    #define InstallFchInitEnvUsbOhci    &FchInitEnvUsbOhci
+    #define InstallFchInitMidUsbOhci    &FchInitMidUsbOhci
+    #define InstallFchInitLateUsbOhci   &FchInitLateUsbOhci
+  #else
+    #define InstallFchInitResetUsbOhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbOhci    &FchTaskDummy
+    #define InstallFchInitMidUsbOhci    &FchTaskDummy
+    #define InstallFchInitLateUsbOhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_XHCI_SUPPORT
+    #define InstallFchInitResetUsbXhci  &FchInitResetXhci
+    #define InstallFchInitEnvUsbXhci    &FchInitEnvUsbXhci
+    #define InstallFchInitMidUsbXhci    &FchInitMidUsbXhci
+    #define InstallFchInitLateUsbXhci   &FchInitLateUsbXhci
+  #else
+    #define InstallFchInitResetUsbXhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbXhci    &FchTaskDummy
+    #define InstallFchInitMidUsbXhci    &FchTaskDummy
+    #define InstallFchInitLateUsbXhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IMC_SUPPORT
+    #define BLOCK_IMC_SIZE              sizeof (FCH_IMC)
+    #define InstallFchInitResetImc      &FchInitResetImc
+    #define InstallFchInitEnvImc        &FchInitEnvImc
+    #define InstallFchInitMidImc        &FchInitMidImc
+    #define InstallFchInitLateImc       &FchInitLateImc
+  #else
+    #define BLOCK_IMC_SIZE              0
+    #define InstallFchInitResetImc      &FchTaskDummy
+    #define InstallFchInitEnvImc        &FchTaskDummy
+    #define InstallFchInitMidImc        &FchTaskDummy
+    #define InstallFchInitLateImc       &FchTaskDummy
+  #endif
+
+
+  #ifndef FCH_NO_SD_SUPPORT
+    #define BLOCK_SD_SIZE               sizeof (FCH_SD)
+    #define InstallFchInitResetSd       &FchTaskDummy
+    #define InstallFchInitEnvSd         &FchInitEnvSd
+    #define InstallFchInitMidSd         &FchTaskDummy
+    #define InstallFchInitLateSd        &FchTaskDummy
+  #else
+    #define BLOCK_SD_SIZE               0
+    #define InstallFchInitResetSd       &FchTaskDummy
+    #define InstallFchInitEnvSd         &FchTaskDummy
+    #define InstallFchInitMidSd         &FchTaskDummy
+    #define InstallFchInitLateSd        &FchTaskDummy
+  #endif
+
+    #define BLOCK_IR_SIZE               0
+    #define InstallFchInitResetIr       &FchTaskDummy
+    #define InstallFchInitEnvIr         &FchTaskDummy
+    #define InstallFchInitMidIr         &FchTaskDummy
+    #define InstallFchInitLateIr        &FchTaskDummy
+
+  #ifndef FCH_NO_AZALIA_SUPPORT
+    #define BLOCK_AZALIA_SIZE           sizeof (FCH_AZALIA)
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchInitEnvAzalia
+    #define InstallFchInitMidAzalia     &FchInitMidAzalia
+    #define InstallFchInitLateAzalia    &FchInitLateAzalia
+  #else
+    #define BLOCK_AZALIA_SIZE           0
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchTaskDummy
+    #define InstallFchInitMidAzalia     &FchTaskDummy
+    #define InstallFchInitLateAzalia    &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_HWM_SUPPORT
+    #define BLOCK_HWM_SIZE              sizeof (FCH_HWM)
+    #define InstallFchInitResetHwm      &FchTaskDummy
+    #define InstallFchInitEnvHwm        &FchTaskDummy
+    #define InstallFchInitMidHwm        &FchTaskDummy
+    #define InstallFchInitLateHwm       &FchInitLateHwm
+  #else
+    #define InstallFchInitResetHwm      &FchTaskDummy
+    #define InstallFchInitEnvHwm        &FchTaskDummy
+    #define InstallFchInitMidHwm        &FchTaskDummy
+    #define InstallFchInitLateHwm       &FchTaskDummy
+  #endif
+
+
+  #define BLOCK_SMBUS_SIZE      sizeof (FCH_SMBUS)
+  #define BLOCK_HPET_SIZE       sizeof (FCH_HPET)
+  #define BLOCK_GCPU_SIZE       sizeof (FCH_GCPU)
+  #define BLOCK_SDB_SIZE        sizeof (FCH_SERIALDB)
+  #define BLOCK_MISC_SIZE       sizeof (FCH_MISC)
+
+
+  // Optionally declare OEM hooks after each phase
+  #ifndef FCH_INIT_RESET_HOOK
+    #define InstallFchInitResetHook     FchTaskDummy
+  #else
+    #define InstallFchInitResetHook     OemFchInitResetHook
+  #endif
+
+
+  //
+  // Define FCH build time options and configurations
+  //
+  #ifdef BLDCFG_SMBUS0_BASE_ADDRESS
+    #define CFG_SMBUS0_BASE_ADDRESS           BLDCFG_SMBUS0_BASE_ADDRESS
+  #else
+    #define CFG_SMBUS0_BASE_ADDRESS           DFLT_SMBUS0_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SMBUS1_BASE_ADDRESS
+    #define CFG_SMBUS1_BASE_ADDRESS           BLDCFG_SMBUS1_BASE_ADDRESS
+  #else
+    #define CFG_SMBUS1_BASE_ADDRESS           DFLT_SMBUS1_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SIO_PME_BASE_ADDRESS
+    #define CFG_SIO_PME_BASE_ADDRESS          BLDCFG_SIO_PME_BASE_ADDRESS
+  #else
+    #define CFG_SIO_PME_BASE_ADDRESS          DFLT_SIO_PME_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
+    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
+    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
+    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
+    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
+    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       DFLT_ACPI_GPE0_BLOCK_ADDRESS
+  #endif
+
+
+  #ifdef BLDCFG_WATCHDOG_TIMER_BASE
+    #define CFG_WATCHDOG_TIMER_BASE           BLDCFG_WATCHDOG_TIMER_BASE
+  #else
+    #define CFG_WATCHDOG_TIMER_BASE           DFLT_WATCHDOG_TIMER_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
+    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       BLDCFG_ACPI_PMA_BLK_ADDRESS
+  #else
+    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       DFLT_ACPI_PMA_CNT_BLK_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
+    #define CFG_SMI_CMD_PORT_ADDRESS          BLDCFG_SMI_CMD_PORT_ADDRESS
+  #else
+    #define CFG_SMI_CMD_PORT_ADDRESS          DFLT_SMI_CMD_PORT
+  #endif
+
+  #ifdef BLDCFG_ROM_BASE_ADDRESS
+    #define CFG_SPI_ROM_BASE_ADDRESS          BLDCFG_ROM_BASE_ADDRESS
+  #else
+    #define CFG_SPI_ROM_BASE_ADDRESS          DFLT_SPI_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_GEC_SHADOW_ROM_BASE
+    #define CFG_GEC_SHADOW_ROM_BASE           BLDCFG_GEC_SHADOW_ROM_BASE
+  #else
+    #define CFG_GEC_SHADOW_ROM_BASE           DFLT_GEC_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_HPET_BASE_ADDRESS
+    #define CFG_HPET_BASE_ADDRESS           BLDCFG_HPET_BASE_ADDRESS
+  #else
+    #define CFG_HPET_BASE_ADDRESS           DFLT_HPET_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_AZALIA_SSID
+    #define CFG_AZALIA_SSID                 BLDCFG_AZALIA_SSID
+  #else
+    #define CFG_AZALIA_SSID                 DFLT_AZALIA_SSID
+  #endif
+
+  #ifdef BLDCFG_SMBUS_SSID
+    #define CFG_SMBUS_SSID                  BLDCFG_SMBUS_SSID
+  #else
+    #define CFG_SMBUS_SSID                  DFLT_SMBUS_SSID
+  #endif
+
+  #ifdef BLDCFG_IDE_SSID
+    #define CFG_IDE_SSID                    BLDCFG_IDE_SSID
+  #else
+    #define CFG_IDE_SSID                    DFLT_IDE_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_AHCI_SSID
+    #define CFG_SATA_AHCI_SSID              BLDCFG_SATA_AHCI_SSID
+  #else
+    #define CFG_SATA_AHCI_SSID              DFLT_SATA_AHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_IDE_SSID
+    #define CFG_SATA_IDE_SSID               BLDCFG_SATA_IDE_SSID
+  #else
+    #define CFG_SATA_IDE_SSID               DFLT_SATA_IDE_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_RAID5_SSID
+    #define CFG_SATA_RAID5_SSID             BLDCFG_SATA_RAID5_SSID
+  #else
+    #define CFG_SATA_RAID5_SSID             DFLT_SATA_RAID5_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_RAID_SSID
+    #define CFG_SATA_RAID_SSID              BLDCFG_SATA_RAID_SSID
+  #else
+    #define CFG_SATA_RAID_SSID              DFLT_SATA_RAID_SSID
+  #endif
+
+  #ifdef BLDCFG_EHCI_SSID
+    #define CFG_EHCI_SSID                   BLDCFG_EHCI_SSID
+  #else
+    #define CFG_EHCI_SSID                   DFLT_EHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_OHCI_SSID
+    #define CFG_OHCI_SSID                   BLDCFG_OHCI_SSID
+  #else
+    #define CFG_OHCI_SSID                   DFLT_OHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_LPC_SSID
+    #define CFG_LPC_SSID                    BLDCFG_LPC_SSID
+  #else
+    #define CFG_LPC_SSID                    DFLT_LPC_SSID
+  #endif
+
+  #ifdef BLDCFG_SD_SSID
+    #define CFG_SD_SSID                     BLDCFG_SD_SSID
+  #else
+    #define CFG_SD_SSID                     DFLT_SD_SSID
+  #endif
+
+  #ifdef BLDCFG_XHCI_SSID
+    #define CFG_XHCI_SSID                   BLDCFG_XHCI_SSID
+  #else
+    #define CFG_XHCI_SSID                   DFLT_XHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB
+    #define CFG_FCH_PORT80_BEHIND_PCIB      BLDCFG_FCH_PORT80_BEHIND_PCIB
+  #else
+    #define CFG_FCH_PORT80_BEHIND_PCIB      DFLT_FCH_PORT80_BEHIND_PCIB
+  #endif
+
+  #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
+    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
+  #else
+    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_LINK_CONFIG
+    #define CFG_FCH_GPP_LINK_CONFIG         BLDCFG_FCH_GPP_LINK_CONFIG
+  #else
+    #define CFG_FCH_GPP_LINK_CONFIG         DFLT_FCH_GPP_LINK_CONFIG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
+    #define CFG_FCH_GPP_PORT0_PRESENT       BLDCFG_FCH_GPP_PORT0_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT0_PRESENT       DFLT_FCH_GPP_PORT0_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
+    #define CFG_FCH_GPP_PORT1_PRESENT       BLDCFG_FCH_GPP_PORT1_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT1_PRESENT       DFLT_FCH_GPP_PORT1_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
+    #define CFG_FCH_GPP_PORT2_PRESENT       BLDCFG_FCH_GPP_PORT2_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT2_PRESENT       DFLT_FCH_GPP_PORT2_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
+    #define CFG_FCH_GPP_PORT3_PRESENT       BLDCFG_FCH_GPP_PORT3_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT3_PRESENT       DFLT_FCH_GPP_PORT3_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
+    #define CFG_FCH_GPP_PORT0_HOTPLUG       BLDCFG_FCH_GPP_PORT0_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT0_HOTPLUG       DFLT_FCH_GPP_PORT0_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
+    #define CFG_FCH_GPP_PORT1_HOTPLUG       BLDCFG_FCH_GPP_PORT1_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT1_HOTPLUG       DFLT_FCH_GPP_PORT1_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
+    #define CFG_FCH_GPP_PORT2_HOTPLUG       BLDCFG_FCH_GPP_PORT2_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT2_HOTPLUG       DFLT_FCH_GPP_PORT2_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
+    #define CFG_FCH_GPP_PORT3_HOTPLUG       BLDCFG_FCH_GPP_PORT3_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT3_HOTPLUG       DFLT_FCH_GPP_PORT3_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP
+    #define CFG_FCH_ESATA_PORT_BITMAP       BLDCFG_FCH_ESATA_PORT_BITMAP
+  #else
+    #define CFG_FCH_ESATA_PORT_BITMAP       0
+  #endif
+
+  #ifdef BLDCFG_FCH_IR_PIN_CONTROL
+    #define CFG_FCH_IR_PIN_CONTROL          BLDCFG_FCH_IR_PIN_CONTROL
+  #else
+    #define CFG_FCH_IR_PIN_CONTROL          (BIT5 | BIT1 | BIT0)
+  #endif
+
+  #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL
+    #define CFG_FCH_SD_CLOCK_CONTROL        BLDCFG_FCH_SD_CLOCK_CONTROL
+  #else
+    #define CFG_FCH_SD_CLOCK_CONTROL        Sd50MhzTraceCableLengthWithinSixInches
+  #endif
+
+  #ifdef BLDCFG_FCH_SCI_MAP_LIST
+    #define CFG_FCH_SCI_MAP_LIST            BLDCFG_FCH_SCI_MAP_LIST
+  #else
+    #define CFG_FCH_SCI_MAP_LIST            NULL
+  #endif
+
+  #ifdef BLDCFG_FCH_SATA_PHY_LIST
+    #define CFG_FCH_SATA_PHY_LIST           BLDCFG_FCH_SATA_PHY_LIST
+  #else
+    #define CFG_FCH_SATA_PHY_LIST           NULL
+  #endif
+
+  #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST
+    #define CFG_FCH_GPIO_CONTROL_LIST       BLDCFG_FCH_GPIO_CONTROL_LIST
+  #else
+    #define CFG_FCH_GPIO_CONTROL_LIST       NULL
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      //
+      // Define task list for InitReset phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitResetTaskTable[] = {
+        InstallFchInitResetHwAcpiP,
+        InstallFchInitResetAb,
+        InstallFchInitResetSpi,
+        InstallFchInitResetGec,
+        InstallFchInitResetHwAcpi,
+        InstallFchInitResetSata,
+        InstallFchInitResetLpc,
+        InstallFchInitResetPcib,
+        InstallFchInitResetPcie,
+        InstallFchInitResetGpp,
+        InstallFchInitAllinoneGPP,
+        InstallFchInitResetUsb,
+        InstallFchInitResetUsbEhci,
+        InstallFchInitResetUsbOhci,
+        InstallFchInitResetUsbXhci,
+        InstallFchInitResetImc,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      //
+      // Define task list for InitEnv phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitEnvTaskTable[] = {
+        InstallFchInitEnvHwAcpiP,
+        InstallFchInitEnvPcib,
+        InstallFchInitEnvPcie,
+        InstallFchInitEnvGpp,
+        InstallFchInitEnvIr,
+        InstallFchInitEnvHwAcpi,
+        InstallFchInitEnvSpi,
+        InstallFchInitEnvSd,
+        InstallFchInitEnvImc,
+        InstallFchInitEnvUsb,
+        InstallFchInitEnvUsbEhci,
+        InstallFchInitEnvUsbOhci,
+        InstallFchInitEnvUsbXhci,
+        InstallFchInitEnvSata,
+        InstallFchInitEnvIde,
+        InstallFchInitEnvGec,
+        InstallFchInitEnvAzalia,
+        InstallFchInitEnvAb,
+        InstallFchInitEnvHwm,
+        InstallFchInitEnvGppPhaseII,
+        InstallFchInitEnvAbS,
+        NULL
+      };
+    #endif
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      //
+      // Define task list for InitMid phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitMidTaskTable[] = {
+        InstallFchInitMidImc,
+        InstallFchInitMidUsb,
+        InstallFchInitMidUsbEhci,
+        InstallFchInitMidUsbOhci,
+        InstallFchInitMidUsbXhci,
+        InstallFchInitMidSata,
+        InstallFchInitMidIde,
+        InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
+        InstallFchInitMidHwm,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      //
+      // Define task list for InitLate phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitLateTaskTable[] = {
+        InstallFchInitLatePcie,
+        InstallFchInitLatePcib,
+        InstallFchInitLateSpi,
+        InstallFchInitLateUsb,
+        InstallFchInitLateUsbEhci,
+        InstallFchInitLateUsbOhci,
+        InstallFchInitLateUsbXhci,
+        InstallFchInitLateSata,
+        InstallFchInitLateIde,
+        InstallFchInitLateGec,
+        InstallFchInitLateAzalia,
+        InstallFchInitLateImc,
+        InstallFchInitLateHwm,
+        InstallFchInitLateGpp,
+        InstallFchInitLateHwAcpi,
+        NULL
+      };
+    #endif
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      //
+      // Define task list for S3 resume before PCI phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitS3EarlyTaskTable[] = {
+        InstallFchInitEnvPcie,
+        InstallFchInitEnvPcib,
+        InstallFchInitEnvGpp,
+        InstallFchInitEnvIr,
+        InstallFchInitEnvHwAcpi,
+        InstallFchInitEnvSpi,
+        InstallFchInitEnvSd,
+        InstallFchInitEnvUsb,
+        InstallFchInitEnvUsbXhci,
+        InstallFchInitEnvSata,
+        InstallFchInitEnvIde,
+        InstallFchInitEnvGec,
+        InstallFchInitEnvAzalia,
+        InstallFchInitEnvAb,
+        InstallFchInitEnvGppPhaseII,
+        InstallFchInitEnvAbS,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      //
+      // Define task list for S3 resume after PCI phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitS3LateTaskTable[] = {
+        InstallFchInitLatePcie,
+        InstallFchInitLatePcib,
+        InstallFchInitLateSpi,
+        InstallFchInitLateUsb,
+        InstallFchInitLateUsbEhci,
+        InstallFchInitLateUsbOhci,
+        InstallFchInitLateUsbXhci,
+        InstallFchInitMidSata,
+        InstallFchInitMidIde,
+        InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
+        InstallFchInitLateSata,
+        InstallFchInitLateIde,
+        InstallFchInitLateHwAcpi,
+        InstallFchInitLateGpp,
+        InstallFchInitEnvHwm,
+        InstallFchInitLateGpp,
+        InstallFchInitLateHwm,
+        NULL
+      };
+    #endif
+  #endif
+  FCH_TASK_ENTRY   *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
+
+
+#else   // FCH_SUPPORT == FALSE
+  /* FCH Interface entries */
+  extern  FCH_INIT     CommonFchInitStub;
+
+  #define FP_FCH_INIT_RESET              &CommonFchInitStub
+  #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
+  #define FP_FCH_INIT_ENV                &CommonFchInitStub
+  #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
+  #define FP_FCH_INIT_MID                &CommonFchInitStub
+  #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
+  #define FP_FCH_INIT_LATE               &CommonFchInitStub
+  #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
+
+  #define CFG_SMBUS0_BASE_ADDRESS            0
+  #define CFG_SMBUS1_BASE_ADDRESS            0
+  #define CFG_SIO_PME_BASE_ADDRESS           0
+  #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS      0
+  #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_GPE0_BLOCK_ADDRESS        0
+  #define CFG_SPI_ROM_BASE_ADDRESS           0
+  #define CFG_WATCHDOG_TIMER_BASE            0
+  #define CFG_HPET_BASE_ADDRESS              0
+  #define CFG_SMI_CMD_PORT_ADDRESS           0
+  #define CFG_ACPI_PMA_CNTBLK_ADDRESS        0
+  #define CFG_GEC_SHADOW_ROM_BASE            0
+  #define CFG_AZALIA_SSID                    0
+  #define CFG_SMBUS_SSID                     0
+  #define CFG_IDE_SSID                       0
+  #define CFG_SATA_AHCI_SSID                 0
+  #define CFG_SATA_IDE_SSID                  0
+  #define CFG_SATA_RAID5_SSID                0
+  #define CFG_SATA_RAID_SSID                 0
+  #define CFG_EHCI_SSID                      0
+  #define CFG_OHCI_SSID                      0
+  #define CFG_LPC_SSID                       0
+  #define CFG_SD_SSID                        0
+  #define CFG_XHCI_SSID                      0
+  #define CFG_FCH_PORT80_BEHIND_PCIB         0
+  #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP     0
+  #define CFG_FCH_GPP_LINK_CONFIG            0
+  #define CFG_FCH_GPP_PORT0_PRESENT          0
+  #define CFG_FCH_GPP_PORT1_PRESENT          0
+  #define CFG_FCH_GPP_PORT2_PRESENT          0
+  #define CFG_FCH_GPP_PORT3_PRESENT          0
+  #define CFG_FCH_GPP_PORT0_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT1_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT2_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT3_HOTPLUG          0
+
+  #define CFG_FCH_ESATA_PORT_BITMAP          0
+  #define CFG_FCH_IR_PIN_CONTROL             0
+  #define CFG_FCH_SD_CLOCK_CONTROL           0
+  #define CFG_FCH_SCI_MAP_LIST               0
+  #define CFG_FCH_SATA_PHY_LIST              0
+  #define CFG_FCH_GPIO_CONTROL_LIST          0
+
+#endif
+
+
+CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
+  FP_FCH_INIT_RESET,
+  FP_FCH_INIT_RESET_CONSTRUCT,
+  FP_FCH_INIT_ENV,
+  FP_FCH_INIT_ENV_CONSTRUCT,
+  FP_FCH_INIT_MID,
+  FP_FCH_INIT_MID_CONSTRUCT,
+  FP_FCH_INIT_LATE,
+  FP_FCH_INIT_LATE_CONSTRUCT,
+};
+
+#endif  // _OPTION_FCH_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecovery.h
new file mode 100644
index 0000000..1d96113
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecovery.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD GFX Recovery option API.
+ *
+ * Contains structures and values used to control the GfxRecovery option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_GFX_RECOVERY_H_
+#define _OPTION_GFX_RECOVERY_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#define GFX_RECOVERY_STRUCT_VERSION  0x01
+
+/// The Option Configuration of GFX Recovery
+typedef struct  {
+  UINT16              OptGfxRecoveryVersion;       ///< The version number of GFX Recovery
+  OPTION_GFX_RECOVERY_FEATURE  *GfxRecoveryFeature;        ///< The Option Feature of GFX Recovery
+} OPTION_GFX_RECOVERY_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_GFX_RECOVERY_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecoveryInstall.h
new file mode 100644
index 0000000..75ae37e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecoveryInstall.h
@@ -0,0 +1,53 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GfxRecovery
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
+#define _OPTION_GFX_RECOVERY_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+
+#endif  // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h
new file mode 100644
index 0000000..a1b9166
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD ALIB option API.
+ *
+ * Contains structures and values used to control the ALIB option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 86709 $   @e \$Date: 2013-01-24 17:39:09 -0600 (Thu, 24 Jan 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_GNB_H_
+#define _OPTION_GNB_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+typedef AGESA_STATUS OPTION_GNB_FEATURE (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+typedef AGESA_STATUS F_ALIB_UPDATE (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+typedef VOID* F_ALIB_GET (
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/// The Option Configuration
+typedef struct {
+  UINT64                Type;                   ///< Type
+  OPTION_GNB_FEATURE    *GnbFeature;            ///< The GNB Feature
+  UINT8                 TestPoint;              ///< The post code for each entry
+} OPTION_GNB_CONFIGURATION;
+
+/// The Build time options configuration
+typedef struct {
+  BOOLEAN               IgfxModeAsPcieEp;                   ///< Itegrated Gfx mode Pcie EP or Legacy
+  BOOLEAN               LclkDeepSleepEn;                    ///< Default for LCLK deep sleep
+  BOOLEAN               LclkDpmEn;                          ///< Default for LCLK DPM
+  UINT8                 GmcPowerGating;                     ///< Control GMC power gating
+  BOOLEAN               SmuSclkClockGatingEnable;           ///< Control SMU SCLK gating
+  BOOLEAN               PcieAspmBlackListEnable;            ///< Control Pcie Aspm Black List
+  BOOLEAN               IvrsRelativeAddrNamesSupport;       ///< Support for relative address names
+  BOOLEAN               GnbLoadRealF1Table;
+  UINT32                CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+  UINT32                CfgGnbLinkL0Pooling;                ///< Pooling for link to get to L0 in us
+  UINT32                CfgGnbLinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
+  UINT32                CfgGnbLinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us
+  UINT8                 CfgGnbTrainingAlgorithm;            ///< distribution of training across interface calls
+  BOOLEAN               CfgForceCableSafeOff;               ///< Force cable safe off
+  BOOLEAN               CfgOrbClockGatingEnable;            ///< Control ORB clock gating
+  UINT8                 CfgPciePowerGatingFlags;            ///< Pcie Power gating flags
+  BOOLEAN               CfgStub;
+  BOOLEAN               CfgIocSclkClockGatingEnable;        ///< Control IOC SCLK clock gating
+  BOOLEAN               CfgIommuL1ClockGatingEnable;        ///< Control IOMMU L1 clock gating
+  BOOLEAN               CfgIommuL2ClockGatingEnable;        ///< Control IOMMU L2 clock gating
+  BOOLEAN               CfgAltVddNb;                        ///< AltVDDNB support
+  BOOLEAN               CfgBapmSupport;                     ///< BAPM support
+  BOOLEAN               CfgUnusedSimdPowerGatingEnable;     ///< Control unused SIMD power gate
+  BOOLEAN               CfgUnusedRbPowerGatingEnable;       ///< Control unused SIMD power gate
+  BOOLEAN               CfgNbdpmEnable;                     ///< NBDPM refers to dynamically reprogramming High and Low NB Pstates under different system usage scenarios
+  BOOLEAN               CfgGmcClockGating;                  ///< Control GMC clock power gate
+  BOOLEAN               CfgMaxPayloadEnable;                ///< Enables configuration of Max_Payload_Size in PCIe device links
+  BOOLEAN               CfgOrbDynWakeEnable;                ///< Enables ORB Dynamic wake up
+  BOOLEAN               CfgLoadlineEnable;                  ///< Enable Loadline Optimization
+  BOOLEAN               CfgPciePhyIsolationEnable;          ///< Enable Pcie Phy Isolation
+  BOOLEAN               CfgLhtcSupport;                     ///< LHTC support
+  UINT8                 CfgSviRevision;                     ///< SVI revision
+  BOOLEAN               CfgScsSupport;                      ///< Scs support
+  BOOLEAN               CfgSamuPatchEnabled;
+  UINT8                 OemIdString[6];                     ///< Configurable ACPI OEM Id
+  UINT8                 OemTableIdString[8];                ///< Configurable ACPI OEM Table Id
+  BOOLEAN               CfgTdcSupport;                      ///< TDC tracking support
+  BOOLEAN               CfgPkgPowerTrackingSupport;         ///< Package Power tracking
+  BOOLEAN               CfgNativeGen1PLL;                   ///< Control Native Gen1 PLL
+  UINT8                 CfgUmaSteering;                     ///< Configurable UMA Steering
+} GNB_BUILD_OPTIONS;
+
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_GNB_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionGnbInstall.h
new file mode 100644
index 0000000..a648cc4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionGnbInstall.h
@@ -0,0 +1,932 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GNB
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 87849 $   @e \$Date: 2013-02-11 15:37:58 -0600 (Mon, 11 Feb 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_GNB_INSTALL_H_
+#define _OPTION_GNB_INSTALL_H_
+
+#include "S3SaveState.h"
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+//---------------------------------------------------------------------------------------------------
+// Family installation
+//---------------------------------------------------------------------------------------------------
+
+
+
+#define GNB_TYPE_TN   FALSE
+#define GNB_TYPE_BK   FALSE
+#define GNB_TYPE_KV   FALSE
+#define GNB_TYPE_KB   FALSE
+#define GNB_TYPE_BK   FALSE
+#define GNB_TYPE_ML   FALSE
+
+#if (OPTION_FAMILY15H_TN == TRUE)
+  #undef  GNB_TYPE_TN
+  #define GNB_TYPE_TN  TRUE
+#endif
+
+
+#if (OPTION_FAMILY16H_KB == TRUE)
+  #undef  GNB_TYPE_KB
+  #define GNB_TYPE_KB  TRUE
+#endif
+
+
+#if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE)
+//---------------------------------------------------------------------------------------------------
+// Service installation
+//---------------------------------------------------------------------------------------------------
+
+  #include "Gnb.h"
+  #include "GnbPcie.h"
+  #include "GnbGfx.h"
+
+  #define SERVICES_POINTER  NULL
+  #if (GNB_TYPE_TN == TRUE)
+    #include "GnbInitTNInstall.h"
+  #endif
+  #if (GNB_TYPE_KB == TRUE)
+    #include "GnbInitKBInstall.h"
+  #endif
+  GNB_SERVICE   *ServiceTable = SERVICES_POINTER;
+
+//---------------------------------------------------------------------------------------------------
+// BUILD options
+//---------------------------------------------------------------------------------------------------
+
+  #ifndef CFG_IGFX_AS_PCIE_EP
+    #define CFG_IGFX_AS_PCIE_EP                           TRUE
+  #endif
+
+  #ifndef CFG_LCLK_DEEP_SLEEP_EN
+    #if (GNB_TYPE_TN == TRUE)
+      #define  CFG_LCLK_DEEP_SLEEP_EN                       FALSE
+    #else
+      #define  CFG_LCLK_DEEP_SLEEP_EN                       TRUE
+    #endif
+  #endif
+
+  #ifndef CFG_LCLK_DPM_EN
+    #define CFG_LCLK_DPM_EN                                 TRUE
+  #endif
+
+  #ifndef CFG_GMC_POWER_GATING
+    #if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE))
+      #define CFG_GMC_POWER_GATING                          GmcPowerGatingWithStutter
+    #else
+      #define CFG_GMC_POWER_GATING                          GmcPowerGatingDisabled
+    #endif
+  #endif
+
+  #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
+    #if (GNB_TYPE_TN == TRUE)
+      #define  CFG_SMU_SCLK_CLOCK_GATING_ENABLE           TRUE
+    #else
+      #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+    #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE               TRUE
+  #endif
+
+  #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
+    #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT      FALSE
+  #endif
+
+  #ifndef CFG_GNB_LOAD_REAL_FUSE
+    #define  CFG_GNB_LOAD_REAL_FUSE                       TRUE
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
+    #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING  (60 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_L0_POOLING
+    #define CFG_GNB_PCIE_LINK_L0_POOLING                  (60 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
+    #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME      (2 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
+    #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME      (2 * 1000)
+  #endif
+
+  #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
+  #else
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
+  #endif
+
+  #ifndef CFG_GNB_FORCE_CABLESAFE_OFF
+    #define CFG_GNB_FORCE_CABLESAFE_OFF                   FALSE
+  #endif
+
+  #ifndef CFG_ORB_CLOCK_GATING_ENABLE
+      #define CFG_ORB_CLOCK_GATING_ENABLE                 TRUE
+  #endif
+
+  #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
+    #define CFG_GNB_PCIE_POWERGATING_FLAGS                0x0
+  #endif
+
+
+  #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
+    #if (GNB_TYPE_TN == TRUE)
+      #define  CFG_IOC_SCLK_CLOCK_GATING_ENABLE           TRUE
+    #else
+      #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
+    #if (GNB_TYPE_TN == TRUE)
+      #define  CFG_IOMMU_L1_CLOCK_GATING_ENABLE           TRUE
+    #else
+      #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE            FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
+    #if (GNB_TYPE_TN == TRUE)
+      #define  CFG_IOMMU_L2_CLOCK_GATING_ENABLE           TRUE
+    #else
+      #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE            FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_GNB_ALTVDDNB_SUPPORT
+    #define CFG_GNB_ALTVDDNB_SUPPORT                      TRUE
+  #endif
+
+  #ifndef CFG_GNB_BAPM_SUPPORT
+    #if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE))
+      #define CFG_GNB_BAPM_SUPPORT                        TRUE
+    #else
+      #define CFG_GNB_BAPM_SUPPORT                        FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_GNB_LHTC_SUPPORT
+    #if (GNB_TYPE_KB == TRUE)
+      #define CFG_GNB_LHTC_SUPPORT                        TRUE
+    #else
+      #define CFG_GNB_LHTC_SUPPORT                        FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
+    #define CFG_UNUSED_SIMD_POWERGATING_ENABLE            TRUE
+  #endif
+
+  #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
+    #define CFG_UNUSED_RB_POWERGATING_ENABLE              FALSE
+  #endif
+
+  #ifndef CFG_NBDPM_ENABLE
+    #if ((GNB_TYPE_KB == TRUE))
+      #define CFG_NBDPM_ENABLE                              FALSE
+    #else
+      #define CFG_NBDPM_ENABLE                              TRUE
+    #endif
+  #endif
+
+  #ifndef CFG_MAX_PAYLOAD_ENABLE
+    #define CFG_MAX_PAYLOAD_ENABLE                        TRUE
+  #endif
+
+
+  #ifndef CFG_ORB_DYN_WAKE_ENABLE
+    #if (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      #define  CFG_ORB_DYN_WAKE_ENABLE                    TRUE
+    #else
+      #define CFG_ORB_DYN_WAKE_ENABLE                     TRUE
+    #endif
+  #endif
+
+  #ifndef CFG_LOADLINE_ENABLE
+    #define CFG_LOADLINE_ENABLE                           TRUE
+  #endif
+
+  #ifndef CFG_PCIE_PHY_ISOLATION_SUPPORT
+    #if (GNB_TYPE_KB == TRUE)
+      #define CFG_PCIE_PHY_ISOLATION_SUPPORT             TRUE
+    #else
+      #define CFG_PCIE_PHY_ISOLATION_SUPPORT             FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_SVI_REVISION
+    #if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE)
+      #define CFG_SVI_REVISION             2
+    #else
+      #define CFG_SVI_REVISION             1
+    #endif
+  #endif
+
+  #ifndef CFG_SCS_SUPPORT
+    #if ((GNB_TYPE_KB == TRUE))
+      #define CFG_SCS_SUPPORT             TRUE
+    #else
+      #define CFG_SCS_SUPPORT             FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_SAMU_PATCH_ENABLED
+    #define CFG_SAMU_PATCH_ENABLED      TRUE
+  #endif
+
+  #ifndef CFG_GNB_TDC_SUPPORT
+    #define CFG_GNB_TDC_SUPPORT          TRUE
+  #endif
+  #ifndef CFG_NATIVE_GEN1_PLL_ENABLE
+    #define CFG_NATIVE_GEN1_PLL_ENABLE   TRUE
+  #endif
+
+  #ifndef CFG_UMA_STEERING
+    #define CFG_UMA_STEERING             0
+  #endif
+
+  GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
+    CFG_IGFX_AS_PCIE_EP,
+    CFG_LCLK_DEEP_SLEEP_EN,
+    CFG_LCLK_DPM_EN,
+    CFG_GMC_POWER_GATING,
+    CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
+    CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
+    CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
+    CFG_GNB_LOAD_REAL_FUSE,
+    CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
+    CFG_GNB_PCIE_LINK_L0_POOLING,
+    CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
+    CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
+    CFG_GNB_PCIE_TRAINING_ALGORITHM,
+    CFG_GNB_FORCE_CABLESAFE_OFF,
+    CFG_ORB_CLOCK_GATING_ENABLE,
+    CFG_GNB_PCIE_POWERGATING_FLAGS,
+    TRUE,
+    CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
+    CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
+    CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
+    CFG_GNB_ALTVDDNB_SUPPORT,
+    CFG_GNB_BAPM_SUPPORT,
+    CFG_UNUSED_SIMD_POWERGATING_ENABLE,
+    CFG_UNUSED_RB_POWERGATING_ENABLE,
+    CFG_NBDPM_ENABLE,
+    TRUE,
+    CFG_MAX_PAYLOAD_ENABLE,
+    CFG_ORB_DYN_WAKE_ENABLE,
+    CFG_LOADLINE_ENABLE,
+    CFG_PCIE_PHY_ISOLATION_SUPPORT,
+    CFG_GNB_LHTC_SUPPORT,
+    CFG_SVI_REVISION,
+    CFG_SCS_SUPPORT,
+    CFG_SAMU_PATCH_ENABLED,
+    {CFG_ACPI_SET_OEM_ID},
+    {CFG_ACPI_SET_OEM_TABLE_ID},
+    CFG_GNB_TDC_SUPPORT,
+    TRUE,
+    CFG_NATIVE_GEN1_PLL_ENABLE,
+    CFG_UMA_STEERING
+  };
+
+  //---------------------------------------------------------------------------------------------------
+  // SMU Firmware
+  //---------------------------------------------------------------------------------------------------
+
+
+
+  //---------------------------------------------------------------------------------------------------
+  // Module entries
+  //---------------------------------------------------------------------------------------------------
+
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_EARLY_INIT
+      #define OPTION_NB_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbEarlyInterfaceTN;
+      #define OPTION_GNBEARLYINTERFACETN_ENTRY            {AMD_FAMILY_TN, GnbEarlyInterfaceTN, TpGnbEarlyInterface},
+    #else
+      #define OPTION_GNBEARLYINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GnbEarlyInterfaceKB;
+      #define OPTION_GNBEARLYINTERFACEKB_ENTRY            {AMD_FAMILY_KB, GnbEarlyInterfaceKB, TpGnbEarlyInterface},
+    #else
+      #define OPTION_GNBEARLYINTERFACEKB_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CONFIG_MAP
+      #define OPTION_PCIE_CONFIG_MAP TRUE
+    #endif
+    #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                 PcieConfigurationMap;
+      #define OPTION_PCIECONFIGURATIONMAP_ENTRY          {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationMap, TpGnbPcieConfigurationMap},
+    #else
+      #define OPTION_PCIECONFIGURATIONMAP_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_EARLY_INIT
+      #define OPTION_PCIE_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  PcieEarlyInterfaceTN;
+      #define OPTION_PCIEEARLYINTERFACETN_ENTRY           {AMD_FAMILY_TN, PcieEarlyInterfaceTN, TpGnbPcieEarlyInterface},
+    #else
+      #define  OPTION_PCIEEARLYINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieEarlyInterfaceKB;
+      #define OPTION_PCIEEARLYINTERFACEKB_ENTRY           {AMD_FAMILY_KB, PcieEarlyInterfaceKB, TpGnbPcieEarlyInterface},
+    #else
+      #define OPTION_PCIEEARLYINTERFACEKB_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
+      OPTION_GNBEARLYINTERFACETN_ENTRY
+      OPTION_GNBEARLYINTERFACEKB_ENTRY
+      OPTION_PCIECONFIGURATIONMAP_ENTRY
+      OPTION_PCIEEARLYINTERFACETN_ENTRY
+      OPTION_PCIEEARLYINTERFACEKB_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CONFIG_INIT
+      #define OPTION_PCIE_CONFIG_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieConfigurationInit;
+      #define OPTION_PCIECONFIGURATIONINIT_ENTRY          {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationInit, TpGnbEarlierPcieConfigurationInit},
+    #else
+      #define OPTION_PCIECONFIGURATIONINIT_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_EARLIER_INIT
+      #define OPTION_NB_EARLIER_INIT TRUE
+    #endif
+    #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbEarlierInterfaceTN;
+      #define OPTION_GNBEARLIERINTERFACETN_ENTRY          {AMD_FAMILY_TN, GnbEarlierInterfaceTN, TpGnbEarlierInterface},
+    #else
+      #define OPTION_GNBEARLIERINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GnbEarlierInterfaceKB;
+      #define OPTION_GNBEARLIERINTERFACEKB_ENTRY          {AMD_FAMILY_KB, GnbEarlierInterfaceKB, TpGnbEarlierInterface},
+    #else
+      #define OPTION_GNBEARLIERINTERFACEKB_ENTRY
+    #endif
+
+    #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  OptionGnbInstall581;
+      #define OPTION_GNBSCSINTERFACEKB_ENTRY          {AMD_FAMILY_KB, OptionGnbInstall581, TpGnbEarlierInterface},
+    #else
+      #define OPTION_GNBSCSINTERFACEKB_ENTRY
+    #endif
+
+
+    OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
+      OPTION_PCIECONFIGURATIONINIT_ENTRY
+      OPTION_GNBEARLIERINTERFACETN_ENTRY
+      OPTION_GNBEARLIERINTERFACEKB_ENTRY
+      OPTION_GNBSCSINTERFACEKB_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_POST_INIT
+      #define OPTION_GFX_CONFIG_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxConfigPostInterface;
+      #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY         {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigPostInterface, TpGnbGfxConfigPostInterface},
+    #else
+      #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_POST_INIT
+      #define OPTION_GFX_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GfxPostInterfaceTN;
+      #define OPTION_GFXPOSTINTERFACETN_ENTRY             {AMD_FAMILY_TN, GfxPostInterfaceTN, TpGnbGfxPostInterface},
+    #else
+      #define OPTION_GFXPOSTINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxPostInterfaceKB;
+      #define OPTION_GFXPOSTINTERFACEKB_ENTRY             {AMD_FAMILY_KB, GfxPostInterfaceKB, TpGnbGfxPostInterface},
+    #else
+      #define OPTION_GFXPOSTINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_POST_INIT
+      #define OPTION_NB_POST_INIT TRUE
+    #endif
+    #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbPostInterfaceTN;
+      #define OPTION_GNBPOSTINTERFACETN_ENTRY             {AMD_FAMILY_TN, GnbPostInterfaceTN, TpGnbPostInterface},
+    #else
+      #define OPTION_GNBPOSTINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GnbPostInterfaceKB;
+      #define OPTION_GNBPOSTINTERFACEKB_ENTRY             {AMD_FAMILY_KB, GnbPostInterfaceKB, TpGnbPostInterface},
+    #else
+      #define OPTION_GNBPOSTINTERFACEKB_ENTRY
+    #endif
+
+    //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POST_EARLY_INIT
+      #define OPTION_PCIE_POST_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  PciePostEarlyInterfaceTN;
+      #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY       {AMD_FAMILY_TN, PciePostEarlyInterfaceTN, TpGnbPciePostEarlyInterface},
+    #else
+      #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PciePostEarlyInterfaceKB;
+      #define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY       {AMD_FAMILY_KB, PciePostEarlyInterfaceKB, TpGnbPciePostEarlyInterface},
+    #else
+      #define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POST_INIT
+      #define OPTION_PCIE_POST_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  PciePostInterfaceTN;
+      #define OPTION_PCIEPOSTINTERFACETN_ENTRY            {AMD_FAMILY_TN, PciePostInterfaceTN, TpGnbPciePostInterface},
+    #else
+      #define OPTION_PCIEPOSTINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PciePostInterfaceKB;
+      #define OPTION_PCIEPOSTINTERFACEKB_ENTRY            {AMD_FAMILY_KB, PciePostInterfaceKB, TpGnbPciePostInterface},
+    #else
+      #define OPTION_PCIEPOSTINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
+      OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
+      OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
+      OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+      OPTION_GFXPOSTINTERFACETN_ENTRY
+      OPTION_GFXPOSTINTERFACEKB_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+
+    OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
+      OPTION_GNBPOSTINTERFACETN_ENTRY
+      OPTION_GNBPOSTINTERFACEKB_ENTRY
+      OPTION_PCIEPOSTINTERFACETN_ENTRY
+      OPTION_PCIEPOSTINTERFACEKB_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_ENV == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_ENV_INIT
+      #define OPTION_NB_ENV_INIT TRUE
+    #endif
+    #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbEnvInterfaceTN;
+      #define OPTION_GNBENVINTERFACETN_ENTRY              {AMD_FAMILY_TN, GnbEnvInterfaceTN, TpGnbEnvInterface},
+    #else
+      #define OPTION_GNBENVINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GnbEnvInterfaceKB;
+      #define OPTION_GNBENVINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GnbEnvInterfaceKB, TpGnbEnvInterface},
+    #else
+      #define OPTION_GNBENVINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_ENV_INIT
+      #define OPTION_GFX_CONFIG_ENV_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                   GfxConfigEnvInterface;
+      #define OPTION_GFXCONFIGENVINTERFACE_ENTRY          {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigEnvInterface, TpGnbGfxConfigEnvInterface},
+    #else
+      #define  OPTION_GFXCONFIGENVINTERFACE_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_ENV_INIT
+      #define OPTION_GFX_ENV_INIT TRUE
+    #endif
+    #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GfxEnvInterfaceTN;
+      #define OPTION_GFXENVINTERFACETN_ENTRY              {AMD_FAMILY_TN, GfxEnvInterfaceTN, TpGnbGfxEnvInterface},
+    #else
+      #define OPTION_GFXENVINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxEnvInterfaceKB;
+      #define OPTION_GFXENVINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GfxEnvInterfaceKB, TpGnbGfxEnvInterface},
+    #else
+      #define OPTION_GFXENVINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_ENV_INIT
+      #define OPTION_PCIE_ENV_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE PcieEnvInterfaceTN;
+      #define OPTION_PCIEENVINTERFACETN_ENTRY             {AMD_FAMILY_TN, PcieEnvInterfaceTN, TpGnbPcieEnvInterface},
+    #else
+      #define OPTION_PCIEENVINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieEnvInterfaceKB;
+      #define OPTION_PCIEENVINTERFACEKB_ENTRY             {AMD_FAMILY_KB, PcieEnvInterfaceKB, TpGnbPcieEnvInterface},
+    #else
+      #define OPTION_PCIEENVINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+
+    OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
+      OPTION_GNBENVINTERFACETN_ENTRY
+      OPTION_GNBENVINTERFACEKB_ENTRY
+      OPTION_PCIEENVINTERFACETN_ENTRY
+      OPTION_PCIEENVINTERFACEKB_ENTRY
+      OPTION_GFXCONFIGENVINTERFACE_ENTRY
+      OPTION_GFXENVINTERFACETN_ENTRY
+      OPTION_GFXENVINTERFACEKB_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_MID == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_MID_INIT
+      #define OPTION_GFX_MID_INIT TRUE
+    #endif
+    #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GfxMidInterfaceTN;
+      #define OPTION_GFXMIDINTERFACETN_ENTRY              {AMD_FAMILY_TN, GfxMidInterfaceTN, TpGnbGfxMidInterface},
+    #else
+      #define OPTION_GFXMIDINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxMidInterfaceKB;
+      #define OPTION_GFXMIDINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GfxMidInterfaceKB, TpGnbGfxMidInterface},
+    #else
+      #define OPTION_GFXMIDINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
+      #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
+    #endif
+    #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GfxIntInfoTableInterfaceTN;
+      #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY     {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN},
+    #else
+      #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxIntInfoTableInterfaceKB;
+      #define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY     {AMD_FAMILY_KB, GfxIntInfoTableInterfaceKB},
+    #else
+      #define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIe_MID_INIT
+      #define OPTION_PCIe_MID_INIT TRUE
+    #endif
+    #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  PcieMidInterfaceTN;
+      #define OPTION_PCIEMIDINTERFACETN_ENTRY             {AMD_FAMILY_TN, PcieMidInterfaceTN, TpPcieMidInterface},
+    #else
+      #define OPTION_PCIEMIDINTERFACETN_ENTRY
+    #endif
+    #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieMidInterfaceKB;
+      #define OPTION_PCIEMIDINTERFACEKB_ENTRY             {AMD_FAMILY_KB, PcieMidInterfaceKB, TpPcieMidInterface},
+    #else
+      #define OPTION_PCIEMIDINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_MID_INIT
+      #define OPTION_NB_MID_INIT TRUE
+    #endif
+    #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbMidInterfaceTN;
+      #define OPTION_GNBMIDINTERFACETN_ENTRY              {AMD_FAMILY_TN, GnbMidInterfaceTN, TpGnbMidInterface},
+    #else
+      #define OPTION_GNBMIDINTERFACETN_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_POST_INIT
+      #define OPTION_GFX_CONFIG_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxConfigMidInterface;
+      #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY         {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigMidInterface, TpGnbGfxConfigMidInterface},
+    #else
+      #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GnbMidInterfaceKB;
+      #define OPTION_GNBMIDINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GnbMidInterfaceKB, TpGnbMidInterface},
+    #else
+      #define OPTION_GNBMIDINTERFACEKB_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_MAXPAYLOAD_INTERFACE
+      #define OPTION_PCIE_MAXPAYLOAD_INTERFACE TRUE
+    #endif
+    #if (OPTION_PCIE_MAXPAYLOAD_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieMaxPayloadInterface;
+      #define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY        {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieMaxPayloadInterface, TpGnbPcieMaxPayloadInterface},
+    #else
+      #define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CLK_PM_INTERFACE
+      #define OPTION_PCIE_CLK_PM_INTERFACE FALSE
+      #if (GNB_TYPE_TN == TRUE  &&  (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE))
+        #undef  OPTION_PCIE_CLK_PM_INTERFACE
+        #define OPTION_PCIE_CLK_PM_INTERFACE TRUE
+      #endif
+      #if (GNB_TYPE_KB == TRUE)
+        #undef  OPTION_PCIE_CLK_PM_INTERFACE
+        #define OPTION_PCIE_CLK_PM_INTERFACE TRUE
+      #endif
+    #endif
+
+    #if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieClkPmInterface;
+      #define OPTION_PCIECLKPMINTERFACE_ENTRY             {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieClkPmInterface, TpGnbPcieClkPmInterface},
+    #else
+      #define OPTION_PCIECLKPMINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_ASPM_INTERFACE
+      #define OPTION_PCIE_ASPM_INTERFACE TRUE
+    #endif
+    #if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  PcieAspmInterface;
+      #define OPTION_PCIEASPMINTERFACE_ENTRY              {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieAspmInterface, TpGnbPcieAspmInterface},
+    #else
+      #define OPTION_PCIEASPMINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GNB_IOAPIC_INTERFACE
+      #define OPTION_GNB_IOAPIC_INTERFACE TRUE
+    #endif
+    #if (OPTION_GNB_IOAPIC_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GnbNbIoapicInterface;
+      #define OPTION_GNBNBIOAPICINTERFACE_ENTRY          {AMD_FAMILY_KB, GnbNbIoapicInterface, TpGnbNbIoapicInterface},
+    #else
+      #define OPTION_GNBNBIOAPICINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
+      OPTION_GFXCONFIGMIDINTERFACE_ENTRY
+      OPTION_GFXMIDINTERFACETN_ENTRY
+      OPTION_GFXMIDINTERFACEKB_ENTRY
+      OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
+      OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY
+      OPTION_PCIEMIDINTERFACETN_ENTRY
+      OPTION_PCIEMIDINTERFACEKB_ENTRY
+      OPTION_GNBMIDINTERFACETN_ENTRY
+      OPTION_GNBMIDINTERFACEKB_ENTRY
+      OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY
+      OPTION_PCIECLKPMINTERFACE_ENTRY
+      OPTION_PCIEASPMINTERFACE_ENTRY
+      OPTION_GNBNBIOAPICINTERFACE_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_ALIB
+      #define OPTION_ALIB FALSE
+    #endif
+    #if (OPTION_ALIB == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      #define ALIB_CALL_TABLE
+      #define ALIB_CALL_TABLEV2
+      #if (GNB_TYPE_TN == TRUE)
+        #if ((OPTION_FM2_SOCKET_SUPPORT == TRUE) || (OPTION_FM2r2_SOCKET_SUPPORT == TRUE))
+          extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
+          extern F_ALIB_GET PcieAlibGetBaseTableTNFM2;
+          F_ALIB_GET  *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2;
+          #undef ALIB_CALL_TABLE
+          #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo,
+        #else
+          extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
+          extern F_ALIB_GET PcieAlibGetBaseTableTNFS1;
+          F_ALIB_GET  *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1;
+          extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo;
+          extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo;
+          #undef ALIB_CALL_TABLE
+          #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \
+                                  PcieAlibUpdateVoltageInfo, \
+                                  PcieAlibUpdatePcieInfo,
+
+        #endif
+      #endif
+
+
+      #if (GNB_TYPE_KB == TRUE)
+        extern F_ALIB_GET PcieAlibGetBaseTableKB;
+        F_ALIB_GET  *AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
+        extern F_ALIB_UPDATE PcieAlibUpdateVoltageData;
+        extern F_ALIB_UPDATE PcieAlibUpdatePcieData;
+        #undef ALIB_CALL_TABLEV2
+        #define ALIB_CALL_TABLEV2 PcieAlibUpdateVoltageData, \
+                                  PcieAlibUpdatePcieData,
+      #endif
+
+
+      F_ALIB_UPDATE* AlibDispatchTable [] = {
+        ALIB_CALL_TABLE
+        NULL
+      };
+      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
+        ALIB_CALL_TABLEV2
+        NULL
+      };
+      #if (GNB_TYPE_TN == TRUE)
+        OPTION_GNB_FEATURE                                  PcieAlibFeature;
+        #define OPTION_PCIEALIBFEATURE_ENTRY                {AMD_FAMILY_TN, PcieAlibFeature, TpGnbPcieAlibFeature},
+      #endif
+      #if ((GNB_TYPE_KB == TRUE))
+        OPTION_GNB_FEATURE                                  PcieAlibV2Feature;
+        #define OPTION_PCIEALIBV2FEATURE_ENTRY              {AMD_FAMILY_KB, PcieAlibV2Feature, TpGnbPcieAlibFeature},
+      #endif
+    #else
+      F_ALIB_GET  *AlibGetBaseTable = NULL;
+      F_ALIB_GET  *AlibGetBaseTableV2 = NULL;
+      F_ALIB_UPDATE* AlibDispatchTable [] = {
+        NULL
+      };
+      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
+        NULL
+      };
+      #define OPTION_PCIEALIBFEATURE_ENTRY
+      #define OPTION_PCIEALIBV2FEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_IOMMU_ACPI_IVRS
+      #if (CFG_IOMMU_SUPPORT == TRUE)
+        #define OPTION_IOMMU_ACPI_IVRS TRUE
+      #else
+        #define OPTION_IOMMU_ACPI_IVRS FALSE
+      #endif
+    #endif
+    #if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbIommuIvrsTable;
+      #define OPTIONIOMMUACPIIVRSLATE_ENTRY               {AMD_FAMILY_TN, GnbIommuIvrsTable},
+    #else
+      #define OPTIONIOMMUACPIIVRSLATE_ENTRY
+    #endif
+    #if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbIommuScratchMemoryRangeInterface;
+      #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY          {AMD_FAMILY_TN, GnbIommuScratchMemoryRangeInterface, TpGnbIommuIvrsTable},
+    #else
+      #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
+      #if (GNB_TYPE_TN == TRUE)
+        OPTION_PCIEALIBFEATURE_ENTRY
+      #endif
+      #if ((GNB_TYPE_KB == TRUE))
+        OPTION_PCIEALIBV2FEATURE_ENTRY
+      #endif
+      OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
+      OPTIONIOMMUACPIIVRSLATE_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_S3SAVE == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_INIT_SVIEW
+      #define OPTION_GFX_INIT_SVIEW TRUE
+    #endif
+    #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitSview;
+      #define OPTION_GFXINITSVIEW_ENTRY                   {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxInitSview},
+    #else
+      #define OPTION_GFXINITSVIEW_ENTRY
+    #endif
+
+    OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[] = {
+      OPTION_GFXINITSVIEW_ENTRY
+      {0, NULL, EndGnbTestPoints}
+    };
+  #endif
+
+  #if  (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
+    #define GNBS3RESTOREV4
+    #define GNBS3RESTOREV7
+    #if (GNB_TYPE_TN == TRUE)
+      S3_DISPATCH_FUNCTION  GnbSmuServiceRequestV4S3Script;
+      #undef  GNBS3RESTOREV4
+      #define GNBS3RESTOREV4 {GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script},
+    #endif
+    #if (GNB_TYPE_KB == TRUE)
+      S3_DISPATCH_FUNCTION  GnbSmuServiceRequestV7S3Script;
+      #undef  GNBS3RESTOREV7
+      #define GNBS3RESTOREV7 {GnbSmuServiceRequestV7S3Script_ID, GnbSmuServiceRequestV7S3Script},
+    #endif
+    S3_DISPATCH_FUNCTION  GnbLibStallS3Script;
+    #define PCIELATERESTORETN
+    #define PCIELATERESTOREKB
+    #define GFXSCLKRESTORETN
+    #if (GNB_TYPE_TN == TRUE)
+      S3_DISPATCH_FUNCTION  PcieLateRestoreInitTNS3Script;
+      S3_DISPATCH_FUNCTION  GfxRequestSclkTNS3Script;
+      #undef  PCIELATERESTORETN
+      #define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script},
+      #undef  GFXSCLKRESTORETN
+      #define GFXSCLKRESTORETN  {GfxRequestSclkTNS3Script_ID,  GfxRequestSclkTNS3Script     },
+    #endif
+    #if (GNB_TYPE_KB == TRUE)
+      S3_DISPATCH_FUNCTION  PcieLateRestoreInitKBS3Script;
+      #undef  PCIELATERESTOREKB
+      #define PCIELATERESTOREKB {PcieLateRestoreKBS3Script_ID, PcieLateRestoreInitKBS3Script},
+    #endif
+    #define GNB_S3_DISPATCH_FUNCTION_TABLE \
+    GNBS3RESTOREV4      \
+    GNBS3RESTOREV7      \
+    PCIELATERESTORETN \
+    GFXSCLKRESTORETN  \
+    PCIELATERESTOREKB \
+    {GnbLibStallS3Script_ID, GnbLibStallS3Script},
+
+
+
+#endif
+
+#endif
+#endif  // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionHtInstall.h
new file mode 100644
index 0000000..06c5463
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionHtInstall.h
@@ -0,0 +1,244 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Ht
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84154 $   @e \$Date: 2012-12-12 17:02:37 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HT_INSTALL_H_
+#define _OPTION_HT_INSTALL_H_
+
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htTopologies.h"
+/*
+ * Advanced Option only, hardware socket naming is the preferred method.
+ */
+#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
+#else
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
+#endif
+
+/*
+ * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
+ */
+#ifndef OPTION_IS_RECOVERY_HT
+  #define OPTION_IS_RECOVERY_HT TRUE
+#endif
+
+/*
+ * Macros will generate the correct item reference based on options
+ */
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  // Select the interface and features
+  #if ((OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY16H_KB == TRUE))
+    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+    #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
+    #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
+  #endif
+  // Select Northbridge components
+  #if OPTION_FAMILY15H == TRUE
+    #if OPTION_FAMILY15H_TN == TRUE
+      #define INTERNAL_HT_OPTION_FAM15TN_NB     &HtFam15Mod1xNb,
+    #else
+      #define INTERNAL_HT_OPTION_FAM15TN_NB
+    #endif
+  #else
+    #define INTERNAL_HT_OPTION_FAM15TN_NB
+  #endif
+
+  #if OPTION_FAMILY16H == TRUE
+    #if OPTION_FAMILY16H_KB == TRUE
+      #define INTERNAL_HT_OPTION_FAM16KB_NB     &HtFam16Nb,
+    #else
+      #define INTERNAL_HT_OPTION_FAM16KB_NB
+    #endif
+  #else
+    #define INTERNAL_HT_OPTION_FAM16KB_NB
+  #endif
+
+  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
+  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
+    #undef INTERNAL_ONLY_NB_LIST_ITEM
+    #define INTERNAL_ONLY_NB_LIST_ITEM
+  #endif
+
+  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
+   * is ok to have a comma because the final item (NULL) is added below.
+   */
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
+                                             INTERNAL_ONLY_NB_LIST_ITEM \
+                                             INTERNAL_HT_OPTION_FAM15TN_NB \
+                                             INTERNAL_HT_OPTION_FAM16KB_NB
+
+
+
+
+#else
+  // Not Init Early
+  #define INTERNAL_HT_OPTION_FEATURES     NULL
+  #define INTERNAL_HT_OPTION_INTERFACE    NULL
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
+  #define HT_OPTIONS_PLATFORM             NULL
+  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+#endif
+
+#ifdef AGESA_ENTRY_INIT_EARLY
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+
+    extern HT_FEATURES HtFeaturesDefault;
+    extern HT_FEATURES HtFeaturesCoherentOnly;
+    extern HT_FEATURES HtFeaturesNone;
+    extern HT_INTERFACE HtInterfaceDefault;
+    extern HT_INTERFACE HtInterfaceCoherentOnly;
+    extern HT_INTERFACE HtInterfaceMapsOnly;
+    extern HT_INTERFACE HtInterfaceNone;
+    extern NORTHBRIDGE HtFam15Mod4xNb;
+    extern NORTHBRIDGE HtFam15Mod1xNb;
+    extern NORTHBRIDGE HtFam16Nb;
+
+    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
+      INTERNAL_HT_OPTION_SUPPORTED_NBS
+      NULL
+    };
+
+    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
+    {
+      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
+      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
+      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
+      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
+      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
+      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
+      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
+      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
+    };
+    #ifndef HT_OPTIONS_PLATFORM
+      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
+    #endif
+
+    /**
+     * A list of all the supported topologies.
+     *
+     */
+    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
+      {
+        amdHtTopologySingleNode,
+        amdHtTopologyDualNode,
+        amdHtTopologyThreeLine,
+        amdHtTopologyTriangle,
+        amdHtTopologyFourLine,
+        amdHtTopologyFourStar,
+        amdHtTopologyFourDegenerate,
+        amdHtTopologyFourSquare,
+        amdHtTopologyFourKite,
+        amdHtTopologyFourFully,
+        amdHtTopologyFiveFully,
+        amdHtTopologyFiveTwistedLadder,
+        amdHtTopologySixFully,
+        amdHtTopologySixDoubloonLower,
+        amdHtTopologySixDoubloonUpper,
+        amdHtTopologySixTwistedLadder,
+        amdHtTopologySevenFully,
+        amdHtTopologySevenTwistedLadder,
+        amdHtTopologyEightFully,
+        amdHtTopologyEightDoubloon,
+        amdHtTopologyEightTwistedLadder,
+        amdHtTopologyEightStraightLadder,
+        amdHtTopologySixTwinTriangles,
+        amdHtTopologyEightTwinFullyFourWays,
+        NULL
+      };
+      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
+    #endif
+
+    /**
+     * Declare the instance of the Ht option configuration structure
+     */
+    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
+      OPTION_IS_RECOVERY_HT,
+      CFG_SET_HTCRC_SYNC_FLOOD,
+      CFG_USE_UNIT_ID_CLUMPING,
+      HT_OPTIONS_PLATFORM,
+      INTERNAL_HT_OPTION_INTERFACE,
+      INTERNAL_HT_OPTION_FEATURES,
+      &HtInstalledFamilyNorthbridgeList,
+      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+    };
+
+  #endif
+#endif
+
+#ifndef OPTION_HT_INIIT_RESET_ENTRY
+
+  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+  #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
+
+  #if ((OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY16H == TRUE))
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY NULL
+    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
+  #endif
+
+#endif
+
+#ifdef AGESA_ENTRY_INIT_RESET
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+
+    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      0                                            // Unused by options
+    };
+
+    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
+      OPTION_HT_INIIT_RESET_ENTRY,
+      OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    };
+  #endif
+
+#endif
+
+#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionHtcInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionHtcInstall.h
new file mode 100644
index 0000000..8f5079c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionHtcInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Hardware Thermal Control (HTC).
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HTC_INSTALL_H_
+#define _OPTION_HTC_INSTALL_H_
+
+#include "cpuHtc.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_HTC_FEAT
+#define F15_TN_HTC_SUPPORT
+#define F16_KB_HTC_SUPPORT
+
+#if OPTION_CPU_HTC == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
+          #undef OPTION_CPU_HTC_FEAT
+          #define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
+          extern CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport;
+          #undef F15_TN_HTC_SUPPORT
+          #define F15_TN_HTC_SUPPORT {AMD_FAMILY_15_TN, &F15TnHtcSupport},
+        #endif
+      #endif
+    #endif
+
+    // Family 16h
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
+          #undef OPTION_CPU_HTC_FEAT
+          #define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
+          extern CONST HTC_FAMILY_SERVICES ROMDATA F16KbHtcSupport;
+          #undef F16_KB_HTC_SUPPORT
+          #define F16_KB_HTC_SUPPORT {AMD_FAMILY_16_KB, &F16KbHtcSupport},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtcFamilyServiceArray[] =
+{
+  F15_TN_HTC_SUPPORT
+  F16_KB_HTC_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtcFamilyServiceTable =
+{
+  (sizeof (HtcFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &HtcFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_HTC_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
new file mode 100644
index 0000000..b5a566f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
@@ -0,0 +1,506 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option Install File
+ *
+ * This file generates the defaults tables for family 10h model 5 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_INSTALL_H_
+#define _OPTION_IDS_INSTALL_H_
+#include "Ids.h"
+#include "IdsHt.h"
+#include "IdsLib.h"
+#include "IdsDebugPrint.h"
+#ifdef __IDS_EXTENDED__
+  #include OPTION_IDS_EXT_INSTALL_FILE
+#endif
+
+#define IDS_LATE_RUN_AP_TASK
+
+#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    // Check for all families which include HT Features.To add new family support replace FALSE
+    #if (FALSE) && (AGESA_ENTRY_INIT_POST == TRUE)
+      #undef M_HTIDS_PORT_OVERRIDE_HOOK
+      #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
+    #endif
+  #endif
+#endif // OPTION_IDS_LEVEL
+CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
+
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+    #undef IDS_LATE_RUN_AP_TASK
+    #define IDS_LATE_RUN_AP_TASK  {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate},
+  #endif
+#endif // OPTION_IDS_LEVEL
+
+#if (IDSOPT_TRACING_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+    #include <mu.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+      { (UINT32) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+      { (UINT32) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
+    };
+  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+    #include <mru.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+      { (UINT32) (UINT64) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
+      { (UINT32) (UINT64) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
+    };
+  #else
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+      { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
+      { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
+    };
+  #endif
+#else
+  CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+    { (UINT32) CommonReturnFalse, "DefRet()"},
+    { (UINT32) CommonReturnFalse,  "DefRet()"},
+    { (UINT32) CommonReturnFalse,    "DefRet()"}
+  };
+#endif
+
+
+#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
+#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
+       ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
+        (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
+        (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
+    #if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
+      #define OPTION_IDS_NV_TO_CMOS_COMMON
+
+      //Family 15h TN
+      #ifdef OPTION_FAMILY15H_TN
+        #if OPTION_FAMILY15H_TN == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F15_TN\
+            {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
+        #endif
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
+        #define OPTION_IDS_NV_TO_CMOS_F15_TN
+      #endif
+
+
+      //Family 16h KB
+      #ifdef OPTION_FAMILY16H_KB
+        #if OPTION_FAMILY16H_KB == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F16_KB\
+            {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
+        #endif
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F16_KB
+        #define OPTION_IDS_NV_TO_CMOS_F16_KB
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
+        #define OPTION_IDS_NV_TO_CMOS_EXTEND
+      #endif
+
+      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+        OPTION_IDS_NV_TO_CMOS_COMMON
+        OPTION_IDS_NV_TO_CMOS_F15_TN
+        OPTION_IDS_NV_TO_CMOS_F16_KB
+        OPTION_IDS_NV_TO_CMOS_EXTEND
+        OPTION_IDS_NV_TO_CMOS_END
+      };
+    #else
+      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+        OPTION_IDS_NV_TO_CMOS_END
+      };
+    #endif
+  #else
+    IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+      OPTION_IDS_NV_TO_CMOS_END
+    };
+  #endif
+#else
+  IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+    OPTION_IDS_NV_TO_CMOS_END
+  };
+#endif
+
+///Ids Feat Options
+#if ((IDSOPT_IDS_ENABLED == TRUE) && \
+     ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
+      (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
+      (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    #ifndef OPTION_IDS_EXTEND_FEATS
+      #define OPTION_IDS_EXTEND_FEATS
+    #endif
+
+    #define OPTION_IDS_FEAT_ECCCTRL
+
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN \
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
+
+
+    #define OPTION_IDS_FEAT_CPB_CTRL
+
+    #define OPTION_IDS_FEAT_HTC_CTRL\
+                OPTION_IDS_FEAT_HTC_CTRL_F15_TN \
+                OPTION_IDS_FEAT_HTC_CTRL_F16_KB
+
+
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING\
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN \
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
+
+
+    #define OPTION_IDS_FEAT_HT_ASSIST
+
+/*----------------------------------------------------------------------------
+ *                        Family 15 TN feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+    #ifdef OPTION_FAMILY15H_TN
+      #if OPTION_FAMILY15H_TN == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
+        #undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+        #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
+                    &IdsFeatHtcControlBlockF15Tn,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
+        &IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
+        &IdsFeatMemoryMappingChIntlvBlockF15Tn,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
+      #endif
+    #endif
+
+
+/*----------------------------------------------------------------------------
+ *                        Family 16 KB feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_HTC_CTRL_F16_KB
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
+    #ifdef OPTION_FAMILY16H_KB
+      #if OPTION_FAMILY16H_KB == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF16Kb;
+        #undef OPTION_IDS_FEAT_HTC_CTRL_F16_KB
+        #define OPTION_IDS_FEAT_HTC_CTRL_F16_KB\
+                    &IdsFeatHtcControlBlockF16Kb,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF16Kb;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB\
+        &IdsFeatMemoryMappingPostBeforeBlockF16Kb,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF16Kb;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB &IdsFeatGnbPlatformCfgBlockF16Kb,
+      #endif
+    #endif
+
+    #define OPTION_IDS_FEAT_NV_TO_CMOS
+    #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+      #undef OPTION_IDS_FEAT_NV_TO_CMOS
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
+      #define OPTION_IDS_FEAT_NV_TO_CMOS\
+        &IdsFeatNvToCmosSaveBlock, \
+        &IdsFeatNvToCmosRestoreBlock,
+
+    #endif
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
+    {
+      IDS_FEAT_UCODE_UPDATE,
+      IDS_ALL_CORES,
+      IDS_UCODE,
+      IDS_FAMILY_ALL,
+      IdsSubUCode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
+    {
+      IDS_FEAT_POWER_POLICY,
+      IDS_ALL_CORES,
+      IDS_PLATFORMCFG_OVERRIDE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerPolicyOverride
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
+    {
+      IDS_FEAT_TARGET_PSTATE,
+      IDS_BSP_ONLY,
+      IDS_INIT_LATE_AFTER,
+      IDS_FAMILY_ALL,
+      IdsSubTargetPstate
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
+    {
+      IDS_FEAT_POSTPSTATE,
+      IDS_ALL_CORES,
+      IDS_CPU_Early_Override,
+      IDS_FAMILY_ALL,
+      IdsSubPostPState
+    };
+
+    //Dram controller Features
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
+    {
+      IDS_FEAT_DCT_ALLMEMCLK,
+      IDS_BSP_ONLY,
+      IDS_ALL_MEMORY_CLOCK,
+      IDS_FAMILY_ALL,
+      IdsSubAllMemClkEn
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
+    {
+      IDS_FEAT_DCT_GANGMODE,
+      IDS_BSP_ONLY,
+      IDS_GANGING_MODE,
+      IDS_FAMILY_ALL,
+      IdsSubGangingMode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_INIT_POST_BEFORE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerDownCtrl
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_POWERDOWN_MODE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerDownMode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
+    {
+      IDS_FEAT_HDTOUT,
+      IDS_BSP_ONLY,
+      IDS_INIT_EARLY_BEFORE,
+      IDS_FAMILY_ALL,
+      IdsSubHdtOut
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
+    {
+      IDS_FEAT_HT_SETTING,
+      IDS_BSP_ONLY,
+      IDS_HT_CONTROL,
+      IDS_FAMILY_ALL,
+      IdsSubHtLinkControl
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
+    {
+      &IdsFeatUcodeBlock,
+      &IdsFeatPowerPolicyBlock,
+
+      &IdsFeatTargetPstateBlock,
+
+      &IdsFeatPostPstateBlock,
+
+      OPTION_IDS_FEAT_NV_TO_CMOS
+
+      OPTION_IDS_FEAT_ECCCTRL
+
+      &IdsFeatDctAllMemClkBlock,
+
+      &IdsFeatDctGangModeBlock,
+
+      &IdsFeatDctPowerDownCtrlBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      OPTION_IDS_FEAT_HT_ASSIST
+
+      &IdsFeatHdtOutBlock,
+
+      &IdsFeatHtSettingBlock,
+
+      OPTION_IDS_FEAT_GNB_PLATFORMCFG
+
+      OPTION_IDS_FEAT_CPB_CTRL
+
+      OPTION_IDS_FEAT_HTC_CTRL
+
+      OPTION_IDS_FEAT_MEMORY_MAPPING
+
+      OPTION_IDS_EXTEND_FEATS
+
+      NULL
+    };
+  #else
+    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
+    {
+      NULL
+    };
+  #endif//IDSOPT_CONTROL_ENABLED
+
+  #define OPTION_IDS_FAM_REGACC_F15TN
+  #ifdef OPTION_FAMILY15H_TN
+    #if OPTION_FAMILY15H_TN == TRUE
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
+      #undef OPTION_IDS_FAM_REGACC_F15TN
+      #define OPTION_IDS_FAM_REGACC_F15TN \
+                &IdsFeatRegGmmxF15Tn,
+    #endif
+  #endif
+
+
+  #define OPTION_IDS_FAM_REGACC_F16KB
+  #ifdef OPTION_FAMILY16H_KB
+    #if OPTION_FAMILY16H_KB == TRUE
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF16Kb;
+      #undef OPTION_IDS_FAM_REGACC_F16KB
+      #define OPTION_IDS_FAM_REGACC_F16KB \
+                &IdsFeatRegGmmxF16Kb,
+    #endif
+  #endif
+
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
+  {
+    OPTION_IDS_FAM_REGACC_F15TN
+    OPTION_IDS_FAM_REGACC_F16KB
+    NULL
+  };
+
+/*----------------------------------------------------------------------------
+ *                        IDS TRACING SERVICES
+ *
+ *----------------------------------------------------------------------------
+ */
+  #if IDSOPT_TRACING_ENABLED == TRUE
+    #define IDS_TRACING_CONSOLE_HDTOUT
+    #define IDS_TRACING_CONSOLE_SERIALPORT
+    #define IDS_TRACING_CONSOLE_REDIRECT_IO
+    #define IDS_TRACING_CONSOLE_RAM
+
+    #ifdef IDSOPT_TRACING_CONSOLE_HDTOUT
+      #if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
+        #undef IDS_TRACING_CONSOLE_HDTOUT
+        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintHdtoutInstance;
+        #define IDS_TRACING_CONSOLE_HDTOUT &IdsDebugPrintHdtoutInstance,
+      #endif
+    #endif
+
+    #ifdef IDSOPT_TRACING_CONSOLE_SERIALPORT
+      #if IDSOPT_TRACING_CONSOLE_SERIALPORT == TRUE
+        #undef IDS_TRACING_CONSOLE_SERIALPORT
+        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintSerialInstance;
+        #define IDS_TRACING_CONSOLE_SERIALPORT &IdsDebugPrintSerialInstance,
+      #endif
+    #endif
+
+    #ifdef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+      #if IDSOPT_TRACING_CONSOLE_REDIRECT_IO == TRUE
+        #undef IDS_TRACING_CONSOLE_REDIRECT_IO
+        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRedirectIoInstance;
+        #define IDS_TRACING_CONSOLE_REDIRECT_IO &IdsDebugPrintRedirectIoInstance,
+      #endif
+    #endif
+
+    #ifdef IDSOPT_TRACING_CONSOLE_RAM
+      #if IDSOPT_TRACING_CONSOLE_RAM == TRUE
+        #undef IDS_TRACING_CONSOLE_RAM
+        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRamInstance;
+        #define IDS_TRACING_CONSOLE_RAM &IdsDebugPrintRamInstance,
+      #endif
+    #endif
+
+
+    CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
+    {
+      IDS_TRACING_CONSOLE_SERIALPORT
+      IDS_TRACING_CONSOLE_HDTOUT
+      IDS_TRACING_CONSOLE_REDIRECT_IO
+      IDS_TRACING_CONSOLE_RAM
+      NULL
+    };
+  #else
+    CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
+    {
+      NULL
+    };
+  #endif
+
+#else
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
+  {
+    NULL
+  };
+
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
+  {
+    NULL
+  };
+
+  CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
+  {
+    NULL
+  };
+#endif// IDSOPT_IDS_ENABLED
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionIoCstateInstall.h
new file mode 100644
index 0000000..e466c9e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionIoCstateInstall.h
@@ -0,0 +1,103 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: IO C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_IO_CSTATE_INSTALL_H_
+#define _OPTION_IO_CSTATE_INSTALL_H_
+
+#include "cpuIoCstate.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define OPTION_IO_CSTATE_FEAT
+#define F15_TN_IO_CSTATE_SUPPORT
+#define F16_KB_IO_CSTATE_SUPPORT
+
+#if OPTION_IO_CSTATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport;
+          #undef F15_TN_IO_CSTATE_SUPPORT
+          #define F15_TN_IO_CSTATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnIoCstateSupport},
+        #endif
+
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F16KbIoCstateSupport;
+          #undef F16_KB_IO_CSTATE_SUPPORT
+          #define F16_KB_IO_CSTATE_SUPPORT {AMD_FAMILY_16_KB, &F16KbIoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
+{
+  F15_TN_IO_CSTATE_SUPPORT
+  F16_KB_IO_CSTATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
+{
+  (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &IoCstateFamilyServiceArray[0]
+};
+
+#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
new file mode 100644
index 0000000..8d34603
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
@@ -0,0 +1,79 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: L3 Dependent Features
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_L3_FEATURES_INSTALL_H_
+#define _OPTION_L3_FEATURES_INSTALL_H_
+
+#include "cpuL3Features.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_L3_FEAT
+#define L3_FEAT_AP_DISABLE_CACHE
+#define L3_FEAT_AP_ENABLE_CACHE
+
+#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE)
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+
+    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+    #undef L3_FEAT_AP_DISABLE_CACHE
+    #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
+    #undef L3_FEAT_AP_ENABLE_CACHE
+    #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
+{
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
+{
+  (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &L3FeatureFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_L3_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionLowPwrPstateInstall.h
new file mode 100644
index 0000000..3834bd4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionLowPwrPstateInstall.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
+#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
+#define F15_OR_LOW_PWR_PSTATE_SUPPORT
+
+
+#endif  // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h
new file mode 100644
index 0000000..23b5109
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h
@@ -0,0 +1,365 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 85859 $   @e \$Date: 2013-01-14 02:57:14 -0600 (Mon, 14 Jan 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_H_
+#define _OPTION_MEMORY_H_
+
+/* Memory Includes */
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mp.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MAX_FF_TYPES      6   ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+* STANDARD MEMORY FEATURE FUNCTION POINTER
+*/
+
+typedef BOOLEAN OPTION_MEM_FEATURE_NB (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+typedef BOOLEAN MEM_TECH_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+typedef UINT8 MEM_TABLE_FEAT (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+
+#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION  0x01
+
+/**
+ *  MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Northbridge devices supported by
+ *  AGESA.
+ */
+typedef struct _MEM_FEAT_BLOCK_NB {
+  UINT16              OptMemFeatVersion; ///< Version of memory feature block.
+  OPTION_MEM_FEATURE_NB  *OnlineSpare; ///< Online spare support.
+  OPTION_MEM_FEATURE_NB  *InterleaveBanks; ///< Bank (Chip select) interleaving support.
+  OPTION_MEM_FEATURE_NB  *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
+  OPTION_MEM_FEATURE_NB  *CheckInterleaveNodes; ///< Check for Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveNodes; ///< Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveChannels; ///< Channel interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveRegion;  ///< Interleave Region support.
+  OPTION_MEM_FEATURE_NB  *CheckEcc; ///< Check for ECC support.
+  OPTION_MEM_FEATURE_NB  *InitEcc; ///< ECC support.
+  OPTION_MEM_FEATURE_NB  *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
+  OPTION_MEM_FEATURE_NB  *LvDdr3; ///< Low voltage DDR3 dimm support
+  OPTION_MEM_FEATURE_NB  *OnDimmThermal; ///< On-Dimm thermal management
+  MEM_TECH_FEAT          *DramInit; ///< Choose the type of Dram init (hardware based or software based).
+  OPTION_MEM_FEATURE_NB  *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_NB  *InitEarlySampleSupport; ///< Initialize early sample support.
+  OPTION_MEM_FEATURE_NB  *InitCPG; ///< Continuous pattern generation.
+  OPTION_MEM_FEATURE_NB  *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
+  OPTION_MEM_FEATURE_NB  *InitAMP; ///< AMP initialization.
+  OPTION_MEM_FEATURE_NB  *DataEye; ///< Get 2D training data eye.
+  OPTION_MEM_FEATURE_NB  *InitRdWr2DTraining; ///< Initialize Read and/or Write 2D Training Feature.
+  OPTION_MEM_FEATURE_NB  *AggressorInit; ///< Aggressor initialization.
+} MEM_FEAT_BLOCK_NB;
+
+typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+typedef BOOLEAN MEM_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *mmSharedPtr,     ///< Pointer to Memory scratchpad
+  IN       UINT8 NodeID
+  );
+
+typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+typedef VOID MEM_INITIALIZER (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+ );
+
+typedef AGESA_STATUS MEM_PLATFORM_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN UINT8 SocketID,
+  IN CH_DEF_STRUCT *CurrentChannel
+  );
+
+typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_TECH_TRAINING_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+typedef AGESA_STATUS MEM_FLOW_CFG (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemData
+  );
+
+#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION  0x01
+
+/**
+ * MAIN FEATURE BLOCK - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_BLOCK_MAIN {
+  UINT16              OptMemFeatVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
+  OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
+  OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
+  OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
+  OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
+  OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
+  OPTION_MEM_FEATURE_MAIN *MemCrat; ///< Memory CRAT Support.
+  OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
+  OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
+  OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
+  OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
+  OPTION_MEM_FEATURE_MAIN *MemS3Save; ///< Memory S3 Save
+  OPTION_MEM_FEATURE_MAIN *AggressorDetermination; ///< Aggressor Chipselects for all DCTs on all nodes.
+} MEM_FEAT_BLOCK_MAIN;
+
+#define MEM_NB_SUPPORT_STRUCT_VERSION  0x01
+#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION  0x01
+#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION  0x01
+#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
+/**
+ *  MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_FEAT_BLOCK {
+  UINT16  OptMemTechFeatVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
+  MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
+  MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
+  MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
+  MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
+  MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
+  MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
+  MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
+  MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
+  MEM_TECH_FEAT *RdDqs2DTraining; ///< 2D Rd DQS Training
+} MEM_TECH_FEAT_BLOCK;
+
+/**
+ *  MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various LRDIMM features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_LRDIMM {
+  UINT16  OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
+} MEM_TECH_LRDIMM;
+
+/**
+ * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
+ * options together in a list to provide a single access point for all code to use
+ * and to ensure that everything corresponding to the same NB type is grouped together.
+ *
+ * The Technology Block pointers are not included in this structure because DRAM technology
+ * needs to be decoupled from the northbridge type.
+ *
+ */
+typedef struct _MEM_NB_SUPPORT {
+  UINT16              MemNBSupportVersion; ///< Version of northbridge support.
+  MEM_NB_CONSTRUCTOR  *MemConstructNBBlock; ///< NorthBridge block constructor.
+  MEM_INITIALIZER     *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
+  MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
+  MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
+  MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
+} MEM_NB_SUPPORT;
+
+/*
+ *  MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
+ *  memory non-training feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology devices supported by
+ *  AGESA.
+ */
+
+/**
+ * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_TRAIN_SEQ {
+  UINT16              OptMemTrainingSequenceListVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
+  OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
+  MEM_TECH_FEAT_BLOCK      *MemTechFeatBlock; ///< Memory feature block.
+} MEM_FEAT_TRAIN_SEQ;
+
+/**
+ * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
+ * entries which are used by PSC engine
+ */
+typedef struct _MEM_PSC_TABLE_BLOCK {
+  PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
+  PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
+  PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
+  PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
+  PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
+  PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
+  PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
+  PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
+  PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
+  PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
+  PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
+  PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
+  PSC_TBL_ENTRY **TblEntryOfS2D; ///< Table entry of 2D training configs
+  PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed
+  PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed
+} MEM_PSC_TABLE_BLOCK;
+
+typedef BOOLEAN MEM_PSC_FLOW (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/**
+ * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
+ * specific configuration.
+ */
+typedef struct _MEM_PSC_FLOW_BLOCK {
+  MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
+  MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
+  MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
+  MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
+  MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
+  MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
+  MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
+  MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
+  MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
+  MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
+  MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
+  MEM_PSC_FLOW *S2D; ///< Sub-engine which performs 2D training configuration  checking
+  MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction
+} MEM_PSC_FLOW_BLOCK;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+/* Feature Default Return */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN MemMDefRet (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+/* Table Feature Default Return */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+/* S3 Feature Default Return */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemProcessConditionalOverrides (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 PsoAction,
+  IN       UINT8 Dimm
+   );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
new file mode 100644
index 0000000..07becd2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
@@ -0,0 +1,1629 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 85859 $   @e \$Date: 2013-01-14 02:57:14 -0600 (Mon, 14 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_INSTALL_H_
+#define _OPTION_MEMORY_INSTALL_H_
+
+/* Memory Includes */
+#include "OptionMemory.h"
+
+/*-------------------------------------------------------------------------------
+ *  This option file is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+/*----------------------------------------------------------------------------------
+ * FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return FALSE;
+}
+
+BOOLEAN MemMDefRet (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return TRUE;
+}
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return FALSE;
+}
+/*----------------------------------------------------------------------------------
+ * TABLE FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  )
+{
+  return 0;
+}
+/*----------------------------------------------------------------------------------
+ * FEATURE S3 BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return TRUE;
+}
+
+#if (OPTION_MEMCTLR_TN == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) || ((AGESA_ENTRY_INIT_POST) && (OPTION_S3_MEM_SUPPORT == TRUE)))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockTN;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemS3ResumeConstructNBBlockTN
+      #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+        extern OPTION_MEM_FEATURE_MAIN MemMS3Save;
+        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMS3Save
+      #else
+        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
+      #endif
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet
+      #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet
+    #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorTN;
+    #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorTN
+  #else
+    #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+
+#if (OPTION_MEMCTLR_KB == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) || ((AGESA_ENTRY_INIT_POST) && (OPTION_S3_MEM_SUPPORT == TRUE)))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockKB;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB MemS3ResumeConstructNBBlockKB
+      #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+        extern OPTION_MEM_FEATURE_MAIN MemMS3Save;
+        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMS3Save
+      #else
+        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
+      #endif
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB MemFS3DefConstructorRet
+      #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB MemFS3DefConstructorRet
+    #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorKB;
+    #define MEM_IDENDIMM_KB MemNIdentifyDimmConstructorKB
+  #else
+    #define MEM_IDENDIMM_KB MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+
+
+/*----------------------------------------------------------------------------------
+ * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
+ *
+ *----------------------------------------------------------------------------------
+*/
+#define MEM_NB_SUPPORT_TN
+#define MEM_NB_SUPPORT_KB
+#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
+
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+  /*----------------------------------------------------------------------------------
+   * FLOW CONTROL FUNCTION
+   *
+   *  This section selects the function that controls the memory initialization sequence
+   *  based upon the number of processor families that the BIOS will support.
+   */
+  extern MEM_FLOW_CFG MemMFlowDef;
+
+  #if (OPTION_MEMCTLR_TN == TRUE)
+    extern MEM_FLOW_CFG MemMFlowTN;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowTN,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowDef,
+  #endif
+
+
+  #if (OPTION_MEMCTLR_KB == TRUE)
+    extern MEM_FLOW_CFG MemMFlowKB;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_KB MemMFlowKB,
+  #else
+    extern MEM_FLOW_CFG MemMFlowDef;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_KB MemMFlowDef,
+  #endif
+
+
+  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+    MEM_MAIN_FLOW_CONTROL_PTR_TN
+    MEM_MAIN_FLOW_CONTROL_PTR_KB
+    NULL
+  };
+
+  #if (OPTION_ONLINE_SPARE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
+    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
+    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
+  #else
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
+    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
+  #endif
+
+  #if (OPTION_MEM_RESTORE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
+    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
+  #else
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
+  #endif
+
+  #if (OPTION_BANK_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
+    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
+  #else
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
+  #endif
+
+  #if (OPTION_NODE_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
+    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
+  #else
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
+  #endif
+
+  #if (OPTION_DCT_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
+  #else
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
+  #endif
+
+  #if (OPTION_ECC == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
+    #define MEM_MAIN_FEATURE_ECC  MemMEcc
+    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
+    extern OPTION_MEM_FEATURE_NB MemFInitECC;
+    #define MEM_FEATURE_CK_ECC   MemFCheckECC
+    #define MEM_FEATURE_ECC   MemFInitECC
+    #define MEM_FEATURE_ECCX8  MemMDefRet
+  #else
+    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
+    #define MEM_FEATURE_CK_ECC   MemFDefRet
+    #define MEM_FEATURE_ECC   MemFDefRet
+    #define MEM_FEATURE_ECCX8  MemMDefRet
+  #endif
+
+  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
+  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
+
+  #if (OPTION_AGGRESSOR == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMAggressor;
+    #define MEM_MAIN_FEATURE_AGGRESSOR  MemMAggressor
+    extern OPTION_MEM_FEATURE_NB MemFAggressorInit;
+    #define MEM_FEATURE_AGGRESSOR  MemFAggressorInit
+  #else //#if (OPTION_AGGRESSOR == FALSE)
+    #define MEM_MAIN_FEATURE_AGGRESSOR  MemMDefRet
+    #define MEM_FEATURE_AGGRESSOR  MemFDefRet
+  #endif
+
+  #if (OPTION_DMI == TRUE)
+    #if (OPTION_DDR3 == TRUE)
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
+    #else
+      #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
+    #endif
+  #else
+    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
+  #endif
+
+  #if (OPTION_CRAT == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemFCratSupport;
+    #define MEM_MAIN_FEATURE_MEM_CRAT MemFCratSupport
+  #else
+    #define MEM_MAIN_FEATURE_MEM_CRAT MemMDefRet
+  #endif
+
+  #if (OPTION_DDR3 == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
+    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
+    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
+    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
+  #else
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
+    #define MEM_FEATURE_LVDDR3 MemFDefRet
+  #endif
+
+  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
+  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
+
+  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
+  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
+
+  #if (OPTION_PARALLEL_TRAINING == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
+  #else
+    #ifndef EXTERN_MEMMSTANDARDTRAINING
+    #define EXTERN_MEMMSTANDARDTRAINING
+        extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #endif
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+  #endif
+
+  #if (OPTION_DIMM_EXCLUDE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
+    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
+  #else
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
+  #endif
+
+  #if (OPTION_AMP == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFAMP;
+    #define MEM_FEATURE_AMP  MemFAMP
+  #else
+    #define MEM_FEATURE_AMP  MemFDefRet
+  #endif
+
+  #if (OPTION_DATA_EYE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemF2DDataEyeInit;
+    #define MEM_FEATURE_DATA_EYE  MemF2DDataEyeInit
+  #else //#if (OPTION_DATA_EYE == FALSE)
+    #define MEM_FEATURE_DATA_EYE  MemFDefRet
+  #endif
+
+  /*----------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
+   *
+   *----------------------------------------------------------------------------------
+  */
+  #if OPTION_DDR2 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
+    #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+#endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR2
+  #endif
+  #if OPTION_DDR3 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
+    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+  /*---------------------------------------------------------------------------------------------------
+   * FEATURE BLOCKS
+   *
+   *  This section instantiates a feature block structure for each memory controller installed
+   *  by the platform solution install file.
+   *---------------------------------------------------------------------------------------------------
+   */
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * TRINITY FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_TN == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_MAIN_FEATURE_LVDDR3
+      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
+      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_EARLY_SAMPLES == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportTN;
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportTN
+    #else
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
+    #else
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #if (OPTION_RDDQS_2D_TRAINING == TRUE)
+      extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies;
+      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTrainingUsingAdjacentDies
+    #else
+      extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #endif
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockTN = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MemFDefRet,
+      MemFDefRet,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MEM_FEATURE_REGION_INTERLEAVE,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_EARLY_SAMPLE_SUPPORT,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN,
+      MEM_FEATURE_AMP,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet
+    };
+
+    #undef MEM_NB_SUPPORT_TN
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockTN;
+    extern MEM_INITIALIZER MemNInitDefaultsTN;
+    #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockTN, MemNInitDefaultsTN, &MemFeatBlockTN, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN },
+  #endif // OPTION_MEMCTRL_TN
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * KABINI FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_KB == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_MAIN_FEATURE_LVDDR3
+      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
+      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_EARLY_SAMPLES == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportKB;
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportKB
+    #else
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
+    #else
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #if (OPTION_RDDQS_2D_TRAINING == TRUE)
+      extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies;
+      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTrainingUsingAdjacentDies
+      extern OPTION_MEM_FEATURE_NB MemFRdWr2DTrainingInitKB;
+      #define MEM_FEATURE_RDWR_2D_TRAINING MemFRdWr2DTrainingInitKB
+    #else
+      #ifndef EXTERN_MEMMSTANDARDTRAINING
+      #define EXTERN_MEMMSTANDARDTRAINING
+        extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+      #endif
+      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+      #define MEM_FEATURE_RDWR_2D_TRAINING MemFDefRet
+    #endif
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockKB = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_EARLY_SAMPLE_SUPPORT,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN,
+      MemFDefRet,
+      MemFDefRet,
+      MEM_FEATURE_RDWR_2D_TRAINING,
+      MemFDefRet
+    };
+
+    #undef MEM_NB_SUPPORT_KB
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockKB;
+    extern MEM_INITIALIZER MemNInitDefaultsKB;
+    #define MEM_NB_SUPPORT_KB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockKB, MemNInitDefaultsKB, &MemFeatBlockKB, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB, MEM_IDENDIMM_KB },
+  #endif // OPTION_MEMCTRL_KB
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
+    MEM_MAIN_FEATURE_TRAINING,
+    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
+    MEM_MAIN_FEATURE_ONLINE_SPARE,
+    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
+    MEM_MAIN_FEATURE_ECC,
+    MEM_MAIN_FEATURE_MEM_CLEAR,
+    MEM_MAIN_FEATURE_MEM_DMI,
+    MEM_MAIN_FEATURE_MEM_CRAT,
+    MEM_MAIN_FEATURE_LVDDR3,
+    MEM_MAIN_FEATURE_UMAALLOC,
+    MEM_MAIN_FEATURE_MEM_SAVE,
+    MEM_MAIN_FEATURE_MEM_RESTORE,
+    MEM_MAIN_FEATURE_MEM_S3_SAVE,
+    MEM_MAIN_FEATURE_AGGRESSOR
+  };
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * Technology Training SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
+
+  #if OPTION_MEMCTLR_TN
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceTN;
+    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          extern MEM_TECH_FEAT MemNRdPosTrnTN;
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemNRdPosTrnTN
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_RDDQS_2D_TRAINING == TRUE)
+        #undef TECH_TRAIN_DQS_2D_DDR3
+        #define TECH_TRAIN_DQS_2D_DDR3    MemTAmdRdDqs2DTraining
+      #else
+        #undef TECH_TRAIN_DQS_2D_DDR3
+        #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
+      #endif
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3TN = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS_2D_DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceTN, &memTechTrainingFeatSequenceDDR3TN },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+
+  #if OPTION_MEMCTLR_KB
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceKB;
+    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          extern MEM_TECH_FEAT MemNRdPosTrnKB;
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemNRdPosTrnKB
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_RDDQS_2D_TRAINING == TRUE)
+        extern  MEM_TECH_FEAT MemFAmdRdDqs2DTraining;
+        #undef TECH_TRAIN_DQS_2D_DDR3
+        #define TECH_TRAIN_DQS_2D_DDR3    MemFAmdRdDqs2DTraining
+      #else
+        #undef TECH_TRAIN_DQS_2D_DDR3
+        #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
+      #endif
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3KB = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS_2D_DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceKB, &memTechTrainingFeatSequenceDDR3KB },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+
+
+  #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
+  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
+  };
+
+  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NB_TRAIN_FLOW_DDR2,
+    NB_TRAIN_FLOW_DDR3,
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+    MEM_TECH_CONSTRUCTOR_DDR2
+    MEM_TECH_CONSTRUCTOR_DDR3
+    NULL
+  };
+   /*---------------------------------------------------------------------------------------------------
+   * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  /*---------------------------------------------------------------------------------------------------
+   * PLATFORM-SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+
+  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+    NULL
+  };
+  CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
+
+  /*---------------------------------------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_PSC_FLOW_BLOCK_END NULL
+  #define PSC_TBL_END NULL
+  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
+
+  #define PSC_TBL_TN_UDIMM3_S2D_FM2
+  #define PSC_TBL_TN_SODIMM3_S2D_FS1
+  #define PSC_TBL_TN_SODIMM3_S2D_FP2
+  #define PSC_TBL_TN_SODIMM3_S2D_FM2
+  #if OPTION_MEMCTLR_TN
+    #if OPTION_FS1_SOCKET_SUPPORT
+      extern PSC_TBL_ENTRY TNClkDisMapEntSOFS1;
+      #define PSC_TBL_TN_CLK_DIS_FS1 &TNClkDisMapEntSOFS1,
+      extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFS1;
+      #define PSC_TBL_TN_ODT_TRI_FS1 &TNSODdr3ODTTriEntFS1,
+      extern PSC_TBL_ENTRY TNSODdr3CSTriEntFS1;
+      #define PSC_TBL_TN_CS_TRI_FS1 &TNSODdr3CSTriEntFS1,
+    #endif
+    #if (OPTION_FM2_SOCKET_SUPPORT || OPTION_FM2r2_SOCKET_SUPPORT)
+      extern PSC_TBL_ENTRY TNClkDisMapEntUFM2;
+      #define PSC_TBL_TN_CLK_DIS_FM2 &TNClkDisMapEntUFM2,
+      extern PSC_TBL_ENTRY TNUDdr3ODTTriEntFM2;
+      #define PSC_TBL_TN_ODT_TRI_FM2 &TNUDdr3ODTTriEntFM2,
+      extern PSC_TBL_ENTRY TNUDdr3CSTriEntFM2;
+      #define PSC_TBL_TN_CS_TRI_FM2 &TNUDdr3CSTriEntFM2,
+    #endif
+    #if OPTION_FP2_SOCKET_SUPPORT
+      extern PSC_TBL_ENTRY TNClkDisMapEntSOFP2;
+      #define PSC_TBL_TN_CLK_DIS_FP2 &TNClkDisMapEntSOFP2,
+      extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFP2;
+      #define PSC_TBL_TN_ODT_TRI_FP2 &TNSODdr3ODTTriEntFP2,
+      extern PSC_TBL_ENTRY TNSODdr3CSTriEntFP2;
+      #define PSC_TBL_TN_CS_TRI_FP2 &TNSODdr3CSTriEntFP2,
+    #endif
+    #if OPTION_UDIMMS
+      extern PSC_TBL_ENTRY TNMaxFreqTblEntU;
+      #define PSC_TBL_TN_UDIMM3_MAX_FREQ  &TNMaxFreqTblEntU,
+      extern PSC_TBL_ENTRY RLMaxFreqTblEntU;
+      #define PSC_TBL_RL_UDIMM3_MAX_FREQ  &RLMaxFreqTblEntU,
+      extern PSC_TBL_ENTRY TNDramTermTblEntU;
+      #define PSC_TBL_TN_UDIMM3_DRAM_TERM  &TNDramTermTblEntU,
+      extern PSC_TBL_ENTRY TNSAOTblEntU3;
+      #define PSC_TBL_TN_UDIMM3_SAO  &TNSAOTblEntU3,
+      #if (OPTION_FM2_SOCKET_SUPPORT || OPTION_FM2r2_SOCKET_SUPPORT)
+        extern PSC_TBL_ENTRY TNMaxFreqTblEntUFM2;
+        #define PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2  &TNMaxFreqTblEntUFM2,
+        extern PSC_TBL_ENTRY RLMaxFreqTblEntUFM2;
+        #define PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2  &RLMaxFreqTblEntUFM2,
+        #undef PSC_TBL_TN_UDIMM3_S2D_FM2
+        extern PSC_TBL_ENTRY S2DTblEntUFM2;
+        #define PSC_TBL_TN_UDIMM3_S2D_FM2  &S2DTblEntUFM2,
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      extern PSC_TBL_ENTRY TNSAOTblEntSO3;
+      #define PSC_TBL_TN_SODIMM3_SAO  &TNSAOTblEntSO3,
+      extern PSC_TBL_ENTRY TNDramTermTblEntSO;
+      #define PSC_TBL_TN_SODIMM3_DRAM_TERM  &TNDramTermTblEntSO,
+      #if OPTION_FS1_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY TNMaxFreqTblEntSOFS1;
+        #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1  &TNMaxFreqTblEntSOFS1,
+        #undef PSC_TBL_TN_SODIMM3_S2D_FS1
+        #define PSC_TBL_TN_SODIMM3_S2D_FS1
+      #endif
+      #if (OPTION_FM2_SOCKET_SUPPORT || OPTION_FM2r2_SOCKET_SUPPORT)
+        extern PSC_TBL_ENTRY TNMaxFreqTblEntSO;
+        #define PSC_TBL_TN_SODIMM3_MAX_FREQ  &TNMaxFreqTblEntSO,
+        #undef PSC_TBL_TN_SODIMM3_S2D_FM2
+        extern PSC_TBL_ENTRY S2DTblEntUFM2;
+        #define PSC_TBL_TN_SODIMM3_S2D_FM2 &S2DTblEntUFM2,
+      #endif
+      #if OPTION_FP2_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY TNSAOTblEntSODWNSO3;
+        #define PSC_TBL_TN_SODWN_SODIMM3_SAO  &TNSAOTblEntSODWNSO3,
+        extern PSC_TBL_ENTRY TNDramTermTblEntSODWNSO;
+        #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM  &TNDramTermTblEntSODWNSO,
+        extern PSC_TBL_ENTRY TNMaxFreqTblEntSODWNSO;
+        #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ  &TNMaxFreqTblEntSODWNSO,
+        extern PSC_TBL_ENTRY TNMaxFreqTblEntSOFP2;
+        #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2  &TNMaxFreqTblEntSOFP2,
+        extern PSC_TBL_ENTRY RLMaxFreqTblEntSOFP2;
+        #define PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2  &RLMaxFreqTblEntSOFP2,
+        #undef PSC_TBL_TN_SODIMM3_S2D_FP2
+        #define PSC_TBL_TN_SODIMM3_S2D_FP2
+      #endif
+    #endif
+    extern PSC_TBL_ENTRY TNMR0WrTblEntry;
+    extern PSC_TBL_ENTRY TNMR0CLTblEntry;
+    extern PSC_TBL_ENTRY TNDdr3CKETriEnt;
+    extern PSC_TBL_ENTRY TNOdtPatTblEnt;
+
+
+    #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ
+      #define PSC_TBL_TN_SODIMM3_MAX_FREQ
+    #endif
+    #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
+      #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
+    #endif
+    #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
+      #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
+    #endif
+    #ifndef PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
+      #define PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
+    #endif
+    #ifndef PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ
+      #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ
+    #endif
+    #ifndef PSC_TBL_TN_UDIMM3_MAX_FREQ
+      #define PSC_TBL_TN_UDIMM3_MAX_FREQ
+    #endif
+    #ifndef PSC_TBL_RL_UDIMM3_MAX_FREQ
+      #define PSC_TBL_RL_UDIMM3_MAX_FREQ
+    #endif
+    #ifndef PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2
+      #define PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2
+    #endif
+    #ifndef PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2
+      #define PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2
+    #endif
+    #ifndef PSC_TBL_TN_UDIMM3_DRAM_TERM
+      #define PSC_TBL_TN_UDIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_TN_SODIMM3_DRAM_TERM
+      #define PSC_TBL_TN_SODIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
+      #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_TN_SODIMM3_SAO
+      #define PSC_TBL_TN_SODIMM3_SAO
+    #endif
+    #ifndef PSC_TBL_TN_SODWN_SODIMM3_SAO
+      #define PSC_TBL_TN_SODWN_SODIMM3_SAO
+    #endif
+    #ifndef PSC_TBL_TN_UDIMM3_SAO
+      #define PSC_TBL_TN_UDIMM3_SAO
+    #endif
+    #ifndef PSC_TBL_TN_CLK_DIS_FM2
+      #define PSC_TBL_TN_CLK_DIS_FM2
+    #endif
+    #ifndef PSC_TBL_TN_ODT_TRI_FM2
+      #define PSC_TBL_TN_ODT_TRI_FM2
+    #endif
+    #ifndef PSC_TBL_TN_CS_TRI_FM2
+      #define PSC_TBL_TN_CS_TRI_FM2
+    #endif
+    #ifndef PSC_TBL_TN_CLK_DIS_FS1
+      #define PSC_TBL_TN_CLK_DIS_FS1
+    #endif
+    #ifndef PSC_TBL_TN_ODT_TRI_FS1
+      #define PSC_TBL_TN_ODT_TRI_FS1
+    #endif
+    #ifndef PSC_TBL_TN_CS_TRI_FS1
+      #define PSC_TBL_TN_CS_TRI_FS1
+    #endif
+    #ifndef PSC_TBL_TN_CLK_DIS_FP2
+      #define PSC_TBL_TN_CLK_DIS_FP2
+    #endif
+    #ifndef PSC_TBL_TN_ODT_TRI_FP2
+      #define PSC_TBL_TN_ODT_TRI_FP2
+    #endif
+    #ifndef PSC_TBL_TN_CS_TRI_FP2
+      #define PSC_TBL_TN_CS_TRI_FP2
+    #endif
+
+    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayTN[] = {
+      PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
+      PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
+      PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
+      PSC_TBL_TN_SODIMM3_MAX_FREQ
+      PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ
+      PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2
+      PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2
+      PSC_TBL_TN_UDIMM3_MAX_FREQ
+      PSC_TBL_RL_UDIMM3_MAX_FREQ
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblDramTermArrayTN[] = {
+      PSC_TBL_TN_UDIMM3_DRAM_TERM
+      PSC_TBL_TN_SODIMM3_DRAM_TERM
+      PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblODTPatArrayTN[] = {
+      &TNOdtPatTblEnt,
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblSAOArrayTN[] = {
+      PSC_TBL_TN_SODIMM3_SAO
+      PSC_TBL_TN_SODWN_SODIMM3_SAO
+      PSC_TBL_TN_UDIMM3_SAO
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblMR0WRArrayTN[] = {
+      &TNMR0WrTblEntry,
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblMR0CLArrayTN[] = {
+      &TNMR0CLTblEntry,
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblGenArrayTN[] = {
+      &TNDdr3CKETriEnt,
+      PSC_TBL_TN_CLK_DIS_FM2
+      PSC_TBL_TN_ODT_TRI_FM2
+      PSC_TBL_TN_CS_TRI_FM2
+      PSC_TBL_TN_CLK_DIS_FS1
+      PSC_TBL_TN_ODT_TRI_FS1
+      PSC_TBL_TN_CS_TRI_FS1
+      PSC_TBL_TN_CLK_DIS_FP2
+      PSC_TBL_TN_ODT_TRI_FP2
+      PSC_TBL_TN_CS_TRI_FP2
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblS2DArrayTN[] = {
+      PSC_TBL_TN_UDIMM3_S2D_FM2
+      PSC_TBL_TN_SODIMM3_S2D_FS1
+      PSC_TBL_TN_SODIMM3_S2D_FP2
+      PSC_TBL_TN_SODIMM3_S2D_FM2
+      PSC_TBL_END
+    };
+
+    MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = {
+      (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN,
+      (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN,
+      (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN,
+      (PSC_TBL_ENTRY **)&memPSCTblSAOArrayTN,
+      (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayTN,
+      (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayTN,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      (PSC_TBL_ENTRY **)&memPSCTblGenArrayTN,
+      (PSC_TBL_ENTRY **)&memPSCTblS2DArrayTN,
+      NULL,
+      NULL
+    };
+
+    extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
+    extern MEM_PSC_FLOW MemPGetRttNomWr;
+    extern MEM_PSC_FLOW MemPGetODTPattern;
+    extern MEM_PSC_FLOW MemPGetSAO;
+    extern MEM_PSC_FLOW MemPGetMR0WrCL;
+    extern MEM_PSC_FLOW MemPGetS2D;
+
+    MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = {
+      &memPSCTblBlockTN,
+      MemPGetMaxFreqSupported,
+      MemPGetRttNomWr,
+      MemPGetODTPattern,
+      MemPGetSAO,
+      MemPGetMR0WrCL,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MemPGetS2D,
+      MEM_PSC_FLOW_DEFTRUE
+    };
+    #define MEM_PSC_FLOW_BLOCK_TN &memPlatSpecFlowTN,
+  #else
+    #define MEM_PSC_FLOW_BLOCK_TN
+  #endif
+
+
+  #define PSC_TBL_KB_UDIMM3_S2D_FT3
+  #define PSC_TBL_KB_SODIMM3_S2D_FT3
+  #if OPTION_MEMCTLR_KB
+    #if OPTION_FT3_SOCKET_SUPPORT
+      extern PSC_TBL_ENTRY KBClkDisMapEntSOFT3;
+      #define PSC_TBL_KB_CLK_DIS_FT3 &KBClkDisMapEntSOFT3,
+      extern PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3;
+      #define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3,
+      extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3;
+      #define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3,
+    #endif
+    #if OPTION_UDIMMS
+      extern PSC_TBL_ENTRY KBMaxFreqTblEntU;
+      #define PSC_TBL_KB_UDIMM3_MAX_FREQ  &KBMaxFreqTblEntU,
+      extern PSC_TBL_ENTRY KBDramTermTblEntU;
+      #define PSC_TBL_KB_UDIMM3_DRAM_TERM  &KBDramTermTblEntU,
+      extern PSC_TBL_ENTRY KBSAOTblEntU3;
+      #define PSC_TBL_KB_UDIMM3_SAO  &KBSAOTblEntU3,
+      #undef PSC_TBL_KB_UDIMM3_S2D_FT3
+      extern PSC_TBL_ENTRY S2DTblEntUFT3;
+      #define PSC_TBL_KB_UDIMM3_S2D_FT3  &S2DTblEntUFT3,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_FT3_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY KBSAOTblEntSO3;
+        #define PSC_TBL_KB_SODIMM3_SAO  &KBSAOTblEntSO3,
+        extern PSC_TBL_ENTRY KBSAOTblEntSoDwnPlusSODIMM3;
+        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO  &KBSAOTblEntSoDwnPlusSODIMM3,
+        extern PSC_TBL_ENTRY KBSAOTblEntSoDwn3;
+        #define PSC_TBL_KB_SODWN_SAO  &KBSAOTblEntSoDwn3,
+        extern PSC_TBL_ENTRY KBDramTermTblEntSO3;
+        #define PSC_TBL_KB_SODIMM3_DRAM_TERM  &KBDramTermTblEntSO3,
+        extern PSC_TBL_ENTRY KBDramTermTblEntSoDwnPlusSODIMM3;
+        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM  &KBDramTermTblEntSoDwnPlusSODIMM3,
+        extern PSC_TBL_ENTRY KBDramTermTblEntSoDwn3;
+        #define PSC_TBL_KB_SODWN_DRAM_TERM  &KBDramTermTblEntSoDwn3,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntSO6L;
+        #define PSC_TBL_KB_SODIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntSO6L,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntSO4L;
+        #define PSC_TBL_KB_SODIMM3_MAX_FREQ_4L  &KBMaxFreqTblEntSO4L,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM6L;
+        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntSoDwnPlusSODIMM6L,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM4L;
+        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L  &KBMaxFreqTblEntSoDwnPlusSODIMM6L,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn;
+        #define PSC_TBL_KB_SODWN_MAX_FREQ  &KBMaxFreqTblEntSoDwn,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L;
+        #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntU6L,
+        extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L;
+        #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L  &KBMaxFreqTblEntU4L,
+        #undef PSC_TBL_KB_SODIMM3_S2D_FT3
+        #define PSC_TBL_KB_SODIMM3_S2D_FT3
+      #endif
+    #endif
+    extern PSC_TBL_ENTRY KBMR0WrTblEntry;
+    extern PSC_TBL_ENTRY KBMR0CLTblEntry;
+    extern PSC_TBL_ENTRY KBDdr3CKETriEnt;
+    extern PSC_TBL_ENTRY KB1DOdtPatTblEnt;
+    extern PSC_TBL_ENTRY KB2DOdtPatTblEnt;
+
+    #ifndef PSC_TBL_KB_SODIMM3_MAX_FREQ_6L
+      #define PSC_TBL_KB_SODIMM3_MAX_FREQ_6L
+    #endif
+    #ifndef PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
+      #define PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L
+      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
+      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_MAX_FREQ
+      #define PSC_TBL_KB_SODWN__MAX_FREQ
+    #endif
+    #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_6L
+      #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L
+    #endif
+    #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
+      #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
+    #endif
+    #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM
+      #define PSC_TBL_KB_UDIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM
+      #define PSC_TBL_KB_SODIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
+      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_DRAM_TERM
+      #define PSC_TBL_KB_SODWN_DRAM_TERM
+    #endif
+    #ifndef PSC_TBL_KB_SODIMM3_SAO
+      #define PSC_TBL_KB_SODIMM3_SAO
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
+      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
+    #endif
+    #ifndef PSC_TBL_KB_SODWN_SAO
+      #define PSC_TBL_KB_SODWN_SAO
+    #endif
+    #ifndef PSC_TBL_KB_UDIMM3_SAO
+      #define PSC_TBL_KB_UDIMM3_SAO
+    #endif
+    #ifndef PSC_TBL_KB_CLK_DIS_FT3
+      #define PSC_TBL_KB_CLK_DIS_FT3
+    #endif
+    #ifndef PSC_TBL_KB_ODT_TRI_FT3
+      #define PSC_TBL_KB_ODT_TRI_FT3
+    #endif
+    #ifndef PSC_TBL_KB_CS_TRI_FT3
+      #define PSC_TBL_KB_CS_TRI_FT3
+    #endif
+
+    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayKB[] = {
+      // 4 layer tables block
+      PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
+      PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
+      PSC_TBL_KB_SODWN_MAX_FREQ
+      PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
+      PSC_TBL_END,
+      // 6 layer tables block
+      PSC_TBL_KB_SODIMM3_MAX_FREQ_6L
+      PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L
+      PSC_TBL_KB_SODWN_MAX_FREQ
+      PSC_TBL_KB_UDIMM3_MAX_FREQ_6L
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = {
+      PSC_TBL_KB_UDIMM3_DRAM_TERM
+      PSC_TBL_KB_SODIMM3_DRAM_TERM
+      PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
+      PSC_TBL_KB_SODWN_DRAM_TERM
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblODTPatArrayKB[] = {
+      &KB1DOdtPatTblEnt,
+      &KB2DOdtPatTblEnt,
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblSAOArrayKB[] = {
+      PSC_TBL_KB_SODIMM3_SAO
+      PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
+      PSC_TBL_KB_SODWN_SAO
+      PSC_TBL_KB_UDIMM3_SAO
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblMR0WRArrayKB[] = {
+      &KBMR0WrTblEntry,
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblMR0CLArrayKB[] = {
+      &KBMR0CLTblEntry,
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblGenArrayKB[] = {
+      &KBDdr3CKETriEnt,
+      PSC_TBL_KB_CLK_DIS_FT3
+      PSC_TBL_KB_ODT_TRI_FT3
+      PSC_TBL_KB_CS_TRI_FT3
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblS2DArrayKB[] = {
+      PSC_TBL_KB_UDIMM3_S2D_FT3
+      PSC_TBL_KB_SODIMM3_S2D_FT3
+      PSC_TBL_END
+    };
+
+    MEM_PSC_TABLE_BLOCK memPSCTblBlockKB = {
+      (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayKB,
+      (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayKB,
+      (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayKB,
+      (PSC_TBL_ENTRY **)&memPSCTblSAOArrayKB,
+      (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayKB,
+      (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayKB,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      (PSC_TBL_ENTRY **)&memPSCTblGenArrayKB,
+      (PSC_TBL_ENTRY **)&memPSCTblS2DArrayKB,
+      NULL,
+      NULL
+    };
+
+    extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
+    extern MEM_PSC_FLOW MemPGetRttNomWr;
+    extern MEM_PSC_FLOW MemPGetODTPattern;
+    extern MEM_PSC_FLOW MemPGetSAO;
+    extern MEM_PSC_FLOW MemPGetMR0WrCL;
+    extern MEM_PSC_FLOW MemPGetS2D;
+
+    MEM_PSC_FLOW_BLOCK memPlatSpecFlowKB = {
+      &memPSCTblBlockKB,
+      MemPGetMaxFreqSupported,
+      MemPGetRttNomWr,
+      MemPGetODTPattern,
+      MemPGetSAO,
+      MemPGetMR0WrCL,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MEM_PSC_FLOW_DEFTRUE,
+      MemPGetS2D,
+      MEM_PSC_FLOW_DEFTRUE
+    };
+    #define MEM_PSC_FLOW_BLOCK_KB &memPlatSpecFlowKB,
+  #else
+    #define MEM_PSC_FLOW_BLOCK_KB
+  #endif
+
+
+  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+    MEM_PSC_FLOW_BLOCK_TN
+    MEM_PSC_FLOW_BLOCK_KB
+    MEM_PSC_FLOW_BLOCK_END
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+  *
+  *  LRDIMM CONTROL
+  *
+  *---------------------------------------------------------------------------------------------------
+  */
+  #if (OPTION_LRDIMMS == TRUE)
+    #if (OPTION_MEMCTLR_BK == TRUE)
+      #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
+    #else
+      #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
+    #endif
+  #else //#if (OPTION_LRDIMMS == FALSE)
+    #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
+  #endif
+  MEM_TECH_LRDIMM memLrdimmSupported = {
+    MEM_TECH_LRDIMM_STRUCT_VERSION,
+    MEM_TECH_FEATURE_LRDIMM_INIT
+  };
+#else
+  /*---------------------------------------------------------------------------------------------------
+   * MAIN FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY MAP
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT NORTHBRIDGE SUPPORT LIST
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_TN == TRUE)
+    #undef MEM_NB_SUPPORT_TN
+    #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN },
+  #endif
+  #if (OPTION_MEMCTLR_KB == TRUE)
+    #undef MEM_NB_SUPPORT_KB
+    #define MEM_NB_SUPPORT_KB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB, MEM_IDENDIMM_KB },
+  #endif
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT Technology Training
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if OPTION_DDR2
+    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
+      NULL
+    };
+    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+      NULL
+    };
+  #endif
+  #if OPTION_DDR3
+    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
+      NULL
+    };
+    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+      NULL
+    };
+  #endif
+    /*---------------------------------------------------------------------------------------------------
+     * DEFAULT Platform Specific list
+     *
+     *
+     *---------------------------------------------------------------------------------------------------
+     */
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+    NULL
+  };
+
+  /*----------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+    NULL
+  };
+
+  MEM_TECH_LRDIMM memLrdimmSupported = {
+    MEM_TECH_LRDIMM_STRUCT_VERSION,
+    NULL
+  };
+#endif
+
+/*---------------------------------------------------------------------------------------------------
+ * NORTHBRIDGE SUPPORT LIST
+ *
+ *
+ *---------------------------------------------------------------------------------------------------
+ */
+MEM_NB_SUPPORT memNBInstalled[] = {
+  MEM_NB_SUPPORT_TN
+  MEM_NB_SUPPORT_KB
+  MEM_NB_SUPPORT_END
+};
+
+UINT8 SizeOfNBInstalledTable = sizeof (memNBInstalled) / sizeof (memNBInstalled[0]);
+
+
+#endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecovery.h
new file mode 100644
index 0000000..79f7796
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecovery.h
@@ -0,0 +1,62 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_RECOVERY_H_
+#define _OPTION_MEMORY_RECOVERY_H_
+
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+
+typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_REC_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecoveryInstall.h
new file mode 100644
index 0000000..0ed16d5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecoveryInstall.h
@@ -0,0 +1,231 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
+#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
+
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+
+  #if (OPTION_MEMCTLR_TN == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockTN;
+    #define MEM_REC_NB_SUPPORT_TN MemRecConstructNBBlockTN,
+  #else
+    #define MEM_REC_NB_SUPPORT_TN
+  #endif
+
+  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
+    MEM_REC_NB_SUPPORT_TN
+    NULL
+  };
+
+  #define MEM_REC_TECH_CONSTRUCTOR_DDR2
+  #if (OPTION_DDR3 == TRUE)
+    extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
+    #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
+  #else
+    #define MEM_REC_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+  MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
+    MEM_REC_TECH_CONSTRUCTOR_DDR3
+    MEM_REC_TECH_CONSTRUCTOR_DDR2
+    NULL
+  };
+
+  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_PSC_REC_FLOW_BLOCK_END NULL
+  #define PSC_REC_TBL_END NULL
+  #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) MemRecDefTrue
+
+  #if OPTION_MEMCTLR_TN
+    #if OPTION_UDIMMS
+      extern PSC_TBL_ENTRY RecTNDramTermTblEntU;
+      #define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM  &RecTNDramTermTblEntU,
+      extern PSC_TBL_ENTRY RecTNSAOTblEntU3;
+      #define PSC_REC_TBL_TN_UDIMM3_SAO  &RecTNSAOTblEntU3,
+    #endif
+    #if OPTION_SODIMMS
+      extern PSC_TBL_ENTRY RecTNSAOTblEntSO3;
+      #define PSC_REC_TBL_TN_SODIMM3_SAO  &RecTNSAOTblEntSO3,
+      extern PSC_TBL_ENTRY RecTNDramTermTblEntSO;
+      #define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM  &RecTNDramTermTblEntSO,
+    #endif
+    extern PSC_TBL_ENTRY RecTNMR0WrTblEntry;
+    extern PSC_TBL_ENTRY RecTNMR0CLTblEntry;
+    extern PSC_TBL_ENTRY RecTNDdr3CKETriEnt;
+    extern PSC_TBL_ENTRY RecTNOdtPatTblEnt;
+
+    #ifndef PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
+      #define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
+      #define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
+    #endif
+    #ifndef PSC_REC_TBL_TN_SODIMM3_SAO
+      #define PSC_REC_TBL_TN_SODIMM3_SAO
+    #endif
+    #ifndef PSC_REC_TBL_TN_UDIMM3_SAO
+      #define PSC_REC_TBL_TN_UDIMM3_SAO
+    #endif
+
+    PSC_TBL_ENTRY* memRecPSCTblDramTermArrayTN[] = {
+      PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
+      PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
+      PSC_REC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memRecPSCTblODTPatArrayTN[] = {
+      &RecTNOdtPatTblEnt,
+      PSC_REC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memRecPSCTblSAOArrayTN[] = {
+      PSC_REC_TBL_TN_SODIMM3_SAO
+      PSC_REC_TBL_TN_UDIMM3_SAO
+      PSC_REC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayTN[] = {
+      &RecTNMR0WrTblEntry,
+      PSC_REC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayTN[] = {
+      &RecTNMR0CLTblEntry,
+      PSC_REC_TBL_END
+    };
+
+    MEM_PSC_TABLE_BLOCK memRecPSCTblBlockTN = {
+      NULL,
+      (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayTN,
+      (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayTN,
+      (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayTN,
+      (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayTN,
+      (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayTN,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      NULL
+    };
+    extern MEM_PSC_FLOW MemPRecGetRttNomWr;
+    #define PSC_REC_FLOW_TN_DRAM_TERM   MemPRecGetRttNomWr
+    extern MEM_PSC_FLOW MemPRecGetODTPattern;
+    #define PSC_REC_FLOW_TN_ODT_PATTERN   MemPRecGetODTPattern
+    extern MEM_PSC_FLOW MemPRecGetSAO;
+    #define PSC_REC_FLOW_TN_SAO   MemPRecGetSAO
+    extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
+    #define PSC_REC_FLOW_TN_MR0_WRCL   MemPRecGetMR0WrCL
+
+    MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowTN = {
+      &memRecPSCTblBlockTN,
+      MEM_REC_PSC_FLOW_DEFTRUE,
+      PSC_REC_FLOW_TN_DRAM_TERM,
+      PSC_REC_FLOW_TN_ODT_PATTERN,
+      PSC_REC_FLOW_TN_SAO,
+      PSC_REC_FLOW_TN_MR0_WRCL,
+      MEM_REC_PSC_FLOW_DEFTRUE,
+      MEM_REC_PSC_FLOW_DEFTRUE,
+      MEM_REC_PSC_FLOW_DEFTRUE,
+      MEM_REC_PSC_FLOW_DEFTRUE,
+      MEM_REC_PSC_FLOW_DEFTRUE,
+      MEM_REC_PSC_FLOW_DEFTRUE
+    };
+    #define MEM_PSC_REC_FLOW_BLOCK_TN &memRecPlatSpecFlowTN,
+  #else
+    #define MEM_PSC_REC_FLOW_BLOCK_TN
+  #endif
+
+  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
+    MEM_PSC_REC_FLOW_BLOCK_TN
+    MEM_PSC_REC_FLOW_BLOCK_END
+  };
+
+#else
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {    // Types of technology installed
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT NORTHBRIDGE SUPPORT LIST
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
+    NULL
+  };
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
+    NULL
+  };
+  /*----------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
+    NULL
+  };
+#endif
+#endif  // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMmioMapInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMmioMapInstall.h
new file mode 100644
index 0000000..0150c1b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMmioMapInstall.h
@@ -0,0 +1,93 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: MMIO map manager
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MMIO_MAP_INSTALL_H_
+#define _OPTION_MMIO_MAP_INSTALL_H_
+
+#include "mmioMapManager.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define F15_MMIO_MAP_SUPPORT
+#define F16_MMIO_MAP_SUPPORT
+
+#if ((AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+  // Family 15h
+  #ifdef OPTION_FAMILY15H
+    #if OPTION_FAMILY15H == TRUE
+      extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport;
+      #undef F15_MMIO_MAP_SUPPORT
+      #define F15_MMIO_MAP_SUPPORT {AMD_FAMILY_15, &F15MmioMapSupport},
+    #endif
+  #endif
+
+  // Family 16h
+  #ifdef OPTION_FAMILY16H
+    #if OPTION_FAMILY16H == TRUE
+      extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F16MmioMapSupport;
+      #undef F16_MMIO_MAP_SUPPORT
+      #define F16_MMIO_MAP_SUPPORT {AMD_FAMILY_16, &F16MmioMapSupport},
+    #endif
+  #endif
+
+#endif
+
+
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MmioMapFamilyServiceArray[] =
+{
+  F15_MMIO_MAP_SUPPORT
+  F16_MMIO_MAP_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MmioMapFamilyServiceTable =
+{
+  (sizeof (MmioMapFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &MmioMapFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_MMIO_MAP_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMsgBasedC1eInstall.h
new file mode 100644
index 0000000..d99bb7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMsgBasedC1eInstall.h
@@ -0,0 +1,70 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Message-Based C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
+#define _OPTION_MSG_BASED_C1E_INSTALL_H_
+
+#include "cpuMsgBasedC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_MSG_BASED_C1E_FEAT
+#define F15_BK_MSG_BASED_C1E_SUPPORT
+#if OPTION_MSG_BASED_C1E == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+
+
+    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
+    {
+      {0, NULL}
+    };
+    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
+    {
+      (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+      &MsgBasedC1eFamilyServiceArray[0]
+    };
+  #endif
+#endif
+#endif  // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocket.h
new file mode 100644
index 0000000..c266aad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocket.h
@@ -0,0 +1,215 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Multi-socket option API.
+ *
+ * Contains structures and values used to control the multi-socket option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MULTISOCKET_H_
+#define _OPTION_MULTISOCKET_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * This function loops through all possible socket locations, gathering the number
+ * of power management steps each populated socket requires, and returns the
+ * highest number.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_PM_STEPS (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, starting core 0 of
+ * each populated socket to perform the passed in AP_TASK.  After starting all
+ * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by
+ * the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ * @return     The most severe error code from AP_TASK
+ *
+ */
+typedef AGESA_STATUS OPTION_MULTISOCKET_PM_CORE0_TASK (
+  IN       VOID *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+/**
+ * This function loops through all possible socket locations, comparing the
+ * maximum NB frequencies to determine the slowest.  This function also
+ * determines if all coherent NB frequencies are equivalent.
+ *
+ * @param[in]  NbPstate                    NB P-state number to check (0 = fastest)
+ * @param[in]  PlatformConfig              Platform profile/build option config structure.
+ * @param[out] SystemNbCofNumerator        NB frequency numerator for the system in MHz
+ * @param[out] SystemNbCofDenominator      NB frequency denominator for the system
+ * @param[out] SystemNbCofsMatch           Whether or not all NB frequencies are equivalent
+ * @param[out] NbPstateIsEnabledOnAllCPUs  Whether or not NbPstate is valid on all CPUs
+ * @param[in]  StdHeader                   Config handle for library and services
+ *
+ * @retval     TRUE                        At least one processor has NbPstate enabled.
+ * @retval     FALSE                       NbPstate is disabled on all CPUs
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
+  IN       UINT32 NbPstate,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32 *SystemNbCofNumerator,
+     OUT   UINT32 *SystemNbCofDenominator,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, checking whether
+ * any populated sockets require NB COF VID programming.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, collecting any
+ * power management initialization errors that may have occurred.  These errors
+ * are transferred from the core 0s of the socket in which the errors occurred
+ * to the BSC's heap.  The BSC's heap is then searched for the most severe error
+ * that occurred, and returns it.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations and Nb Pstates,
+ * comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
+ * the system.
+ *
+ * @param[in]  PlatformConfig      Platform profile/build option config structure.
+ * @param[out] MinSysNbFreq        NB frequency numerator for the system in MHz
+ * @param[out] MinP0NbFreq         NB frequency numerator for P0 in MHz
+ * @param[in]  StdHeader           Config handle for library and services
+ */
+typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32                 *MinSysNbFreq,
+     OUT   UINT32                 *MinP0NbFreq,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * This function returns the current running core's PCI Config Space address.
+ *
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[in]    StdHeader    Header for library and services.
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS (
+     OUT   PCI_ADDR               *PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ *  This function writes to all nodes on the executing core's socket.
+ *
+ *  @param[in]     PciAddress    The Function and Register to update
+ *  @param[in]     Mask          The bitwise AND mask to apply to the current register value
+ *  @param[in]     Data          The bitwise OR mask to apply to the current register value
+ *  @param[in]     StdHeader     Header for library and services.
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI (
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 Mask,
+  IN       UINT32                 Data,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#define MULTISOCKET_STRUCT_VERSION  0x01
+
+/**
+ * Provide build configuration of cpu multi-socket or single socket support.
+ *
+ */
+typedef struct  {
+  UINT16              OptMultiSocketVersion;                       ///< Table version
+  OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps;           ///< Method: Get number of power mgt tasks
+  OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s;   ///< Method: Perform tasks on Core 0 of each processor
+  OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings;         ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate;    ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
+  OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors;  ///< Method: Gathers error information from all Core 0s.
+  OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof;                   ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
+  OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr;              ///< Method: Get PCI Config Space Address for the current running core.
+  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci;  ///< Method: Writes to all nodes on the executing core's socket.
+} OPTION_MULTISOCKET_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_MULTISOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocketInstall.h
new file mode 100644
index 0000000..cc79ceb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocketInstall.h
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Multiple Socket Support
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MULTISOCKET_INSTALL_H_
+#define _OPTION_MULTISOCKET_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#ifndef OPTION_MULTISOCKET
+  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+
+#if OPTION_MULTISOCKET == TRUE
+  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
+  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrMulti
+  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
+  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sMulti
+  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
+  #define GET_SYS_NB_COF      GetSystemNbCofMulti
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
+  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
+  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
+  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
+  OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
+  #define GET_MIN_NB_COF GetMinNbCofMulti
+  OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti;
+  #define GET_PCI_ADDRESS GetCurrPciAddrMulti
+  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti;
+  #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti
+#else
+  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
+  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrSingle
+  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
+  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sSingle
+  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
+  #define GET_SYS_NB_COF      GetSystemNbCofSingle
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
+  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
+  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
+  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
+  OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
+  #define GET_MIN_NB_COF GetMinNbCofSingle
+  OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle;
+  #define GET_PCI_ADDRESS GetCurrPciAddrSingle
+  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle;
+  #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle
+#endif
+
+/*  Declare the instance of the multisocket option configuration structure  */
+OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
+  MULTISOCKET_STRUCT_VERSION,
+  GET_NUM_PM_STEPS,
+  CORE0_PM_TASK,
+  GET_SYS_NB_COF,
+  GET_SYS_NB_COF_UPDATE,
+  GET_EARLY_PM_ERRORS,
+  GET_MIN_NB_COF,
+  GET_PCI_ADDRESS,
+  MODIFY_CURR_SOCKET_PCI
+};
+
+#endif  // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
new file mode 100644
index 0000000..aa510aa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Prefetch Mode
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PREFETCH_MODE_INSTALL_H_
+#define _OPTION_PREFETCH_MODE_INSTALL_H_
+
+#include "cpuPrefetchMode.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_PREFETCH_MODE_FEAT
+#define CPU_PREFETCH_MODE_AP_TASK
+#define F15_PREFETCH_MODE_SUPPORT
+#define F16_PREFETCH_MODE_SUPPORT
+
+#if OPTION_PREFETCH_MODE == TRUE
+  #if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+    #undef CPU_PREFETCH_MODE_AP_TASK
+    #define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask},
+
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePrefetchMode;
+        #undef OPTION_PREFETCH_MODE_FEAT
+        #define OPTION_PREFETCH_MODE_FEAT &CpuFeaturePrefetchMode,
+        extern CONST PREFETCH_MODE_FAMILY_SERVICES ROMDATA F15PrefetchModeSupport;
+        #undef F15_PREFETCH_MODE_SUPPORT
+        #define F15_PREFETCH_MODE_SUPPORT {AMD_FAMILY_15, &F15PrefetchModeSupport},
+      #endif
+    #endif
+
+
+    ///@todo
+    // Family 16h
+    //#ifdef OPTION_FAMILY16H
+    //  #if OPTION_FAMILY16H == TRUE
+    //    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePrefetchMode;
+    //    #undef OPTION_PREFETCH_MODE_FEAT
+    //    #define OPTION_PREFETCH_MODE_FEAT &CpuFeaturePrefetchMode,
+    //    extern CONST PREFETCH_MODE_FAMILY_SERVICES ROMDATA F16PrefetchModeSupport;
+    //    #undef F16_PREFETCH_MODE_SUPPORT
+    //    #define F16_PREFETCH_MODE_SUPPORT {AMD_FAMILY_16, &F16PrefetchModeSupport},
+    //  #endif
+    //#endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PrefetchModeFamilyServiceArray[] =
+{
+  F15_PREFETCH_MODE_SUPPORT
+  F16_PREFETCH_MODE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PrefetchModeFamilyServiceTable =
+{
+  (sizeof (PrefetchModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &PrefetchModeFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_PREFETCH_MODE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPreserveMailboxInstall.h
new file mode 100644
index 0000000..1f32fee
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPreserveMailboxInstall.h
@@ -0,0 +1,57 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Preserve Mailbox
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
+#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
+
+#include "PreserveMailbox.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_PRESERVE_MAILBOX_FEAT
+#define F15_PRESERVE_MAILBOX_SUPPORT
+
+
+#endif  // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPsiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPsiInstall.h
new file mode 100644
index 0000000..8e89107
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPsiInstall.h
@@ -0,0 +1,103 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Power Status Indicator (PSI).
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PSI_INSTALL_H_
+#define _OPTION_PSI_INSTALL_H_
+
+#include "cpuPsi.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_PSI_FEAT
+#define F15_TN_PSI_SUPPORT
+#define F16_KB_PSI_SUPPORT
+
+#if OPTION_CPU_PSI == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
+          #undef OPTION_CPU_PSI_FEAT
+          #define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
+          extern CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport;
+          #undef F15_TN_PSI_SUPPORT
+          #define F15_TN_PSI_SUPPORT {AMD_FAMILY_15_TN, &F15TnPsiSupport},
+        #endif
+      #endif
+    #endif
+
+    // Family 16h
+    #ifdef OPTION_FAMILY16H
+      #if OPTION_FAMILY16H == TRUE
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
+          #undef OPTION_CPU_PSI_FEAT
+          #define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
+          extern CONST PSI_FAMILY_SERVICES ROMDATA F16KbPsiSupport;
+          #undef F16_KB_PSI_SUPPORT
+          #define F16_KB_PSI_SUPPORT {AMD_FAMILY_16_KB, &F16KbPsiSupport},
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PsiFamilyServiceArray[] =
+{
+  F15_TN_PSI_SUPPORT
+  F16_KB_PSI_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PsiFamilyServiceTable =
+{
+  (sizeof (PsiFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &PsiFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_PSI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstate.h
new file mode 100644
index 0000000..683af0a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstate.h
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD ACPI PState option API.
+ *
+ * Contains structures and values used to control the PStates option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_PSTATE_H_
+#define _OPTION_PSTATE_H_
+
+#include "cpuPstateTables.h"
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_SSDT_FEATURE (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **AcpiPstatePtr
+  );
+
+typedef UINT32 OPTION_ACPI_FEATURE (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **AcpiPStatePtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+typedef AGESA_STATUS OPTION_PSTATE_GATHER (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#define PSTATE_STRUCT_VERSION  0x01
+
+/// Indirection vectors for POST/PEI PState code
+typedef struct  {
+  UINT16                  OptPstateVersion;     ///< revision of this structure
+  OPTION_PSTATE_GATHER    *PstateGather;        ///< vector for data gathering routine
+  OPTION_PSTATE_LEVELING  *PstateLeveling;      ///< vector for leveling routine
+} OPTION_PSTATE_POST_CONFIGURATION;
+
+/// Indirection vectors for LATE/DXE PState code
+typedef struct  {
+  UINT16                  OptPstateVersion;     ///< revision of this structure
+  OPTION_SSDT_FEATURE     *SsdtFeature;         ///< vector for routine to generate SSDT
+  OPTION_ACPI_FEATURE     *PstateFeature;       ///< vector for routine to generate ACPI PState Objects
+  OPTION_ACPI_FEATURE     *CstateFeature;       ///< vector for routine to generate ACPI CState Objects
+  BOOLEAN                 CfgPstatePpc;         ///< boolean for creating _PPC method
+  BOOLEAN                 CfgPstatePct;         ///< boolean for creating _PCT method
+  BOOLEAN                 CfgPstatePsd;         ///< boolean for creating _PSD method
+  BOOLEAN                 CfgPstatePss;         ///< boolean for creating _PSS method
+  BOOLEAN                 CfgPstateXpss;        ///< boolean for creating _XPSS method
+  UINT8                   OemIdString[6];       ///< Configurable OEM Id
+  UINT8                   OemTableIdString[8];  ///< Configurable OEM Table Id
+} OPTION_PSTATE_LATE_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateHpcModeInstall.h
new file mode 100644
index 0000000..58699e6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateHpcModeInstall.h
@@ -0,0 +1,57 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Pstate HPC mode.
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
+#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_
+
+#include "cpuPstateHpcMode.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_PSTATE_HPC_MODE_FEAT
+#define F15_PSTATE_HPC_MODE_SUPPORT
+
+
+#endif  // _OPTION_PSTATE_HPC_MODE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateInstall.h
new file mode 100644
index 0000000..a3c5fa3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateInstall.h
@@ -0,0 +1,230 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: PState
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PSTATE_INSTALL_H_
+#define _OPTION_PSTATE_INSTALL_H_
+
+#include "cpuPstateTables.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define F15_TN_PSTATE_SERVICE_SUPPORT
+#define F16_KB_PSTATE_SERVICE_SUPPORT
+
+#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
+  //
+  //Define Pstate CPU Family service
+  //
+  #ifdef OPTION_FAMILY15H
+    #if OPTION_FAMILY15H == TRUE
+      #ifdef OPTION_FAMILY15H_TN
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
+          #undef F15_TN_PSTATE_SERVICE_SUPPORT
+          #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
+        #endif
+      #endif
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY16H
+    #if OPTION_FAMILY16H == TRUE
+      #ifdef OPTION_FAMILY16H_KB
+        #if OPTION_FAMILY16H_KB == TRUE
+          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F16KbPstateServices;
+          #undef F16_KB_PSTATE_SERVICE_SUPPORT
+          #define F16_KB_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_16_KB, &F16KbPstateServices},
+        #endif
+      #endif
+    #endif
+  #endif
+  //
+  //Define ACPI Pstate objects.
+  //
+  #ifndef OPTION_ACPI_PSTATES
+    #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
+  #endif
+  #if (OPTION_ACPI_PSTATES == TRUE)
+    OPTION_SSDT_FEATURE               GenerateSsdt;
+    #define USER_SSDT_MAIN            GenerateSsdt
+    #ifndef OPTION_MULTISOCKET
+      #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+    #endif
+
+    OPTION_ACPI_FEATURE               CreatePStateAcpiTables;
+    OPTION_PSTATE_GATHER              PStateGatherMain;
+    #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
+      OPTION_PSTATE_LEVELING          PStateLevelingMain;
+      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingMain
+    #else
+      OPTION_PSTATE_LEVELING            PStateLevelingStub;
+      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+    #endif
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      #define USER_PSTATE_OPTION_MAIN   CreatePStateAcpiTables
+    #else
+      OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
+      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #endif
+    #if AGESA_ENTRY_INIT_POST == TRUE
+      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
+    #else
+      OPTION_PSTATE_GATHER              PStateGatherStub;
+      #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+    #endif
+    #if CFG_ACPI_PSTATES_PPC == TRUE
+      #define USER_PSTATE_CFG_PPC   TRUE
+    #else
+      #define USER_PSTATE_CFG_PPC   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PCT == TRUE
+      #define USER_PSTATE_CFG_PCT   TRUE
+    #else
+      #define USER_PSTATE_CFG_PCT   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PSD == TRUE
+      #define USER_PSTATE_CFG_PSD   TRUE
+    #else
+      #define USER_PSTATE_CFG_PSD   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PSS == TRUE
+      #define USER_PSTATE_CFG_PSS   TRUE
+    #else
+      #define USER_PSTATE_CFG_PSS   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_XPSS == TRUE
+      #define USER_PSTATE_CFG_XPSS   TRUE
+    #else
+      #define USER_PSTATE_CFG_XPSS   FALSE
+    #endif
+
+    #if OPTION_IO_CSTATE == TRUE
+      OPTION_ACPI_FEATURE             CreateCStateAcpiTables;
+      #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
+    #else
+      OPTION_ACPI_FEATURE             CreateAcpiTablesStub;
+      #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
+    #endif
+  #else
+    OPTION_SSDT_FEATURE               GenerateSsdtStub;
+    OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
+    OPTION_PSTATE_GATHER              PStateGatherStub;
+    OPTION_PSTATE_LEVELING            PStateLevelingStub;
+    #define USER_SSDT_MAIN            GenerateSsdtStub
+    #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+    #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+    #define USER_PSTATE_CFG_PPC    FALSE
+    #define USER_PSTATE_CFG_PCT    FALSE
+    #define USER_PSTATE_CFG_PSD    FALSE
+    #define USER_PSTATE_CFG_PSS    FALSE
+    #define USER_PSTATE_CFG_XPSS   FALSE
+
+    // If ACPI Objects are disabled for PStates, we still need to check
+    // whether ACPI Objects are enabled for CStates
+    #if OPTION_IO_CSTATE == TRUE
+      OPTION_SSDT_FEATURE               GenerateSsdt;
+      OPTION_PSTATE_GATHER              PStateGatherMain;
+      OPTION_ACPI_FEATURE               CreateCStateAcpiTables;
+      #undef  USER_SSDT_MAIN
+      #define USER_SSDT_MAIN            GenerateSsdt
+      #undef  USER_PSTATE_OPTION_GATHER
+      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
+      #undef  USER_CSTATE_OPTION_MAIN
+      #define USER_CSTATE_OPTION_MAIN   CreateCStateAcpiTables
+    #endif
+  #endif
+#else
+  OPTION_SSDT_FEATURE               GenerateSsdtStub;
+  OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
+  OPTION_PSTATE_GATHER              PStateGatherStub;
+  OPTION_PSTATE_LEVELING            PStateLevelingStub;
+  #define USER_SSDT_MAIN            GenerateSsdtStub
+  #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+  #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
+  #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+  #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+  #define USER_PSTATE_CFG_PPC    FALSE
+  #define USER_PSTATE_CFG_PCT    FALSE
+  #define USER_PSTATE_CFG_PSD    FALSE
+  #define USER_PSTATE_CFG_PSS    FALSE
+  #define USER_PSTATE_CFG_XPSS   FALSE
+#endif
+
+/*  Declare the instance of the PSTATE option configuration structure  */
+OPTION_PSTATE_POST_CONFIGURATION      OptionPstatePostConfiguration = {
+  PSTATE_STRUCT_VERSION,
+  USER_PSTATE_OPTION_GATHER,
+  USER_PSTATE_OPTION_LEVEL
+};
+
+OPTION_PSTATE_LATE_CONFIGURATION      OptionPstateLateConfiguration = {
+  PSTATE_STRUCT_VERSION,
+  USER_SSDT_MAIN,
+  USER_PSTATE_OPTION_MAIN,
+  USER_CSTATE_OPTION_MAIN,
+  USER_PSTATE_CFG_PPC,
+  USER_PSTATE_CFG_PCT,
+  USER_PSTATE_CFG_PSD,
+  USER_PSTATE_CFG_PSS,
+  USER_PSTATE_CFG_XPSS,
+  {CFG_ACPI_SET_OEM_ID},
+  {CFG_ACPI_SET_OEM_TABLE_ID}
+};
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
+{
+  F15_TN_PSTATE_SERVICE_SUPPORT
+  F16_KB_PSTATE_SERVICE_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
+{
+  (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &PstateCpuFamilyServiceArray[0]
+};
+#endif  // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionS3ScriptInstall.h
new file mode 100644
index 0000000..d36004f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionS3ScriptInstall.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: S3SCRIPT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_S3SCRIPT_INSTALL_H_
+#define _OPTION_S3SCRIPT_INSTALL_H_
+
+#include "S3SaveState.h"
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#ifndef OPTION_S3SCRIPT
+  #define OPTION_S3SCRIPT  FALSE    //if not define assume PI not use script
+#endif
+
+#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  #if OPTION_S3SCRIPT == TRUE
+    #define P_S3_SCRIPT_INIT      S3ScriptInitState
+  #endif
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+  #if OPTION_S3SCRIPT == TRUE
+    #define P_S3_SCRIPT_RESTORE   S3ScriptRestoreState
+  #endif
+#endif
+
+#ifndef P_S3_SCRIPT_INIT
+  #define P_S3_SCRIPT_INIT        S3ScriptInitStateStub
+#endif
+
+#ifndef P_S3_SCRIPT_RESTORE
+  #define P_S3_SCRIPT_RESTORE     S3ScriptInitStateStub
+  #undef  GNB_S3_DISPATCH_FUNCTION_TABLE
+#endif
+
+#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
+  #define GNB_S3_DISPATCH_FUNCTION_TABLE
+#endif
+
+/*  Declare the instance of the S3SCRIPT option configuration structure  */
+S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
+  P_S3_SCRIPT_INIT,
+  P_S3_SCRIPT_RESTORE
+};
+
+S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
+  GNB_S3_DISPATCH_FUNCTION_TABLE
+  {0, NULL}
+};
+#endif  // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionSlit.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionSlit.h
new file mode 100644
index 0000000..8ee229a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionSlit.h
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD SLIT option API.
+ *
+ * Contains structures and values used to control the SLIT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_SLIT_H_
+#define _OPTION_SLIT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Create the ACPI System Locality Distance Information Table.
+ *
+ */
+typedef AGESA_STATUS OPTION_SLIT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+
+/**
+ * Clean up DRAM used during SLIT creation.
+ *
+ */
+typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define SLIT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of SLIT
+typedef struct  {
+  UINT16              OptSlitVersion;       ///< The version number of SLIT
+  OPTION_SLIT_FEATURE  *SlitFeature;        ///< The Option Feature of SLIT
+  OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
+  UINT8               OemIdString[6];       ///< Configurable OEM Id
+  UINT8               OemTableIdString[8];  ///< Configurable OEM Table Id
+} OPTION_SLIT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_SLIT_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionSlitInstall.h
new file mode 100644
index 0000000..2e42384
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionSlitInstall.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: SLIT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SLIT_INSTALL_H_
+#define _OPTION_SLIT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_SLIT
+    #error  BLDOPT: Option not defined: "OPTION_SLIT"
+  #endif
+  #if OPTION_SLIT == TRUE
+    OPTION_SLIT_FEATURE               GetAcpiSlitMain;
+    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBuffer;
+    #define USER_SLIT_OPTION     GetAcpiSlitMain
+    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
+  #else
+    OPTION_SLIT_FEATURE               GetAcpiSlitStub;
+    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
+    #define USER_SLIT_OPTION     GetAcpiSlitStub
+    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
+  #endif
+#else
+  OPTION_SLIT_FEATURE               GetAcpiSlitStub;
+  OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
+  #define USER_SLIT_OPTION     GetAcpiSlitStub
+  #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
+#endif
+/*  Declare the instance of the SLIT option configuration structure  */
+OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
+  SLIT_STRUCT_VERSION,
+  USER_SLIT_OPTION,
+  USER_SLIT_RELEASE_BUFFER,
+  {CFG_ACPI_SET_OEM_ID},
+  {CFG_ACPI_SET_OEM_TABLE_ID}
+};
+
+#endif  // _OPTION_SLIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionSrat.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionSrat.h
new file mode 100644
index 0000000..4bce6a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionSrat.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD SRAT option API.
+ *
+ * Contains structures and values used to control the SRAT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_SRAT_H_
+#define _OPTION_SRAT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_SRAT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+
+#define SRAT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of SRAT
+typedef struct  {
+  UINT16              OptSratVersion;       ///< The version number of SRAT
+  OPTION_SRAT_FEATURE  *SratFeature;        ///< The Option Feature of SRAT
+  UINT8               OemIdString[6];       ///< Configurable OEM Id
+  UINT8               OemTableIdString[8];  ///< Configurable OEM Table Id
+} OPTION_SRAT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_SRAT_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionSratInstall.h
new file mode 100644
index 0000000..0e3fb29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionSratInstall.h
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: SRAT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SRAT_INSTALL_H_
+#define _OPTION_SRAT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_SRAT
+    #error  BLDOPT: Option not defined: "OPTION_SRAT"
+  #endif
+  #if OPTION_SRAT == TRUE
+    OPTION_SRAT_FEATURE          GetAcpiSratMain;
+    #define USER_SRAT_OPTION     GetAcpiSratMain
+  #else
+    OPTION_SRAT_FEATURE          GetAcpiSratStub;
+    #define USER_SRAT_OPTION     GetAcpiSratStub
+  #endif
+#else
+  OPTION_SRAT_FEATURE            GetAcpiSratStub;
+  #define USER_SRAT_OPTION       GetAcpiSratStub
+#endif
+
+/*  Declare the instance of the WHEA option configuration structure  */
+OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
+  SRAT_STRUCT_VERSION,
+  USER_SRAT_OPTION,
+  {CFG_ACPI_SET_OEM_ID},
+  {CFG_ACPI_SET_OEM_TABLE_ID}
+};
+
+#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionTdpLimitingInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionTdpLimitingInstall.h
new file mode 100644
index 0000000..843bd85
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionTdpLimitingInstall.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: TDP Limiting.
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_TDP_LIMITING_INSTALL_H_
+#define _OPTION_TDP_LIMITING_INSTALL_H_
+
+#include "cpuTdpLimiting.h"
+
+/*  This option is designed to be included into the CPU features install
+ *  file. The CPU features install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_TDP_LIMIT_FEAT
+#define F15_TDP_LIMIT_SUPPORT
+
+#if OPTION_CPU_TDP_LIMITING == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureTdpLimit;
+        #undef OPTION_TDP_LIMIT_FEAT
+        #define OPTION_TDP_LIMIT_FEAT &CpuFeatureTdpLimit,
+        extern CONST TDP_LIMIT_FAMILY_SERVICES ROMDATA F15TdpLimitSupport;
+        #undef F15_TDP_LIMIT_SUPPORT
+        #define F15_TDP_LIMIT_SUPPORT {AMD_FAMILY_15, &F15TdpLimitSupport},
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA TdpLimitFamilyServiceArray[] =
+{
+  F15_TDP_LIMIT_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA TdpLimitFamilyServiceTable =
+{
+  (sizeof (TdpLimitFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &TdpLimitFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_TDP_LIMITING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionWhea.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionWhea.h
new file mode 100644
index 0000000..7f5d0d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionWhea.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD WHEA option API.
+ *
+ * Contains structures and values used to control the WHEA option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_WHEA_H_
+#define _OPTION_WHEA_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_WHEA_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+#define WHEA_STRUCT_VERSION  0x01
+
+/// The Option Configuration of WHEA
+typedef struct  {
+  UINT16              OptWheaVersion;       ///< The version number of WHEA
+  OPTION_WHEA_FEATURE  *WheaFeature;        ///< The Option Feature of WHEA
+} OPTION_WHEA_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_WHEA_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionWheaInstall.h
new file mode 100644
index 0000000..afbd325
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionWheaInstall.h
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: WHEA
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_WHEA_INSTALL_H_
+#define _OPTION_WHEA_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_WHEA
+    #error  BLDOPT: Option not defined: "OPTION_WHEA"
+  #endif
+  #if OPTION_WHEA == TRUE
+    OPTION_WHEA_FEATURE          GetAcpiWheaMain;
+    #define USER_WHEA_OPTION     GetAcpiWheaMain
+  #else
+    OPTION_WHEA_FEATURE          GetAcpiWheaStub;
+    #define USER_WHEA_OPTION     GetAcpiWheaStub
+  #endif
+
+#else
+  OPTION_WHEA_FEATURE            GetAcpiWheaStub;
+  #define USER_WHEA_OPTION       GetAcpiWheaStub
+#endif
+
+/*  Declare the instance of the WHEA option configuration structure  */
+OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
+  WHEA_STRUCT_VERSION,
+  USER_WHEA_OPTION
+};
+
+#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Options.h b/src/vendorcode/amd/agesa/f16kb/Include/Options.h
new file mode 100644
index 0000000..19e161c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/Options.h
@@ -0,0 +1,68 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AGESA options structures
+ *
+ * Contains options control structures for the AGESA build options
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _OPTIONS_H_
+#define _OPTIONS_H_
+
+/**
+ * Provide topology limits for loops and runtime, based on supported families.
+ */
+typedef struct {
+  UINT32              PlatformNumberOfSockets;                  ///< The limit to the number of processors based on
+                                                                ///< supported families and other build options.
+  UINT32              PlatformNumberOfModules;                  ///< The limit to the number of modules in a processor, based
+                                                                ///< on supported families.
+} OPTIONS_CONFIG_TOPOLOGY;
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+  UINT32              FunctionId;                   ///< The function id specified.
+  IMAGE_ENTRY         EntryPoint;                   ///< The corresponding entry point to call.
+} DISPATCH_TABLE;
+
+
+#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionsHt.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionsHt.h
new file mode 100644
index 0000000..51f056d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionsHt.h
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD HyperTransport option API.
+ *
+ * Contains option pre-compile logic.  This file is used by the options
+ * installer and internally by the HT code initializers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_HT_H_
+#define _OPTION_HT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Provide HT build option results
+ */
+typedef struct {
+  CONST BOOLEAN IsUsingRecoveryHt;                   ///< Manual BUID Swap List processing should assume that HT Recovery was used.
+  CONST BOOLEAN IsSetHtCrcFlood;                     ///< Enable setting of HT CRC Flood.
+                                                     ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
+  CONST BOOLEAN IsUsingUnitIdClumping;               ///< Enable automatically HT Spec compliant Unit Id Clumping.
+                                                     ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
+  CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults;  ///< A set of build time options for HT constructor.
+  CONST VOID *HtOptionInternalInterface;             ///< Use this internal interface initializer.
+  CONST VOID *HtOptionInternalFeatures;              ///< Use this internal feature set initializer.
+  CONST VOID *HtOptionFamilyNorthbridgeList;         ///< Use this list of northbridge initializers.
+  CONST UINT8 *CONST *HtOptionBuiltinTopologies;     ///< Use this list of built-in topologies.
+} OPTION_HT_CONFIGURATION;
+
+typedef AGESA_STATUS
+F_OPTION_HT_INIT_RESET (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
+
+typedef AGESA_STATUS
+F_OPTION_HT_RESET_CONSTRUCTOR (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
+
+/**
+ * Provide HT reset initialization build option results
+ */
+typedef struct {
+  PF_OPTION_HT_INIT_RESET HtInitReset;               ///< Method: HT reset initialization.
+  PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
+} OPTION_HT_INIT_RESET;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_HT_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
new file mode 100644
index 0000000..136b0f4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
@@ -0,0 +1,2361 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a combination of package type, processor, and features.
+ *
+ * This file generates the defaults tables for the all platform solution
+ * combinations.  The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 85818 $   @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  Int32FromChar ('0', '0', '0', '0'),
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*  Process user desired AGESA entry points  */
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+/*  Default the late AP entry point to off.  It can be enabled
+    by any family that may need the late AP functionality, or
+    by any feature code that may need it.  The IBVs no longer
+    have control over this entry point.  */
+#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+#endif
+#define AGESA_ENTRY_LATE_RUN_AP_TASK    FALSE
+
+
+
+/* Process solution defined socket / family installations
+ *
+ * As part of the release package for each image, define the options below to select the
+ * AGESA processor support included in that image.
+ */
+
+/*  Default sockets to off  */
+#define OPTION_FT3_SOCKET_SUPPORT    FALSE
+
+/*  Default families to off  */
+#define OPTION_FAMILY15H_MODEL_1x    FALSE
+#define OPTION_FAMILY16H_MODEL_0x    FALSE
+
+
+/*  Enable the appropriate socket support  */
+
+#ifdef INSTALL_FT3_SOCKET_SUPPORT
+  #if  INSTALL_FT3_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FT3_SOCKET_SUPPORT
+    #define OPTION_FT3_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+
+
+// F16_0x is supported in FT3
+#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
+  #if  INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
+    #undef OPTION_FAMILY16H
+    #define OPTION_FAMILY16H     TRUE
+    #undef OPTION_FAMILY16H_MODEL_0x
+    #define OPTION_FAMILY16H_MODEL_0x     TRUE
+  #endif
+#endif
+
+/*  Turn off families not required by socket designations */
+#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
+  #undef OPTION_FAMILY15H
+  #define OPTION_FAMILY15H     FALSE
+#endif
+
+#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
+  #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY16H_MODEL_0x
+    #define OPTION_FAMILY16H_MODEL_0x  FALSE
+  #endif
+#endif
+
+
+#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
+  #undef OPTION_FAMILY16H
+  #define OPTION_FAMILY16H     FALSE
+#endif
+
+
+#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
+    #error No FT3 supported families included in the build
+  #endif
+#endif
+
+
+/* Process AGESA private data
+ *
+ * Turn on appropriate CPU models and memory controllers,
+ * as well as some other memory controls.
+ */
+
+/*  Default all models to off  */
+#define OPTION_FAMILY15H_TN          FALSE
+#define OPTION_FAMILY16H_KB          FALSE
+#define OPTION_FAMILY15H_UNKNOWN     FALSE
+
+/*  Default all memory controllers to off  */
+#define OPTION_MEMCTLR_TN            FALSE
+#define OPTION_MEMCTLR_KB            FALSE
+
+/*  Default all memory controls to off  */
+#define OPTION_HW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
+#define OPTION_MAX_RD_LAT_TRAINING              FALSE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     FALSE
+#define OPTION_S3_MEM_SUPPORT                   FALSE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+#define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
+#define OPTION_RDDQS_2D_TRAINING                FALSE
+#define OPTION_PRE_MEM_INIT                     FALSE
+#define OPTION_POST_MEM_INIT                    FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_UDIMMS                           FALSE
+#define OPTION_RDIMMS                           FALSE
+#define OPTION_SODIMMS                          FALSE
+#define OPTION_LRDIMMS                          FALSE
+#define OPTION_DDR2                             FALSE
+#define OPTION_DDR3                             FALSE
+#define OPTION_ECC                              FALSE
+#define OPTION_BANK_INTERLEAVE                  FALSE
+#define OPTION_DCT_INTERLEAVE                   FALSE
+#define OPTION_NODE_INTERLEAVE                  FALSE
+#define OPTION_PARALLEL_TRAINING                FALSE
+#define OPTION_ONLINE_SPARE                     FALSE
+#define OPTION_MEM_RESTORE                      FALSE
+#define OPTION_DIMM_EXCLUDE                     FALSE
+#define OPTION_AMP                              FALSE
+#define OPTION_DATA_EYE                         FALSE
+#define OPTION_AGGRESSOR                        FALSE
+
+/*  Default all CPU controls to off  */
+#define OPTION_MULTISOCKET                      FALSE
+#define OPTION_CRAT                             FALSE
+#define OPTION_CDIT                             FALSE
+#define OPTION_SRAT                             FALSE
+#define OPTION_SLIT                             FALSE
+#define OPTION_HT_ASSIST                        FALSE
+#define OPTION_ATM_MODE                         FALSE
+#define OPTION_NBR_CACHE                        FALSE
+#define OPTION_CPU_CORELEVELING                 FALSE
+#define OPTION_MSG_BASED_C1E                    FALSE
+#define OPTION_CPU_CFOH                         FALSE
+#define OPTION_C6_STATE                         FALSE
+#define OPTION_IO_CSTATE                        FALSE
+#define OPTION_CPB                              FALSE
+#define OPTION_CPU_APM                          FALSE
+#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT   FALSE
+#define OPTION_CPU_PSTATE_HPC_MODE              FALSE
+#define OPTION_CPU_TDP_LIMITING                 FALSE
+#define OPTION_CPU_PSI                          FALSE
+#define OPTION_CPU_HTC                          FALSE
+#define OPTION_S3SCRIPT                         FALSE
+#define OPTION_GFX_RECOVERY                     FALSE
+#define OPTION_CPU_SCS                          FALSE
+#define OPTION_PREFETCH_MODE                    FALSE
+
+/*  Default FCH controls to off  */
+#define FCH_SUPPORT                             FALSE
+
+/*  Enable all private controls based on socket/family enables  */
+
+#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
+    #undef FCH_SUPPORT
+    #define FCH_SUPPORT          TRUE
+    #undef OPTION_FAMILY16H_KB
+    #define OPTION_FAMILY16H_KB  TRUE
+    #undef OPTION_MEMCTLR_KB
+    #define OPTION_MEMCTLR_KB    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_CONTINOUS_PATTERN_GENERATION
+    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
+    #undef OPTION_HW_DQS_REC_EN_TRAINING
+    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
+    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_RDDQS_2D_TRAINING
+    #define OPTION_RDDQS_2D_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_GFX_RECOVERY
+    #define OPTION_GFX_RECOVERY  TRUE
+    #undef OPTION_CPU_CORELEVELING
+    #define OPTION_CPU_CORELEVELING  TRUE
+    #undef OPTION_C6_STATE
+    #define OPTION_C6_STATE  TRUE
+    #undef OPTION_IO_CSTATE
+    #define OPTION_IO_CSTATE TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_CPU_APM
+    #define OPTION_CPU_APM TRUE
+    #undef OPTION_CPB
+    #define OPTION_CPB  TRUE
+    #undef OPTION_CPU_HTC
+    #define OPTION_CPU_HTC TRUE
+    #undef OPTION_CPU_PSI
+    #define OPTION_CPU_PSI TRUE
+    #undef OPTION_CDIT
+    #define OPTION_CDIT  TRUE
+    #undef OPTION_CRAT
+    #define OPTION_CRAT  TRUE
+    #undef OPTION_CPU_SCS
+    #define OPTION_CPU_SCS TRUE
+    #undef OPTION_S3SCRIPT
+    #define OPTION_S3SCRIPT  TRUE
+    ///@todo
+    //#undef OPTION_PREFETCH_MODE
+    //#define OPTION_PREFETCH_MODE TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+
+#if (OPTION_FAMILY16H_KB == TRUE)
+  #undef  GNB_SUPPORT
+  #define GNB_SUPPORT   TRUE
+#endif
+
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+#define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
+#define OPTION_ALIB                     TRUE
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
+  #if  BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
+    #undef  OPTION_DDR3
+    #define OPTION_DDR3               FALSE
+  #endif
+#endif
+#if ((OPTION_DDR3 == FALSE))
+  #error  BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
+#endif
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
+    #undef  OPTION_LRDIMMS
+    #define OPTION_LRDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
+  #if  BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
+    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
+    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_CRAT
+  #if  BLDOPT_REMOVE_CRAT == TRUE
+    #undef  OPTION_CRAT
+    #define OPTION_CRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_CDIT
+  #if  BLDOPT_REMOVE_CDIT == TRUE
+    #undef  OPTION_CDIT
+    #define OPTION_CDIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_AMP_SUPPORT
+  #if  BLDOPT_REMOVE_AMP_SUPPORT == TRUE
+    #undef  OPTION_AMP
+    #define OPTION_AMP        FALSE
+  #endif
+#endif
+
+#ifdef OPTION_RDDQS_2D_TRAINING
+  #if OPTION_RDDQS_2D_TRAINING == FALSE
+    #undef OPTION_DATA_EYE
+    #define OPTION_DATA_EYE     FALSE
+  #else
+    #ifdef BLDOPT_REMOVE_DATA_EYE
+      #if BLDOPT_REMOVE_DATA_EYE == TRUE
+        #undef OPTION_DATA_EYE
+        #define OPTION_DATA_EYE     FALSE
+      #endif
+    #endif
+  #endif
+#else
+  #undef OPTION_DATA_EYE
+  #define OPTION_DATA_EYE     FALSE
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_ATM_MODE
+  #if  BLDOPT_REMOVE_ATM_MODE == TRUE
+    #undef  OPTION_ATM_MODE
+    #define OPTION_ATM_MODE      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
+  #if  BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
+    #undef  OPTION_NBR_CACHE
+    #define OPTION_NBR_CACHE      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_C6_STATE
+  #if  BLDOPT_REMOVE_C6_STATE == TRUE
+    #undef  OPTION_C6_STATE
+    #define OPTION_C6_STATE      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_GFX_RECOVERY
+  #if  BLDOPT_REMOVE_GFX_RECOVERY == TRUE
+    #undef  OPTION_GFX_RECOVERY
+    #define OPTION_GFX_RECOVERY         FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
+  #if  BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
+    #undef OPTION_RDDQS_2D_TRAINING
+    #define OPTION_RDDQS_2D_TRAINING      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
+  #if  BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT  == TRUE
+    #undef  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
+    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT    FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_AGGRESSOR
+  #if  BLDOPT_REMOVE_AGGRESSOR == TRUE
+    #undef  OPTION_AGGRESSOR
+    #define OPTION_AGGRESSOR      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_PSTATE_HPC_MODE
+  #if  BLDCFG_PSTATE_HPC_MODE  == TRUE
+    #undef  OPTION_CPU_PSTATE_HPC_MODE
+    #define OPTION_CPU_PSTATE_HPC_MODE    TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
+    #define CFG_ACPI_PSTATES_PSD_POLICY     (BLDCFG_ACPI_PSTATES_PSD_POLICY)
+#else
+    #define CFG_ACPI_PSTATES_PSD_POLICY     PsdPolicyProcessorDefault
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
+  #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
+    #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
+    #define CFG_VRM_NB_HIGH_SPEED_ENABLE    TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_STARTING_BUSNUM
+  #define CFG_STARTING_BUSNUM         (BLDCFG_STARTING_BUSNUM)
+#else
+  #define CFG_STARTING_BUSNUM         (0)
+#endif
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#ifdef BLDCFG_MAXIMUM_BUSNUM
+  #define CFG_MAXIMUM_BUSNUM          (BLDCFG_MAXIMUM_BUSNUM)
+#else
+  #define CFG_MAXIMUM_BUSNUM          (0xF8)
+#endif
+
+#ifdef BLDCFG_ALLOCATED_BUSNUM
+  #define CFG_ALLOCATED_BUSNUM        (BLDCFG_ALLOCATED_BUSNUM)
+#else
+  #define CFG_ALLOCATED_BUSNUM        (0x20)
+#endif
+
+#ifdef BLDCFG_BUID_SWAP_LIST
+  #define CFG_BUID_SWAP_LIST         (BLDCFG_BUID_SWAP_LIST)
+#else
+  #define CFG_BUID_SWAP_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
+  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
+#else
+  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
+  #define CFG_HTFABRIC_LIMITS_LIST         (BLDCFG_HTFABRIC_LIMITS_LIST)
+#else
+  #define CFG_HTFABRIC_LIMITS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
+  #define CFG_HTCHAIN_LIMITS_LIST         (BLDCFG_HTCHAIN_LIMITS_LIST)
+#else
+  #define CFG_HTCHAIN_LIMITS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_BUS_NUMBERS_LIST
+  #define CFG_BUS_NUMBERS_LIST         (BLDCFG_BUS_NUMBERS_LIST)
+#else
+  #define CFG_BUS_NUMBERS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_IGNORE_LINK_LIST
+  #define CFG_IGNORE_LINK_LIST         (BLDCFG_IGNORE_LINK_LIST)
+#else
+  #define CFG_IGNORE_LINK_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
+  #define CFG_LINK_SKIP_REGANG_LIST         (BLDCFG_LINK_SKIP_REGANG_LIST)
+#else
+  #define CFG_LINK_SKIP_REGANG_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
+  #define CFG_SET_HTCRC_SYNC_FLOOD         (BLDCFG_SET_HTCRC_SYNC_FLOOD)
+#else
+  #define CFG_SET_HTCRC_SYNC_FLOOD         (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
+  #define CFG_USE_UNIT_ID_CLUMPING         (BLDCFG_USE_UNIT_ID_CLUMPING)
+#else
+  #define CFG_USE_UNIT_ID_CLUMPING         (FALSE)
+#endif
+
+#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
+  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
+#else
+  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_USE_HT_ASSIST
+  #define CFG_USE_HT_ASSIST               (BLDCFG_USE_HT_ASSIST)
+#else
+  #define CFG_USE_HT_ASSIST               (TRUE)
+#endif
+
+#ifdef BLDCFG_USE_ATM_MODE
+  #define CFG_USE_ATM_MODE                (BLDCFG_USE_ATM_MODE)
+#else
+  #define CFG_USE_ATM_MODE                (TRUE)
+#endif
+
+#ifdef BLDCFG_USE_NEIGHBOR_CACHE
+  #define CFG_USE_NBR_CACHE                (BLDCFG_USE_NEIGHBOR_CACHE)
+#else
+  #define CFG_USE_NBR_CACHE                (TRUE)
+#endif
+
+#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
+  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
+#else
+  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (Nfcm)
+#endif
+
+#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
+  #define CFG_PERFORMANCE_HARDWARE_PREFETCHER  (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
+#else
+  #define CFG_PERFORMANCE_HARDWARE_PREFETCHER  (HARDWARE_PREFETCHER_AUTO)
+#endif
+
+#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
+  #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES  (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
+#else
+  #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES  (SOFTWARE_PREFETCHES_AUTO)
+#endif
+
+#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
+  #define CFG_PERFORMANCE_DRAM_PREFETCHER  (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
+#else
+  #define CFG_PERFORMANCE_DRAM_PREFETCHER  (DRAM_PREFETCHER_AUTO)
+#endif
+
+#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
+  #define CFG_PLATFORM_DEEMPHASIS_LIST  (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
+#else
+  #define CFG_PLATFORM_DEEMPHASIS_LIST  (NULL)
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                DFLT_VRM_SLEW_RATE
+#endif
+
+#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
+  #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  (0)
+#endif
+
+#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+  #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  (0)
+#endif
+
+#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
+  #define CFG_VRM_SVI_OCP_LEVEL     BLDCFG_VRM_SVI_OCP_LEVEL
+#else
+  #define CFG_VRM_SVI_OCP_LEVEL     0
+#endif
+
+#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
+  #define CFG_VRM_NB_SVI_OCP_LEVEL  BLDCFG_VRM_NB_SVI_OCP_LEVEL
+#else
+  #define CFG_VRM_NB_SVI_OCP_LEVEL  0
+#endif
+
+#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
+  #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
+#else
+  #define CFG_VRM_NB_CURRENT_LIMIT         (0)
+#endif
+
+#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
+  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   (0)
+#endif
+
+#ifdef BLDCFG_VRM_NB_SLEW_RATE
+  #define CFG_VRM_NB_SLEW_RATE             BLDCFG_VRM_NB_SLEW_RATE
+#else
+  #define CFG_VRM_NB_SLEW_RATE             DFLT_VRM_SLEW_RATE
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
+  #define CFG_C1E_OPDATA1                     BLDCFG_PLATFORM_C1E_OPDATA1
+#else
+  #define CFG_C1E_OPDATA1                     0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
+  #define CFG_C1E_OPDATA2                     BLDCFG_PLATFORM_C1E_OPDATA2
+#else
+  #define CFG_C1E_OPDATA2                     0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
+  #define CFG_C1E_OPDATA3                     BLDCFG_PLATFORM_C1E_OPDATA3
+#else
+  #define CFG_C1E_OPDATA3                     0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeC6
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
+  #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
+#else
+  #define CFG_CSTATE_IO_BASE_ADDRESS       0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CPB_MODE
+  #define CFG_CPB_MODE                        BLDCFG_PLATFORM_CPB_MODE
+#else
+  #define CFG_CPB_MODE                        CpbModeAuto
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_TDP_LIMIT
+  #define CFG_AMD_POWER_CEILING            BLDCFG_AMD_TDP_LIMIT
+#else
+  #define CFG_AMD_POWER_CEILING            0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              DFLT_MEMORY_QUADRANK_TYPE
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
+  #define CFG_MEMORY_LRDIMM_CAPABLE              BLDCFG_MEMORY_LRDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_LRDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         DFLT_SCRUB_DRAM_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           DFLT_SCRUB_L2_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           DFLT_SCRUB_L3_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           DFLT_SCRUB_IC_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           DFLT_SCRUB_DC_RATE
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          TRUE
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_FORCE_TRAINING_MODE
+  #define CFG_FORCE_TRAIN_MODE                BLDCFG_FORCE_TRAINING_MODE
+#else
+  #define CFG_FORCE_TRAIN_MODE                FORCE_TRAIN_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G           FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
+  #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG      BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
+#else
+  #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG      DDR3_TECHNOLOGY
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   TRUE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DYNAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         200
+#endif
+
+#ifdef BLDCFG_STEREO_3D_PINOUT
+  #define CFG_GNB_STEREO_3D_PINOUT           BLDCFG_STEREO_3D_PINOUT
+#else
+  #define CFG_GNB_STEREO_3D_PINOUT           0
+#endif
+
+#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
+  #define CFG_GNB_REMOTE_DISPLAY_SUPPORT     BLDCFG_REMOTE_DISPLAY_SUPPORT
+#else
+  #define CFG_GNB_REMOTE_DISPLAY_SUPPORT     FALSE
+#endif
+
+// Define pin configuration for SYNCFLOOD
+// Default to FALSE (Use pin as SYNCFLOOD)
+#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
+  #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI       BLDCFG_USE_SYNCFLOOD_AS_NMI
+#else
+  #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI       FALSE
+#endif
+
+#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
+  #define CFG_GNB_THERMAL_SENSOR_CORRECTION  BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
+#else
+  #define CFG_GNB_THERMAL_SENSOR_CORRECTION  0
+#endif
+
+#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
+  #define CFG_GNB_IGPU_SSID                  BLDCFG_IGPU_SUBSYSTEM_ID
+#else
+  #define CFG_GNB_IGPU_SSID                  0
+#endif
+
+#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
+  #define CFG_GNB_HDAUDIO_SSID               BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
+#else
+  #define CFG_GNB_HDAUDIO_SSID               0
+#endif
+
+#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
+  #define CFG_IGPU_ENABLE_DISABLE_POLICY    BLDCFG_IGPU_ENABLE_DISABLE_POLICY
+#else
+  #define CFG_IGPU_ENABLE_DISABLE_POLICY    IGPU_DISABLE_AUTO
+#endif
+
+#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
+  #define CFG_GNB_PCIE_SSID                  BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
+#else
+  #define CFG_GNB_PCIE_SSID                  0x12341022ul
+#endif
+
+#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
+#else
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               0
+#endif
+
+#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
+#else
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
+#endif
+
+#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+#else
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000ul
+#endif
+
+#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
+  #define CFG_ENABLE_EXTERNAL_VREF                BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
+#else
+  #define CFG_ENABLE_EXTERNAL_VREF                FALSE
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_ALIB
+  #if  BLDOPT_REMOVE_ALIB == TRUE
+    #undef  OPTION_ALIB
+    #define OPTION_ALIB                 FALSE
+  #else
+    #undef  OPTION_ALIB
+    #define OPTION_ALIB                 TRUE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FCH_COMPONENT
+  #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
+    #undef FCH_SUPPORT
+    #define FCH_SUPPORT                            FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_IOMMU_SUPPORT
+  #define CFG_IOMMU_SUPPORT             BLDCFG_IOMMU_SUPPORT
+#else
+  #define CFG_IOMMU_SUPPORT             TRUE
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
+  #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             0
+#endif
+
+#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
+  #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
+#else
+  #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
+  #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
+  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
+  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         0
+#endif
+
+#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
+  #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
+#else
+  #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             0
+#endif
+
+#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
+  #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
+#else
+  #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           0
+#endif
+
+
+// BLDCFG_LVDS_24BBP_PANEL_MODE
+// This specifies the LVDS 24 BBP mode.
+// 0 - Use LDI mode (default).
+// 1 - Use FPDI mode.
+#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
+  #define CFG_LVDS_24BBP_PANEL_MODE                 BLDCFG_LVDS_24BBP_PANEL_MODE
+#else
+  #define CFG_LVDS_24BBP_PANEL_MODE                 0
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
+  #define CFG_LVDS_MISC_888_FPDI_MODE                 BLDCFG_LVDS_MISC_888_FPDI_MODE
+#else
+  #define CFG_LVDS_MISC_888_FPDI_MODE                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
+  #define CFG_LVDS_MISC_DL_CH_SWAP                 BLDCFG_LVDS_MISC_DL_CH_SWAP
+#else
+  #define CFG_LVDS_MISC_DL_CH_SWAP                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
+  #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE            BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
+#else
+  #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE            FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
+  #define CFG_LVDS_MISC_VOLT_ADJUSTMENT               BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
+#else
+  #define CFG_LVDS_MISC_VOLT_ADJUSTMENT               0
+#endif
+
+#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
+  #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE            BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
+#else
+  #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE            FALSE
+#endif
+
+#ifdef BLDCFG_DP_FIXED_VOLT_SWING
+  #define CFG_DP_FIXED_VOLT_SWING               BLDCFG_DP_FIXED_VOLT_SWING
+#else
+  #define CFG_DP_FIXED_VOLT_SWING               0
+#endif
+
+#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
+  #define CFG_PLATFORM_POWER_POLICY_MODE  (BLDCFG_PLATFORM_POWER_POLICY_MODE)
+#else
+  #define CFG_PLATFORM_POWER_POLICY_MODE  (Performance)
+#endif
+
+#ifdef BLDCFG_NB_PSTATES_SUPPORTED
+  #define CFG_NB_PSTATES_SUPPORTED        (BLDCFG_NB_PSTATES_SUPPORTED)
+#else
+  #define CFG_NB_PSTATES_SUPPORTED        (TRUE)
+#endif
+
+#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
+  #define CFG_HTC_TEMPERATURE_LIMIT        (BLDCFG_HTC_TEMPERATURE_LIMIT)
+#else
+  #define CFG_HTC_TEMPERATURE_LIMIT        (0)
+#endif
+
+#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
+  #define CFG_LHTC_TEMPERATURE_LIMIT        (BLDCFG_LHTC_TEMPERATURE_LIMIT)
+#else
+  #define CFG_LHTC_TEMPERATURE_LIMIT        (0)
+#endif
+
+#ifdef BLDCFG_PCI_MMIO_BASE
+  #define CFG_PCI_MMIO_BASE               (BLDCFG_PCI_MMIO_BASE)
+#else
+  #define CFG_PCI_MMIO_BASE               (0)
+#endif
+
+#ifdef BLDCFG_PCI_MMIO_SIZE
+  #define CFG_PCI_MMIO_SIZE               (BLDCFG_PCI_MMIO_SIZE)
+#else
+  #define CFG_PCI_MMIO_SIZE               (0)
+#endif
+
+#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
+  #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
+#else
+  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
+#endif
+
+#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
+  #define CFG_IOMMU_EXCLUSION_RANGE_LIST      (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
+#else
+  #define CFG_IOMMU_EXCLUSION_RANGE_LIST      (NULL)
+#endif
+
+#ifdef BLDCFG_HYBRID_BOOST_ENABLE
+  #define CFG_HYBRID_BOOST_ENABLE            BLDCFG_HYBRID_BOOST_ENABLE
+#else
+  #define CFG_HYBRID_BOOST_ENABLE            TRUE
+#endif
+
+#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
+  #define CFG_GNB_IOAPIC_ADDRESS             BLDCFG_GNB_IOAPIC_ADDRESS
+#else
+  #define CFG_GNB_IOAPIC_ADDRESS             NULL
+#endif
+
+#ifdef BLDCFG_GNB_IOMMU_ADDRESS
+  #define CFG_GNB_IOMMU_ADDRESS             BLDCFG_GNB_IOMMU_ADDRESS
+#else
+  #define CFG_GNB_IOMMU_ADDRESS             NULL
+#endif
+
+#ifdef BLDCFG_ENABLE_DATA_EYE
+  #define CFG_ENABLE_DATA_EYE              BLDCFG_ENABLE_DATA_EYE
+#else
+  #define CFG_ENABLE_DATA_EYE              TRUE
+#endif
+
+#ifdef BLDCFG_ACPI_SET_OEM_ID
+  #define CFG_ACPI_SET_OEM_ID             BLDCFG_ACPI_SET_OEM_ID
+#else
+  #define CFG_ACPI_SET_OEM_ID             'A','M','D',' ',' ',' '
+#endif
+
+#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
+  #define CFG_ACPI_SET_OEM_TABLE_ID       BLDCFG_ACPI_SET_OEM_TABLE_ID
+#else
+  #define CFG_ACPI_SET_OEM_TABLE_ID       'A','G','E','S','A',' ',' ',' '
+#endif
+
+#ifdef BLDCFG_DOCKED_TDP_HEADROOM
+  #define CFG_DOCKED_TDP_HEADROOM         BLDCFG_DOCKED_TDP_HEADROOM
+#else
+  #define CFG_DOCKED_TDP_HEADROOM         TRUE
+#endif
+
+#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
+  #define CFG_DRAM_DOUBLE_REFRESH_RATE             BLDCFG_DRAM_DOUBLE_REFRESH_RATE
+#else
+  #define CFG_DRAM_DOUBLE_REFRESH_RATE             FALSE
+#endif
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #if OPTION_LRDIMMS == FALSE
+        #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
+        #error   BLDCFG: No dimm type is capable
+      #endif
+    #endif
+  #endif
+#endif
+// Check LRDIMM CODE and LRDIMM CFG item
+#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
+  #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
+    #error   Warning: LRDIMM capability is false, but LRIDMM support code included
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
+              #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
+                #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
+                  #error    BLDCFG: Unsupported memory bus frequency
+                #endif
+              #endif
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #if AGESA_ENTRY_INIT_POST == TRUE
+      #error     BLDCFG: Invalid power down mode set
+    #endif
+  #endif
+#endif
+
+// Ensure P-state dependence settings do not conflict
+#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
+  #error     BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
+#endif
+
+#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
+  #error     BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
+#endif
+
+#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
+  #error     BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
+#endif
+
+
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTablesMain
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+// Consolidate P-state dependence setings
+#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
+  #undef CFG_ACPI_PSTATES_PSD_POLICY
+  #define CFG_ACPI_PSTATES_PSD_POLICY  PsdPolicyIndependent
+#endif
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "Options.h"
+#include  "OptionCpuFamiliesInstall.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionCrat.h"
+#include  "OptionCratInstall.h"
+#include  "OptionCdit.h"
+#include  "OptionCditInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionGfxRecovery.h"
+#include  "OptionGfxRecoveryInstall.h"
+#include  "OptionGnb.h"
+#include  "OptionGnbInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#include  "OptionFchInstall.h"
+#include  "OptionMmioMapInstall.h"
+#include  "OptionPrefetchModeInstall.h"
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+
+FCH_PLATFORM_POLICY  FchUserOptions = {
+  CFG_SMBUS0_BASE_ADDRESS,              // CfgSmbus0BaseAddress
+  CFG_SMBUS1_BASE_ADDRESS,              // CfgSmbus1BaseAddress
+  CFG_SIO_PME_BASE_ADDRESS,             // CfgSioPmeBaseAddress
+  CFG_ACPI_PM1_EVT_BLOCK_ADDRESS,       // CfgAcpiPm1EvtBlkAddr
+  CFG_ACPI_PM1_CNT_BLOCK_ADDRESS,       // CfgAcpiPm1CntBlkAddr
+  CFG_ACPI_PM_TMR_BLOCK_ADDRESS,        // CfgAcpiPmTmrBlkAddr
+  CFG_ACPI_CPU_CNT_BLOCK_ADDRESS,       // CfgCpuControlBlkAddr
+  CFG_ACPI_GPE0_BLOCK_ADDRESS,          // CfgAcpiGpe0BlkAddr
+  CFG_SMI_CMD_PORT_ADDRESS,             // CfgSmiCmdPortAddr
+  CFG_ACPI_PMA_CNTBLK_ADDRESS,          // CfgAcpiPmaCntBlkAddr
+  CFG_GEC_SHADOW_ROM_BASE,              // CfgGecShadowRomBase
+  CFG_WATCHDOG_TIMER_BASE,              // CfgWatchDogTimerBase
+  CFG_SPI_ROM_BASE_ADDRESS,             // CfgSpiRomBaseAddress
+  CFG_HPET_BASE_ADDRESS,                // CfgHpetBaseAddress
+  0x780D1022ul,
+  CFG_SMBUS_SSID,                       // CfgSmbusSsid
+  CFG_IDE_SSID,                         // CfgIdeSsid
+  CFG_SATA_AHCI_SSID,                   // CfgSataAhciSsid
+  CFG_SATA_IDE_SSID,                    // CfgSataIdeSsid
+  CFG_SATA_RAID5_SSID,                  // CfgSataRaid5Ssid
+  CFG_SATA_RAID_SSID,                   // CfgSataRaidSsid
+  CFG_EHCI_SSID,                        // CfgEhcidSsid
+  CFG_OHCI_SSID,                        // CfgOhcidSsid
+  CFG_LPC_SSID,                         // CfgLpcSsid
+  CFG_SD_SSID,                          // CfgSdSsid
+  CFG_XHCI_SSID,                        // CfgXhciSsid
+  CFG_FCH_PORT80_BEHIND_PCIB,           // CfgFchPort80BehindPcib
+  CFG_FCH_ENABLE_ACPI_SLEEP_TRAP,       // CfgFchEnableAcpiSleepTrap
+  CFG_FCH_GPP_LINK_CONFIG,              // CfgFchGppLinkConfig
+  CFG_FCH_GPP_PORT0_PRESENT,            // CfgFchGppPort0Present
+  CFG_FCH_GPP_PORT1_PRESENT,            // CfgFchGppPort1Present
+  CFG_FCH_GPP_PORT2_PRESENT,            // CfgFchGppPort2Present
+  CFG_FCH_GPP_PORT3_PRESENT,            // CfgFchGppPort3Present
+  CFG_FCH_GPP_PORT0_HOTPLUG,            // CfgFchGppPort0HotPlug
+  CFG_FCH_GPP_PORT1_HOTPLUG,            // CfgFchGppPort1HotPlug
+  CFG_FCH_GPP_PORT2_HOTPLUG,            // CfgFchGppPort2HotPlug
+  CFG_FCH_GPP_PORT3_HOTPLUG,            // CfgFchGppPort3HotPlug
+
+  CFG_FCH_ESATA_PORT_BITMAP,