[coreboot-gerrit] New patch to review for coreboot: 1f9ba6d cbmem: Implement ARM support

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4311

-gerrit

commit 1f9ba6df447bf82d04c5b7f97460613acd65efd4
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jun 19 15:39:09 2013 -0700

    cbmem: Implement ARM support
    
    on ARM the CBMEM utility requires the procfs entry
    /proc/device-tree/firmware/coreboot/coreboot-table
    provided by the FDT (dynamically created by depthcharge
    at the moment)
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    
    Change-Id: If5f961afb23791af6f32dd4fc9a837a1aa41b70e
    Reviewed-on: https://gerrit.chromium.org/gerrit/59322
    Reviewed-by: Stefan Reinauer <reinauer at chromium.org>
    Tested-by: Stefan Reinauer <reinauer at chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer at chromium.org>
---
 util/cbmem/cbmem.c | 31 +++++++++++++++++++++++++++----
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index e05a72a..cb95556 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -26,6 +26,7 @@
 #include <getopt.h>
 #include <errno.h>
 #include <fcntl.h>
+#include <arpa/inet.h>
 #include <sys/types.h>
 #include <sys/stat.h>
 #include <sys/mman.h>
@@ -81,7 +82,7 @@ static void *map_memory(u64 physical)
 {
 	void *v;
 	off_t p;
-	int page = getpagesize();
+	u64 page = getpagesize();
 
 	/* Mapped memory must be aligned to page size */
 	p = physical & ~(page - 1);
@@ -569,9 +570,6 @@ static void print_usage(const char *name)
 
 int main(int argc, char** argv)
 {
-	int j;
-	static const int possible_base_addresses[] = { 0, 0xf0000 };
-
 	int print_defaults = 1;
 	int print_console = 0;
 	int print_coverage = 0;
@@ -631,11 +629,36 @@ int main(int argc, char** argv)
 		return 1;
 	}
 
+#ifdef __arm__
+	int dt_fd;
+	uint32_t cbtable_base;
+
+	dt_fd = open("/proc/device-tree/firmware/coreboot/coreboot-table",
+			O_RDONLY, 0);
+	if (dt_fd < 0) {
+		fprintf(stderr, "Failed to open device tree node: %s\n",
+			strerror(errno));
+		return 1;
+	}
+
+	if (read(dt_fd, &cbtable_base, 4) != 4) {
+		fprintf(stderr, "Failed to read device tree node: %s\n",
+			strerror(errno));
+		return 1;
+	}
+	close(dt_fd);
+
+	parse_cbtable(ntohl(cbtable_base));
+#else
+	int j;
+	static const int possible_base_addresses[] = { 0, 0xf0000 };
+
 	/* Find and parse coreboot table */
 	for (j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) {
 		if (parse_cbtable(possible_base_addresses[j]))
 			break;
 	}
+#endif
 
 	if (print_console)
 		dump_console();