[coreboot-gerrit] New patch to review for coreboot: 70468cd lynxpoint: Add configuration option for SATA gen3 DTLE registers
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Dec 4 00:36:02 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4475
-gerrit
commit 70468cdcef3b51cecae12d21631999926807ffbf
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date: Tue Aug 13 10:45:21 2013 -0700
lynxpoint: Add configuration option for SATA gen3 DTLE registers
Allow DTLE DATA / EDGE registers to be configured in board-specific
devicetree.
Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea
Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65716
Reviewed-by: Marc Jones <marc.jones at se-eng.com>
---
src/southbridge/intel/lynxpoint/chip.h | 3 +++
src/southbridge/intel/lynxpoint/pch.h | 8 ++++++++
src/southbridge/intel/lynxpoint/sata.c | 25 +++++++++++++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index bb4c004..1b4ac2a 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -72,6 +72,9 @@ struct southbridge_intel_lynxpoint_config {
uint8_t sata_port_map;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
+ uint32_t sata_port0_gen3_dtle;
+ uint32_t sata_port1_gen3_dtle;
+
/* SATA DEVSLP Mux
* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 67b6679..3396367 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -351,6 +351,14 @@ int early_pch_init(const void *gpio_map,
/* SATA IOBP Registers */
#define SATA_IOBP_SP0G3IR 0xea000151
#define SATA_IOBP_SP1G3IR 0xea000051
+#define SATA_IOBP_SP0DTLE_DATA 0xea002550
+#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
+#define SATA_IOBP_SP1DTLE_DATA 0xea002750
+#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
+
+#define SATA_DTLE_MASK 0xF
+#define SATA_DTLE_DATA_SHIFT 24
+#define SATA_DTLE_EDGE_SHIFT 16
/* EHCI PCI Registers */
#define EHCI_PWR_CTL_STS 0x54
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 8912865..a8d8319 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -233,6 +233,31 @@ static void sata_init(struct device *dev)
pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
config->sata_port1_gen3_tx);
+ /* Set Gen3 DTLE DATA / EDGE registers if needed */
+ if (config->sata_port0_gen3_dtle) {
+ pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
+ ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
+ (config->sata_port0_gen3_dtle & SATA_DTLE_MASK)
+ << SATA_DTLE_DATA_SHIFT);
+
+ pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
+ ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
+ (config->sata_port0_gen3_dtle & SATA_DTLE_MASK)
+ << SATA_DTLE_EDGE_SHIFT);
+ }
+
+ if (config->sata_port1_gen3_dtle) {
+ pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
+ ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
+ (config->sata_port1_gen3_dtle & SATA_DTLE_MASK)
+ << SATA_DTLE_DATA_SHIFT);
+
+ pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
+ ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
+ (config->sata_port1_gen3_dtle & SATA_DTLE_MASK)
+ << SATA_DTLE_EDGE_SHIFT);
+ }
+
/* Additional Programming Requirements */
/* Power Optimizer */
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